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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 24452. Отображено 100.
05-01-2012 дата публикации

Semiconductor substrate and semiconductor device

Номер: US20120001195A1
Автор: Isao Makabe, Keiichi Yui, Ken Nakata, Takamitsu Kitamura
Принадлежит: Sumitomo Electric Industries Ltd

A semiconductor substrate inclu8des an AlN layer that is formed so as to contact a Si substrate and has an FWMH of a rocking curve of a (002) plane by x-ray diffraction, the FWMH being less than or equal to 1500 seconds, and a GaN-based semiconductor layer formed on the AlN layer.

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Номер записи: 1
19-01-2012 дата публикации

Performance of nitride semiconductor devices

Номер: US20120012894A1
Автор: Jinwook Chung, Tomas Apostol Palacios
Принадлежит: Massachusetts Institute of Technology

A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region.

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Номер записи: 2
26-01-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120018742A1
Автор: Masahiro Nishi
Принадлежит: Sumitomo Electric Device Innovations Inc

A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

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Номер записи: 3
26-01-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120021582A1
Автор: Masahiro Nishi
Принадлежит: Sumitomo Electric Device Innovations Inc

A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

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Номер записи: 4
02-02-2012 дата публикации

Semiconductor wafer, method of producing semiconductor wafer, method of judging quality of semiconductor wafer, and electronic device

Номер: US20120025271A1
Автор: Tsuyoshi Nakano
Принадлежит: Sumitomo Chemical Co Ltd

There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.

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Номер записи: 5
23-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120043587A1
Автор: Tsuyoshi Takahashi
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.

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Номер записи: 6
15-03-2012 дата публикации

Transistor devices and methods of making

Номер: US20120061684A1
Автор: John C. Arnold, Rangarajan Jagannathan, Stefan Schmitz, Xuefeng Hua
Принадлежит: International Business Machines Corp

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

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Номер записи: 7
22-03-2012 дата публикации

Field modulating plate and circuit

Номер: US20120068772A1
Автор: Ronaldus Johannus Martinus van Boxtel, Saad Kheder Murad
Принадлежит: Individual

Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.

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Номер записи: 8
29-03-2012 дата публикации

Microwave semiconductor device using compound semiconductor and method for manufacturing the same

Номер: US20120074470A1
Автор: Hisao Kawasaki
Принадлежит: Toshiba Corp

An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17 - 2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

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Номер записи: 9
03-05-2012 дата публикации

Method of manufacturing a semiconductor device

Номер: US20120108025A1
Автор: Masahiro Fukuda, Yosuke Shimamune
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.

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Номер записи: 10
10-05-2012 дата публикации

Formation of a graphene layer on a large substrate

Номер: US20120112164A1
Автор: Alfred Grill, Christos D. Dimitrakopoulos, Jack O. Chu, Marcus O. Freitag, Robert L. Wisnieff, Timothy J. McArdle
Принадлежит: International Business Machines Corp

A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

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Номер записи: 11
17-05-2012 дата публикации

METHOD FOR FABRICATING A GaN-BASED THIN FILM TRANSISTOR

Номер: US20120122281A1
Автор: Chia-Hua Chang, YI Chang, Yueh-Chin Lin
Принадлежит: National Chiao Tung University NCTU

A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.

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Номер записи: 12
07-06-2012 дата публикации

Reducing wafer distortion through a low cte layer

Номер: US20120138945A1
Автор: Chi-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Ho-Yung David Hwang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

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Номер записи: 13
07-06-2012 дата публикации

Island matrixed gallium nitride microwave and power switching transistors

Номер: US20120138950A1
Автор: Ahmad Mizan, Girvan Patterson, Greg Klowak, John Roberts
Принадлежит: GaN Systems Inc

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

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Номер записи: 14
07-06-2012 дата публикации

Compound semiconductor device and manufacturing method thereof

Номер: US20120138955A1
Автор: Atsushi Yamada, Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer.

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Номер записи: 15
07-06-2012 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20120138956A1
Автор: Atsushi Yamada, Kenji Imanishi, Sanae Shimizu, Toyoo Miyajima
Принадлежит: Fujitsu Ltd

A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including Al x Ga 1-x N(0≦x≦1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

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Номер записи: 16
07-06-2012 дата публикации

Semiconductor device and fabrication method thereof

Номер: US20120139007A1
Автор: Atsuhiro Kinoshita, Kosuke Tatsumura
Принадлежит: Toshiba Corp

According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si 1-x Ge x (0≦x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source/drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source/drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source/drain regions by using the edge portions of the source/drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.

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Номер записи: 17
07-06-2012 дата публикации

Compound semiconductor device and manufacturing method thereof

Номер: US20120139038A1
Автор: Kenji Imanishi, Toshihide Kikkawa
Принадлежит: Fujitsu Ltd

A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1<x2≦1” is found when a composition of the first AlGaN layer is represented by Al x1 Ga 1-x1 N, and a composition of the second AlGaN layer is represented by Al x2 Ga 1-x2 N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

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Номер записи: 18
14-06-2012 дата публикации

Jfet devices with increased barrier height and methods of making the same

Номер: US20120146049A1
Автор: Chandra Mouli
Принадлежит: Micron Technology Inc

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

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Номер записи: 19
14-06-2012 дата публикации

Nitride based semiconductor device

Номер: US20120146094A1
Автор: Kiyeol Park, Woochul Jeon, Younghwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a cathode structure ohmic-contacting the semiconductor layer; and an anode structure having a schottky electrode schottky-contacting the semiconductor layer and an ohmic electrode ohmic-contacting the nitride layer.

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Номер записи: 20
21-06-2012 дата публикации

Semiconductor Device And Method Of Manufacturing The Same

Номер: US20120153261A1
Автор: Hyun-gi Hong, Jun-Youn Kim, Su-hee Chae, Young-jo Tak
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

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Номер записи: 21
21-06-2012 дата публикации

Ohmic cathode electrode on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride substrates

Номер: US20120153297A1
Автор: Chia-Lin Hsiung, Hiroaki Ohta, Shuji Nakamura, Steven P. DenBaars, You-Da Lin
Принадлежит: UNIVERSITY OF CALIFORNIA

Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.

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Номер записи: 22
28-06-2012 дата публикации

Semiconductor device

Номер: US20120161153A1
Автор: Masahiko Kuraguchi, Miki Yumoto
Принадлежит: Toshiba Corp

A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.

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Номер записи: 23
05-07-2012 дата публикации

Semiconductor element, hemt element, and method of manufacturing semiconductor element

Номер: US20120168771A1
Автор: Makoto Miyoshi, Mikiya Ichimura, Mitsuhiro Tanaka, Shigeaki Sumiya, Tomohiko Sugiyama
Принадлежит: NGK Insulators Ltd

A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In x1 Al y1 Ga z1 N, a barrier layer formed of a second group-III nitride having a composition of In x2 Al y2 N, and a contact layer formed of a third group-III nitride having insularity and adjacent to the barrier layer, and the Schottky electrode is connected to the contact layer. In addition, a heat treatment is performed under a nitrogen atmosphere after the gate electrode has been formed.

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Номер записи: 24
05-07-2012 дата публикации

Heterostructure device and associated method

Номер: US20120171824A1
Автор: Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan, Vinayak Tilak
Принадлежит: General Electric Co

A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

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Номер записи: 25
12-07-2012 дата публикации

Ohmic contact to semiconductor device

Номер: US20120175682A1
Автор: Daniel Namishia, Helmut Hagleitner
Принадлежит: Cree Inc

Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

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Номер записи: 26
12-07-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120178226A1
Автор: Kozo Makiyama
Принадлежит: Fujitsu Ltd

A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.

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Номер записи: 27
02-08-2012 дата публикации

Fabrication of a vertical heterojunction tunnel-fet

Номер: US20120193678A1
Автор: Amlan Majumdar, Isaac Lauer, Paul M. Solomon, Steven J. Koester
Принадлежит: International Business Machines Corp

Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

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Номер записи: 28
09-08-2012 дата публикации

N-type doping of zinc telluride

Номер: US20120202341A1
Автор: Anthony Renau, Ludovic Godet, Xiangfeng LU
Принадлежит: Varian Semiconductor Equipment Associates Inc

ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.

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Номер записи: 29
30-08-2012 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20120217543A1
Автор: Toshihide Kikkawa, Toshihiro Ohki, Yuichi Minoura
Принадлежит: Fujitsu Ltd

At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.

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Номер записи: 30
30-08-2012 дата публикации

Method of producing semiconductor device and semiconductor device

Номер: US20120217545A1
Автор: Yoichi Kamada
Принадлежит: Fujitsu Ltd

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

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Номер записи: 31
30-08-2012 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20120217591A1
Автор: Yoichi Kamada
Принадлежит: Fujitsu Ltd

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

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Номер записи: 32
06-09-2012 дата публикации

Semiconductor diodes with low reverse bias currents

Номер: US20120223319A1
Автор: Yuvaraj Dora
Принадлежит: Transphorm Inc

A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

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Номер записи: 33
13-09-2012 дата публикации

High temperature performance capable gallium nitride transistor

Номер: US20120228675A1
Автор: Sten Heikman, Yifeng Wu
Принадлежит: Cree Inc

A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

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Номер записи: 34
13-09-2012 дата публикации

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

Номер: US20120229167A1
Автор: Evan Heller, Faquir Chand Jain
Принадлежит: Individual

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

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Номер записи: 35
20-09-2012 дата публикации

Normally-Off Semiconductor Devices

Номер: US20120235160A1
Автор: Sten Heikman, Yifeng Wu
Принадлежит: Individual

Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

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Номер записи: 36
27-09-2012 дата публикации

Semiconductor device based on the cubic silicon carbide single crystal thin film

Номер: US20120241764A1
Автор: Masaaki Sakuta, Mitsuhiko Ogihara
Принадлежит: Oki Data Corp

A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al x Ga 1-x As (0.6>x≧ 0 ) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the Al x Ga 1-x As (0.6>x≧ 0 ) in direct contact with the metal layer.

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Номер записи: 37
01-11-2012 дата публикации

Epitaxial substrate for electronic device and method of producing the same

Номер: US20120273759A1
Автор: Jo Shimizu, Tetsuya Ikuta, Tomohiko Shibata
Принадлежит: Dowa Electronics Materials Co Ltd

An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 Ω·cm.

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Номер записи: 38
22-11-2012 дата публикации

Functional element and manufacturing method of same

Номер: US20120292642A1
Автор: Akihiro Urata, Masahiro Araki, Masahiro Shiota, Takaaki Utsumi
Принадлежит: Sharp Corp

Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ 1 - 100], [ - 1010], and [ 01 - 01] of the substrate from a [ 0001 ] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

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Номер записи: 39
06-12-2012 дата публикации

Lateral trench mesfet

Номер: US20120305932A1
Автор: Andreas Peter Meiser, Franz Hirler
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

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Номер записи: 40
06-12-2012 дата публикации

Compound semiconductor device and method for manufacturing the same

Номер: US20120307534A1
Автор: Atsushi Yamada
Принадлежит: Fujitsu Ltd

An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

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Номер записи: 41
17-01-2013 дата публикации

Semiconductor structure and method of forming the same

Номер: US20130015460A1
Автор: Chun Lin Tsai, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu, Po-Chih Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

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Номер записи: 42
14-02-2013 дата публикации

Semiconductor device

Номер: US20130037823A1
Автор: Masaki Kondo, Takahisa Kanemura
Принадлежит: Toshiba Corp

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

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Номер записи: 43
21-02-2013 дата публикации

Metal chloride gas generator, hydride vapor phase epitaxy growth apparatus, and nitride semiconductor template

Номер: US20130043442A1
Автор: Hajime Fujikura, Michiko Matsuda, Taichiroo Konno
Принадлежит: Hitachi Cable Ltd

A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.

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Номер записи: 44
21-02-2013 дата публикации

Hemt with integrated low forward bias diode

Номер: US20130043484A1
Автор: Gilberto Curatola, Oliver Häberlen
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

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Номер записи: 45
21-02-2013 дата публикации

Nitride semiconductor transistor

Номер: US20130043492A1
Автор: Tetsuzo Ueda, Toshiyuki Takizawa
Принадлежит: Panasonic Corp

A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

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Номер записи: 46
21-02-2013 дата публикации

Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound

Номер: US20130043508A1
Автор: Clement Merckling
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

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Номер записи: 47
21-03-2013 дата публикации

CRYSTAL PRODUCING APPARATUS, CRYSTAL PRODUCING METHOD, SUBSTRATE PRODUCING METHOD, GALLIUM NITRIDE CRYSTAL, AND GALLIUM NITRIDE SUBSTRATE

Номер: US20130069078A1
Автор: Iwata Hirokazu, Sarayama Seiji
Принадлежит:

A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal. 123-. (canceled)24. A method for producing a columnar-shaped group-III nitride crystal , the method comprising:{'sup': 5', '−2, '(a) obtaining a first group-III nitride crystal, grown by a flux method at a first crystal-growth speed, and having a dislocation density equal to or less than 10cm;'}{'sup': 5', '−2, '(b) growing a second group-III nitride crystal at a second crystal-growth speed, by vapor phase epitaxy method on a surface of the first group-III nitride crystal having the dislocation density equal to or less than 10cm,'}wherein the second crystal-growth speed is faster than the first crystal-growth speed, andwherein the first group-III nitride crystal is in a columnar shape, in which a length in a c-axis direction is longer than a length in an a-axis direction.25. The method according to claim 24 , further comprising slicing the first group-III nitride crystal before performing the growing.26. The method according to claim 25 , wherein the first group-III nitride crystal is capable of being reused.27. The method according to claim 24 , wherein the first group-III nitride crystal and the second group-III nitride crystal are gallium nitride crystals.28. The method according to claim 24 , wherein the flux method includes:detecting a temperature of the seed crystal and first group-III nitride crystal and a temperature of a melt mixture; andcontrolling a flow rate of the nitrogen source gas supplied into the melt mixture, to change the temperature of the seed crystal and ...

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Номер записи: 48
21-03-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130069113A1
Автор: Atsushi Yamada
Принадлежит: Fujitsu Ltd

An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.

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Номер записи: 49
28-03-2013 дата публикации

Semiconductor device

Номер: US20130075750A1
Автор: Yuichi Minoura
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area.

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Номер записи: 50
28-03-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130075751A1
Автор: Kenji Imanishi
Принадлежит: Fujitsu Ltd

An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.

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Номер записи: 51
28-03-2013 дата публикации

SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES

Номер: US20130075754A1
Автор: Hirako Akira, Nomura Akihiro, Ohkawa Kazuhiro
Принадлежит:

In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NHgas is fed onto the nucleation layer. This turns the surface of the nucleation layer into a group-V element and then forms a group-III-V compound layer of AlN. Then, a mixed gas of TMAl gas and NHgas is fed onto the group-III-V compound layer so as to form another group-III-V compound layer. Finally, a group-III nitride semiconductor layer is crystal-grown on the group-III compound layer. 1. A method for fabricating a semiconductor device , the method comprising:{'sub': 3', '5', '12, 'forming a buffer layer, containing a group-III-V compound, on a substrate formed of YAlO; and'}forming a group-III nitride semiconductor layer on the buffer layer,wherein the forming the buffer layer includes forming a nucleation layer made of a group-III element in at least a part on the substrate,wherein the substrate is a single-crystal substrate of any of surface orientations (100) and (110).2. A method for fabricating a semiconductor device according to claim 1 , wherein the nucleation layer is formed by supplying a first gas containing a group-III element onto the substrate.3. A method for fabricating a semiconductor device according to claim 1 , wherein the forming a buffer layer further includes changing at least a part of the surface of the nucleation layer into a group-III-V compound by combining the at least a part of the surface of the nucleation layer with a group V element.4. A method for fabricating a semiconductor device according to claim 3 , wherein the at least a part of the surface of the nucleation layer is changed into a group-III-V compound by supplying a second gas containing a group-V element onto the nucleation layer.5. A method for ...

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Номер записи: 52
28-03-2013 дата публикации

Semiconductor device

Номер: US20130075786A1
Автор: Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

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Номер записи: 53
28-03-2013 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20130077352A1
Автор: Atsushi Yamada, Sanae Shimizu
Принадлежит: Fujitsu Ltd

A semiconductor device includes a substrate; a first nitride semiconductor layer provided over the substrate and having a nitride-polar surface; a gate electrode provided over the first nitride semiconductor layer; and a semiconductor layer provided on the first nitride semiconductor layer and only under the gate electrode, and exhibiting a polarization.

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Номер записи: 54
04-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130082256A1
Автор: Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region. 1. A semiconductor device comprising:a gate electrode layer;a gate insulating layer over the gate electrode layer;a first oxide semiconductor layer over the gate electrode layer with the gate insulating layer interposed therebetween;a second oxide semiconductor layer on the first oxide semiconductor layer;a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer,wherein the first oxide semiconductor layer comprises indium and zinc,wherein the second oxide semiconductor layer comprises indium and zinc,wherein the second oxide semiconductor layer comprises a first crystalline region, andwherein the first crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer.2. The semiconductor device according to claim 1 , wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×10/cm.3. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises ...

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Номер записи: 55
04-04-2013 дата публикации

Nitride semiconductor device and manufacturing method thereof

Номер: US20130082277A1
Автор: Ki Yeol Park, Seok Yoon HONG, Woo Chul Jeon, Young Hwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.

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Номер записи: 56
04-04-2013 дата публикации

Compound semiconductor device and method for fabricating the same

Номер: US20130082360A1
Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Toyoo Miyajima
Принадлежит: Fujitsu Ltd

A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

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Номер записи: 57
11-04-2013 дата публикации

Epitaxial growth substrate, semiconductor device, and epitaxial growth method

Номер: US20130087807A1
Автор: Daisuke Hino, Tetsuya Ikuta, Tomohiko Shibata
Принадлежит: Dowa Electronics Materials Co Ltd

In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.

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Номер записи: 58
11-04-2013 дата публикации

Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects

Номер: US20130087831A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material. 1. A device comprising:a first semiconductor layer of a first semiconductor material;a first insulator layer disposed on the first semiconductor layer; anda semiconductor region having a first portion disposed in the first insulator layer and a second portion disposed in the first semiconductor layer, the second portion in contact with the first portion and having a width greater than a width of the first portion, and the first portion of a second semiconductor material different from the first semiconductor material.2. The device of claim 1 , wherein a sidewall of the first portion and a sidewall of the second portion are substantially vertical.3. The device of claim 1 , further comprising:a substrate of a third semiconductor material; anda second insulator layer in contact with and disposed between the substrate and the first semiconductor layer, the second portion of the semiconductor region extending through the first semiconductor layer and in contact with the second insulator layer.4. The device of claim 3 , wherein the second insulator layer is a buried oxide claim 3 , and wherein the first semiconductor material and the third semiconductor material are a same material.5. The device of claim 1 , wherein the first insulator layer is an oxide of the first semiconductor material.6. The device of claim 1 , wherein the second portion of the semiconductor region is formed of a fourth semiconductor material different from the second semiconductor material claim 1 , the second semiconductor material and fourth semiconductor material both ...

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Номер записи: 59
18-04-2013 дата публикации

GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130092951A1
Автор: HUANG CHIA-HUNG, HUANG SHIH-CHENG, TU PO-MIN, YANG SHUN-KUEI
Принадлежит: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.

A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. 1. A composite substrate for a semiconductor to grow thereon comprising:a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein, the second surface being configured for growth of the semiconductor thereon; anda filler filled into the plurality of grooves on the first surface of the silicon substrate, a thermal expansion coefficient of the filler being bigger than that of the silicon substrate.2. The composite substrate as claimed in claim 1 , wherein the plurality of grooves are uniformly arranged in the first surface.3. The composite substrate as claimed in claim 1 , wherein the plurality of grooves have a same depth.4. The composite substrate as claimed in claim 1 , wherein the depth of the grooves is in a range from one third of a thickness of the silicon substrate to a half of the thickness of the silicon substrate.5. The composite substrate as claimed in claim 1 , wherein the filler is selected from the group consisting of AlO claim 1 , SiC claim 1 , AlN claim 1 , InN claim 1 , MgN claim 1 , ZnO claim 1 , GaAs claim 1 , GaP and Ge.6. A gallium nitride-based semiconductor device comprising: a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein; and', 'a filler filled into ...

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Номер записи: 60
18-04-2013 дата публикации

EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE

Номер: US20130092953A1
Автор: ICHIMURA Mikiya, MAEHARA Sota, MIYOSHI Makoto, SUMIYA Shigeaki, TANAKA Mitsuhiro
Принадлежит: NGK Insulators, Ltd.

Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer. 1. An epitaxial substrate in which a group of group-III nitride layers are formed on a base substrate made of (111)-oriented single crystal silicon such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:a buffer layer formed of a plurality of lamination units being continuously laminated; anda crystal layer formed on said buffer layer, a composition modulation layer formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein;', 'a termination layer formed on an uppermost portion of said composition modulation layer, said termination layer acting to maintain said compressive strain existing in said composition modulation layer; and', 'a strain reinforcing layer formed on said termination layer, said strain reinforcing layer acting to enhance said compressive strain existing in said composition modulation layer., 'said lamination unit ...

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Номер записи: 61
18-04-2013 дата публикации

NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS

Номер: US20130092958A1
Автор: Chen Hongwei, Chen Jing, YUAN Li, Zhou Chunhua
Принадлежит: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. 1. A tunnel junction field-effect transistor (TJ-FET) having prospective locations for a source , a gate , and a drain , the TJ-FET comprising:a substrate comprising a buffer layer deposited on the substrate and a bather layer deposited on the buffer layer, the buffer layer and the barrier layer forming a heterojunction at an interface of the buffer layer and the barrier layer; anda metal region adjacent to the buffer layer, proximate to the prospective location for the source, and spanning a portion of the heterojunction.2. The TJ-FET of claim 1 , the substrate comprising at least one of sapphire claim 1 , silicon (111) claim 1 , silicon carbide (SiC) claim 1 , aluminum nitride (AlN) claim 1 , or GaN.3. The TJ-FET of claim 1 , the buffer layer is deposited on the substrate over a nucleation layer comprised of a group III-nitride.4. The TJ-FET of claim 1 , the substrate comprises sapphire claim 1 , the buffer layer comprises undoped GaN claim 1 , and the bather layer comprises a III-nitride barrier layer.5. The TJ-FET of claim 1 , further comprising:an insulating dielectric layer deposited above the bather layer proximate to the prospective location for the gate.6. The TJ-FET of claim 5 , further comprising:the gate deposited above the insulating dielectric layer.7. The TJ-FET of claim 6 , the gate further ...

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Номер записи: 62
18-04-2013 дата публикации

Deposited Material and Method of Formation

Номер: US20130093048A1
Автор: Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

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Номер записи: 63
25-04-2013 дата публикации

FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE

Номер: US20130099245A1
Автор: ANDO Yuji, Endo Kazuomi, Inoue Takashi, Nakayama Tatsuo, Okamoto Yasuhiro, OTA Kazuki
Принадлежит: NEC Corporation

The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer a channel layer a barrier layer and a spacer layer is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer the lattice-relaxed channel layer and the barrier layer having a tensile strain, and the spacer layer are laminated on a substrate in this order. The gate insulating film is arranged on the spacer layer The gate electrode is arranged on the gate insulating film The source electrode and the drain electrode are electrically connected to the channel layer directly or via another component. 1. A field effect transistor comprising:a substrate;a buffer layer;a channel layer;a barrier layer;a spacer layer;a gate insulating film;a gate electrode;a source electrode; anda drain electrode, wherein{'sub': x', '1-x, 'the buffer layer is formed of lattice-relaxed AlGaN (0≦x<1),'}{'sub': x', '1-x, 'the channel layer is formed of AlGaN (0≦x<1) with the same composition as the buffer layer,'}{'sub': z', '1-z, 'the barrier layer is formed of AlGaN (x Подробнее

Номер записи: 64
25-04-2013 дата публикации

SUBSTRATE FOR EPITAXIAL GROWTH

Номер: US20130099246A1
Автор: Czernecki Robert, Leszczynski Michal, Perlin Piotr, Sarzynski Marcin, Suski Tadeusz
Принадлежит:

A surface of the substrate consists in plurality of neighbouring stripe shaped flat surfaces of a width from 1 to 2000 μm. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to the crystallographic plane of gallium nitride crystal defined by Miller-Bravais indices (0001), (11-22) or (11-20). Disorientation angle of each of the flat surfaces is between 0 and 3 degree and is different for each pair of neighbouring flat surfaces. Substrate according to the invention allows epitaxial growth of a layered AlInGaN structure by MOCVD or MBE method which permits for realization of a non-absorbing mirrors laser diode emitting a light of the wavelength from 380 to 550 nm and a laser diodes array which may emit simultaneously light of various wavelengths in the range of 380 to 550 nm. 1. A substrate for epitaxial growth made of gallium nitride crystal , and having epi-ready growth surface , characterized in that the growth surface consists of set of neighbouring flat surfaces in form of stripes of a width from 1 to 2000 μm , longer edges of the stripes are parallel on to another , planes of the stripes are disoriented relatively to the crystallographic plane defined by Miller-Bravais indices (0001) , (10-10) , (11-22) or (11-20) and disorientation angle of each of the flat surfaces is from 0 to 3 degree and it is different for each of two neighbouring surfaces.2. The substrate according to claim 1 , characterized in that all the flat surfaces are disoriented relatively to the crystallographic plane defined by the Miller-Bravais indices (0001).3. The substrate according to claim 2 , characterized in that the longer edges of all the flat surfaces are parallel to a given crystallographic direction of gallium nitride crystal while the flat surfaces are delimited by said longer edges and form over the whole crystal an array of repeating sequences.4. The substrate according to claim 3 , characterized in that the ...

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Номер записи: 65
25-04-2013 дата публикации

SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE

Номер: US20130099247A1
Автор: Lu Bin, Matioli Elison de Nazareth, Palacios Tomas Apostol
Принадлежит: Massachusetts Institute of Technology

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. 1. A field effect transistor , comprising:a source region;a drain region;a semiconductor region between the source region and the drain region, the semiconductor region having trenches extending along a direction that extends between the source region and the drain region;a conductive electrode having conductive regions formed in the trenches, the conductive electrode extending no more than a portion of a distance between the source region and the drain region; andan insulating region between the semiconductor region and the conductive electrode, the insulating region extending at least partially across an interface between the semiconductor region and the conductive electrode.2. The field effect transistor of claim 1 , wherein the first semiconductor region includes a III-N semiconductor material.3. The field effect transistor of claim 2 , wherein the III-N semiconductor material includes GaN.4. The field effect transistor of claim 1 , wherein the semiconductor region is a first semiconductor region claim 1 , and the field effect transistor further comprises a second semiconductor region between the first semiconductor region and the insulating region and/or conductive electrode.5. The field effect transistor of claim 4 , wherein the first semiconductor region includes a first III-N semiconductor material and the second semiconductor region includes a second III-N semiconductor material claim 4 , and wherein the first III-N semiconductor material has a different bandgap from that of the ...

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Номер записи: 66
25-04-2013 дата публикации

Group iii-nitride metal-insulator-semiconductor heterostructure field-effect transistors

Номер: US20130099284A1
Автор: Hua-Quen Tserng, Paul Saunier
Принадлежит: Triquint Semiconductor Inc

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.

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Номер записи: 67
25-04-2013 дата публикации

Gan-on-si switch devices

Номер: US20130099324A1
Автор: Jenn Hwa Huang, Weixiao Huang
Принадлежит: Individual

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

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Номер записи: 68
02-05-2013 дата публикации

FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE

Номер: US20130105811A1
Автор: ANDO Yuji, Endo Kazuomi, Inoue Takashi, Nakayama Tatsuo, Okamoto Yasuhiro, OTA Kazuki
Принадлежит: NEC Corporation

The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer , a channel layer , a barrier layer , and a spacer layer is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer , the channel layer having a compressive strain, and the barrier layer having a tensile strain, and the spacer layer having a compressive strain are laminated on a substrate in this order. The gate insulating film is arranged on the spacer layer . The gate electrode is arranged on the gate insulating film . The source electrode and the drain electrode are electrically connected to the channel layer directly or via another component. 1. A field effect transistor comprising:a substrate;a buffer layer;a channel layer;a barrier layer;a spacer layer;a gate insulating film;a gate electrode;a source electrode; anda drain electrode, wherein{'sub': x', '1-x, 'the buffer layer is formed of lattice-relaxed AlGaN (0 Подробнее

Номер записи: 69
02-05-2013 дата публикации

Semiconductor device

Номер: US20130105812A1
Автор: Akihisa Terano, Kazuhiro Mochizuki, Ryuta Tsuchiya, Takashi Ishigaki
Принадлежит: HITACHI LTD

A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

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Номер записи: 70
02-05-2013 дата публикации

Active Area Shaping for III-Nitride Devices

Номер: US20130105814A1
Автор: Bridger Paul, Briere Michael A., Cao Jianjun
Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. 120-. (canceled)21. A III-nitride semiconductor device comprising:a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body; 'a gate well having a first mouth defined in said first insulation body, and a second mouth defined in said second insulation body, said second mouth being wider than said first mouth;', 'a first insulation body situated over said second III-nitride body, and a second insulation body situated over said first insulation body;'}a gate arrangement disposed at least partially within said gate well, said gate arrangement including a gate dielectric formed along said first mouth and said second mouth in said gate well, and a gate electrode over said gate dielectric, said gate arrangement filling said gate well.22. The III-nitride semiconductor device of claim 21 , further comprising a drain electrode and a source electrode on respective sides of said gate arrangement.23. The III-nitride semiconductor device of claim 21 , wherein said first insulation body comprises silicon nitride.24. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises a nitride dielectric.25. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises silicon nitride.26. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises aluminum nitride.27. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises titanium nitride.28. The III-nitride semiconductor device of claim 21 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.29. A method of fabricating a III-nitride semiconductor device ...

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Номер записи: 71
02-05-2013 дата публикации

DIODE

Номер: US20130105815A1
Автор: SHIBATA Daisuke
Принадлежит: Panasonic Corporation

A diode includes: a semiconductor layer stack; cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; and a protection film covering a region of an upper surface of the semiconductor layer stack. The semiconductor layer stack includes a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, and has a channel. The anode electrode includes: a p-type third nitride semiconductor layer formed on the semiconductor layer stack; a first metal layer being in ohmic contact with the third nitride semiconductor layer; and a second metal layer being in contact with the first metal layer, and being in ohmic contact with the channel. 1. A diode comprising:a semiconductor layer stack formed on a principal surface of a substrate, including a first nitride semiconductor layer, and a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer, and having a channel through which electrons travel in a direction parallel to the principal surface of the substrate;cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; anda protection film covering a region of an upper surface of the semiconductor layer stack between the cathode and anode electrodes, wherein a p-type third nitride semiconductor layer formed on the semiconductor layer stack;', 'a first metal layer formed on the third nitride semiconductor layer, and being in ohmic contact with the third nitride semiconductor layer; and', 'a second metal layer being in contact with the first metal layer, being opposite to the cathode electrode with respect to the third nitride semiconductor layer, and being in ohmic contact with the channel., 'the anode electrode includes2. The diode of claim 1 , whereinthe first nitride semiconductor layer ...

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Номер записи: 72
02-05-2013 дата публикации

PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER

Номер: US20130105858A1
Автор: Fujiwara Shinsuke, Miyanaga Michimasa, Nakahata Hideaki, Satoh Issei
Принадлежит: Sumitomo Electric Industries, Ltd.

SiCAlNcrystals in a mixed crystal state are formed. A method for manufacturing an easily processable SiCAlNsubstrate, a method for manufacturing an epitaxial wafer, a SiCAlNsubstrate, and an epitaxial wafer are provided. 13-. (canceled)4. A SiCAlNsubstrate comprising a SiCAlNlayer (0 Подробнее

Номер записи: 73
02-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130105859A1
Автор: Li Chunlong, Wang Guilei, Zhao Chao
Принадлежит:

The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability. 1. A semiconductor device , comprising: a substrate , an insulating isolation layer formed on the substrate , a first active region layer and a second active region layer formed in the insulating isolation layer , characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate.2. The semiconductor device according to claim 1 , wherein the hole mobility of the first active region layer is higher than that of the substrate claim 1 , and the electron mobility of the second active region layer is higher than that of the substrate.3. The semiconductor device according to claim 2 , wherein the substrate is formed of silicon claim 2 , the first active region layer is formed of Ge claim 2 , and the second active region layer is formed of InSb.4. The semiconductor device according to claim 3 , wherein a buffer layer formed of GaAs or GaN exists between the second active region layer and the substrate.5. The ...

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Номер записи: 74
09-05-2013 дата публикации

Gallium Nitride Semiconductor Devices and Method Making Thereof

Номер: US20130112986A1
Автор: Chen-Ju YU, Chih-Wen Hsiung, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.

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Номер записи: 75
09-05-2013 дата публикации

Gallium Nitride Devices with Compositionally-Graded Transition Layer

Номер: US20130112990A1
Автор: Gehrke Thomas, JR. T. Warren, Linthicum Kevin J., Piner Edwin L., Weeks
Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. 115-. (canceled)1635-. (canceled)36. A semiconductor device comprising:a transition layer;a III-nitride layer over said transition layer;wherein a composition of said transition layer at a top surface thereof substantially matches a composition of said III-nitride layer at a bottom surface thereof.37. The semiconductor device of claim 36 , wherein said transition layer is situated over a substrate.38. The semiconductor device of claim 37 , wherein said substrate comprises silicon.39. The semiconductor device of claim 37 , wherein said substrate consists of only silicon.40. The semiconductor device of claim 36 , wherein said III-nitride layer comprises gallium nitride.41. The semiconductor device of claim 36 , wherein said III-nitride layer consists of only gallium nitride.42. The semiconductor device of claim 36 , wherein said composition is graded continuously across said transition layer.43. The semiconductor device of claim 36 , wherein said transition layer comprises an alloy of gallium nitride selected from the group consisting of AlInGaN claim 36 , InGaN claim 36 , and AlGaN.44. The semiconductor device of claim 40 , ...

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Номер записи: 76
09-05-2013 дата публикации

SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130112995A1
Автор: Abbondanza Giuseppe
Принадлежит: STMICROELECTRONICS S.R.L.

An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon. 18-. (canceled)9. A semiconductor wafer , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate; anda layer of monocrystalline silicon disposed over the layer of the material.10. The semiconductor wafer of wherein at least one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon includes a dopant.11. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon is bowed.12. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon has a bow in a range of approximately 20-30 μm.13. The semiconductor wafer of wherein the layer of the material has a thickness in a range of approximately 2-6 μm.14. The semiconductor wafer of wherein the material includes silicon carbide.15. The semiconductor wafer of wherein the material includes monocrystalline silicon carbide.16. The semiconductor wafer of wherein the material includes 3C silicon carbide.17. The semiconductor wafer of wherein the material includes gallium nitride.18. The semiconductor wafer of wherein the layer of monocrystalline silicon has a thickness in a range of approximately 1-3 μm.19. An integrated circuit claim 9 , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate;a layer of monocrystalline silicon disposed over the layer of the material; anda device ...

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Номер записи: 77
09-05-2013 дата публикации

FIELD EFFECT TRANSISTOR

Номер: US20130113018A1
Автор: ISHIDA Masahiro, SHIBATA Daisuke, TAMURA Satoshi, TANAKA Kenichiro, WAKITA Naohide
Принадлежит: Panasonic Corporation

A first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10cm, and located in a region under an edge of a gate electrode closer to a drain electrode, a thickness d of the low carbon concentration region satisfies 1. A field effect transistor , comprising:a substrate;a first group III nitride semiconductor layer formed on the substrate;a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer, and having a band gap wider than that of the first group III nitride semiconductor layer;a source electrode and a drain electrode formed on the second group III nitride semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode; anda field plate formed on the second group III nitride semiconductor layer to be connected to the gate electrode or the source electrode, and to cover an edge of the gate electrode closer to the drain electrode, wherein{'sup': 17', '−3, 'the first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10cm, and located in at least a region under the edge of the gate electrode closer to the drain electrode,'}{'b': '2', 'claim-text': {'br': None, 'i': V', '·d', 'd', 'V', '·d, 'sub': m', 'm, '/(1101)≦2 Подробнее

Номер записи: 78
16-05-2013 дата публикации

NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACUTRING THE SAME

Номер: US20130119397A1
Автор: Eum Youngshin, Jang Taehoon
Принадлежит:

Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode. 1. A nitride-based heterojunction semiconductor device comprising:a first drain electrode;a conductive semiconductor layer comprising a nitride-based semiconductor disposed on the first drain electrode;a channel layer disposed on the conductive semiconductor layer;a barrier layer disposed on the channel layer;a source electrode and a second drain electrode spaced from each other on the barrier layer; anda gate electrode disposed between the source electrode and the second drain electrode.2. The nitride-based heterojunction semiconductor device according to claim 1 , further comprising:a current barrier layer disposed between the conductive semiconductor layer and the channel layer,wherein the current barrier layer has an opening at least at the side of the second drain electrode.3. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer is disposed at least at a lower side of the gate electrode.4. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer extends from a lower side of the source electrode to the lower side of the gate electrode.5. The nitride-based heterojunction semiconductor device according to claim 1 , wherein the current barrier layer comprises high-resistance gallium nitride.6. The nitride- ...

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Номер записи: 79
16-05-2013 дата публикации

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20130119398A1
Автор: KATO Ryou, OYA Mitsuaki, Yamada Atsushi, YOKOGAWA Toshiya
Принадлежит: Panasonic Corporation

A nitride-based semiconductor light-emitting device includes a GaN substrate , of which the principal surface is an m-plane , a semiconductor multilayer structure that has been formed on the m-plane of the GaN-based substrate , and an electrode arranged on the semiconductor multilayer structure . The electrode includes an Mg layer , which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 1. A nitride-based semiconductor device comprising:a nitride-based semiconductor multilayer structure including a p-type semiconductor region, a surface of the p-type semiconductor region being an m-plane; andan electrode that is arranged on the p-type semiconductor region; wherein{'sub': x', 'y', 'z, 'the p-type semiconductor region is made of an AlInGaN semiconductor (where x+y+z=1, x≧0, y≧0, z>0);'}the electrode comprises a Mg layer, a metal alloy layer, and a metal layer;the Mg layer is in contact with the p-type semiconductor region;the Mg layer consists of magnesium, gallium, and nitride;the Mg layer is covered with the metal alloy layer;the Mg layer is made up of islands of Mg portions that are present on a surface of the p-type semiconductor region;the metal layer is made of at least one metal that would make an alloy with Mg less easily than Au;the metal alloy layer consists of magnesium and the same metal as the metal of the metal layer; anda concentration of gallium included in the Mg layer is greater than a concentration of nitride included in the Mg layer.2. The nitride-based semiconductor device according to claim 1 , whereinthe metal alloy layer is made up of islands of Mg-alloy portions each covering at least one of the island of Mg portions.3. The nitride-based semiconductor device according to claim 1 , whereina portion of the metal alloy layer is in contact with the p-type semiconductor region.4. The nitride-based semiconductor device according to claim 1 , whereina portion of the metal layer is in contact with ...

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Номер записи: 80
16-05-2013 дата публикации

METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA

Номер: US20130119399A1
Автор: HASHIMOTO Tadao, IKARI Masanori, LETTS Edward
Принадлежит: SIXPOINT MATERIALS, INC.

The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control. 1. A certified Group III-nitride wafer comprising (i) a documentation of a value of a physical property in combination with (ii) a wafer from a first set of Group III-nitride substrates cut from an ingot formed using a seed material , wherein the value of the physical property is derived by a method comprisinga) selecting substrates from the first set of substrates to form a second set of substrates, the second set of substrates being a subset of the first set and therefore being a selection of substrates from the first set of substrates that does not include all members from the first set of substrates, the second set of substrates having at least one substrate selected from the substrates cut from a portion of the ingot located on one side of a seed used to form the ingot, and the second set of substrates having at least one substrate selected from the substrates cut from a second portion of the ingot located on the other side of the seed,b) analyzing samples taken from the substrates of the second set to assess values of a first property of each of the substrates of the second set, i) applying said correlation to substrates not in said second set of substrates to provide estimated values of said first property for said substrates; or', 'ii) comparing said correlation against a value of said property for ...

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Номер записи: 81
16-05-2013 дата публикации

SELF-ALIGNED SIDEWALL GATE GaN HEMT

Номер: US20130119400A1
Автор: Burmham Shawn D., Corrion Andrea, Hashimoto Paul B., Kazemi Hooman, Micovic Miroslav, Regan Dean C., Shinohara Keisuke, Willadsen Peter J.
Принадлежит: HRL LABORATORIES

A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length. 127-. (canceled)28. A GaN HEMT comprising:a substrate;a buffer layer comprising a first epitaxial layer on the substrate;a channel comprising a second epitaxial layer on the buffer layer;a top barrier comprising a third epitaxial layer on the second epitaxial layer;a first sidewall dielectric spacer on the third epitaxial layer;a second sidewall dielectric spacer on the third epitaxial layer;a sidewall gate on the third epitaxial layer between the first sidewall dielectric spacer and the second sidewall dielectric spacer;a first ohmic contact for a source separated from the sidewall gate by the first sidewall dielectric spacer;a source contact on the first ohmic contact;a second ohmic contact for a drain separated from the sidewall gate by the second sidewall dielectric spacer;a drain contact on the second ohmic contact;a photoresist over the first ohmic contact, the source contact, the second ohmic contact, and the drain contact such that the first and second sidewall dielectric spacers and the sidewall gate protrude from the photoresist; anda gate head in contact with the sidewall gate, wherein a width of the gate head is wider than a width of the sidewall gate.29. The GaN HEMT of wherein:the first epitaxial layer comprises AlGaN;the second epitaxial layer comprises GaN; andthe third epitaxial layer comprises AlGaN or AlN; andthe substrate comprises sapphire, SiC, silicon, or GaN.30. The GaN HEMT of :wherein the sidewall gate is refractory gate material comprising W, TiW, Ta, Mo, or TaN.31 ...

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Номер записи: 82
16-05-2013 дата публикации

DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE

Номер: US20130119404A1
Автор: Beam, Dumpka Deep C., III Edward A., III Paul, Saunier
Принадлежит: TRIQUINT SEMICONDUCTOR, INC.

Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed. 1. A method comprising: a first substrate;', 'an etch stop layer including aluminum gallium arsenide or indium gallium phosphide formed over the first substrate;', 'an inverted epitaxial structure formed over etch stop layer in a manner such that the etch stop layer is between the first substrate and the inverted epitaxial structure and such that a frontside of the inverted epitaxial structure faces the etch stop layer and a backside of the inverted epitaxial structure faces away from the etch stop layer; and', 'a bonding layer formed over the backside of the inverted epitaxial structure;, 'providing an apparatus includingafter providing the apparatus, forming a second substrate over the bonding layer such that the bonding layer is between the backside and the second substrate; andafter said forming the second substrate, removing the first substrate and the etch stop layer to expose the frontside of the inverted epitaxial structure.2. The method of claim 1 , wherein said forming the second substrate comprises forming a high thermal conductivity material over the oxide layer.3. The method of claim 2 , wherein the high thermal conductivity material comprises a material selected from polycrystalline silicon carbide claim 2 , diamond claim 2 , or aluminum nitride.4. The method of claim 1 , wherein said forming of the second substrate over the oxide layer comprises wafer bonding the second substrate to the oxide ...

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Номер записи: 83
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130119437A1
Автор: KURAOKA Yoshitaka, MIYOSHI Makoto
Принадлежит: NGK Insulators, Ltd.

A semiconductor device having small leakage current and high breakdown voltage during reverse blocking, small on-state resistance and large output current at forward conduction, short reverse recovery time at shutoff, and high peak surge current value is provided. An n-type layer is made of a group-III nitride, and a p-type layer is made of a group-IV semiconductor material having a smaller band gap than the group-III nitride. The energy level at the top of the valence band of the n-type layer is lower than the energy level at the top of the valence band of the p-type layer, so that a P-N junction semiconductor device satisfying the above requirements is obtained. Further, a combined structure of P-N junction and Schottky junction by additionally providing an anode electrode to be in Schottky contact with the n-type layer also achieves the effect of decreasing voltage at the rising edge of current resulting from the Schottky junction. 2. The semiconductor device according to claim 1 , whereinsaid second semiconductor layer is deposited on a partial region of a main surface of said first semiconductor layer to create said first junction, andsaid third electrode is formed on surfaces of said first semiconductor layer and said anode electrode to create said second junction adjacent to said first junction.3. The semiconductor device according to claim 1 , wherein{'sub': 1-x', 'x, 'said group-III nitride has a composition of AlGaN (0≦x≦1) at least in the vicinity of said first junction of said first semiconductor layer.'}4. The semiconductor device according to claim 1 , wherein{'sup': 19', '3, 'a hole density is 1×10/cmor higher at least in the vicinity of said first junction of said second semiconductor layer.'}5. The semiconductor device according to claim 1 , wherein{'sup': 20', '3, 'an acceptor density is 1×10/cmor higher at least in the vicinity of said first junction of said second semiconductor layer.'}6. The semiconductor device according to claim 5 , wherein{' ...

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Номер записи: 84
23-05-2013 дата публикации

Aluminum gallium nitride etch stop layer for gallium nitride bases devices

Номер: US20130126884A1
Автор: Andrew P. Edwards, David P. Bour, Hui Nie, Isik C. Kizilyalli, Linda Romano, Mahdan Raj, Richard J. Brown, Thomas R. Prunty
Принадлежит: ePowersoft Inc

A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

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Номер записи: 85
23-05-2013 дата публикации

Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap

Номер: US20130126889A1
Автор: Sandeep Bahl
Принадлежит: Texas Instruments Inc

An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.

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Номер записи: 86
23-05-2013 дата публикации

P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors

Номер: US20130126892A1
Автор: Foxon C. Thomas, LEVANDER ALEJANDRO X., Novikov Sergei V., Walukiewicz Wladyslaw, Yu Kin Man
Принадлежит: The Regents of the University of California

A new composition of matter is described, amorphous GaNAs:Mg, wherein 0 Подробнее

Номер записи: 87
23-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130126893A1
Автор: Tanaka Masayasu
Принадлежит: RENESAS ELECTRONICS CORPORATION

A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). 1. A semiconductor device , comprising:a semiconductor substrate that includes a nitride semiconductor layer formed from a nitride semiconductor on at least one surface side;an impurity region that is provided on the one surface side in the nitride semiconductor layer and contains a first conductivity type impurity;an amorphous region that is a part of the impurity region and is located in a surface layer of the impurity region; anda metallic layer that comes into contact with the amorphous region.2. The semiconductor device according to claim 1 ,wherein the amorphous region includes a crystal defect that is formed by ion implantation of the impurity.3. The semiconductor device according to claim 1 ,wherein the amorphous region and the metallic layer come into ohmic contact with each other.4. The semiconductor device according to claim 1 ,wherein the amorphous region includes a microcrystalline region in which a grain size is equal to or less than 10 nm.5. The semiconductor device according to claim 1 , further comprising:a source region that is provided in the nitride semiconductor layer and is a first of the impurity region;a drain region that is provided in the nitride semiconductor layer to be spaced apart from the source region in a plan view and that is a second of the impurity region;a ...

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Номер записи: 88
23-05-2013 дата публикации

Low voltage diode with reduced parasitic resistance and method for fabricating

Номер: US20130126894A1
Автор: Primit Parikh, Sten Heikman
Принадлежит: Cree Inc

A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an Al x Ga 1-x N barrier layer, and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

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Номер записи: 89
23-05-2013 дата публикации

Gallium Nitride Devices with Vias

Номер: US20130126895A1
Автор: Hanson Allen W., Johnson Jerry W., Therrien Robert J.
Принадлежит: INTERNATIONAL RECTIFIER CORPORATION

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. 127-. (canceled)2842-. (canceled)43. A transistor comprising a source electrode , a drain electrode and a gate electrode , said transistor further comprising:a substrate;a transition layer situated over said substrate;a gallium nitride layer situated over said transition layer;a via that extends through at least a portion of said substrate;a barrier layer along sidewalls of said via;an electrically conductive layer on a back surface of said substrate.44. The transistor of claim 43 , wherein said substrate comprises silicon.45. The transistor of claim 43 , wherein said electrically conductive layer comprises aluminum.46. The transistor of claim 43 , wherein said electrically conductive layer includes a first portion comprising gold and a second portion comprising aluminum.47. The transistor of further comprising a passivating layer situated over said gallium nitride layer.48. The transistor of claim 43 , wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.49. The transistor of ...

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Номер записи: 90
23-05-2013 дата публикации

III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME

Номер: US20130126896A1
Автор: Arena Chantal, Bertram Ronald, Datta Ranjan, Lindow Ed, Mahajan Subhash
Принадлежит: SOITEC

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. 1. An indium gallium nitride (InGaN) layer , comprising:a first InGaN sublayer; andat least a second InGaN sublayer disposed over the first InGaN sublayer;wherein a total thickness of the InGaN layer equals a sum of a thickness of the first InGaN sublayer and a thickness of the at least a second InGaN sublayer, the total thickness of the InGaN layer being greater than a critical thickness of the first InGaN sublayer and less than a critical thickness of the at least a second InGaN sublayer.2. The InGaN layer of claim 1 , wherein a concentration of indium in the first InGaN sublayer is at least substantially equal to a concentration of indium in the at least a second InGaN sublayer.3. The InGaN layer of claim 1 , wherein a concentration of indium in the InGaN layer is at least substantially constant across the total thickness of the InGaN layer.4. The InGaN layer of claim 1 , wherein the InGaN layer is at least substantially free of strain relaxation.5. The InGaN layer of claim 1 , wherein the InGaN layer has an indium concentration of at least about 5% and a total thickness of at least about 200 nm.6. The InGaN layer of claim 1 , wherein the InGaN layer has a concentration of indium of at least about 8% and a total thickness of at least about 150 nm.7. An indium gallium nitride (InGaN) layer claim 1 , comprising:a first InGaN sublayer having a thickness less than or equal to a critical thickness of ...

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Номер записи: 91
23-05-2013 дата публикации

DIAMOND GaN DEVICES AND ASSOCIATED METHODS

Номер: US20130126903A1
Автор: Sung Chien-Min
Принадлежит:

Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. 1. A method of making a semiconductor device , comprising:polishing a working surface of a diamond layer to a substantially flat surface;depositing a buffer layer on the working surface of the diamond layer; anddepositing a semiconductor layer on the buffer layer.2. The method of claim 1 , wherein the buffer layer c-axis is oriented perpendicular to the working surface of the diamond layer.3. The method of claim 1 , wherein the buffer layer is a member selected from the group consisting of a carbide claim 1 , an oxide claim 1 , a nitride claim 1 , and combinations thereof claim 1 , and wherein the buffer layer is domain matched with the diamond layer.4. The method of claim 1 , wherein the buffer layer is a member selected from the group consisting of TiC claim 1 , ZrC claim 1 , graphene claim 1 , AlN claim 1 , (B claim 1 ,Al)N claim 1 , TiN claim 1 , TaN claim 1 , ZnO claim 1 , NiO claim 1 , and combinations thereof.5. The method of claim 1 , wherein the substantially flat surface has an RA that is from about 1 nm to about 10 nm.6. The method of claim 1 , wherein the diamond layer is a layer of CVD diamond deposited on a silicon substrate.7. The method of claim 1 , wherein the semiconductor layer is a member selected from the group consisting of GaN claim 1 , (B claim 1 ,Al)N claim 1 , AlN claim 1 , and combinations thereof.8. The method of claim 1 , further comprising doping at least one of the diamond layer and the semiconductor layer.9. The method of claim 1 , wherein the diamond layer is ...

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Номер записи: 92
23-05-2013 дата публикации

Semiconductor Device with Multiple Space-Charge Control Electrodes

Номер: US20130127521A1
Автор: Grigory Simin, Michael Shur, Remigijus Gaska
Принадлежит: Sensor Electronic Technology Inc

A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

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Номер записи: 93
30-05-2013 дата публикации

Metallization structure for high power microelectronic devices

Номер: US20130134433A1
Автор: Henning Jason, Ward Allan
Принадлежит:

A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. 1. A semiconductor device structure comprising:a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and Group III nitrides; a first diffusion barrier layer on a surface of a portion of the semiconductor device structure selected from the group consisting of said wide-bandgap semiconductor portion, an ohmic contact, a Schottky contact, and a dielectric layer;', 'a first high electrical conductivity layer on a surface of the first diffusion barrier layer opposite the portion of the semiconductor device structure;', 'a second diffusion barrier layer on a surface of the first high electrical conductivity layer opposite the first diffusion barrier layer; and', 'a second high electrical conductivity layer on a surface of the second diffusion barrier layer opposite the first high electrical conductivity layer, wherein each of the conductivity layers has a thickness greater than 800 Angstroms;, 'an interconnect structure to said wide-bandgap semiconductor portion, said interconnect structure comprising a plurality of diffusion barrier layers alternating with a plurality of high electrical conductivity ...

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Номер записи: 94
30-05-2013 дата публикации

EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT

Номер: US20130134439A1
Автор: ICHIMURA Mikiya, MIYOSHI Makoto, Sugiyama Tomohiko, TANAKA Mitsuhiro
Принадлежит: NGK Insulators, Ltd.

Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0). 1. An epitaxial substrate for use in a semiconductor element , in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:{'sub': x1', 'y1', 'z1, 'a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0);'}{'sub': x2', 'y2, 'a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0);'}an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and{'sub': x3', 'y3', 'z3, 'a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0).'}2. The epitaxial substrate according to claim 1 , whereina band gap of said second group-III nitride is larger than a band gap of said first group-III nitride.3. The epitaxial substrate according to claim 1 , wherein{'sub': x2', 'y2, 'said second group-III nitride is InAlN (x2+y2=1, 0.14≦x2≦0.24),'}{'sub': y3', 'z3, 'said third group-III nitride is ...

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Номер записи: 95
30-05-2013 дата публикации

NITRIDE SEMICONDUCTOR DIODE

Номер: US20130134443A1
Автор: MOCHIZUKI Kazuhiro, TERANO Akihisa, TSUCHIYA Tomonobu
Принадлежит: Hitachi, Ltd.

Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. 1. A nitride semiconductor diode comprising:a substrate;a heterojunction stacked film on which a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer greater in band gap energy than the first nitride semiconductor layer are stacked;a cathode electrode ohmically connected with the side face of the stacked film; andan anode electrode,wherein the stacked film is provided with a recessed portion which reaches the depth of a heterojunction surface being the interface of the first and second nitride semiconductor layers,wherein the recessed portion is provided with an region where at least one type of impurity selected from among a group of carbon (C), iron (Fe), zinc (Zn), and magnesium (Mg) is implanted, andwherein the anode electrode contacts the region and is Schottky connected with the stacked film.2. The nitride semiconductor diode according to claim 1 , wherein the region is formed by implanting the impurity into the stacked film itself or forming a film including the impurity.3. The nitride semiconductor diode according to claim 1 , wherein the region includes C or Fe with a density of 4×10cmor more or Mg with a density of 1×10cmor more.4. The nitride semiconductor diode according to claim 1 , wherein the density of the impurity in the region is higher than that of the impurity in the stacked film of the interface between the cathode ...

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Номер записи: 96
30-05-2013 дата публикации

Formation of Devices by Epitaxial Layer Overgrowth

Номер: US20130134480A1
Автор: Bai Jie, Cheng Zhinyuan, Fiorenza James, Hydrick Jennifer M., Li Jizhong, Lochtefeld Anthony J., Park Ji-Soo
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer. 1. A semiconductor structure comprising:a substrate;a first semiconductor layer over the substrate, the first semiconductor layer comprising a first p-n junction having a first band gap;a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a second p-n junction having a second band gap, the second band gap being greater than the first band gap; anda third semiconductor layer over the second semiconductor layer, the third semiconductor layer comprising a third p-n junction having a third band gap, the third band gap being greater than the second band gap.2. The semiconductor structure of claim 1 , wherein the first semiconductor layer is approximately 2 micrometers.3. The semiconductor structure of claim 1 , wherein the first semiconductor layer comprises InGaAs claim 1 , the second semiconductor layer comprises GaAs claim 1 , and the third semiconductor layer comprises InGaP.4. The semiconductor structure of further comprising a buffer layer between the first semiconductor layer and the second ...

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Номер записи: 97
13-06-2013 дата публикации

THIN FILM SEMICONDUCTOR MATERIAL PRODUCED THROUGH REACTIVE SPUTTERING OF ZINC TARGET USING NITROGEN GASES

Номер: US20130146871A1
Автор: Ye Yan
Принадлежит:

The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility. 1. A semiconductor film comprising a ternary compound of zinc , oxygen , and nitrogen.2. The semiconductor film of claim 1 , wherein the film has a sheet resistance of between about 100 ohm/sq to about 1×10ohm/sq.3. The semiconductor film of claim 1 , wherein the film has a resistivity of between about 0.001 to about 30 ohm-cm.4. The semiconductor film of claim 1 , wherein the film has a mobility of greater than about 30 cm/V-s.5. The semiconductor film of claim 4 , wherein the film has a mobility of greater than about 90 cm/V-s6. The semiconductor film of claim 1 , wherein the film has a transmittance of up to about 80 percent.7. The semiconductor film of claim 1 , wherein the film has a graded band gap energy between about 3.1 eV and about 1.2 eV.8. The semiconductor film of claim 1 , wherein the compound comprises ZnNO.9. The semiconductor film of claim 8 , wherein the compound comprises a dopant.10. The semiconductor film of claim 9 , wherein the dopant comprises aluminum.11. The semiconductor film of claim 10 , ...

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Номер записи: 98
13-06-2013 дата публикации

Monolithic semiconductor device and method for manufacturing the same

Номер: US20130146888A1
Автор: Ki Yeol Park, Seok Yoon HONG, Woo Chul Jeon, Young Hwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein is a monolithic semiconductor device including: a substrate; a high electron mobility transistor (HEMT) structure that is a first device structure formed on the substrate; and a laterally diffused metal oxide field effect transistor (LDMOSFET) structure that is a second device structure formed to be connected with the HEMT structure on the substrate.The monolithic semiconductor device according to preferred embodiments of the present invention is a device having characteristics of a normally-off device while maintaining high current characteristics in a normally-on state, thereby improving high current and high voltage operation characteristics.

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Номер записи: 99
13-06-2013 дата публикации

Ultraviolet Reflective Contact

Номер: US20130146907A1
Автор: Dobrinsky Alexander, Gaska Remigijus, Lunev Alexander, Shatalov Maxim S., Shur Michael
Принадлежит: SENSOR ELECTRONIC TECHNOLOGY, INC.

A contact including an ohmic layer and a reflective layer located on the ohmic layer is provided. The ohmic layer is transparent to radiation having a target wavelength, while the reflective layer is at least approximately eighty percent reflective of radiation having the target wavelength. The target wavelength can be ultraviolet light, e.g., having a wavelength within a range of wavelengths between approximately 260 and approximately 360 nanometers. 1. A contact comprising:an ohmic layer, wherein the ohmic layer is transparent to radiation having a target wavelength; anda reflective layer located on the ohmic layer, wherein the reflective layer is at least approximately eighty percent reflective of radiation having the target wavelength, and wherein the target wavelength is within a range of wavelengths between approximately 260 and approximately 360 nanometers.2. The contact of claim 1 , further comprising an ohmic protective layer located between the ohmic layer and the reflective layer claim 1 , wherein the ohmic protective layer is configured to prevent diffusion of the reflective layer into the ohmic layer.3. The contact of claim 2 , wherein the ohmic protective layer comprises rhodium.4. The contact of claim 1 , further comprising a conductive layer located on the reflective layer claim 1 , wherein the conductive layer is formed of a material having a high electrical conductivity.5. The contact of claim 4 , further comprising a reflector protective layer located between the reflective layer and the conductive layer claim 4 , wherein the reflector protective layer is configured to prevent diffusion of the conductive layer into the reflective layer.6. The contact of claim 4 , further comprising a dielectric adhesion layer located on the conductive layer claim 4 , wherein the dielectric adhesion layer is configured to promote adhesion of an insulating dielectric film to the contact.7. The contact of claim 1 , wherein the ohmic layer is formed of at least two ...

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Номер записи: 100