Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter

The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.

Calibration Circuit and Method for Calibrating Capacitive Compensation in Digital-to-Analog Converters

A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Minimum differential non-linearity trim DAC

A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.

Time-interleaved analog-to-digital converter bandwidth matching

A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Methods and systems are provided for calibrating nonlinearity correction during analog-to-digital conversions on received analog signals. Correction-parameters may be estimated, such as to reduce, when applied to total spectral content, distortion resulting from the nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity correction calibration may be performed during reception and handling of the analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. 120-. (canceled)21. A method , comprising: determining when nonlinearity is exhibited during analog-to-digital conversion of received analog signals;', 'when nonlinearity is exhibited, generating correction estimation parameters associated with the received analog signals, wherein applying the correction estimation parameters to total spectral content reduces distortion in originally-unoccupied spectral regions, the distortion resulting from the nonlinearity; and', 'correcting based on the correction estimation parameters, digital signals generated based on sampling of the received analog signals., 'in a device that performs analog-to-digital conversion22. The method according to claim 21 , comprising calibrating nonlinearity correction in the device during reception and handling of the analog signals.23. The method according to claim 21 , comprising generating the correction estimation parameters based on signals in particular spectral regions.24. The method according to claim 23 , wherein the particular spectral regions correspond ...

Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same

A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. 120-. (canceled)21. A method for wireless communication , the method comprising:receiving an analog signal on a chip;converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); andreducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal.22. The method according to claim 21 , comprising estimating said complex coupling coefficients utilizing a decorrelation algorithm running in timing offset estimation and compensation circuitry.23. The method according to claim 21 , comprising approximating an amplitude of a blocker signal as linear within a desired frequency bandwidth.24. The method according to claim 21 , comprising performing a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said chip.25. The method ...

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Nonlinearity correction in a device that performs analog-to-digital conversion on received analog signals, may be calibrated by generating correction-parameters estimation which when applied to the total spectral content reduces distortion resulting from said nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity calibration may be performed during reception and handling of said analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. 1. A method , comprising:in a device that performs analog-to-digital conversion, calibrating nonlinearity associated with analog-to-digital conversion of received analog signals, said calibrating comprises generating correction estimation parameters, wherein applying said correction estimation parameters to total spectral content reduces distortion in originally-unoccupied spectral regions, said distortion resulting from said nonlinearity; andcorrecting based on said correction estimation parameters, digital signals generated based on sampling of said received analog signals.2. The method according to claim 1 , comprising performing said calibration during reception and handling of said analog signals.3. The method according to claim 1 , comprising generating said correction estimation parameters based on signals in particular spectral regions.4. The method according to claim 3 , wherein said particular spectral regions correspond to said originally-unoccupied spectral regions.5. The method according to claim 3 , comprising injecting specific signals ...

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION

In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes. 1. A system comprising: one or more conversion circuits, wherein each conversion circuit is configured to handle one or more bits in an input to the DAC; and', detect one or more types of errors that occur during operation of the DAC;', 'determine one or more adjustments for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors;', 'apply at least one of the one or more adjustments, wherein the one or more control circuits are configured to apply at least one of the one or more adjustments to only a subset of the one or more conversion circuits., 'one or more control circuits configured to apply], 'a digital-to-analog converter (DAC) that is configured to apply digital-to-analog conversions, the DAC comprising2. The system of claim 1 , wherein the DAC is configured to switch among a plurality of modes; andthe one or more control circuits are configured to apply adjustments only in one or more of the plurality of modes but not in all of the plurality of modes.3. The system of claim 2 , wherein the plurality of modes comprises a normal mode and a correction mode; andthe one or ...

APPARATUS AND METHOD FOR SINGLE TEMPERATURE SUBTHRESHOLD FACTOR TRIMMING FOR HYBRID THERMAL SENSOR

An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code. 1. An apparatus comprising:a first circuitry to compare a proportional-to-absolute-temperature (PTAT) voltage and a complementary-to-absolute-temperature (CTAT) voltage;an analog-to-digital converter (ADC) coupled to the first circuitry, wherein the ADC is to provide a digital code representing a temperature;a second circuitry to generate temperature independent first and second voltages;a first switch coupled to a node providing the CTAT voltage; anda second switch coupled to the second circuity and to the node providing the CTAT voltage, wherein the second switch is to provide one of the first or second voltages.2. The apparatus of claim 1 , wherein the PTAT voltage is derived from one or more n-type devices or p-type devices in weak inversion.3. The apparatus of claim 1 , wherein the CTAT voltage is generated by a p-n junction diode.4. The apparatus of comprises logic to trim the digital code for subthreshold factor variation claim 1 , wherein the output of the logic is a trimmed digital code.5. The apparatus of comprises a finite state machine claim 1 , wherein the first and second switches are controllable by the finite state machine.6. The apparatus of claim 1 , wherein the ADC is to implement a successive approximation algorithm.7. The apparatus of claim 1 , wherein the first circuity is part of a thermal sensor claim 1 , and wherein the secondary circuitry is part of a built-in-self-test circuitry.8. The apparatus of comprises:a first memory to store the digital code during a first temperature;a second memory to store the digital ...

Method and apparatus to reduce effect of dielectric absorption in sar adc

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs). 1. A method for managing dynamic element matching in a digital-to-analog converter (DAC) , during digital-to-analog conversion , comprising:determining one or more parameters associated with said DAC and/or a signal being converted via said DAC;assessing based on the one or more parameters, one or more conditions affecting the dynamic element matching; anddynamically adjusting dynamic element matching based on said assessing of said one or more conditions.2. The method of claim 1 , wherein the adjusting comprises switching the dynamic element matching on or off.3. The method of claim 2 , wherein said switching comprises switching the dynamic element matching in whole and switching only one or more individual dynamic element matching elements.4. The method of claim 1 , wherein the one or more conditions comprise signal backoff; and further comprising:determining that adjustments to the dynamic element matching are needed based on comparing of amount of signal backoff to one or more pre-set thresholds.5. The method of claim 4 , wherein the one or more parameters comprise measured power for said signal; and further comprising:assessing said amount of backing off based on said measured power for said signal.6. The method of claim 5 , comprising determining said measured power for said signal ...

Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) Timing Calibration

An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL DEVICE

To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage. 1. A semiconductor device , comprising:a first node coupled to a first voltage through a reference resistance;a plurality of second nodes coupled to a second voltage through measurement resistances;a plurality of selector switches for selecting the second node to be coupled to the first node;a correction circuit that generates a voltage obtained by adding the second voltage to a voltage between the second node selected by the selector switches and the first node as a correction voltage; anda double integral analog-digital conversion circuit that finds a first integral time elapsed when a difference voltage of the correction voltage with respect to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when a difference voltage of the first voltage with respect to the voltage of the first node is integrated to the correction voltage.2. The semiconductor device according to claim 1 ,wherein the double integral analog-digital conversion circuit has:an integrating circuit that performs a first integral operation of integrating the difference ...

Analog-To-Digital Converter System

It is provided a provided a time-interleaved analog-to-digital converter (ADC) system comprising an input port configured to receive an analog signal, an ADC-array comprising M, M≥2, ADCs arranged in parallel. Each ADC is configured to receive and to convert a portion of the analog signal into a digital signal at a sample rate f. The ADC-system further comprises a reference ADC configured to receive and to convert the analog signal into a digital reference signal at an average sampling rate flower than f. Each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and the ADC to select for each reference ADC sampling instant is randomized over time. The ADC-system also comprises a correction module configured to adjust the digital signal outputs of the ADC-array into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the corresponding selected ADCs. It is also provided a method for time-interleaved analog-to-digital conversion. 123-. (canceled)24. A time-interleaved analog-to-digital converter (ADC) system , comprising:an input port configured to receive an analog signal;{'sub': 's', 'an ADC-array comprising M ADCs arranged in parallel, each ADC being configured to receive and to convert a portion of the analog signal into a digital signal at a sample rate f, where M≥2;'}{'sub': ref', 's, 'a reference ADC configured to receive and to convert the analog signal into a digital reference signal at an average sampling rate flower than f, wherein each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and wherein the ADC to select for each reference ADC sampling instant is randomized over time; and'}a correction module configured to adjust the digital signal outputs of the ADC-array into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the ...

GAIN CALIBRATION DEVICE AND METHOD FOR RESIDUE AMPILIFIER OF PIPELINE ANALOG TO DIGITAL CONVERTER

A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range. 1. A gain calibration device for an analog to digital converter (ADC) residual amplifier , the gain calibration device comprising:a digital to analog converter (DAC) configured to convert a digital signal to an analog signal, wherein the DAC includes a calibration module used in a gain calibration of the ADC residue amplifier; anda flash analog to digital converter (ADC) configured to generate the digital signal and including a plurality of comparators,wherein a number of the plurality of comparators is equal to a number of output bits of the flash ADC, and wherein the plurality of comparators are uneven comparators providing a plurality of threshold voltages that are unevenly distributed in a input range.2. The gain calibration device according to claim 1 , wherein the flash ADC is configured to generate the digital signal by digitally converting a sampling signal of an input signal.3. The gain calibration device according to claim 2 , further including a part of a stage of a pipeline analog-digital converter (ADC) claim 2 , wherein the pipeline ADC includes the ADC residue amplifier configured to amplify a residue signal.4. The gain calibration device according to claim 3 , wherein the residue signal is generated by subtracting the analog signal from the sampling signal of the input signal.5. The gain calibration device according to claim 2 , wherein the input range includes a zero point voltage of the input signal.6. ...

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Methods and systems are provided for reconstructing bands in received signals. A first band in a received multiband signal may be reconstructed, during processing of the multiband signal, when the first band is self-aliased during sampling of a second band. The reconstructing may comprise generating a plurality of components corresponding to the first band, based on the sampling of the second band, and combining the plurality of components to reconstruct the first band. Generating a first component may comprise applying high-pass filtering and/or decimation to an input corresponding to an output of the sampling of the second band. Generating a second component may comprise applying low-pass filtering and/or re-sampling to an input corresponding to an output of the sampling of the second band. An adjustment may be applied, when generating the second component, based on sampling of the first band. The adjustment may comprise a subtraction from sampling output. 120-. (canceled)21. A system , comprising: generate a plurality of components corresponding to the first band based on the sampling of the second band; and', 'combine the plurality of components to reconstruct the first band., 'one or more circuits for use in a signal receiver to reconstruct a first band in a received multiband signal, wherein the first band is self-aliased during sampling of a second band, the one or more circuits being operable to22. The system of claim 21 , wherein the one or more circuits are operable to apply claim 21 , when generating a first one of the plurality of components claim 21 , high-pass filtering to an input corresponding to an output of the sampling of the second band.23. The system of claim 21 , wherein the one or more circuits are operable to apply claim 21 , when generating a first one of the plurality of components claim 21 , decimation to an input corresponding to an output of the sampling of the second band.24. The system of claim 21 , wherein the one or more circuits are ...

Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) Timing Calibration

An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

EFFICIENT CALIBRATION OF ERRORS IN MULTI-STAGE ANALOG-TO-DIGITAL CONVERTER

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC. 1. A multi-stage analog-to-digital converter with digitally assisted calibration , the multi-stage analog-to-digital converter comprising:analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal; a dedicated memory element for storing correction terms;', 'a multiplexer selecting one of the correction terms in the dedicated memory element based on the respective output code; and', 'circuitry for correcting an error of the multi-stage analog-to-digital converter based on the selected correction term; and, 'wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprisesdigital circuitry for computing the correction terms in the dedicated memory elements, wherein computing correction terms used for a given analog-to-digital converter stage takes into account an error term from one or more earlier analog-to-digital converter stages.2. The multi-stage analog-to-digital converter of claim 1 , wherein the circuitry for correcting ...

Circuit for Stabilizing a Digital-to-Analog Converter Reference Voltage

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

MULTICORE SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER

The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier. 1. An analog to digital converter (ADC) comprising:a successive approximation register (SAR) unit including one or more capacitive networks to take a sample of an analog signal and one or more comparators to approximate digital values based on the analog signal sample via successive comparison;a preamplifier coupled to the SAR unit, the preamplifier to amplify the analog signal for application to the capacitive networks for sampling; anda rough buffer coupled to the SAR unit, the rough buffer to pre-charge the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.2. The ADC of claim 1 , wherein the SAR unit includes a plurality of SAR cores claim 1 , each including at least one of the capacitive networks and at least one of the comparators claim 1 , and wherein the SAR cores are configured to operate in parallel by sampling the analog signal at different points in an SAR unit duty cycle.3. The ADC of claim 2 , wherein the SAR cores share access to the rough buffer.4. The ADC of claim 2 , wherein the SAR cores share access to the preamplifier.5. The ADC of claim 2 , further comprising a SAR controller coupled to the SAR unit claim 2 , the SAR controller to interleave digital values from the SAR cores into a digital signal ...

Signal path linearization

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Methods and systems are provided for handling nonlinearity corrections during analog-to-digital conversions. A system for handling nonlinearity corrections may include a modem configured to receive a communication signal and generate a frequency spectrum of the communication signal, and a digital signal processor (DSP) configured to analyze the frequency spectrum of the communication signal to determine one or more characteristics of the communication signal, which may occur due to a nonlinear device that operates on the communication signal. The DSP may generate a corrected digital signal by applying a compensation signal to a distorted digital signal generated as a result of application of analog-to-digital conversion to the communication signal. The DSP may generate the compensation signal based on nonlinearity estimation and a spectral analysis of the corrected digital signal. 120-. (canceled)21. A system , comprising:a modem configured to receive a communication signal and generate a frequency spectrum of the communication signal; anda digital signal processor (DSP) configured to analyze the frequency spectrum of the communication signal to determine one or more characteristics of the communication signal,wherein the one or more characteristics of the communication signal occur due to a nonlinear device that operates on the communication signal.22. The system according to claim 21 , wherein the modem comprises an analog-to-digital converter (ADC) that generates a distorted digital signal by sampling the communication signal.23. The system according to claim 22 , wherein the DSP generates a corrected digital signal by applying a compensation signal to the distorted digital signal.24. The system according to claim 23 , wherein the DSP generates the compensation signal according to a nonlinearity estimation and a spectral analysis of the corrected digital signal.25. The system according to claim 23 , wherein the compensation signal is based on a particular ...

GAIN CALIBRATION FOR ADC WITH EXTERNAL REFERENCE

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation. 130-. (canceled)31. An analog-to-digital converter (ADC) , comprising:a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;a digital-to-analog converter (DAC) capacitance coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node; anda calibration capacitance coupled at the first node, the calibration capacitance adjustable to minimize a difference between a capacitance value of the SH capacitance and a capacitance value comprising a sum of the calibration capacitance and the DAC capacitance.32. The ADC of claim 31 , further comprising a comparator coupled at the first node and a successive approximation register (SAR) coupled to an output of the comparator claim 31 , an output of the SAR comprising a digital output of the ADC.33. The ADC of claim 32 , wherein the DAC capacitance comprises an array of multiple switched capacitances claim 32 , the ADC further comprising a calibration logic module arranged to receive the output of the SAR and to adjust the calibration capacitance based on how many of the multiple capacitances of the DAC capacitance are switched to the reference voltage.34. The ADC of claim 31 , wherein the calibration capacitance is arranged to track the DAC capacitance and to reduce or eliminate a deviation between a capacitance value of the DAC capacitance and a capacitance value of the SH capacitance.35. The ADC of claim 31 , wherein the ADC does not implement a buffer.36. The ADC of claim 31 , wherein the calibration capacitance is arranged ...

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC. 1. A method comprising:determining one or more parameters associated with a digital-to-analog converter (DAC) and/or a signal being converted via said DAC;assessing based on said one or more parameters, one or more conditions affecting dynamic element matching in said DAC;determining based on said assessing of said one or more conditions, one or more adjustments; anddynamically applying said one or more adjustments to said dynamic element matching in said DAC.2. The method of claim 1 , wherein said one or more adjustments comprise switching said dynamic element matching on or off.3. The method of claim 2 , comprising switching said dynamic element matching on or off in whole.4. The method of claim 2 , comprising comprises switching on or off only one or more individual dynamic element matching elements.5. The method of claim 1 , comprising determining that said one or more adjustments to said dynamic element matching are needed based on one or more pre-set thresholds.6. The method of claim 1 , wherein said one or more parameters comprise measured power for said signal claim 1 , and further comprising:determining that said one or more adjustments to said dynamic element matching are needed based on said measured power for said signal.7. The method of claim 6 , comprising determining said measured power for said signal based on received signal strength indicator (RSSI) measurements.8. A system comprising:a digital-to-analog converter (DAC) that is operable to apply digital-to-analog conversions, ...

DATA CONVERTERS FOR MITIGATING TIME-INTERLEAVED ARTIFACTS

A data converter includes multiple subunits to convert an input such as a radio frequency (RF) signal. The subunits are selected to sample the input in an order that varies over time. Two or more subunits are enabled at the same time. The selected subunits are configured to convert the input from an analog signal to a digital signal or vice versa. 1. A data converter comprising:a plurality of subunits configured to convert an input; anda scrambler configured to select the plurality of subunits to sample the input in an order that varies over time, at least two subunits of the plurality of subunits enabled at a same time.2. The data converter of claim 1 , in which an idle subunit is enabled for calibration.3. The data converter of claim 1 , in which a selection order is determined according to a pseudorandom number generator.4. The data converter of claim 3 , in which the at least two subunits sample at least one of the input or a calibration signal during the same time interval.5. The data converter of claim 1 , further comprising a plurality of multi-phase clock generators coupled to each of the subunits separately and having variable selectable clock phases.6. The data converter of claim 1 , in which the input comprises a radio frequency signal and a selected subunit is configured to convert the input from an analog signal to a digital signal.7. The data converter of claim 1 , in which the input comprises a radio frequency signal claim 1 , and a selected subunit is configured to convert the input from a digital signal to an analog signal.8. A method for data conversion claim 1 , comprising:simultaneously selecting a plurality of subunits to convert an input signal, the plurality of subunits selected, by a scrambler, according to a variable hopping frequency, one of the plurality of subunits enabled for calibration.9. The method of claim 8 , in which the input signal comprises a radio frequency signal and in which the radio frequency signal is converted from an ...

SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL DEVICE

To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage. 1. An analog-to-digital conversion circuit configured to output a digital value of an input voltage by comparing the input voltage with a reference voltage , the analog-to-digital conversion circuit comprising:an internal terminal configured to receive the input voltage;a reference terminal configured to receive the reference voltage; andan integrator circuit configured to integrate a voltage difference between the input voltage and the reference voltage,wherein the reference voltage is variable.2. An analog-to-digital conversion circuit according to claim 1 , further comprising a correction circuit configured to supply the reference voltage to the reference terminal based on a voltage difference between the internal terminal and a measurement terminal.3. An analog-to-digital conversion circuit according to claim 2 , further comprising a selector switch coupled with the internal terminal and the measurement terminal.4. An analog-to-digital conversion circuit according to claim 3 ,wherein the measurement terminal is configured to couple with a measurement resistor.5. An electronic device ...

PROGRAMMABLE SEQUENCE CONTROLLER FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER

The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC. 1. An analog to digital converter comprising:an input for receiving an analog signal;a capacitive network configured to store a sample of the analog signal;a successive approximation register;a comparator structured to compare the sample of the analog signal stored in the capacitive network to a value stored in the successive approximation register; anda programmable sequencer including at least one memory, the programmable sequencer configured to generate control signals that control operation of the successive approximation register.2. The analog to digital converter of further comprising:an output coupled to the successive approximation register and structured to deliver a digital representation of the analog signal from the analog to digital converter.3. The analog to digital converter of in which the programmable sequencer comprises a program memory and a control memory.4. The analog to digital converter of in which the program memory of the programmable sequencer is configured to store at least two sequence instructions.5. The analog to digital converter of in ...

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Methods and systems are provided for generating correction estimates. Training signals may be injected into one or more particular spectral regions, and one or more correction estimation parameters may be determined based on the injecting of the training signals, where the one or more correction estimation parameters reduce distortion in at least the one or more particular spectral regions. The particular spectral regions may comprise originally-unoccupied spectral regions. The one or more correction estimation parameters may be applied during correcting of digital signals generated based on processing of received analog signals. The training signals may be generated, such as based on one or more pre-defined characteristics. The one or more correction estimation parameters may then be determined based on the one or more pre-defined characteristics of the training signals and/or changes thereto. 120-. (canceled)21. A method , comprising: injecting training signals into one or more particular spectral regions; and', 'determining based on said injecting of said training signals, one or more correction estimation parameters;', 'wherein said one or more correction estimation parameters reduce distortion in at least said one or more particular spectral regions., 'in an electronic device that performs analog-to-digital conversions22. The method of claim 21 , comprising applying said one or more correction estimation parameters during correcting of digital signals generated based on processing of received analog signals.23. The method of claim 21 , wherein said one or more particular spectral regions comprise originally-unoccupied spectral regions.24. The method of claim 21 , wherein said at least some of said distortion is caused by nonlinearity in said electronic device.25. The method of claim 21 , comprising:isolating signals in said one or more particular spectral regions; anddetermining said one or more correction estimation parameters based on said isolated signals.26 ...

TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER SYSTEM

A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter- leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal. 1. A time-interleaved Analog-to-Digital Converter , ADC , system , comprising:time-interleaved first and second ADC circuits; selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground; and', 'selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground; and, 'a switching circuit configured toan output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.2. The time-interleaved ADC system of claim 1 , wherein in a first operation mode:the switching circuit is configured to supply the analog input signal to the first ADC circuit and the second ADC circuit; andthe output circuit is configured to generate the digital output signal based on the first digital signal and the second digital signal.3. The time-interleaved ADC system of claim 2 , wherein the switching circuit is configured to supply the analog calibration signal to the first ADC circuit and the second ADC circuit in a second operation mode.4. The time-interleaved ADC system of ...

CAPACITANCE-TO-DIGITAL CONVERTER AND METHOD FOR PROVIDING A DIGITAL OUTPUT SIGNAL

A capacitance-to-digital converter () comprises a capacitor arrangement (), a converter () that is coupled on its input side to the capacitor arrangement () and a calibration unit () that is coupled on its input side to the converter (). The capacitor arrangement () comprises an input capacitor (). 1. A capacitance-to-digital converter , comprisinga capacitor arrangement comprising an input capacitor,a converter that is coupled on its input side to the capacitor arrangement, anda calibration unit that is coupled on its input side to the converter.2. The capacitance-to-digital converter according to claim 1 ,wherein the calibration unit is configured to provide a digital output signal that has a polynomial dependency from an input signal of the calibration unit or a signal derived from the input signal.3. The capacitance-to-digital converter according to or claim 1 ,comprising a temperature sensor having an output coupled to the calibration unit and generating a temperature signal, wherein the calibration unit is configured to provide a digital output signal that has a polynomial dependency from an input signal of the calibration unit and from the temperature signal or a signal derived from the temperature signal.4. The capacitance-to-digital converter according to or claim 1 ,comprising a memory that is coupled to the calibration unit, is realized as a non-volatile memory and stores calibration coefficients.5. The capacitance-to-digital converter according to or claim 1 ,wherein the input capacitor is implemented as a capacitive sensor and the capacitor arrangement comprises a further capacitive sensor that detect the same parameter to be measured.6. The capacitance-to-digital converter according to or claim 1 ,wherein the capacitor arrangement comprises a reference capacitor and the reference capacitor is realized such that the capacitance value of the reference capacitor can be trimmed or programmed.7. The capacitance-to-digital converter according to or claim 1 , ...

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes a code data generation circuit that generates code data which changes with time, and a successive approximation type A/D conversion circuit that performs code shift based on the code data and performs A/D conversion of an input signal. The code data generation circuit generates error data of which a frequency characteristic has a shaping characteristic and converts the error data into the code data. 1. A circuit device comprising:a code data generation circuit configured to generate code data which changes with time; anda successive approximation type A/D conversion circuit configured to perform code shift based on the code data and perform A/D conversion of an input signal,wherein the code data generation circuit generates error data of which a frequency characteristic has a shaping characteristic and converts the error data into the code data.2. The circuit device according to claim 1 ,wherein the code data generation circuit converts the error data into the code data by an inverse function of a function of converting the code data into the error data.3. The circuit device according to claim 2 ,wherein the A/D conversion circuit includes a second D/A conversion circuit configured to perform D/A conversion of the code data, andwherein the function is a function based on a conversion characteristic of the second D/A conversion circuit.4. The circuit device according to claim 2 ,wherein, when the code data is referred to as CS, predetermined values corresponding to a range of the code data are referred to as CM and CA, the error data is referred to as ERR, and the function is referred to as f, ERR=f(CS)=(CM−CS)/CA at CS>0, ERR=f(CS)=0 at CS=0, ERR=f(CS)=−(CM+CS)/CA at CS<0.5. The circuit device according to claim 1 ,wherein the code data generation circuit includes a data generation circuit, a modulation circuit configured to modulate generation data from the data generation circuit to generate the error data, and a conversion circuit ...

TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER WITH CALIBRATION

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC. 1. An apparatus comprising:an analog-to-digital converter (ADC) having an input to receive an analog signal and an output to provide a digital representation of the analog signal; anda calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry includes a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first calibration mode and second calibration mode.2. The apparatus of claim 1 , wherein the calibration circuitry includes a first circuitry coupled to an output of the multiplexer claim 1 , wherein the first circuitry is to determine a maximum value of the output of the multiplexer.3. The apparatus of claim 2 , wherein the calibration circuitry includes a second circuitry coupled to an output of the multiplexer claim 2 , wherein the second circuitry is to determine a minimum value of the output of the multiplexer.4. The apparatus of claim 3 , wherein the calibration circuitry comprises a third circuitry to determine an average of the maximum and minimum values.5. The apparatus of claim 4 , wherein the calibration circuitry comprises a fourth circuitry to determine a difference between the maximum and minimum values.6. The apparatus of claim 5 , wherein the calibration circuitry comprises a fifth circuitry to apply the difference to calibrate gain of the ADC.7. The apparatus of claim 6 , wherein the fifth circuitry is to output a modified digital representation of the analog signal.8. The apparatus of ...

SELF-CALIBRATING VCO-BASED ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF

A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal. 1. A circuit comprising:an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal, where N is an integer greater than two;N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively;an output dispatch unit for receiving the N refined data and outputting an output data in accordance with the selection signal;a calibration controller for receiving the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code; anda DAC (digital-to-analog converter) for receiving the digital code and outputting the calibration signal, wherein the selection signal has N possible values, and one of the N dispatched signals as specified by the selection signal is from the calibration signal while the other N−1 dispatched signals are from the input signal.2. The circuit of claim 1 , wherein the selection signal ...

CURRENT SOURCE CALIBRATION TRACKING TEMPERATURE AND BIAS CURRENT

In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures. 120-. (canceled)21. A method for calibrating a trim circuit under variable environmental conditions using a bias setting comprising:measuring a current mismatch between a first current source and a second current source;varying first calibration settings of a first CAL DAC in the trim circuit, wherein the first CAL DAC has a first output current, and the first output current varies with a bias current; 'wherein varying the first calibration settings includes varying the first calibration settings such that the output current tracks the current mismatch.', 'measuring an output current of the trim circuit, wherein the output current of the trim circuit includes the first output current, and'}22. The method of claim 21 , further comprising varying second calibration settings of a second CAL DAC in the trim circuit wherein the second CAL DAC has a second output current claim 21 , and the second output current varies with the bias current.23. The method of claim 22 , wherein the output current of the trim circuit is a sum of the ...

High-Speed DAC

A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current. 1. A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal , comprising:an N-bit DAC having a reference cell and a current source array of unit cells for generating a DAC output; anda back-gate bias generator (“BBGEN”) configured to generate a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA;wherein a back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM,wherein a back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA,wherein the reference cell is configured to generate a main current, andwherein the unit cells are configured to mirror the main current.2. The DAC system of further comprising a multiplexer and a digital controller logic claim 1 ,wherein the digital controller logic is coupled to inputs of the BBGEN for controlling the BBGEN to generate back-gate bias voltages,wherein the multiplexer is configured to receive the generated back-gate bias voltages, andwherein the multiplexer is configured to be operated by the digital controller logic to select one of the generated back-gate bias voltages to be the first back-gate bias voltage PB_CSM and another one of the back-gate bias voltages to be the second ...

SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER CIRCUIT WITH CORRECTION FOR MISMATCH ERROR INTRODUCED BY THE FEEDBACK DIGITAL-TO-ANALOG CONVERTER

A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit. 1. A sigma-delta modulator , comprising:a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal;a K-th order loop filter circuit configured to filter the difference signal and generate a change signal;an N-bit quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of N-bit code words;an N-bit digital-to-analog converter (DAC) circuit configured to convert the stream of N-bit code words to generate the feedback signal, wherein the N-bit DAC circuit has a non-ideal operation due to mismatch error; anda digital DAC copy circuit that provides a digital replication of the N-bit DAC circuit, said digital replication accounting for the non-ideal operation of the N-bit DAC circuit due to mismatch error, the digital DAC copy circuit configured to convert the stream of N-bit code words to output a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.2. The circuit of claim 1 , wherein noise associated with the mismatch error is high pass noise shaped claim 1 , further including a low pass filter configured to ...

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND CALIBRATION METHOD THEREOF

A successive-approximation-register (SAR) analog-to-digital converter (ADC) is provided in the invention. The SAR ADC includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information. 1. A successive-approximation-register (SAR) analog-to-digital converter (ADC) , comprising:an analog circuit; anda digital control circuit, coupled to the analog circuit, wherein the digital control circuit comprises:a calibration circuit, performing a calibration operation;a memory device, coupled to the calibration circuit and storing calibration information generated by performing the calibration operation; andan asynchronous control circuit, coupled to the memory device, and reading the calibration information from the memory device in an asynchronous control mode,wherein in the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes non-idea effects of the SAR ADC according to the calibration information.2. The SAR ADC of claim 1 , wherein the digital control circuit further comprises:a selection circuit, coupled to the calibration circuit and the asynchronous control circuit, and selecting the calibration circuit or the ...

Integrated circuit for converting analog signal to digital signal, system, and operating method thereof

一种集成电路、系统与模拟信号转换至数字信号的方法，其中集成电路用以转换一模拟信号成为至少一数字信号，包括第一输入端、第一组(2 n -1)个反相器与第一加法器。第一输入端用以接收一第一模拟信号。第一组(2 n -1)个反相器用以量化该第一模拟信号，并且输出一第一组(2 n -1)个数字值。第一组(2 n -1)个数字值的各者分别为0或1。第一加法器与该第一组(2 n -1)个反相器耦接。第一加法器加总该第一组(2 n -1)个数字值，并且输出对应于至少一数字信号的一第一整数值。(2 n -1)个反相器所需面积小于传统快闪式模拟至数字转换器中(2 n -1)个比较器所需面积。因此可有效减少集成电路100的晶片尺寸。

Digital / analog conversion circuit

Method of iteration correction of analog-to-digital conversion

Изобретение относитс  к измерительной технике и предназначено дл  прецизионных цифровых информационно-измерительных систем и измерительно-вычислительных комплексов, работающих в услови х промышленных помех. Целью изобретени   вл етс  повышение точности коррекции аналого-цифровых преобразований. Поставленна  цель достигаетс  тем, что согласно способу производ т формирование кода, пропорционального сумме входного аналогового сигнала и помехи, затем формирование вспомогательного аналогового сигнала, пропорционального полученному коду, после чего к нему прибавл ют помеху и далее производ т второе формирование кода, который содержит почти удвоенную погрешность по сравнению с погрешностью первого формировани  кода, и на основе двух кодов вычисл ют скорректированную оценку значени  преобразуемой аналоговой величины. Предлагаемый способ в отличие от способов, использующих фильтрацию или осреднение помех, дл  повышени  точности аналого-цифрового преобразовател  в услови х интенсивных внешних помех не требует знани  статистических характеристик этих помех, т.е. предлагаемый способ инвариантен к низкочастотной внешней помехе. 2 ил. СП С The invention relates to a measurement technique and is intended for precision digital information measuring systems and measuring computer systems operating under industrial interference conditions. The aim of the invention is to improve the accuracy of the correction of analog-to-digital conversions. The goal is achieved by the method of generating a code proportional to the sum of the input analog signal and interference, then generating an auxiliary analog signal proportional to the received code, after which the interference is added to it and then the second code generation is performed, which contains almost doubled the error compared with the error of the first code generation, and on the basis of the two codes, the corrected estimate of the value of the converted analog value is calculated. The proposed method, unlike methods using ...

Serial-parallel type a/d converting device

Parallel-to-series n-digit analog-to-digital converter with automatic correction of conversion function

Изобретение относитс  к информационно-измерительной технике. Изобретение позвол ет повысить точность преобразовани  за счет обеспечени  аналоговой коррекции результатов, формируемых в первом такте преобразовани , что позвол ет использовать быстродействующий и высокостабильный , но непрецизионный ЦАП. Коррекци  производитс  относительно прецизионного регулируемого источника 7 напр жени , точность которого определ ет точность всего устройства. Это достигаетс  тем, что в устройство, содержащее k-разр д- ный аналого-цифровой преобразователь 1, цифроаналоговые преобразователи 4, 11, запоминающее устройство 12, вычитающий усилитель 5, сумматор 8, реверсивный счетчик 13, мультиплексор 15, регистр 2, блок 3 управлени , коммутатор 9, введены коммутатор 10, регистр 2, блок 14 сравнени  кодов , 1 з.п.ф-лы, 2 ил. п-к fiCH n СП с VJ со го VI The invention relates to information and measurement technology. The invention makes it possible to increase the accuracy of the conversion by providing analogue correction of the results generated in the first conversion step, which allows the use of a fast-acting and highly stable but non-precision DAC. The correction is made with respect to a precision adjustable voltage source 7, the accuracy of which determines the accuracy of the entire device. This is achieved in that a device containing k-bit analog-to-digital converter 1, digital-to-analog converters 4, 11, memory 12, subtractive amplifier 5, adder 8, reversible counter 13, multiplexer 15, register 2, block 3 control, switch 9, switch 10 is entered, register 2, code comparison block 14, 1 hp ff, 2 Il. fiCH n SP with VJ from th VI

A kind of threshold correction method of multi thresholds sampling digitizing device

一种多阈值采样数字化器件的阈值校正方法，其步骤为：生成一三角波，测量该三角波波形的上升沿部分的斜率k1、下降沿部分的斜率k2以及其峰值幅度Vpeak，该脉冲高于实际工作阈值Vt部分的宽度DOT表示为DOT（Vt）=(Vpeak-Vt)/k1–(Vpeak–Vt)/k2；设置n组阈值对；根据公式利用测得的脉冲宽度DOT计算出实际工作状态下的阈值；根据实际工作状态阈值与实际设定参考电压之间的对应关系建立阈值校正函数，进而根据该函数对设定的阈值进行校正。该方法可以有效的解决比较器在实际工作状态下因实际设定的设定参考电压与实际工作状态阈值不一致带来的采样精度下降的问题，由于本方法的运用，可以避免MVT器件中使用高精度的比较器，从而有效的降低了MVT器件的成本。

Threshold value rectifying method of multi-threshold value sampling digitalization device

一种多阈值采样数字化器件的阈值校正方法，其步骤为：生成一三角波，测量该三角波波形的上升沿部分的斜率k1、下降沿部分的斜率k2以及其峰值幅度Vpeak，该脉冲高于实际工作阈值Vt部分的宽度DOT表示为DOT（Vt）=(Vpeak-Vt)/k1–(Vpeak–Vt)/k2；设置n组阈值对；根据公式利用测得的脉冲宽度DOT计算出实际工作状态下的阈值；根据实际工作状态阈值与实际设定参考电压之间的对应关系建立阈值校正函数，进而根据该函数对设定的阈值进行校正。该方法可以有效的解决比较器在实际工作状态下因实际设定的设定参考电压与实际工作状态阈值不一致带来的采样精度下降的问题，由于本方法的运用，可以避免MVT器件中使用高精度的比较器，从而有效的降低了MVT器件的成本。

Analog-to-digital converter device of improved time interleaving type, and high-speed signal processing system using the device

RD Converter and Angle Detecting Apparatus

An RD converter is disclosed that has a first multiplier multiplying a resolver signal S 1 by an output of a SIN ROM; a second multiplier multiplying a resolver signal S 2 by an output of a COS ROM; a subtractor subtracting an output of the first multiplier from an output of the second multiplier; a synchronous detecting circuit detecting synchronously an output of the subtractor with reference to an excitation signal; a controller controlling an output angle θ′ to make an output of the synchronous detecting circuit equal to zero; a correction data part outputting a correction angle θ c for the output angle θ′; an adder adding the output angle θ′ and the correction angle θ c ; the SIN ROM producing a sine value of a result from the adder; and the COS ROM producing a cosine value of the result.

Single-precision ADC adaptive threshold quantification method based on large-scale MIMO

本发明公开了一种基于大规模MIMO的单精度ADC自适应门限量化方法，包括以下步骤：对实际场景进行建模，依据建模的大规模MIMO场景得到信道数据作为训练序列，利用LBG线性分类方法对具有相关性的信道数据进行分类，得到每一类的质心和质心间的边界，并依据分类的结果找出质心与量化值、边界与自适应门限的映射关系，并在此基础上建立实际天线模型下利用相关性的自适应门限设置方法；利用已有的大规模MIMO信道模型产生用户不同发送功率下基站端接收到信号，映射出该场景下不同用户发送功率对应的量化门限和量化值；并对实际系统的上行链路进行仿真。该方法有效的提高了信道估计的准确性并降低了上行信号检测的误符号率。

Time-interleaved analog-to-digital converter and high speed signal processing system using the same

A time-interleaved analog-to-digital converter stores in a correction information memory, correction information required to correct an error between signals output by a plurality of N analog-to-digital converters in advance. At this time, in order to enable acquisition of data required for a correction processing within a short period of time, a signal generator causes the plurality of N analog-to-digital converter to input a calibration signal including a plurality of signal components, each of which is positioned at a desired frequency in a bandwidth in which N/2 times of a sampling frequency Fs is defined as an upper limit, the signal components appearing in a bandwidth in which half times of the sampling clock frequency Fs is defined as an upper limit by sampling the analog-to-digital converters. A correction information calculating unit carries out a spectrum analysis relevant to analog-to-digital converted signals output by the plurality of N analog-to-digital converters in response to the calibration signal, thereby obtaining an amplitude and a phase of a plurality of signal components, newly obtaining the correction information, based on the amplitude and phase, and updating contents of the correction information memory in accordance with newly obtained correction information.

Direct input radio frequency complex analog to digital converter with corrective factors

A direct radio frequency complex analog to digital converter (CADC) device provides corrective factors including a plurality of time-interleaved low speed ADCs, wherein each ADC corresponds to an ADC channel. A phase corrective factor is calculated for each ADC channel. An amplitude corrective factor is calculated for each ADC channel. The phase and amplitude corrective factors are applied to complex bandpass filter coefficients to produce filter coefficients corrected for the phase and amplitude imbalances between ADCs. Digital output of each ADC channel is filtered by a complex bandpass filter using the corrected filter coefficients to produce corrected in-phase and quadrature output at baseband. Harmonics produced by the ADCs are canceled by filtering ADC outputs in a first bandpass filter to an intermediate frequency such that the harmonics fall outside the band of interest, a second filter is applied to attenuate the harmonic and produce a signal output at baseband.

Analog-to-digital converter

Apparatus for of digitizing an input analog current signal such as a demodulated servo position error signal in a disk file includes a capacitor which is changed by with the input signal, and a plurality of comparators which compare the resulting capacitor voltage with a plurality of thresholds to produce a comparator output signal for each threshold exceeded by the capacitor voltage. The comparator output signals are sampled, and each sampling period a current corresponding to the thresholds exceeded is generated. The generated current is used to draw off charge from the capacitor until an equilibrium voltage is reached. By knowing the current generated to remove from the capacitor the voltage placed thereon by the input current signal, then the total charge applied to the capacitor can be determined. Further digital processing of the input signal value may be done without the use of a complicated digital to analog converter.

CALIBRATING AN INTERLACED ADC

L'invention concerne un circuit d'étalonnage pour ajuster la largeur de bande d'au moins un sous-convertisseur d'un convertisseur analogique-numérique (ADC) entrelacé, ledit au moins un sous-convertisseur comportant un commutateur d'entrée couplé à une ligne d'entrée (203, 204) de l'ADC, le circuit d'étalonnage comportant un circuit de commande (752) adapté à ajuster une tension de substrat d'un transistor (207, 215) formant le commutateur d'entrée. The invention relates to a calibration circuit for adjusting the bandwidth of at least one sub-converter of an interleaved analog-to-digital converter (ADC), said at least one sub-converter having an input switch coupled to an input line (203, 204) of the ADC, the calibration circuit comprising a control circuit (752) adapted to adjust a substrate voltage of a transistor (207, 215) forming the input switch .

Full scale calibration of analog-to-digital conversion

Methods and arrangements enable ADCs (105) to be calibrated from reference signals with unknown parameters and/or with amplitudes that exceed the dynamic range of the ADCs (105). A given analog reference signal s(t) is supplied to an ADC (105). The output x(k) of the ADC (105) is used by calibration logic (320) to estimate at least one paramater of the reference signal. A FIR filter (455) accepts as input the x(k) signals and outputs and estimate ((k)) as the sampled instances of thes(t) signal. A reconstruction table is created that approximates the analog input signal in the digital domain using the knowledge of the analog input signal waveform type. The actual ADC (105) outputs are compared to the values in the reconstruction table to produce a correction table (350) for calibration. In an alternative embodiment, calibration logic (320) interpolates the output (x(k)) of the ADC (105) to reconstruct clipped portion(s) of the input analog reference signal s(t) when the amplitude of the input analog reference signals s(t) exceeds the full swing of the ADC (105). The FIR filter can thereafter use the reconstructed signal from the interpolation.

Method for correcting faults introduced by a digitization system on an IQ signal and associated devices

Procédé de correction des défauts introduits par un système de numérisation sur un signal IQ et dispositifs associés La présente invention concerne un procédé de correction des défauts introduits par un système de numérisation , les défauts introduits par le système étant modélisables par un ensemble de modèles liant le signal d'entrée du système de numérisation transposé en composantes en phase et en quadrature à une enveloppe du signal de sortie du système de numérisation, le procédé de correction comporte une étape de : - calcul d’une approximation du signal idéal correspondant au signal obtenu en l’absence de défauts, par utilisation d’un filtre, - détermination de chaque coefficient des modèles à l’aide su signal approximé, - reconstruction du signal distordu synthétique à partir des coefficients déterminés, et - correction du signal de sortie du système par soustraction au signal de sortie du signal distordu synthétique. Figure pour l'abrégé : figure 3

PROGRAMMABLE ANALOGUE-DIGITAL CONVERTER

L'invention concerne les convertisseurs analogiques-numériques programmables. Elle se rapporte à un convertisseur dans lequel un réseau en échelle, destiné à transmettre des tensions de référence à des comparateurs, est piloté en plusieurs noeuds de commande par des jeux de tensions programmés provenant par exemple d'un réseau résistif ou d'une source de signaux numériques. La fonction de transfert peut être modifiée en fonction du temps. Application aux appareils ultrasonores de diagnostic médical. The invention relates to programmable analog-to-digital converters. It relates to a converter in which a ladder network, intended to transmit reference voltages to comparators, is driven at several control nodes by programmed voltage sets originating for example from a resistive network or from a source. digital signals. The transfer function can be changed over time. Application to ultrasonic medical diagnostic devices.

Correction of a value of a passive component

Correction d'une valeur d'un composant passif La présente description concerne un circuit intégré comprenant un premier composant passif (Comp) de type capacitif, résistif ou inductif comportant : une pluralité de deuxièmes et troisièmes composants passifs (Compu) dudit type ayant chacun une même première valeur théorique Compu_t, les deuxièmes composants étant connectés entre eux de sorte que leurs valeurs s'ajoutent, et chaque troisième composant étant associé à un premier interrupteur (208) dont l'état détermine si la valeur du troisième composant s'ajoute aux valeurs des deuxièmes composants ; et une pluralité de quatrièmes composants passifs (Compcorr) dudit type chacun associé à un deuxième interrupteur (214) dont l'état détermine si la valeur du quatrième composant s'ajoute aux valeurs des deuxièmes composants, au moins un (Compcorr) des quatrièmes composants (Compcorr) passifs ayant une deuxième valeur théorique égale à (1-P).Compu_t ou à (1+P).Compu_t, avec P positif strictement inférieur à 1/2. Figure pour l'abrégé : Fig. 2 Correction of a value of a passive component The present description relates to an integrated circuit comprising a first passive component (Comp) of the capacitive, resistive or inductive type comprising: a plurality of second and third passive components (Compu) of said type each having a same first theoretical value Compu_t, the second components being connected together so that their values are added, and each third component being associated with a first switch (208) whose state determines whether the value of the third component is added to the values of the second components; and a plurality of fourth passive components (Compcorr) of said type each associated with a second switch (214) whose state determines whether the value of the fourth component is added to the values of the second components, at least one (Compcorr) of the fourth components (Compcorr) liabilities having a second theoretical ...

Image sensor adc and cds per column

A solid state imager converts analog pixel values to digital. A counter (16) coupled to an N-bit DAC (20) produces an analog ramp corresponding to the contents of the counter. A ripple counter (90, 92) is associated with each respective column. Column comparators (22) gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements (26) can create and store a black level values for reduction of fixed pattern noise. Additional buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clocks for the DAC counter and ripple counters can be at the same or different rates.

PROGRAMMABLE ANALOG-TO-DIGITAL CONVERTER

Improvements relating to time-interleaved samplers

This invention relates to a method of calibrating a time-interleaved analogu e- to-digital sampler (10) and to a method of performing analogue-to-digital conversion with a sampler (10) so calibrated. The invention provides a metho d of calibrating a sampler (10) comprising N time-interleaved ADCs (12a-d), th e method comprising the steps of: (a) injecting in turn N calibration signals (13) into the sampler such that each calibration signal (13) occupies one of N related frequencies; (b) determining the input signal for each one of the N calibration frequencies (13); (c) measuring in the frequency domain the outp ut at each of the N related frequencies for each one of the N calibration frequencies; and (d) determining the relationship that relates the input signal to the output at each of the N related frequencies for each one of th e N calibration frequencies.

Digital self-calibration scheme for a pipelined A/D converter

A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Algorithmic A/D converter with digitally calibrated output

A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.

Integral nonlinearity error correction circuitry and method for DAC

An M+N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor ( 17 A) and a second voltage (Vlow) on a second conductor ( 17 B), an output amplifier ( 10 ), a calibration interpolation circuit ( 14 ), a memory circuit ( 36 ) for storing error information corresponding to various values of the first voltage and second voltage, outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of the output amplifier, and switching circuitry responsive to a N-bit portion of a M+N input word coupling the memory to inputs of the of the calibration interpolation circuit so as to correct integral nonlinearity errors associated with the various values of the first and second voltages.

Data conversion circuitry for converting analog signals to digital signals and vice-versa and method therefor

A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Pipeline analog to digital converter and signal conversion method

管線式類比數位轉換器包含多個轉換器電路系統以及校正電路系統。多個轉換器電路系統按照次序轉換輸入訊號為多個第一數位碼。多個轉換器電路系統中之第一轉換器電路系統根據第一訊號執行量化操作以產生第一數位碼中之第一對應數位碼，其中第一訊號為輸入訊號與前級殘餘訊號中由第一轉換器電路系統處理的訊號。校正電路系統組合第一數位碼以輸出第二數位碼，並偵測量化操作是否完成以產生第一與第二生效訊號，並根據第一與第二生效訊號決定是否將第二數位碼設定為第一或第二預設數位碼中之一者。第二生效訊號為第一生效訊號的延遲訊號。

Digital autozero circuit operable in a plurality of modes with separate storage for offset corrections for each mode

An autozero compensation system for autozeroing the output of a data conversion circuit comprising a floating point amplifier and an analog-to-digital converter. The autozero compensation system comprises a source for generating a desired offset voltage, a plurality of digital counters, one for each gain setting of the amplifier, for storing values which are functions of the offset voltages for the gain settings, and a comparator for comparing the output of the A/D converter with the desired offset. Periodically, each of the counters in the autozero circuit is updated for each gain setting by setting the analog input of the amplifier to system ground and the gain of the amplifier set to each of the gain settings, so that the output of the comparator is used to update each of the counters. The outputs of the counters are each converted to analog form by a D/A converter and used to provide the offset correction voltage to the floating point amplifier.

Distortion detecting device, distortion correcting device, and distortion correcting method for digital audio signal

A digital audio signal distortion detecting device is provided for estimating the distortion based on the linearity error of an analog/digital converter at the time of analog/digital conversion from a digital audio signal converted from analog to digital by the analog/digital conversion having linearity error. This device includes storage means (2) for storing the digital audio signal, occurrence frequency detecting means (3) for fetching a plurality of samples from the digital audio signal stored in the storage means (2) and counting the occurrence frequency of the samples for every code expressing the quantization level of the samples, normalizing means (4) for extracting distortion characteristics accompanying the linearity error of an A/D converter (11) from the occurrence frequency for every code detected by the occurrence frequency detecting means (3) as a normalized occurrence frequency, and error bit detecting means (5) for detecting an error bit on the basis of the code corresponding to the characteristics of the normalized occurrence frequency.

ANALOG / DIGITAL CONVERTER

System and method for digitally calibrating an analog-to-digital converter

A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Analog-to-digital converter capable of performing under two-phase dissimilar mode

当转换模拟输入电压为包含多个位的数字信号时，使用包含内建自我测试电路的模拟至数字转换器来实现转换操作并补偿模拟输入电压本身的偏移误差。该模拟至数字转换器的操作包含自我测试模式与正常模式。且该自我测试模式与该正常模式各自包含取样阶段与位循环阶段。

A / D converter and solid-state imaging device including the same

Control method of double integral type A / D converter

Calibration of a redundant number system successive approximation analog-to-digital converter

A system and method calibrate a redundant number system analog-to-digital converter (RNS ADC) using successive approximations of multiple input signals and approximating each input signal at least twice. The RNS ADC includes N analog converter reference elements, each of the analog converter reference elements is associated with a weight in a weight vector W , and N is an integer greater than one. The system and method successively approximate each of M distinct analog input signals twice to generate M respective pairs of successive approximation converter reference element vectors, C 1 j and C 2 j, that correspond to digital approximations of the input signals, wherein j ε {0, 1, . . . , M-1}, wherein M is a positive integer. The system and method utilize differences between the successive approximation converter reference element vectors, C 1 j and C 2 j to determine a final weight vector W B . Thus, in at least one embodiment, the difference between C 1 j · W B and C 2 j · W B can be used to determine the final weight vector W B .

Analog-to-digital converter and related chip

提出了一种模数转换器(10)。所述模数转换器具有模数转换操作模式与量测操作模式。所述模数转换器包括输入端(100)、数模转换器(104)以及输出端(102)。输入端用来接收模拟信号。输出端用来输出数字信号。数模转换器包括多个数模转换单元。当所述模数转换器操作在所述模数转换操作模式时，所述模数转换器用来将所述模拟信号转换为所述数字信号，以及当所述模数转换器操作在所述量测操作模式时，所述数字信号相关于待测数模转换单元的电容值与所述多个数模转换单元的总电容值的比值。

Differential flash ADC with dual resistance ladder legs receiving amplified inputs

A differential analog to digital converter (ADC) comprises a first resistance ladder leg including two resistances having first ends that communicate with a middle node. A second resistance ladder leg includes two resistances having first ends that communicate with a middle node. A first amplifier applies a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg. A second amplifier applies a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg.

Digital self-calibration scheme for a pipelined A/D converter

A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Circuit for A/D conversion of a video RF or IF signal

Switched current-cell with intermediate state

Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to "dump" the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.

The correcting circuit of digital analog converter and bearing calibration

一种数字模拟转换器的校正方法，该数字模拟转换器应用于一连续逼近式模拟数字转换器并且包含一第一电容、多个第二电容及一桥接电容，该方法包含：(a)使该连续逼近式模拟数字转换器的一比较器的两输入端等电位；(b)改变该第一电容的一第一端点的电位；(c)得到该连续逼近式模拟数字转换器的一第一输出；(d)于得到该第一输出后，使该比较器的两输入端等电位；(e)改变该多个第二电容的多个第一端点的电位；(f)得到该连续逼近式模拟数字转换器的一第二输出；以及(g)依据该第一输出及该第二输出校正该数字模拟转换器。

Dynamic tracking nonlinearity correction

An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD 3 , SDFR, and IM 3 measures.

Analogue-to-digital conversion systems

ABSTRACT OF THE DISCLOSURE In known analogue-to-digital conversion systems with multiple inputs of different kinds, it is usual for each input to have its own signal conditioning circuit, which adds to the cost of the system. In the present invention, the system has a multiplexer that provides sequential output samples of all the inputs via an amplifier to an analogue-to-digital converter. A multiplier between the multiplexer and the amplifier spectrally shifts the signals in one sense. The system also has a second multiplier at the output of the converter, which spectrally shifts the signals in the opposite sense to substantially their original spectral content. The second multiplier also spectrally shifts any noise produced by the amplifier. A digital filter attenuates the noise more than the signal and supplies the different outputs to respective registers. One of the inputs is at a zero level and the equivalent output is subtracted from the other outputs, further reducing noise.

Analog-to-digital converter device of improved time interleaving type, and high-speed signal processing system using the device

An A/D converter device of time interleaving type stores a correction information memory in advance with correction information necessary for correcting an error between the individual signals which are outputted by an N-number of A/D converters. In order to acquire data necessary for a correction processing for a short time period, a signal generator inputs a calibration signal, which has a plurality of signal components individually positioned at desired frequencies within a band having an upper limit of N/2 times as high as the frequency (Fs) of a sampling clock fed to each of the N-number of A/D converters and appearing in different frequencies within a band having an upper limit of one half of the frequency (Fs) of the sampling clock, to the N-number of A/D converters. A correction information calculation unit determines the amplitude and phase of the plural signal components by subjecting the calibration signal to a spectral analysis with respect to the A/D converted signals outputted by the N-number of A/D converters, with respect to the correction signal, and determines the correction information newly on the basis of the amplitude and phase, thereby to update the contents of the correction information memory with the correction information newly determined.

METHOD AND DEVICE FOR CALIBRATING AN ANALOG-TO-DIGITAL CONVERTER DEVICE.

Method for correcting a measurement error caused by a measuring arrangement

The method involves starting a test procedure for testing the analog-digital (A/D) converter (7) by a software (10). The input (CH1) of A/D converter is switched to a calibrator (6) which generates a predetermined analog signal from the A/D converter. The difference between the value generated by A/D converter and the predetermined value generated by the calibrator is determined. The input of the A/D converter is switched to the sensor (1), and the A/D converter formed digital measurement value is corrected by the difference. An independent claim is included for device for correcting measurement error of measuring device.

Single pass INL trim algorithm for networks

A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired.

DIGITAL ANALOGUE CONVERSION DEVICE WITH TEMPORARY INTERLACING AND ADAPTIVE AUTO EQUALIZATION.

Analog-to-digital converter

本发明涉及模数转换器。根据一个实施例，模数转换器包括电压生成单元以及多个比较器。电压生成单元被配置来利用多个可变电阻器对基准电压进行分压，以生成多个比较电压。所述多个比较器中的每一个被配置来将所述多个比较电压中的任意一个与模拟输入电压进行比较，以及基于比较电压和模拟输入电压之间的比较结果输出数字信号。所述多个可变电阻器中的每一个包括串联连接的多个可变电阻性元件，并且所述多个可变电阻性元件中的每一个具有根据外部信号可变地设置的电阻值。

Adjustable termination resistor device ued in ic chip

Signal processing method and means

A signal-processor, applicable especially to an analogue-to-digital conversion system, employs an inexpensive device (ADC 40) having a high temperature coefficient and enhances its temperature performance by, in an initial calibration phase, measuring the output of the device for a temperature-stable reference-signal (2V5) applied to its input and, in a subsequent measurement and compensation phase and at substantially the same ambient temperature, measuring the output for the same reference signal applied to the input and measuring the output for an input signal (Va) applied to the input. The digital input-signal reading is then corrected in dependence on a comparison of the two reference-signal readings which appeared at the output of the device. When used in a voltage- and current-measuring ADC arrangement, a stereo differential-input ADC unit (40) is advantageously employed together with voltage and current transformers (44, 45) having centre-tapped secondaries, the centre taps being fed from a signal related to the temperature-stable reference signal (2V5).

Resolver / digital converter and control system using the resolver / digital converter

Calibrating timing, gain and bandwidth mismatch in interleaved ADCs

用于校准交错式模数转换器(ADC)的方法和相应设备包括：向ADC中的所选通道中的闪存元件和乘法数模转换器(MDAC)中的至少一个注入随机确定的量的抖动。执行关联程序以根据总ADC输出来估计出注入的抖动在传播通过通道之后经历的增益。对至少一个附加通道重复注入和关联程序以针对至少一个附加通道中的每一个估计出增益。随后，比较所选通道和至少一个附加通道的估计出的增益以确定所选通道与至少一个附加通道中的每一个之间的失配的程度。至根据所确定的失配的程度来校准至少一个通道。

Digital background calibration in pipelined ADCS

Digital background calibration in a pipelined ADC is performed by extracting a capacitor mismatch value Δ that represents a mismatch between a sampling capacitor C 1 and a feedback capacitor C 2 in the pipelined ADC, and using Δ to correct the capacitor mismatch error. Δ is extracted by performing commutated feedback capacitor switching (CFCS) in a background correlation loop. The error caused by the capacitor mismatch is calibrated out by subtracting the error from a digital output D out of the pipelined ADC. Convergence speed may be accelerated and convergence accuracy may be increased during digital background calibration of pipelined ADCs, by using a higher order LPF. A bandwidth switching scheme may be implemented by the LPF, i.e. a larger bandwidth may be utilized during calibration start-up to increase convergence speed during start-up and a smaller bandwidth may be utilized during steady state to increase convergence accuracy during steady state.

Method and system for monitoring for variation of converter voltage reference

A method and system include a converter such as an analog-to-digital converter (“ADC”) and a controller. The converter is configured to receive a sensor signal, indicative of a physical measured quantity, and generate an output signal based on the sensor signal and the voltage reference. The converter is further configured to alternately receive a calibration voltage in lieu of the sensor signal and generate the output signal based on the calibration voltage and the voltage reference. The controller is configured to compare the output signal based on the calibration voltage and the voltage reference with an expected value of the output signal based on the calibration voltage and an assumed value of the voltage reference to detect variation of the voltage reference, and to compensate the output signal based on the sensor signal and the voltage reference as a function of the detected variation of the voltage reference.

A / D converter

A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

Analog signal input circuitry with an analog-to-digital converter in a semiconductor device

The analog signal input circuit comprises an analog-to-digital circuit and a conversion error measuring circuit. The conversion error measuring circuit comprises the following elements. A first switching device 13 is provided between an analog signal input terminal 5 and the sample/hold circuit 10 for disconnecting the analog-to-digital circuit from the analog signal input terminal 5 in a measurement operation for measuring a conversion error value. A reference voltage generation circuit 15, 22 is provided to be connected via a second switching device 14 to between the first switching device 13 and the sample/hold circuit 10. The correction reference voltage generation circuit 15, 22 generates a correction reference voltage in relation to the A/D conversion reference voltage. The second switching device 14 is operated to connect the analog-to-digital circuit to the correction reference voltage generation circuit in the measurement operation for measuring the conversion error value. A conversion error value memory 12 is provided for storing a conversion error value defined as a difference between the correction reference voltage and the A/D conversion reference voltage.

Digital measurement of feedback dac timing mismatch error

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback

An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs

A multi-channel circuit ( 1 ) comprising a plurality of on-chip channels (CH 1 to CH 4 ), each of which comprises a DAC ( 3 ) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit ( 11 ). The analogue output signals from the DACs ( 3 ) are outputted on output terminals ( 7 ) of the respective channels (CH 1 to CH 4 ). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs ( 3 ) are inputted to the interface and control logic circuit ( 11 ) through an I/O port ( 10 ). DAC registers ( 9 ) are provided in the respective channels (CH 1 to CH 4 ) for storing the digital words to be converted in the corresponding DACs ( 3 ). Analogue input terminals ( 20 ) are provided for receiving analogue input signals ( 20 ), for example, analogue signals from external systems which may be controlled by the output signals from the DACs ( 3 ). A multiplexer ( 15 ) is operable under the control of the interface and control logic circuit ( 11 ) for selectively and sequentially applying the analogue output signals from the DACs ( 3 ) and the analogue input signals from the analogue input terminals ( 20 ) to a monitoring output terminal ( 16 ) for facilitating independent monitoring of the analogue output signals from the DACs ( 3 ), and the analogue inputs on the analogue input terminals ( 20 ).

Interleaved analog to digital converter with digital equalization

An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer. A residual distortions calculator of the residual distortions reduction unit, is responsive to measured frequency responses from the composite ADC and a current set of equalizer coefficients applied to the equalizer, to calculate residual frequency distortions that should have been expected to appear in the output signal of the ADC system if the current equalizer coefficients remain applied to the equalizer.

Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback

An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

On-chip calibration method

A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.