Halbleiterschaltung und ihre Anwendung in einer Operationsschaltung, einem Signalwandler und einem Signalverarbeitungssystem

Digital-Analog-Konverter mit Schaltkreisarchitekturen, um Schalterverluste zu beseitigen

Digital-Analog-Konverter (DAC), umfassend: ein Paar von Operationsverstärkern, wobei jeder einen ersten Eingang hat, um jeweils an eine Quellenspannung zu koppeln; und eine Mehrzahl von Schalter-gesteuerten Zellen, wobei jede Zelle umfasst: einen Widerstand, ein erstes Paar von Schaltern, welche hintereinander geschaltet sind und in Antwort auf einen ersten Zustand eines Steuersignals leitend gemacht sind, wobei ein Zwischenknoten zwischen den Schaltern des ersten Paares an den Widerstand gekoppelt ist, wobei der erste Schalter des ersten Paares ein an einen Ausgang des ersten Verstärkers gekoppelter Setzschalter ist, und wobei der zweite Schalter ersten Paares ein an einen zweiten Eingang des ersten Operationsverstärkers gekoppelter Prüfschalter ist, und ein zweites Paar von Schaltern, welche hintereinander geschaltet sind und in Antwort auf einen zweiten Zustand des Steuersignals leitend gemacht sind, wobei ein Zwischenknoten zwischen den Schaltern des zweiten Paares an den Zwischenknoten ...

A/D-Wandlerschaltung

POTENTIALERZEUGUNGSVORRICHTUNG

DIGITAL-ANALOG-WANDLER

Digital/analog converter for a display driver

An n-bit digital/analog converter has an (n-1) bit bufferless switched capacitor digital/analog converter (10) having an output (Vout) for direct connection to a capacitive load (CLOAD). The (n-1) bit converter (10) also has first and second reference voltage inputs (V1, V2) and an (n-1) bit digital input. An (n-1) bit selective inverter (131, ..., 13n-1, 141, ..., 14n-1) supplies the (n-1) least significant bits to the digital input and inverts them if the most significant bit is 1. A switching arrangement (11, 12) connects the first and second reference voltage inputs (V1, V2) to receive first and second or second and first reference voltages depending on the value of the most significant bit.

DIGITAL TO LOG-ANALOG CONVERTER

... 1,270,686. Selective signalling. TIME/DATA CORP. 13 June, 1969 [3 Sept., 1968], No. 30090/69. Heading G4H. An analogue signal representative of the logarithm of a number represented digitally is produced by summing analogue signals representing the characteristic and mantissa of the required logarithm. As described a 32-bit binary number is inserted into a shift-register 20, Fig. 7, the most significant bit I 1 occupying the extreme left-hand stage of the register, and a counter 22 is set to register 31-i.e., the counter is initially set to register the characteristic of the logarithm to the base two of the digital number if its most significant bit I 1 is a one-bit. If the most significant bit I 1 is not a one-bit, the register is left shifted until the most significant one-bit occupies the extreme left-hand stage of the register and for every shift unity is subtracted from the counter. Thus, when the most significant one-bit occupies the extreme lefthand stage of the register, the counter ...

Digital-to-analog converter and active matrix liquid crystal display

MODIFIED SIGN-MAGNITUDE DAC AND METHOD

An encoder and a decoder with non-linear quantization

... 1,004,967. Selective signalling systems. NIPPON ELECTRIC CO. Ltd. Nov. 1, 1963 [Nov. 8, 1962], No. 43211/63. Heading G4H. A digital-to-analogue converter which may be used in feed-back coding arrangements, has a non-linear characteristic and comprises AND gates 21 and standard power sources 41, the various combinations of the input digits e 1 -e 4 and the individual outputs of sources 41 being chosen to give the desired non-linear input/ output relationship. A theoretical discussion of the way in which the inputs to gates 21 and the individual outputs required from sources 41 may be arrived at to provide a quadratic or a cubic characteristic is given in the Specification.

Process and apparatus allowing to obtain seismic data.

DIGITAL-ANALOG CONVERTER

ANALOG/CDIGITAL TRANSDUCER

A/D CONVERTER WITH GRADUAL APPROXIMATION IN THE LOAD DOMAIN

PROCEDURE FOR THE REGULATION AND PROCESSING OF CORRECTION VALUES FOR SILVER-SHEAR A/D AND D/A TRANSDUCERS AND ARITHMETIC UNIT FOR THE EXECUTION OF THE PROCEDURE

VARIABLE RESISTORS

DIGITAL-TO-ANALOG CONVERTER FOR BIPOLAR SIGNALS

VARIABLE RESISTORS

A compact and inexpensive variable resistor has a value of resistance that can be set by a data signal. The variable resistor includes a number of variable resistances connected in series, an an individual electronic switch being connected in parallel across each individual resistance. A latch holds the data signal and controls the switches until a new data signal is received. Each individual resistor includes a resistance of r/x in addition to the basic chosen value of the individual resistance, where x is the total number of electronic switches. Preferably the values of the individual resistances are chosen from the progression 20, 21, 22, 23, and so on, so that the resistance of the variable resistor corresponds to the binary value of data applied to control the electronic switches. At least four such variable resistances can be constructed on a single normal size integrated circuit chip. To minimize the number of connections to the chip, the integrated circuit further includes a shift ...

ANALOG TRANSMITTER OF POSITION AND DIRECTION OF ROTATION

The invention relates to a device for encoding and remotely transmitting information concerning the position and the direction of rotation of a rotary element. This device comprises an encoder driven by sensors suitable for producing an analog signal whose amplitude varies on each change of state of each sensor by an amount that depends on which sensor changes state. The invention is applicable to electricity meters.

DC CURRENT COMPARATOR CIRCUIT FOR GENERATING AN ADJUSTABLE OUTPUT PROPORTIONAL TO AN INPUT SIGNAL

A DC current-comparator-based circuit generates an adjustable output proportional to an input signal, i.e. an input voltage or current. One use of the circuit is in the formation of a DC resistance bridge that can be controlled automatically by a microprocessor. The ends of a pair of test resistors (the resistances of which are to be compared) are connected to respective ratio windings of the current comparator. The same potential is applied across these resistors by a master power supply. A microprocessor is alternately supplied with two voltage signals, a first being proportional to the current in a variable one of the ratio windings of the comparator, and the second being proportional to any inequality between the current in the other ratio winding and the test resistor to which it is connected. The microprocessor controls a slave power supply that receives both the first signal and a third signal that is indicative of any unbalance in the bridge. Balance is achieved by adjusting the ...

Apparat zur kontinuierlichen Steuerung einer automatischen Maschine

Décodeur pour des signaux d'impulsions codées.

Elektrischer Signalumsetzer zur Umsetzung von Abtastwerten einer elektrischen Welle in Codegruppen von Zifferimpulsen oder umgekehrt

Codierungseinrichtung

Impulsamplituden-Diskriminator

Elektrisches Impulscode-Modulationssystem für das Fernmeldewesen

Elektrischer Impulscodeumsetzer

Schaltungsanordnung zur Digital-Analog-Umformung

Magnetische Triggervorrichtung

Resistance network type digital to analog converter structure

CONVERTISSEUR NUMERIQUE-ANALOGIQUE PERFECTIONNE

Convertisseur numérique-analogique destiné à convertir en signaux analogiques des signaux numériques constitués de bits de signe, de bits de pas et de bits de segment, notamment de signaux codés par compression de données conformément à la loi A, ledit convertisseur comprenant un générateur de signe 4, destiné à recevoir le bit de signe dudit signal numérique, un générateur de pas 7, connecté à la sortie du générateur de signe et destiné à recevoir les bits de pas dudit signal numérique et un générateur de segments 8 connecté au générateur de pas et destiné à recevoir les bits de segment dudit signal de référence, caractérisé en ce que le générateur de segments 8 est connecté au générateur de signe 4 uniquement par l'intermédiaire du générateur de pas 7. (CF DESSIN DANS BOPI) ...

NETWORK RESISTANCE

Systems of coding of impulses

Improvements in or relating to code converting arrangements for pulse code modulationsystems

Systems of coding of impulses

Digital=analogue converter for LCD

Dans un convertisseur numérique-analogique (N/A), de type à condensateur commuté, un groupe de n bits du mot binaire est appliqué, respectivement, à n branches 5 parallèles (A, B, C, D) du convertisseur N/A. Dans une branche donnée (A), le bit correspondant (MSB-3) est appliqué à une borne de commande (GRILLE) d'un commutateur correspondant (MN31) associé à un condensateur commuté correspondant (C1). Suivant le niveau logique du bit, le condensateur commuté est chargé à une tension de référence (5V) ou reste déchargé. Puis, le condensateur commuté de la branche donnée est couplé par un commutateur de transfert (MN51) en parallèle avec un condensateur sommateur (C5) pour fournir une redistribution de charge. Les capacités du condensateur commuté et du condensateur sommateur sont égales. Le temps (1 musec) alloué pour, soit décharger le condensateur commuté (SHTLSB+3), soit opérer une redistribution de charge (FHTMSB), est rendu plus court que le temps (4 musec) alloué pour charger le condensateur ...

파이프라인식 연속 아날로그-투-디지털 변환기

... 다중스테이지 아날로그-투-디지털 데이터 변환(multistage analog-to-digital data conversion)을 제공하기 위한 시스템이 개시되며, 이 시스템은 제 1 기준 신호를 이용하여 제 1 수의 최상위 비트들로 아날로그 입력 신호를 프로세싱하고 제 1 스테이지 잔차(residue) 신호를 출력하도록 구성된 제 1 스테이지 유닛; 상기 제 1 스테이지 잔차 신호를 수신하여 제 2 기준 신호를 이용하여 제 2 수의 잔여 최하위 비트들로 프로세싱하도록 구성된 제 2 스테이지 유닛; 수동(passive) 엘리먼트로 상기 제 2 스테이지 유닛 상에서 상기 제 1 스테이지 유닛으로부터 수신된 제 1 스테이지 잔차 신호를 샘플링하도록 구성된 샘플링 유닛; 및 상기 제 1 수의 최상위 비트들 및 상기 제 2 수의 잔여 최하위 비트들의 결합인 디지털 값을 출력하도록 구성된 출력 유닛을 포함한다.

METHOD AND APPARATUS FOR USE IN SWITCHED CAPACITOR SYSTEMS

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

MEANS FOR COMPENSATING A DATA-DEPENDENT SUPPLY CURRENT IN AN ELECTRONIC CIRCUIT

Electronic circuitry comprising a data processing circuit for processing a digital signal (DS), such as a digital to analog converter (DAC), and a current compensation circuit (CMP). Both the digital to analog converter (DAC) and the current compensation circuit (CMP) are powered by a single power supply (U1). The current taken from the power supply (U1) by the digital to analog converter (DAC) is normally dependent on the digital input signal (DS). This would lead to distortion since the loss-resistances (Rl1, Rl2) which are always present in series with the power supply (U1) then feed a data-dependent supply voltage (U2) to the digital to analog converter (DAC). This problem is overcome by the addition of the current compensation circuit (CMP) which is coupled for receiving the digital signal (DS). The current compensation circuit (CMP) is arranged in such a way that the sum of the data-dependent current drawn by the digital to analog converter (DAC) and the data-dependent current drawn ...

POTENTIAL GENERATING DEVICE

A device which can generate an accurate and stable potential. A D/A converter using binary-weighted (2n) capacitors is constituted by shifting the actual capacitance ratio from 2n. When the D/A converter is used, the capacitance ratio among a plurality of weighted capacitances (C1-C6) fluctuates and, even when the fluctuation becomes the worst, the value of the j-th capacitance is ensured to be larger than the sum of the values of all capacitances from the first one to the (j-1)-th one and, therefore, the "output inversion" of the D/A converter can be prevented surely. In addition, no such additional circuit as the correction circuit, etc., is required and the D/A converter can be manufactured easily at a low cost.

MULTI-INPUT OPERATIONAL AMPLIFIER CIRCUIT, DIGITAL/ANALOG CONVERTER USING SAME, AND DRIVER FOR DISPLAY DEVICE USING SAME

A multi-input operational amplifier circuit operable with a high degree of accuracy and in a small area, a D/A converter using the multi-input operational amplifier circuit, and a drive circuit or driver for a display device, using the D/A converter. In embodiments of the multi-input operational amplifier circuit, a constant current source of a third differential amplifier circuit that causes a doubled constant current i×2 to flow with respect to constant current sources of first and second differential amplifier circuits by application of two types of bias voltages thereto is configured using PMOS of the same number and size. Therefore, operations equivalent to those of a conventional circuit may be realized by the three constant current source PMOSs, and a smaller chip size may be required.

Differential fuse circuit and method utilized in an analog to digital converter

A differential fuse circuit 10 is disclosed herein. A first fuse 12 and a second fuse 14 are coupled to a supply potential VDD (e.g., five volts). Circuitry 16 and 18 for blowing the two fuses 12 and 14 is also provided. A current mirror 46 including a first leg and a second leg is also provided. The current mirror 46 is designed so that a current through the first leg will induce a current in the second leg. The first leg is coupled between the first fuse 12 and a reference potential VSS and the second leg is coupled between the second fuse 14 and the reference potential VSS. An output node 56 is provided between the second fuse 14 and the second leg of the current mirror 46. A differential sense circuit 24 may also be included between the fuses 12 and 14 and the current mirror 46. During operation, the output node is at a potential substantially near the reference potential when the first fuse has a resistance greater than the second fuse and the output node is at a potential substantially ...

Multiplication circuit for multiplying analog inputs by digital inputs

A multiplication circuit for multiplying an analog input by a digital input. The digital input has a plurality of bits. The circuit has a circuit input terminal for receiving the analog input and a circuit output terminal for outputting the results of multiplication of the analog input by the digital input. The circuit also has a plurality of capacitances and a plurality of switching devices.

Digital to analog converter for sigma delta modulator

A second order sigma delta modulator (10) includes a digital to analog converter (26) that provides feedback for system modulation. The digital to analog converter (26) employs a dynamic element matching circuit (72) which randomly selects among main capacitors (Cj) to reduce the effect of capacitor value mismatching. The digital to analog converter (26) also employs a self calibration circuit (80) to trim the values of the main capacitors (Cj) to obtain better capacitor matching. During self calibration, a clock signal (frand) driving a pseudo random number generator (74) of the dynamic element matching circuit (72) is reduced to assist in minimizing variance in a digital output signal for accurate calibration of the main capacitors (Cj). Upon completion of calibration, the clock signal (frand) is returned to a frequency coinciding with the modulator clock rate.

Apparatus for performing successive steps of simultaneous multi-level analog to digital conversion

An A/D converter including a first inverter having a linear characteristic and receiving an analog input voltage, a first quantizing circuit for quantizing the analog input voltage, a capacitive coupling to which an output of the first inverter and the first quantizing circuit are inputted, a second inverter receiving an output of the capacitive coupling and having the same characteristic of the first inverter, and a second quantizing circuit for receiving and quantizing an output of the second inverter. The A/D converter performs successive steps of quantizing/digitizing so as to achieve A/D conversion.

Semiconductor device, and operating device, signal converter, and signal processing system using the semiconductor device

In a semiconductor device in which one terminal of each of several capacitors is connected to a corresponding one of multiple input terminals via a switch and the remaining terminals of the capacitors are commonly connected to a sense amplifier, the output from the sense amplifier is connected to at least one of the multiple input terminals, thereby reducing the circuit scale, improving the operation speed, and saving power.

Digital-to-analog conversion circuit and image display apparatus using the same

A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.

PSEUDO-RANDOM NOISE SIGNAL GENERATOR

A noise generating device comprises a generator (1) including a shift register (1a) which performs shift operations to sequentially shift a bit in an input stage to a next higher significant stage. An exclusive-OR circuit (1b) performs exclusive-OR operations between a pair of bits from selected stages of the shift register and feeds back to the input stage of the shift register. A filter (2) receives the pseudo-random data and outputs an analog signal. The filter comprises an operational amplifier (2a). Respective outputs of the stages of the shift register are alternately applied to non-inverting and inverting inputs of the operational amplifier through respective resistors (R1, . . . ,R23).

Capacitor array for a successive approximation register (SAR) based analog to digital (A/D) converter and method therefor

A capacitor array for a Successive Approximation Register (SAR) based Analog to Digital (A/D) converter. The capacitor array is a capacitive ladder comprising a plurality of capacitive branches. Each capacitive branch is individually coupled to a separate bit of a driver circuit. Each of the plurality of capacitive branches drives an approximately same capacitive value while generating a binary weighted output voltage.

Digital-to-analog converter with binary coded inputs to produce a plurality of outputs in the form of thermometer code

Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits. When the binary value additionally includes binary bits of even greater binary ...

Device and method for low non-linearity analog-to-digital converter

An apparatus and method for converting an analog signal to a digital signal. The apparatus includes a plurality of capacitors. The plurality of capacitors includes at least a first capacitor, a second capacitor and a third capacitor. The first capacitor is associated with a first capacitance, a second capacitor is associated with a second capacitance, and a third capacitor is associated with a third capacitance. The first capacitance is substantially equal to the second capacitance, and the second capacitance is substantially equal to the third capacitance. Additionally, the apparatus includes a plurality of resistors. The plurality of resistors includes at least a first resistor and a second resistor. Moreover, the apparatus includes an operational amplifier.

Analog to digital converter device and capacitor weight calibration method

An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

High-accuracy capacitor digital-to-analog converter

A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2^N capacitors and 2^N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2^N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Differential non-linearity correction scheme

Differential non-linearity errors in an A/D converter are corrected by an analog system. The system produces different analog voltages which are used to correct the input voltage to the capacitor. The input voltage is changed by an amount which is effective to correct the CDeltaV to be the same as it would have been if the DNL error had not occurred.

Digital/analog converter

Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Iratrix (9) comprising capacitor cells (13ij) which are arranged in matrix form in columns and rows and are driven by thermometer-coded control signals via control lines; a first coding device (6) for recoding the n more significant data bits of the data word D to be converted into a thermometer-coded column control signal which has a width of 2n bits and is applied to the capacitor cell matrix (9) via column control lines (8), a second coding device (11) for recoding the m less significant data bits of the data word D to be converted' into a thermometer-coded row control signal which has a width of 2 bits and is applied to the capacitor cell matrix (9) via row control lines (12), each capacitor cell (13ij) of the capacitor cell matrix (9) in each cast having an associated local decoding circuit (1911) which drives switches (34, 35, 36, 37) in a manner dependent on the ...

Multiplying digital-to-analog converter

A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample ...

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

REFERENCE VOLTAGE BUFFER CIRCUIT

A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

Correction circuit for D/A converter

There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted to control a current flowing to the constant current source in accordance with an input digital signal to the D/A converter, so as to reduce a variation of a sum of currents which, when the input digital signal to the D/A converter is changed, flows to the low-potential power source line from the high-potential power source line through the D/A converter and the constant current source, respectively.

METHOD OF APPLYING A DITHER, AND ANALOG TO DIGITAL CONVERTER OPERATING IN ACCORDANCE WITH THE METHOD

An ADC stage is disclosed which comprises an ADC part and a DAC part. Both the ADC and the DAC receive the input signal. A dither can be applied solely to the DAC part or different dithers can be applied to the ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.

Active matrix display device

An active matrix display device comprising a source signal line drive circuit (501) comprising a shift resister circuit (501-1), a latch circuit (501-2), and a D/A converter circuit (501-5) for converting "n" bit digital data ("n": natural number) to analog signals, a gate signal line drive circuit (503), an active matrix circuit (504) comprising a plurality of first thin film transistors wherein respective bits of said "n" bit digital data control a switch and control charge and discharge of electric charges in a capacitance connected to said switch and analog signals are outputted with an offset voltage used as a reference potential wherein said D/A converter circuit comprises a plurality of second thin film transistors which are formed over a same substrate as said plurality of second thin film transistors.

SYSTEM AND METHOD FOR BIASING ACTIVE DEVICES

Liquid crystal display control system

The liquid crystal display control system of the invention comprises a liquid crystal panel, plural data latch means for storing digital gray scale data, and plural DA converters for converting the outputs of the data latch means into analog signals to be applied to the liquid crystal panel. According to the liquid crystal display control system of the invention, the display data is digital signals, and the digital signals are processed up to the DA converters just before the liquid crystal panel. Afterwards, the digital signals are converted into analog signals in the horizontal display period of relatively slow operating speed, and therefore the analog circuits having many adjusting points may be saved. Accordingly, the adjusting positions are reduced, and the adjusting process in mass production is simplified. In the case of large screen display, in particular, although the data transfer speed is high, since the display data are digital signals, a high display quality is obtained by ...

SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

DIGITAL LOG ANALOG UMSETZER

Analog-Digitalumsetzer

Mehrmoden-Analog/Digitalwandler und Verfahren

Digital Analogwandler

Halbleiterschaltung und ihre Anwendung in einer Operationsschaltung, einem Signalwandler und einem Signalverarbeitungssystem

EXPONENTIELLE VERSTAERKUNGSREGELUNG FUER NICHTLINEAREN ANALOG-DIGITALWANDLER.

Digital-to-analogue converters

A method of converting an input signal b(0) to b(3) to a corresponding analogue output voltage vp moves the output voltage from a first value to a second value, wherein the second value corresponds with the value of the digital input signal and the output voltage is moved from the first value to the second value in at least two steps. Capacitors 37 are selectivey charged during clock phase ck1. During clock phase ck2 charged from the three least significant capacitors is transferred to capacitor 41. During clock phase ck3 charge from the most significant capacitor 37 is transferred to capacitor 41. Capacitor 41 is partially discharged during clock phase ck4 and then fully discharged during clock phase ck1. The digital to analogue converter output may be fed to a liquid crystal display.

VARIABLE RESISTORS

Self-calibration method for capacitors in a monolithic integrated circuit

A method of adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors 20-24 in parallel with a primary capacitor 14 and determining, as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance CREF. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor 20-24 has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance 16, the final resultant capacitance is connected in parallel with the reference capacitance CREF to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor 16 until the final resultant capacitance associated with each primary capacitor 14, 16, 18 has been adjusted. Capacitance ...

DIGITAL TO ANALOGUE CONVERTER

An interpolation DAC includes first and second registers 12, 24 which receive the X least significant and Y most significant bits of a digital input word and are clocked at a first clock rate C2. A third register 16 is coupled to an adder 14 and is clocked at a second clock rate C1 which is faster than the first clock rate C2 by a factor equal to the desired oversampling ratio. A Y bit plus 1 bit DAC 30A in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register 24. The duplicate LSB is connected to receive the carry output from the adder 14. A low pass filter 32 is connected to the output of the DAC 30A to produce an analog output representative of the digital input word. The digital-to-analog conversion rate of the Y bit section of the Y bit plus 1 bit DAC 30A can be performed at the slow first clock rate C2. ...

Sign-magnitude DAC

A modified sign-magnitude DAC includes first internal DAC circuitry including a first number of bit switch circuits responsive to an input word including a sign bit and a digital data word. Each bit switch circuit is coupled to a corresponding current source transistor. Second internal DAC circuitry includes the same number of bit switch circuits responsive to the input word. Each bit switch circuit of the second internal DAC circuitry is coupled to a corresponding current source transistor. The same number of binarily weighted bit current determining resistor circuits corresponding to bits of the digital data word are connected to a reference voltage conductor. The emitter of the current source transistor of each bit switch circuit of the first internal DAC circuitry is coupled by a first gain balancing resistor to the corresponding bit current determining resistor. The emitters of the current source transistor of each bit switch circuit of the second internal DAC circuitry is connected ...

A switched capacitor DAC

A switched capacitor digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, comprises a plurality of capacitors (C1 ...C,,), the lower plate of each capacitor is connectable, dependent on a respective bit of the input digital code, to either a first reference voltage (V2) or a second reference voltage (V3) different from the first reference voltage. The converter also comprises at least one further capacitor (Cp), and a switching arrangement 18,19 for connecting the lower plate of the or each first further capacitor to either a third reference voltage or a fourth reference voltage different from the third reference voltage. The input to the first switching arrangement is independent of the input digital code. The third reference voltage may be equal to the first reference voltage, and the fourth reference voltage may be equal to the second reference voltage. In the decoding phase, the output voltage of the converter 13 floats to a ...

DIGITAL-TO-ANALOGUE CONVERTER

... 1,212,920. Digital/analogue converters. SIEMENS A.G. 20 Dec., 1968 [23 Dec.. 1967], No. 60859/68. Heading G4H. In a non-linear digital/analogue converter the output signal represents the product of two quantities derived from the input digits. In the embodiment of Fig. 3 the lower of two decimal digits is converted into a signal on one of 10 leads controlling transistor switches 5 in a decoder 8 so that a resistor is connected between a potential source and the input of an operational amplifier 1 in the feedback loop of which is a converter responsive to the second digit to transmit the feedback signal through an associated resistance. In a modification (Fig. 4, not shown) the decoder in the amplifier input comprises switches responsive to a code representing the decimal digit.

COMPENSATED CAPACITORS FOR SWITCHED CAPACITOR INPUT TO AN ANALOG-TO-DIGITAL CONVERTER

VARIABLE CONDENSER

SILVER-SHEAR A/D AND D/A TRANSDUCER.

SILVER-SHEAR A/D AND D/A TRANSDUCER.

DIFFERENTIAL ANALOGUE-DIGITAL CONVERTER

HIGH-SPEED, HIGHLY SOLUBLE AND ENERGY-SAVING ANALOG/CDIGITAL TRANSDUCER WITH ASYMMETRICAL ENTRANCE

MEANS FOR THE COMPENSATION OF A DATA SENSITIVE SUPPLY CURRENT IN AN ELECTRONIC CIRCUIT

D/a conversion method and d/a converter

FIELD-EFFECT TRANSISTOR CURRENT SWITCHING CIRCUIT

FIELD-EFFECT TRANSISTOR CURRENT SWITCHING CIRCUIT An MOS current steering circuit (10) includes a current mirror arrangement with an input branch (12) and an output branch (16). In the input branch, the conduction channels of a current-limiting transistor (M1) and a current mirror input transistor (M3) are connected in series with each other between a first power supply voltage node V+ and one side of a current source (14). The other side of the current source and the gate of the current-limiting transistor are connected to another supply voltage node (V-). In the output branch, a current mirror output transistor (M4) has one side of its conduction channel connected as a current output node (D). The gates of the input and output transistors are connected together and to the common node (A) of the input transistor and the current source. A control transistor (M2) has its conduction channel connected between the other side of the output transistor and the first voltage supply node. The control ...

DIGITAL-TO-ANALOG CONVERTER

A digital-to-analog converter of a current addition type using weighted resistors, includes an input resistor network (4) for providing a resistance dependent on a digital input signal having a predetermined number of bits, and an adder (3) having a first input terminal coupled to the input resistor network and a second input terminal connectable to receive a reference potential, for adding a signal obtained at the first input terminal and the reference potential. The adder also has an output terminal via which a result of an adding operation is output, and the result of the adding operation shows an analog signal corresponding to the digital input signal. The digital-to-analog converter also includes a feedback resistor network (5) provided between the first input terminal and the output terminal of the adder, the feedback resistor network providing a feedback resistance dependent on a control signal indicating a magnitude of the digital input signal, and a feedback resistor network control ...

Programmable input range adc

Systems of coding of impulses

Systems of coding of impulses

APPAREIL ET PROCEDE POUR LA CORRECTION DE LA TENSION DE DECALAGE DANS UN CONVERTISSEUR ANALOGIQUE-NUMERIQUE.

On décrit un convertisseur analogique-numérique à redistribution de charges, qui permet d'incorporer la correction de la tension de décalage pour réaliser une réflexion exacte du signal analogique d'entrée dans le signal numérique de sortie. Dans un dispositif d'approximations successives, à des condensateurs répartis, aussi bien en un groupe de condensateurs 41 du système relatif au bit le plus significatif qu'en un groupe de condensateurs 43 du système relatif au bit le moins significatif, sont ajoutés d'autres condensateurs 42, 44 qui sont utilisés en relation avec la tension de décalage. La valeur de la tension de décalage est mémorisée dans un registre et le registre détermine différentes positions d'interrupteurs S20-S27, S31-S34, S50-S54, S61-S64 qui déterminent la valeur de la tension d'entrée incorporée dans la tension de sortie finale. (CF DESSIN DANS BOPI) ...

[...]-CALIBRATION METHOD FOR CAPACITORS IN A MONOLITHIC INTEGRATED CIRCUIT

Analogical transmitter of position and direction of rotation

L'invention concerne un dispositif permettant de coder et de transmettre à distance une information de position et de sens de rotation d'un élément tournant. Ce dispositif comprend un encodeur (6) piloté par des capteurs (2a, 2b; 3a, 3b) propre à produire un signal analogique dont l'amplitude varie, à chaque changement d'état de chaque capteur, d'une valeur qui dépend de ce capteur. Application aux compteurs d'électricité.

DIGITAL-TO-ANALOG CONVERTER HAS INTERPOLATION AND PROCEEDED OF SETTING IN ÓOEUVRE.

L'invention concerne les convertisseurs numérique-analogique de haute précision. Un convertisseur numérique-analogique à interpolation comprend notamment un additionneur ayant un premier groupe (13) de X entrées recevant X bits de moindre poids (B0 -B3 ) du mot d'entrée numérique, et un second groupe (17) de X entrées; un registre (16) ayant X entrées connectées à X sorties de l'additionneur, et ayant également X sorties (17) connectées au second groupe de X entrées de l'additionneur; un convertisseur numérique-analogique à Y bits plus 1 bit (30A); et un filtre passe-bas (32) connecté à la sortie du convertisseur pour produire un signal de sortie analogique représentatif de la valeur du mot d'entrée numérique. Application aux systèmes audio numériques. The invention relates to high precision digital-to-analog converters. An interpolation digital-to-analog converter notably comprises an adder having a first group (13) of X inputs receiving X least significant bits (B0 -B3) of the digital input word, and a second group (17) of X inputs; a register (16) having X inputs connected to X outputs of the adder, and also having X outputs (17) connected to the second group of X inputs of the adder; a Y bit plus 1 bit digital to analog converter (30A); and a low pass filter (32) connected to the output of the converter to produce an analog output signal representative of the value of the digital input word. Application to digital audio systems.

Digital to analogue converter and method of operating the same

Method inspection of active matrix substrate, active matrix substrate, liquid crystal device and electronic apparatus

듀얼-스트링 디지털-아날로그 변환기들(DAC들), 및 관련 회로들, 시스템들 및 방법들

... 듀얼-스트링 디지털-아날로그 변환기들(DAC들), 및 관련 회로들, 시스템들 및 방법들이 개시된다. 본 명세서에 개시된 실시예들에서, 듀얼-스트링 DAC의 주 분압기는 적어도 하나의 조절 회로로 구성된다. 조절 회로는, 주 스위치 유닛이 선택된 저항기 노드 쌍을 선택하는 것에 대한 응답으로, 보조 분압기 회로에 걸친 선택된 저항기 노드 쌍의 이상적 전압을 유지하도록 구성된다. 이러한 방식으로, 듀얼-스트링 DAC의 주 분압기와 보조 분압기 회로 사이에 임피던스 분리가 요구되지 않는다. 결과적으로, 비제한적인 예로, 듀얼-스트링 DAC에 대한 집적 회로(IC) 상의 면적이 감소될 수 있고, DAC의 전력 소모가 감소될 수 있고, 그리고/또는 듀얼-스트링 DAC가 안정 시간을 요구하지 않음으로 인해 증가된 성능을 가질 수 있다.

Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter

The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.

Programmable linearity correction circuit for digital-to- analog converter

The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

Low-power area-efficient sar adc using dual capacitor arrays

An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Charge redistribution digital-to-analog converter

Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Digital step attenuator utilizing thermometer encoded multi-bit attenuator stages

A digital step attenuator with thermometer encoded attenuator stages is disclosed. In one embodiment, Embodiments disclosed in the detailed description may include a digital step attenuator, programmable thermometer encoded attenuator stages, the digital step attenuator may include a cascade of programmable thermometer encoded attenuator stages. Each stage may be provided by a programmable impedance array including a plurality of impedances arranged in parallel. The impedance of each of the plurality of each stage may change monotonically by switchably inserting or removing one of the plurality of impedances in the arrays. The control circuit may govern the attenuation level of each of the thermometer encoded accumulator stages as a function of a thermometric codeword, which controls the switches in the arrays.

Digital-to-Analogue Converter and Neuromorphic Circuit Using Such a Converter

A digital-to-analogue converter, with application to electronic circuits with neuromorphic architecture, comprises: transistors of identical nominal geometrical characteristics, but of dispersed current-voltage characteristics, wherein when a constant gate-source voltage is applied to the different transistors, a current varying as a function of the dispersion circulates in the transistor; a digital table receiving a digital word and having a selection output selecting, as a function of the word to be converted, a transistor or transistors supplying a current of desired value representing this word in analogue form. The look-up table is loaded as a function of real measured current-voltage characteristics of different transistors of the set, to establish a look-up between words and current values. The wide variability of characteristics of the transistors, notably their leakage current for a gate-source voltage below the switch-on threshold, allows finding combinations of leakage currents which are a good representation of words to be converted. 1. A digital-to-analogue converter , comprising:a set of several transistors of identical nominal geometrical characteristics but of dispersed current-voltage characteristics such that, when a constant gate-source voltage is applied to the different transistors, a current that is variable as a function of the dispersion circulates in the transistor,a digital look-up table having a digital input for receiving a word to be converted and a selection output for selecting from the set of transistors, as a function of the word to be converted, a transistor or a group of transistors supplying a current of desired value representing this word in analogue form,a current output supplying the current delivered by the selected transistor or group of transistors, all receiving a nominal gate-source voltage, andmeans for loading into the digital look-up table, at a determined address, a datum determining the selection of the transistor or ...

DIGITAL-TO-ANALOG CONVERTER CIRCUITRY WITH WEIGHTED RESISTANCE ELEMENTS

Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element. 1. Digital-to-analog converter circuitry , comprising: a switch coupled to a reference voltage; and', 'a T-network coupled to the switch, wherein the T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element., 'a plurality of weighted resistance elements, wherein a first weighted resistance element comprises2. The digital-to-analog converter circuitry of claim 1 , wherein the T-network comprises:a first resistance coupled to the switch;a second resistance coupled to the first resistance; anda shunt resistance coupled to the first resistance and to the second resistance.3. The digital-to-analog converter circuitry of claim 2 , wherein the T-network further comprises:a third resistance coupled to the shunt resistance; anda fourth resistance coupled to the third resistance and to the shunt resistance.4. The digital-to-analog converter circuitry of claim 3 , wherein the switch is a first high switch claim 3 , the reference voltage is a high reference voltage claim 3 , and the first weighted resistance element further comprises:a first low switch coupled to a low reference voltage and to the first resistance;a second high switch coupled to the high reference voltage and to the third resistance; anda second low switch coupled to the low reference voltage and to the third resistance.5. The digital-to-analog converter circuitry of claim 1 , wherein the plurality of weighted resistance ...

CIRCUIT DEVICE, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more. 1. A circuit device adapted to perform A/D conversion on an analog input signal , comprising:a control circuit having a successive approximation register adapted to hold successive approximation data;a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register; anda comparison circuit adapted to perform a comparison process between the analog input signal and an output signal from the D/A conversion circuit, includes an upper limit value register adapted to hold an upper limit value of a conversion range of A/D conversion result data obtained by the A/D conversion of the analog input signal, and a lower limit value register adapted to hold a lower limit value of the conversion range, and', 'performs at least one of an update of increasing the upper limit value and an update of decreasing the lower limit value in a case in which the comparison circuit has output a same comparison result a predetermined number of times or more in a successive approximation process., 'wherein the control circuit'}2. The circuit device according to claim 1 , whereinin a case in which the comparison circuit has output a same comparison result the predetermined number of times or more from a first comparison in ...

CAPACITIVE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code. 1. A capacitive successive approximation analog-to-digital converter , comprising:a first capacitor array comprising N first capacitors, wherein N is a number of bits of a binary code output by the capacitive successive approximation analog-to-digital converter, and N is a positive integer greater than or equal to 3;a second capacitor array comprising N second capacitors;a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage, wherein the first voltage is determined according to the common mode voltage and the reference voltage, and the second voltage is determined according to the common mode voltage and a ground voltage;a first switch connected between the voltage generation circuit and upper plates of the N first capacitors;a second switch connected between the voltage generation circuit and upper plates of the N second capacitors;N third switches correspondingly connected to lower plates of the N first capacitors ...

2-PHASE SWITCHED CAPACITOR FLASH ADC

An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference 1. An input stage for a switched capacitor analog-to-digital converter , comprising:a switching unit comprising a plurality of switching devicesa differential voltage input receiving an input voltage;a differential reference voltage input receiving a chopped reference voltage;a common voltage connection;a differential output;a pair of input capacitors coupled between the differential voltage input and the differential output via a first switching device of the plurality of switching devices;a pair of reference capacitors coupled between the differential reference voltage input and the differential output via a second switching device of the plurality of switching devices; during the first phase to connect first terminals of the input capacitors via a third switching device of the plurality of switching devices with the common voltage connection and couple first terminals of the reference capacitors via the second switching device with an inverted chopped reference voltage ; and', 'during a second phase to ...

Digital to analog converter with output impedance compensation

A digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.

Digital-to-Analog Conversion Circuit

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

A/d conversion device

An A/D conversion device, which operates in one mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

HIGH-PRECISION ANALOG-TO-DIGITAL CONVERTER AND DNL-BASED PERFORMANCE IMPROVEMENT METHOD

The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter. 1. A high-precision analog-to-digital converter , comprising a redundant weight capacitor array , a comparator , a code reestablishment circuit , a weight storage circuit and a control logic circuit; whereinthe redundant weight capacitor array receives external input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− under the control of the control logic circuit, supplies the output voltages Vout+ and Vout− to the comparator for comparison, and controls each bit of capacitor to participate in a voltage addition and subtraction operation in sequence under the control of the control logic circuit according to a comparison result of the comparator to regenerate output voltages Vout+ and Vout− which are supplied to the comparator for comparison, repeating as such until a last bit of capacitor completes the voltage addition and subtraction operation, and the redundant weight capacitor array is combined with the weight storage circuit to implement digital correction of a capacitor mismatch error, thereby preventing code missing for the analog-to ...

PIPELINED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

A pipelined successive approximation register analog-to-digital converter (), SAR ADC, comprises a first SAR ADC stage (); an inter-stage amplifier () for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage () input from the inter-stage amplifier, wherein the inter-stage amplifier () comprises one or more MOS transistors (), wherein the source and drain terminals of each of the one or more MOS transistors () are connected to each other and may be toggled between ground and a supply voltage. 1. A pipelined successive approximation register analog-to-digital converter , SAR ADC , comprising:a first SAR ADC stage;an inter-stage amplifier for amplifying an analog residue from said first SAR ADC stage; anda second SAR ADC stage input from said inter-stage amplifier, wherein said inter-stage amplifier comprises one or more MOS transistors, wherein the source and drain terminals of each of said one or more MOS transistors are connected to each other and may be toggled between ground and a supply voltage.2. The pipelined SAR ARC of claim 1 , wherein said one or more MOS transistors comprise a complementary pair consisting of an NMOS transistor and a PMOS transistor.3. The pipelined SAR ADC of claim 1 , implemented in CMOS technology.4. The pipelined SAR ADC of claim 1 , wherein said second SAR ADC stage comprises an input capacitor connected to the gate terminal of each of said one or more MOS transistors.5. The pipelined SAR ADC of claim 1 , wherein at least one of said first SAR ADC stage and said second SAR ADC stage is a charge redistribution SAR ADC stage.6. The pipelined SAR ADC of claim 1 , wherein each of said first SAR ADC stage and said second SAR ADC stage is a charge redistribution SAR ADC stage.7. A method of analog-to-digital conversion of an analog level claim 1 , comprising:performing a first successive approximation analog-to-digital conversion of said analog level; inputting said analog residue on the gate terminal of one ...

Digital-analogue converter for multi-threshold counters with partitioning of the bits between resistor ladder and comparator

An X-ray detector includes an N-channel digital-analogue converter controllable with K+L bits. In an embodiment, the digital-analogue converter includes a first voltage source to provide a plurality of first voltage values at tapping points; and a switch unit with N switch matrices, 2 K inputs of the switch matrices being electrically conductively connected to 2 K tapping points of the first voltage source. The digital-analogue converter also includes a second voltage source including N subunits. The X-ray detector further includes a discriminator unit including N comparators, at least one input of the comparators being electrically conductively connected to the associated output of the switch matrix and/or to the associated output of the subunit, so that the associated first voltage value and the associated second voltage value are associable with each comparator. A signal of an output of a pre-amplifier, and the associated first and second voltage values are comparable in the comparator.

CONSTANT CURRENT DIGITAL TO ANALOG CONVERTER SYSTEMS AND METHODS

An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals. 1. An electronic device comprising: receive a plurality of digital signals; and', 'output a plurality of analog signals based at least in part on the received plurality of digital signals; and, 'a digital to analog converter configured toa power source configured to supply current to the digital to analog converter; a first resistor ladder section configured to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series; and', 'a second resistor ladder section configured to electrically couple the output node to a reference voltage via a second number of resistors in series, wherein a sum of the first number of resistors in series and the second number of resistors in series is the same for each of the plurality of analog signals., 'wherein the digital to analog converter comprises2. The electronic device of claim 1 , wherein the digital to analog converter comprises:a first plurality of switches configured to electrically couple the output node to the power source via the first number of resistors in series; anda second plurality of switches configured to electrically couple the output node ...

Five-Level Switched-Capacitance DAC Using Bootstrapped Switches

A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated. 1. An apparatus , comprising: a differential reference voltage;', 'a pair of capacitors;', 'a plurality of switches including a shorting switch; and', the plurality of switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input, wherein the specific switches activated and deactivated in each phase are selected according to the digital input;', 'each capacitor of the pair of capacitors is connected to a respective pin for the output;', 'the shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors; and', 'the shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated., 'wherein], 'a charge transfer digital-to-analog converter (DAC), the DAC comprising2. The apparatus of claim 1 , further comprising a voltage follower circuit configured to provide input into the shorting switch.3. The apparatus of claim 2 , wherein the voltage follower circuit is ...

PSEUDO DIFFERENTIAL RECEIVING MECHANISM FOR SINGLE-ENDED SIGNALING

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry. 1. A circuit comprising:a first input configured to receive a first signal;a second input configured to receive a termination voltage; receive the first signal on a first end; and', 'receive the termination voltage on a second end; and, 'a resistor coupled to receive the first signal on a first terminal;', 'receive the termination voltage on a second terminal; and', 'generate a second signal based on a comparison of a voltage of the first signal to the termination voltage., 'a sense amplifier configured to2. The circuit as recited in claim 1 , wherein each of the resistor and the sense amplifier has an input dependent on a same power supply.3. The circuit as recited in claim 1 , wherein extracting a common mode signal of the first signal comprises receiving the termination voltage on the second end of the resistor from the second input.4. The circuit as recited in claim 1 , wherein the first signal is a single-ended data signal.5. The circuit as recited in claim 1 , wherein the termination voltage is one half of a supply voltage used within the circuit.6. The circuit as recited in claim 1 , wherein the termination voltage is routed to inputs of a plurality of external circuits.7. The circuit as recited in claim 1 , wherein the circuit further comprises electrostatic ...

CIRCUITS AND METHODS FOR REDUCING CHARGE LOSSES IN SWITCHED CAPACITOR ANALOG TO DIGITAL CONVERTERS

Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC. 1. A circuit comprising:a first capacitor coupled between a first sampling terminal and a first summing terminal;a second capacitor coupled between a second sampling terminal and a second summing terminal;first NMOS and PMOS transistors coupled in parallel, the first and second PMOS transistors configured to electrically disconnect the first and second sampling terminals during a sampling phase and to electrically connect the first and second sampling terminals during a transfer phase;a third capacitor coupled between the first summing terminal and a first DAC terminal;a fourth capacitor coupled between the second summing terminal and a second DAC terminal;second NMOS and PMOS transistors coupled in parallel, the second NMOS and PMOS transistors to electrically connect a first DAC output and the first DAC terminal during the transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase;third NMOS and PMOS transistors coupled in parallel, the third NMOS and PMOS transistors to electrically connect a second DAC output and the second DAC terminal during the transfer phase and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase,wherein respective gate signals are configured to be applied to gate terminals of the first, second and third PMOS transistors, and wherein the gate signal configured to be applied to the first PMOS transistor has a ...

DYNAMIC COMPARATOR

The present description relates to a comparator () comprising a ring of gates (A, B, A′, B′, ) in series, wherein: each gate implements an inverting function between a first input () and an output () of the gate; at least one (A′, B′) gate is controllable and is associated with another gate; each controllable gate (A′, B′) comprises a control input () coupled with the output () of said associated gate, and prevents switching of its output () to a high state if its control input () is in the high state, and to a low state otherwise; and the control input () of each controllable gate (A′, B′) receives the output () of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not. 1. A dynamic comparator of a first voltage with a second voltage , of the edge pursuit type , comprising a ring of logic gates in series , wherein:each gate of the ring comprises a first input connected to an output of the preceding gate of the ring;each gate of the ring is configured to implement an inverting function between its first input and its output;at least one of said gates of the ring is controllable and is associated with another one of said gates of the ring;each controllable gate comprises a control input coupled to the output of the gate associated with said controllable gate;each controllable gate is configured to prevent switching of its output to a high state when its control input is in the high state, and to a low state when its control input is in the low state;the control input of each controllable gate is configured to receive the state of the output of the gate associated with said controllable gate if an even number of gates of the ring separates the controllable gate from said associated gate, and to receive the complementary state of said output if not; andthe ring has an even number of logic gates.2. The comparator according to claim 1 , wherein each controllable gate is separated from the gate ...

DIGITAL-TO-ANALOG CONVERSION CIRCUIT

A digital-to-analog conversion circuit, comprising: an R−2R resistive network () configured to be connected between an output end and a ground end; an output voltage selection unit () configured to be connected between the output end of the R−2R resistive network () and a voltage output terminal; an output voltage trimming unit (), wherein the output voltage trimming unit () is provided between a 2R resistor on at least one branch of the R−2R resistive network () and the ground end. 1. A digital-to-analog conversion circuit , comprising:an R−2R resistive network configured to be connected between an output terminal and a ground terminal;an output voltage selection unit configured to be connected between an output terminal of the R−2R resistive network and the output terminal;an output voltage trimming unit, wherein the output voltage trimming unit is provided between a 2R resistor and the ground terminal on at least one branch of the R−2R resistive network.2. The digital-to-analog conversion circuit according to claim 1 , wherein the output voltage selection unit comprises 2selection resistors connecting in parallel with each other claim 1 , each selection resistor is connected to a reference voltage or the ground through a single-pole double-throw switch.5. The digital-to-analog conversion circuit according to claim 2 , further comprising: a first decoder claim 2 , configured to control 2single-pole double-throw switches according to input digital signals.6. The digital-to-analog conversion circuit according to claim 1 , wherein the output voltage trimming unit comprises 2−1 trimming resistors connected in series claim 1 , and each node between the trimming resistors is connected to the ground terminal through a control switch.8. The digital-to-analog conversion circuit according to claim 6 , further comprising: a second decoder claim 6 , configured to control m*2control switches according to input digital signals.9. The digital-analog conversion circuit according ...

TWO-STAGE DAC ARCHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT SERIAL CHARGE REDISTRIBUTION DAC

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. 1. A method of converting a M-bit digital input code to an analog output voltage , comprising the steps of:setting high and low reference voltages of high and low reference voltage nodes to selected levels depending on at least a portion of the M-bit digital input code;coupling a first capacitor between a first capacitor charging node and the low reference voltage input node;coupling a termination capacitor between a charge collection node and the low reference voltage input node;deriving a sequence of one-bit control codes from the M-bit digital input code;selectively coupling the first capacitor charging node to one of the low reference voltage input node and the high reference voltage input node during first capacitor charge cycles in response to instances of the one-bit control code from the sequence of one-bit control codes; andcoupling the first capacitor charging node to the charge collection node during charge redistribution cycles that follow the first capacitor charge cycles to redistribute charge with the termination capacitor.2. The method of claim 1 , wherein setting the high and low reference voltages comprises selecting a pair of adjacent reference voltages from a plurality of pairs of adjacent reference voltages.3. The method of claim 2 , wherein the plurality of pairs of adjacent reference voltages includes Y pairs of adjacent reference voltages claim 2 , and wherein setting the high and low reference voltages comprises selecting the pair of ...

Semiconductor device

The present disclosure provides a semiconductor device including: a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.

Reference precharge techniques for analog-to-digital converters

Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

SWITCHED MEMRISTOR ANALOG-TO-DIGITAL CONVERSION

Switched memristor digital-to-analog conversion employs a set of switch-selectable programmed resistances corresponding to a digital-to-analog conversion mapping to convert a digital input into an analog output. The digital input is to establish an analog resistance of a plurality of switched memristors connected in series that are switch selectable. The plurality of switched memristors is to provide the set of switch-selectable programmed resistances in accordance with the digital-to-analog conversion mapping. 1. A switched memristor digital to analog converter (DAC) comprising:a plurality of switched memristors connected in series to provide a set of switch-selectable programmed resistances, a switched memristor of the plurality comprising a memristor connected in parallel with a switch, the switch to select the memristor, the memristor having a programmable analog resistance to provide a programmed resistance of the set of switch-selectable programmed resistances,wherein the set of switch-selectable programmed resistances comprises predetermined programmed resistances to define a digital-to-analog conversion mapping, the switched memristor DAC to convert a digital input into a corresponding analog output according to the digital-to-analog conversion mapping.2. The switched memristor DAC of claim 1 , wherein the switch of the switched memristor comprises a field effect transistor (FET) with a source of the FET connected to a first terminal of the memristor and a drain of the FET connected to a second terminal of the memristor.3. The switched memristor DAC of claim 1 , wherein the digital-to-analog conversion mapping is a linear weighted mapping claim 1 , the predetermined programmed resistances of the set of switch-selectable programmed resistances representing a binary linear weight sequence of resistances.4. The switched memristor DAC of claim 1 , wherein the digital-to-analog conversion mapping is a logarithmic weighted mapping claim 1 , the predetermined ...

Charge-scaling multiplier circuit with dual scaled capacitor sets

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

Analog-to-digital converter and calibration method thereof and calibration apparatus

A calibration method includes the following: providing a first charge quantity to a first input terminal of a comparator; providing a second charge quantity to a second input terminal of the comparator by one of multiple switch capacitor groups, and providing a compensation charge quantity to the second input terminal of the comparator by at least another one of the switch capacitor groups; comparing a voltage value received by the first input terminal and a voltage value received by the second input terminal, and outputting a voltage comparison result to a controller; and if the controller determines the charge quantity provided to the second input terminal approximates to the charge quantity provided to the first input terminal based on the voltage comparison result, recording a calibration charge quantity in a lookup table stored by the controller. An analog-to-digital converter and a calibration apparatus are also provided.

METHOD OF CALIBRATING A SAR A/D CONVERTER AND SAR-A/D CONVERTER IMPLEMENTING SAID METHOD

The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale. 115-. (canceled)16. A method of self-calibration of a successive approximation register-analog to digital (SAR-A/D) converter comprising an N-bit digital-to-analog converter for outputting an N-bit output code , the digital-to-analog converter comprising a first subconverter having a plurality (N) of thermometer elements and a second subconverter having a plurality of binary-weighted elements N , the output code defined by a thermometer scale having a number of levels equal to N , the method comprising:measuring, for each thermometer element of the plurality of thermometer elements, an error value;determining a mean value of the error values;{'sub': 'Th', 'dividing the plurality of thermometer elements into a first subset (X) and a second subset (Y), each containing an identical number of elements (x, y) equal to N/2, wherein the first subset (X) comprises the thermometer elements whose error values are closer to the mean value when a sum of the error values of thermometer elements of the first subset (X) is not more than the error value of the thermometer element farthest from the mean value of the first subset (X), and the second subset (Y) comprises the thermometer elements of the plurality of thermometer elements that are not contained in the first ...

FORCE SENSING SYSTEMS

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled. 138.-. (canceled)39. A compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor , the compensation circuit comprising:voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor;current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; andamplifier circuitry configured to receive a signal output by the force sensor and the compensating current and to output a compensated output signal in which the offset voltage is at least partially cancelled.40. A compensation circuit according to claim 39 , wherein the force sensor is a resistive force sensor claim 39 , wherein the voltage divider circuitry comprises a plurality of ...

SEMICONDUCTOR INTEGRATED CIRCUIT AND ARITHMETIC SYSTEM

According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit. 1. A semiconductor integrated circuit comprising:a global circuit; anda plurality of DA converters connected to the global circuit, a current source,', 'a capacitive element having a first end and a second end, the second end being connected to a node of a reference potential of the DA converter,', 'an amplifier circuit having an input node,', 'a first switch element having a first end connected to the current source and a second end connected to the first end of the capacitive element,', 'a second switch element having a first end connected to the first end of the capacitive element and a second end connected to the node of the reference potential,', 'a third switch element having a first end connected to the first end of the capacitive element and a second end connected to the input node of the amplifier circuit, and', 'a control circuit configured to maintain the second switch element in an on state while maintaining the first switch element and the third switch element both in an off state in a first period, and to maintain the first switch element in an on state while maintaining the second switch element and the third switch element both in an off state in a second ...

Spatial light modulator (slm) comprising integrated digital-to-analog converters

Arrangement for controlling micromechanical actuators, including a digital-to-analog converter and a plurality of micromechanical actuators; wherein the micromechanical actuators are coupled to a connecting structure; wherein the digital-to-analog converter is configured to provide a voltage to be applied to the connecting structure by an adjustable capacitive voltage division that is dependent on a digital input value of the digital-to-analog converter, wherein the digital-to-analog converter is configured to directly include a capacitance of the connecting structure in the capacitive voltage division.

Device, System and Method for Digital-to-Analogue Conversion

Described herein is a device, system and method for digital-to-analogue conversion. One embodiment provides a digital-to-analogue converter device including: a) a first input configured to receive a digital signal to be converted; b) a second input configured to receive a digital dither signal, the digital dither signal having a predefined amplitude; c) a signal combining module that is configured to combine the digital dither signal with the digital signal in the digital domain to define a combined digital signal; and d) a digital-to-analogue converter module that is configured to process the combined digital signal and to output an analogue signal that is an analogue representation of the combined digital signal. The digital-to-analogue converter module has a predefined output amplitude range. The predefined amplitude of the dither signal is at least 1% of the predefined output amplitude range. 2. The device according to wherein the digital dither signal is deterministic.3. The device according to wherein the predefined amplitude of the dither signal is in the range of 10% to 90% of the predefined output amplitude range.4. The device according to wherein the predefined amplitude of the dither signal is in the range of 40% to 60% of the predefined output amplitude range.5. The device according to comprising:an analogue signal modifier that is configured to modify the analogue signal to reduce effects attributable to the digital dither signal based on known properties of the digital dither signal.6. The device according to wherein the analogue signal modifier includes one or more of the following in any combination:a) a low-pass filter;b) a notch filter;c) a signal inverter configured to process the digital dither signal in the digital domain to provide an inverted dither signal as an output wherein the inverted dither signal is the inverse of the digital dither signal, a secondary digital-to-analogue converter configured to process the inverted dither signal to ...

DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACS), AND RELATED CIRCUITS, SYSTEMS, AND METHODS

Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. 1. A primary voltage divider of a dual-string digital-to-analog converter (DAC) , comprising:a primary resistor string having a total resistance, the primary resistor string comprising a plurality of resistor nodes configured to divide a DAC input voltage applied across the primary resistor string into a plurality of divided voltage levels;a primary switch unit configured to receive a DAC input code and select a resistor node circuit among a plurality of resistor node circuits, the resistor node circuit comprising a selected resistor node pair among the plurality of resistor nodes of the primary resistor string based on the DAC input code to couple a divided voltage level across the selected resistor node pair to a secondary voltage divider circuit of the dual-string DAC; andat least one adjusting circuit comprising at least one first fractional resistance to the selected resistor node configured to maintain an ideal voltage of the selected resistor node pair across the secondary voltage divider circuit in response to the primary switch unit selecting the selected resistor node pair, without impedance isolation ...

Analog to digital converter device and capacitor weight calibration method

An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

DISPLAY DRIVER, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS

A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data. 1. A display driver comprising:a first operational amplifier including a first non-inverting input node to which a reference voltage is input, the first operational amplifier being configured to drive a data line of an electro-optical panel;a first D/A conversion circuit including a first variable resistance circuit including one end to which a first voltage is input and another end connected to a first inverting input node of the first operational amplifier;a first resistance circuit provided between the first inverting input node and a first output node of the first operational amplifier;a second operational amplifier including a second non-inverting input node to which a reference voltage is input;a resistance element provided between a second output node of the second operational amplifier and the first inverting input node;a second D/A conversion circuit including a second variable resistance circuit including one end to which a second voltage is input and another end connected to a second inverting input node of the second operational amplifier; anda second resistance circuit provided between the second inverting input node and the second output node, whereina resistance value of the first variable resistance circuit is set based on upper bit data of display ...

RFDAC (RF (RADIO FREQUENCY) DAC (DIGITAL-TO-ANALOG CONVERTER)) WITH IMPROVED EFFICIENCY AND OUTPUT POWER

High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage. 123-. (canceled).24. A Digital-to-Analog Converter (DAC) , comprising: a first DAC stage configured to receive a first input voltage of the plurality of different input voltages, and generate a first analog signal based on the first input voltage; and', 'a second DAC stage configured to receive a second input voltage of the plurality of different input voltages, and generate a second analog signal based on the second input voltage,, 'a plurality of DAC stages configured to receive a digital input signal and a plurality of different input voltages, respectively, comprisingwherein one of the plurality of different input voltages is selected based on an amplitude of the input digital signal.25. The DAC of claim 24 , wherein the selected one of the plurality of different input voltages is the voltage that is a smallest voltage of the plurality of different input voltages that is greater than or equal to the amplitude of the digital signal.26. The DAC of claim 24 , wherein the DAC is a current source ...

DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port. 118-. (canceled)19. A successive approximation register analog-to-digital converter , comprising:a voltage comparator having a first input, a second input, and an output;a first plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the first input of the voltage comparator and switchably connectable to a common mode voltage, and the second plate switchably connectable to one of a first input voltage, a reference voltage, the common mode voltage, or a ground, and the common mode voltage equal to one-half of the reference voltage;a second plurality of capacitors each having a first plate and a second plate, the first plate in electrical communication with the second input of the voltage comparator and switchably connectable to the common mode voltage, the second plate switchably connectable to one of a second input voltage, the reference voltage, the common mode voltage, or the ground, and the first plurality of capacitors and the second plurality of capacitors collectively representing a set of bits; anda controller configured to implement a collapsible successive approximation register algorithm using ternary values for each bit of the set of bits to encode an analog input.20. The successive approximation register analog-to-digital converter of wherein at least a first capacitor of the first plurality of ...

Analog-to-digital converter device

An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

TWO-CAPACITOR DIGITAL-TO-ANALOG CONVERTER

A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion. 1. A two-capacitor digital-to-analog converter circuit , comprising:a phase and mode controller configured to set an active bit in a digital word, select a mode condition for the active bit, and configure switches according to a first mode or a second mode of a conversion process based on a value of the active bit and the selected mode condition;a redistribution switch configured to, during a redistribution phase of the conversion process, couple a first capacitor and a second capacitor together to generate a redistribution voltage;a buffer amp configured to generate an output voltage based on the redistribution voltage, the buffer amp having an input capacitance at an input; and couple, during an input phase of the conversion process, a reference voltage or a ground to the replica input capacitance based on the value of the active bit, and', 'couple, during the redistribution phase of the conversion process, the replica input capacitance to the input capacitance to adjust the redistribution voltage., 'a capacitance ...

CHARGE-SHARING AND CHARGE-REDISTRIBUTION DAC AND METHOD FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit. 1. A hybrid digital-to-analog converter comprising:a charge-sharing digital-to-analog converter configured to receive a digital input signal having a plurality of bits, wherein the plurality of bits include a most-significant-bit and a least-significant-bit, wherein the charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit; anda charge redistribution digital-to-analog converter configured to convert the least-significant-bit to provide a second portion of the analog signal, wherein the charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.2. The digital-to-analog converter of claim 1 , wherein:the charge-sharing digital-to-analog converter is ...

Sensor device

A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a Δ modulation on the analog input signal which is converted into a digital signal.

Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter

A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an MSB, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an LSB and a next to bit of the LSB.

Method of calibrating a thermometer-code sar a/d converter and thermometer-code sar-a/d converter implementing said method

A method of calibrating a thermometer-code SAR-A/D converter is provided. The thermometer-code SAR-A/D converter includes an N bit -bit digital-to-analog converter (DAC) for outputting an N bit -bit output code. The DAC includes a first subconverter having a plurality of N Th thermometer elements T j and a second subconverter having a plurality of N Bin binary-weighted elements. The N bit output code is equal to the sum of N BitTh and N BitBin where N Th =2 N BitTh and N BitBin is equal to N Bin =N BitBin . The calibration method includes determining an Integral Non-Linearity error value (ε R ) of an R th thermometer-code level of the thermometer elements. The method further includes reducing the highest of the error value ε R to obtain a reduced error value, and generating the output code according to said reduced error.

Successive approximation analog-to-digital converters and methods using shift voltage to support oversampling

An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage.

FORCING AND SENSING DACS SHARING REFERENCE VOLTAGE

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs. 1. A device or assembly including an integrated circuit comprising:reference voltage buffer circuitry, including an amplifier circuit, providing a commonly-routed amplifier shared output voltage node that is shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes located at corresponding DACs; andwherein the first and second individually routed traces are configured with respective first and second routing resistances that are based on an expected or measured current loading from the corresponding DAC to provide an equal voltage drop across the first and second routing resistances for avoiding voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes.2. The device or assembly of claim 1 , further comprising:at least two switches corresponding to the at least two DACs, wherein ...

PIPELINED ANALOG-TO-DIGITAL CONVERTER

A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input 1. A pipelined analog-to-digital converter , comprising:a multiplying digital-to-analog converter, sampling an analog input and performing multiplication on the sampled analog input based on control bits;a first sub-range analog-to-digital converter, providing the multiplying digital-to-analog converter with the control bits; anda second sub-range analog-to-digital converter, coupled to the multiplying digital-to-analog converter for conversion of a multiplied signal output from the multiplying digital-to-analog converter,wherein:the first sub-range analog-to-digital converter samples the analog input to generate the control bits for the multiplying digital-to-analog converter as well as pre-estimated bits for the second sub-range analog-to-digital converter;the second sub-range analog-to-digital converter operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range analog-to-digital converter;a second section of digital bits are provided by the first sub-range analog-to-digital converter; andthe first and ...

ANALOG READOUT PREPROCESSING CIRCUIT FOR CMOS IMAGE SENSOR AND CONTROL METHOD THEREOF

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals. 1. A an analog readout preprocessing circuit for a solid state complementary metal-oxide-semiconductor (CMOS) image sensor , comprising:an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network configured to acquire signals and preprocess the acquired signals to achieve extended count-type integration and analog-to-digital conversion of the signals;an operational amplifier with a positive input terminal and a negative input terminal connected to an output terminal of the extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network and configured to utilize “virtual short” of the two input terminals of the operational amplifier and the charge conservation principle, to achieve extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion;{'sub': ip,cmp', 'in,cmp, 'a voltage comparator with a positive input terminal (V) connected to a positive ...

Correction of a value of a passive component

An integrated circuit including a first passive component of capacitive, resistive, or inductive type, including: a plurality of second and third passive components of said type, each having a same first theoretical value Compu_t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to (1−P).Compu_t or to (1+P).Compu_t, P being positive and smaller than ½. 1. An integrated circuit comprising a first passive component of capacitive , resistive , or inductive type , comprising:{'sub': 'u', 'a plurality of second and third passive components of said type, each having a same first theoretical value Comp_t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and'}a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to (1-P).Compu_t or to (1+P).Compu_t, P being positive and strictly smaller than ½.2. The circuit according to claim 1 , wherein the first component has a target value equal to M.Compu_t claim 1 , M being an integer claim 1 , preferably greater than or equal to 1/P.3. The circuit according to claim 2 , wherein P.Compu_t determines a maximum ...

Sar adc having accurate split capacitor

An array of capacitors includes a first array of k capacitors coupled to a first node and having capacitances which are binary weighted multiples of a unit capacitance value, a second array of m capacitors coupled to a second node and having capacitances which are binary weighted multiples of the unit capacitance value, a coupling capacitor disposed between the first node and the second node, and a trimmable grounded capacitor coupled between the first node and a ground potential.

CIRCUITS FOR CONTINUOUS-TIME CLOCKLESS ANALOG CORRELATORS

Circuits for continuous-time analog correlators are provided, comprising: a first VCO that receives an input signal and that outputs a first pulse frequency modulated (PFM) output signal; a second VCO that receives a reference signal and that outputs a second PFM output signal; a first phase frequency detector (PFD) that receives the first PFM output signal and the second PFM output signal and that produces a first PFD output signal; a first delay cell that receives the first PFM output signal and that produces a first delayed signal (DS); a second delay cell that receives the second PFM output signal and that produces a second DS; a second PFD that receives the first DS and the second DS and that produces a second PFD output signal; and a capacitor-digital-to-analog converter (capacitor-DAC) that receives the first PFD output signal and the second PFD output signal and that produces a correlator output. 1. A circuit for a continuous-time analog correlator , comprising:a first voltage-controlled oscillator (VCO) that receives an input signal and that outputs a first pulse frequency modulated (PFM) output signal;a second VCO that receives a reference signal and that outputs a second PFM output signal;a first phase frequency detector (PFD) that receives the first PFM output signal and the second PFM output signal and that produces a first PFD output signal;a first delay cell that receives the first PFM output signal and that produces a first delayed signal;a second delay cell that receives the second PFM output signal and that produces a second delayed signal;a second PFD that receives the first delayed signal and the second delayed signal and that produces a second PFD output signal; anda capacitor-digital-to-analog converter (capacitor-DAC) that receives the first PFD output signal and the second PFD output signal and that produces a correlator output.2. The circuit of claim 1 , wherein: the first PFD has a first input and a second input; for a first value of a ...

CHARGE LEAKAGE COMPENSATION IN ANALOG-TO-DIGITAL CONVERTER

Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal. 1. An analog-to-digital converter (ADC) circuit , comprising: receive an input signal, the input signal being susceptible to a drift due to a charge leakage;', 'receive a reference signal; and', (a) a leakage-compensated version of the input signal and the reference signal,', '(b) the input signal and a leakage-compensated version of the reference signal, or', '(c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal; and, 'generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of], 'a leakage compensation circuit configured toa quantizer configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.2. The ADC circuit of claim 1 , wherein:the quantizer comprises a comparator having a first transistor and a second transistor;a first gate ...

CHARGE-SCALING ADDER CIRCUIT

An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an ninput of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2*a unit capacitance (C). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground. 1. An adder circuit configured to draw a sum output node to a voltage proportional to a sum of received binary numbers , the adder circuit comprising:a first set of scaled capacitors, each capacitor of the first set of scaled capacitors having an input terminal electrically connected to a corresponding input of a first set of inputs and an output terminal electrically connected to the sum output node, each capacitor further having a corresponding capacitance value proportional to a significance of the corresponding input;a second set of scaled capacitors, each capacitor of the second set of scaled capacitors having an input terminal electrically connected to a corresponding input of a second set of inputs and an output terminal electrically connected to the sum output node, each capacitor further having a capacitance value proportional to a significance of the corresponding input;a reference capacitor electrically connected to ground and electrically connected to the sum output node, a capacitance of the reference capacitor equal to a sum of values of each of least significant (LS) scaled capacitors of the first and second sets of scaled capacitors; anda reset device electrically connected to ground and electrically ...

Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter

Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

D/A converter circuit and semiconductor device

Provided is a D/A converter circuit which copes with high-bit digital signals and has favorable linearity and small occupation area. In a capacitive divider type DAC, capacitances are simply provided in a one-to-one relationship correspondingly to lower order bit digital signals instead of providing capacitances one-to-one correspondingly to bits. In a reset period, voltages having a height corresponding to higher order bit digital signals are provided to one electrodes (first electrodes) of the capacitances thereby charging the capacitances. In a write period, voltages having a height corresponding to lower order bit digital signals are provided to the other electrodes (second electrodes) of the capacitances thereby charging the capacitances.

Digital/analog converter, display driver and display

n-비트 디지털 워드를 대응 전압으로 변환하기 위한 n-비트 디지털/아날로그 변환기가 제공된다. 이 변환기는 용량성 부하(C LOAD )에 직접 접속하기 위한 출력(V out )을 구비하는 (n-1) 비트 버퍼리스 스위치드 커패시터(bufferless switched capacitor) 디지털/아날로그 변환기(10)를 포함한다. (n-1) 비트 변환기(10)는 또한 제1 및 제2 기준 전압 입력(V1, V2)과 (n-1) 비트 디지털 입력을 구비한다. (n-1) 비트 선택성 인버터(13 1 , ..., 13 n-1 , 14 1 , ..., 14 n-1 )는 (n-1) 최하위 비트를 디지털 입력에 공급하고, 최상위 비트가 특정 값을 가지면 이를 반전시킨다. 스위칭 장치(11, 12)는 제1 및 제2 기준 전압 입력(V1, V2)에 접속하여 최상위 비트의 값에 따라 제1 및 제2 또는 제2 및 제1 기준 전압을 수신한다. An n-bit digital-to-analog converter for converting an n-bit digital word to a corresponding voltage is provided. The converter includes an (n-1) bit bufferless switched capacitor digital-to-analog converter 10 having an output V out for direct connection to the capacitive load C LOAD . (n-1) -bit converter 10 also includes first and second reference voltage inputs V1, V2 and (n-1) bit digital inputs. (n-1) bit selectable inverters 13 1 , ..., 13 n-1 , 14 1 , ..., 14 n-1 supply the least significant bit to the digital input, If it has a certain value, it inverts it. The switching devices 11 and 12 are connected to the first and second reference voltage inputs V1 and V2 and receive the first and second or second and first reference voltages according to the value of the most significant bit. 디지털 워드, 디지털/아날로그 변환기, 선택성 인버터; 스위칭 장치 Digital word, digital / analog converter, selectable inverter; Switching device

D / A conversion circuit and image display device using the same

Analoggtoodigital converter

D/a converter

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Two-stage digital-to-analog converter and LCD source driver

本发明提供一种二级数字模拟转换器与液晶显示器源级驱动器。源级驱动器包含二级数字模拟转换器。此二级数字模拟转换器是根据M位数字输入码来输出模拟电压。源级驱动器包含1位串行电荷重布数字模拟转换器和电压选择器。1位串行电荷重布数字模拟转换器具有可接收高参考电压的高参考电压输入节点以及可接收低参考电压的低参考电压输入节点。电压选择器是根据M位数字输入码的至少一部分来将高参考电压和低参考电压设定至选定电压。

D/A converter having capacitances, tone voltage lines, first switches, second switches and third switches

Provided is a D/A converter circuit which copes with high-bit digital signals and has favorable linearity and small occupation area. In a capacitive divider type DAC, capacitances are simply provided in a one-to-one relationship correspondingly to lower order bit digital signals instead of providing capacitances one-to-one correspondingly to bits. In a reset period, voltages having a height corresponding to higher order bit digital signals are provided to one electrodes (first electrodes) of the capacitances thereby charging the capacitances. In a write period, voltages having a height corresponding to lower order bit digital signals are provided to the other electrodes (second electrodes) of the capacitances thereby charging the capacitances.

Modified Sign Absolute Digital-to-Analog Converter and Its Operation Method

수정된 부호 절대값 디지탈-아날로그 변환기(DAC)는 사인 비트를 포함하는 입력 워드와 디지탈 데이타 워드에 응답하는 제1비트 스위치 회로를 구비하는 제1내부 DAC 회로를 포함한다. 각 비트 스위치 회로는 대응 전류소오스 트랜지스터에 접속된다. 제2내부 DAC회로는 상기 입력 워드에 동일한 비트 스위치 회로를 포함한다. 제2내부 DAC회로의 각 비트 스위치 회로는 대응 전류 소오스 트랜지스터에 접속된다. 상기 디지탈 데이타워드의 비트에 대응하는 동일한 이진 가중 비트 전류 결정 저항 회로가 기준 전압 도체에 접속된다. 제1내부 DAC회로와 각 비트 스위치 회로의 전류 소오스 트랜지스터의 이미터는 제1이득 밸런스 저항에 의해서 대응 비트 전류 결정 저항에 접속된다. 제2내부 DAC회로의 각 비트 스위치 회로의 전류 소오스 트랜지스터의 이미터는 제2이득 밸런스 저항에 의해서 동일한 대응 비트 전류 저항에 접속된다. 비트 전류 결정 저항을 공유함으로써 그 요구되는 수가 반으로 줄어들며 또한 그 저항이 동일 비트 전류 절대값에 대해 반으로 되기 때문에 각각의 물리적 크기가 반으로 줄어들게 된다.

Analog-to-digital converter

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Digital-to-analog converter

Digital to analog converters having circuit architectures to overcome switch losses

本发明涉及具有克服开关损耗的电路结构的数模转换器。其中公开了一种数模转换器(DAC)，包括：一对运算放大器，每个运算放大器有与相应的源电压耦合的第一输入；和多个开关控制的单元，每个单元包括：电阻器；第一施加/感测开关对，相互串联耦合且响应于控制信号的第一状态而导电，第一对开关的中间节点与电阻器耦合，第一对的施加开关与第一运算放大器的输出耦合，第一对的感测开关与第一运算放大器的第二输入耦合；第二施加/感测开关对，相互串联耦合且响应于控制信号的第二状态而导电，第二对开关的中间节点与第一对开关的中间节点耦合，第二对的施加开关与第二运算放大器的输出耦合，第二对的感测开关与第二运算放大器的第二输入耦合。

A/d converter and method of decreasing error

내용 없음. No content.

Interpolation dac and method

내용 없음. No content.

Multi-stage dual successive approximation register analog-digtal converter and analog-digtal converting method theerof

본 발명은 다단 듀얼 SAR ADC 및 이를 이용한 아날로그 디지털 변환 방법에 관한 것으로, 본 발명의 다단 듀얼 SAR ADC는, 아날로그 입력 전압을 소정 비트의 디지털 신호로 변환하기 위해 각 단이 2개의 연속 근사 레지스터 아날로그 디지털 변환기(SAR ADC)로 이루어지며 상기 단들이 순차적으로 연결된 복수의 SAR ADC단과, 상기 복수의 SAR ADC단의 각 단 사이에 하나씩 연결되며, 이전 SAR ADC단에서 출력된 잔류 전압을 증폭하여 다음 SAR ADC단으로 출력하는 1개 이상의 잔류 전압 증폭기를 포함하며, 상기 각 단을 이루는 상기 2개의 SAR ADC가 상기 잔류 전압 증폭기를 공유하는 것을 특징으로 한다. SAR, ADC, 잔류 전압 증폭기, SHA, 플래쉬 ADC

Two-stage digital analog converter and liquid crystal display source electrode driver

本发明在此揭露一种二级数字模拟转换器与液晶显示器源级驱动器。此源级驱动器包含二级数字模拟转换器。此二级数字模拟转换器包含1位串行电荷重布数字模拟转换器、电压选择器以及伽玛校正扩充和决定逻辑(Gamma Correction Expansion&Decision Logic)。1位串行电荷重布数字模拟转换器包含一第一电容、终端电容、第一开关电路以及第二开关电路。第一电容是耦接至电容充电节点和低参考电压输入节点间。终端电容是耦接至电荷收集节点和低参考电压输入节点间。第一开关电路是于电容充电周期中，将电容充电节点耦接至低参考电压输入节点和高参考电压输入节点之一。第二开关电路是于电荷重布周期中，将电容充电节点连接至电荷收集节点。

Digital-to-analog conversion circuit and image display apparatus using the same

전하배분형의 D/A 변환회로는, 각각의 커패시턴스가 순차 증가하고, 일단이 공통으로 접속된 복수의 커패시터를 구비한다. 상기 회로는 또, 상기 복수의 커패시터의 각각의 타단에 외부로부터 입력된 디지털신호에 따른 기준전위를 접속하기 위한 복수의 아날로그 스위치도 구비하고 있다. 상기 아날로그 스위치의 구동능력은 순차 증가한다 The charge distribution type D / A conversion circuit includes a plurality of capacitors in which each capacitance is sequentially increased and one end is connected in common. The circuit further includes a plurality of analog switches for connecting the reference potentials according to digital signals input from the outside to the other ends of the plurality of capacitors. The driving capability of the analog switch increases sequentially

Method and apparatus for converting data in electro-luminescensce dispaly panel

본 발명은 외부에서 유연성 있게 감마 직선을 조정하면서 계조 표현력을 확장시킬 수 있는 EL 표시 패널의 데이터 변환 방법 및 장치를 제공하는 것이다. The present invention provides a method and apparatus for converting data of an EL display panel which can expand gray scale expressive power while flexibly adjusting a gamma straight line from the outside. 이를 위하여, 본 발명의 데이터 변환 방법은 감마 모드 변수에 따라 입력된 제1 비디오 데이터를 비트수가 증가된 제2 비디오 데이터로 변환하는 단계와; 상기 제2 비디오 데이터를 감마 전압 세트를 이용하여 아날로그 비디오 신호로 변환하여 EL 표시 패널의 데이터 라인으로 공급하는 단계를 포함한다. To this end, the data conversion method of the present invention comprises the steps of: converting the first video data input according to the gamma mode variable into second video data having an increased number of bits; Converting the second video data into an analog video signal using a gamma voltage set and supplying the second video data to a data line of an EL display panel.

Da converter

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

D / A converter, design method of D / A converter, liquid crystal panel substrate and liquid crystal display device

본 발명은 정확하고 안정한 전위를 고속으로 생성하는 수단을 제공하는 데에있다. 2진하중(2n) 캐패시터를 사용한 D/A 변환기에 있어서, 실제의 용량비를 2n에서 시프트하여 구성된다. 이러한 구성의 D/A 변환기에 의하면, 가중된 복수의 용량(C1∼C6)의 용량비가 불일치, 그 불일치가 최악의 조건이 되어도, j 번째의 용량의 용량값은, 1번째로부터 (j-1) 번째까지의 모든 용량의 용량값의 합계보다 반드시 커지고, 따라서, D/A 변환기에 있어서의 「출력의 역전현상」은 확실하게 방지된다. 또, 보정회로 등이 여분인 회로를 부가할 필요도 없고, 저비용이고, 제조도 용이하다. The present invention is directed to providing a means for generating accurate and stable dislocations at high speed. In a D / A converter using a binary load (2n) capacitor, the actual capacity ratio is shifted from 2n. According to the D / A converter having such a configuration, even when the capacity ratio of the weighted plurality of capacities C1 to C6 is inconsistent and the inconsistency is a worst condition, the capacity value of the jth capacity is determined from the first (j-1). It is always larger than the sum of the capacitance values of all the capacitances up to the first), and therefore, the "output reversal phenomenon" in the D / A converter is surely prevented. In addition, there is no need to add an extra circuit for the correction circuit or the like, and it is low cost and easy to manufacture.

A / D conversion circuit and solid-state imaging device

Patent JPS6347290B2

Parallel analog-digital converter of dynamic type (versions)

FIELD: electric engineering. SUBSTANCE: in versions analog-digital converters of dynamic type are based on simultaneous comparison of input signal voltage to n reference levels, generated by dynamic quantisation; on simultaneous comparison of dynamically varying quantised shifts of input signal voltage to voltage equal to half of reference signal voltage; usage of n-digit line of sources of binary-weighted voltages, from which levels of tracking reference voltages are created on parallel comparators connected relative to input signal. EFFECT: reduced hardware expenses in parallel static ADC by dynamic quantising of reference levels, and also possibility to control range of input signal variation in parallel ADC with dynamic shift of input signal. 5 cl, 12 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) 2 389 133 (13) C1 (51) МПК H03M H03M 1/12 1/36 (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ, ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (21), (22) Заявка: 2008150663/09, 23.12.2008 (24) Дата начала отсчета срока действия патента: 23.12.2008 (45) Опубликовано: 10.05.2010 Бюл. № 13 (73) Патентообладатель(и): Коркин Вячеслав Васильевич (RU), Андреева Ольга Вячеславовна (RU) 2 3 8 9 1 3 3 2 3 8 9 1 3 3 R U (54) ПАРАЛЛЕЛЬНЫЙ АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ ДИНАМИЧЕСКОГО ТИПА (ВАРИАНТЫ) (57) Реферат: Параллельные аналого-цифровые преобразователи динамического типа относятся к области электрорадиотехники, связанной с цифровой обработкой аналоговых сигналов. Технический результат заключается в уменьшении аппаратурных затрат в параллельных статических АЦП путем осуществления динамического квантования опорных уровней, а также возможность регулирования диапазона изменения входного сигнала в параллельных АЦП с динамическим смещением входного сигнала. Для этого в вариантах аналого-цифровые преобразователи динамического типа основаны на одновременном сравнении напряжения входного сигнала с n опорными уровнями, формируемые динамическим ...

Switched capacitor type d/a converter circuit, control method therefor, lcd drive control circuit, lcd drive control method and integrated circuit for controlling lcd drive

(57)【要約】 【課題】ＤＡ変換出力信号が基準電圧レベルに対して上 下対照なレベルとなるＤＡ変換回路及び制御方法と、そ れを応用したＬＣＤ駆動制御回路及び駆動制御方法を得 る。 【解決手段】演算増幅器１と、第１・第２・第３のキャ パシタ２・３・４と、第１から第５のスイッチ６・１１ ・７・９・１４とからなり、第２のキャパシタは基準容 量値の２の０乗倍から２の（Ｎ−１）乗倍までの容量値 のＮ個のキャパシタ列からなる。このキャパシタ列の各 々を第１の基準電圧端子５、あるいは第２の基準電圧端 子８または第３の基準電圧端子１０に前記スイッチを介 して接続制御する。前記スイッチは極性制御信号２０、 基準クロック信号２１及びデジタル信号２２により制御 され、特に極性制御信号を切換えることで、基準電圧端 子１６の電圧レベルに対し上下対照なＤＡ変換アナログ 出力信号１７を得る。

Reconfigurable dac implemented by memristor based neural network

ANALOGUE-DIGITAL AND DIGITAL-ANALOGUE CONVERTER C-2C

ANALOG-DIGITAL CONVERTER AND NEUROMORPHIC CIRCUIT USING SUCH CONVERTER

The converter has a digital look-up table (LUT) with a selection output to select from a set of transistors (T1-T8), as a function of a word (DATA) to be converted, a transistor or group of transistors supplying current of desired value. A current output (S) supplies current delivered by the selected transistor/transistors. A loading unit loads into the table, at a defined address, a datum determining the selection, as a function of real measured voltage-current characteristics of the transistors, to establish look-up between words to be converted and current values obtained by the selection. The transistors have identical nominal geometrical characteristics and dispersed current-voltage characteristics. An independent claim is also included for a neuromorphic circuit.

POWER AMPLIFIER

Digital-to-analog converter

Angular position servo device

Digital-analogue converter

SUBTRACTOR-AMPLIFIER CIRCUIT FOR A DIGITAL CASCADE ANALOG CONVERTER

Correction of a value of a passive component

Correction d'une valeur d'un composant passif La présente description concerne un circuit intégré comprenant un premier composant passif (Comp) de type capacitif, résistif ou inductif comportant : une pluralité de deuxièmes et troisièmes composants passifs (Compu) dudit type ayant chacun une même première valeur théorique Compu_t, les deuxièmes composants étant connectés entre eux de sorte que leurs valeurs s'ajoutent, et chaque troisième composant étant associé à un premier interrupteur (208) dont l'état détermine si la valeur du troisième composant s'ajoute aux valeurs des deuxièmes composants ; et une pluralité de quatrièmes composants passifs (Compcorr) dudit type chacun associé à un deuxième interrupteur (214) dont l'état détermine si la valeur du quatrième composant s'ajoute aux valeurs des deuxièmes composants, au moins un (Compcorr) des quatrièmes composants (Compcorr) passifs ayant une deuxième valeur théorique égale à (1-P).Compu_t ou à (1+P).Compu_t, avec P positif strictement inférieur à 1/2. Figure pour l'abrégé : Fig. 2 Correction of a value of a passive component The present description relates to an integrated circuit comprising a first passive component (Comp) of the capacitive, resistive or inductive type comprising: a plurality of second and third passive components (Compu) of said type each having a same first theoretical value Compu_t, the second components being connected together so that their values are added, and each third component being associated with a first switch (208) whose state determines whether the value of the third component is added to the values of the second components; and a plurality of fourth passive components (Compcorr) of said type each associated with a second switch (214) whose state determines whether the value of the fourth component is added to the values of the second components, at least one (Compcorr) of the fourth components (Compcorr) liabilities having a second theoretical ...

DIGITAL ANALOG CONVERTER HAVING HIGH STABILITY OF OUTPUT VOLTAGE

Un convertisseur numérique analogique CNA, destiné aux fréquences très élevées, est décrit. Il comporte un premier étage, classique, dans lequel une pluralité de charges modulables, montées en parallèle, débitent des courants en progression géométrique dans un transistor 14 transformateur courant-tension. Chaque charge modulable comprend un transistor d'entrée 1, sur la grille duquel est adressé un bit, ainsi qu'une diode 10 et une résistance saturable 2. Le second étage est un décaleur, constitué par un transistor 15 monté en source suiveuse, en série avec au moins une diode 16 et un transistor de rappel 18 dont la source est à un potentiel négatif VS S . La tension au drain A du transistor 14 transformateur est appliquée à la grille du transistor 15 décaleur, et la tension de sortie VS au drain du transistor 18 de rappel est rebouclée sur la grille du transistor 14 transformateur. Application aux circuits intégrés pour conversion numérique analogique en hyperfréquences. A digital to analog converter DAC, intended for very high frequencies, is described. It comprises a first, conventional stage, in which a plurality of adjustable loads, connected in parallel, deliver currents in geometric progression in a transistor 14 current-voltage transformer. Each modulable load comprises an input transistor 1, on the gate of which a bit is addressed, as well as a diode 10 and a saturable resistor 2. The second stage is a shifter, consisting of a transistor 15 mounted as a follower source, in series with at least one diode 16 and a booster transistor 18 whose source is at a negative potential VS S. The voltage at the drain A of the transformer transistor 14 is applied to the gate of the shifting transistor 15, and the output voltage VS at the drain of the return transistor 18 is looped back to the gate of the transformer transistor 14. Application to integrated circuits for digital-to-analog conversion into microwave frequencies.

ANALOG-TO-DIGITAL CONVERTER WITH HIGH OUTPUT VOLTAGE STABILITY

Successive approximation register analog-to-digital converter

一种包括基于分裂电容器的数模转换器的逐次逼近寄存器模数转换器，逐次逼近寄存器数模转换器包括：比较器、包括正电容器阵列和负电容器阵列的基于分裂电容器的数模转换器以及逐次逼近寄存器逻辑电路。正电容器阵列和负电容器阵列各自包括：第一级的正电容器阵列和第一级的负电容器阵列，分别产生比较器的与包括MSB的高比特位相对应的输入信号；第二级的正电容器阵列和第二级的负电容器阵列，产生与中间比特位相对应的输入信号；以及第三级的正电容器阵列和第三级的负电容器阵列，产生与LSB的低比特位和次低于LSB的比特位相对应的输入信号。

Data conversion circuitry for converting analog signals to digital signals and vice-versa and method therefor

A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Digital potentiometer and corresponding control

DIGITAL-ANALOGUE CONVERTER WITH TORQUE LOAD DEVICES

Convertisseur numérique-analogique série utilisant la technologie des dispositifs à charges couplées. Le convertisseur comprend une diffusion de source de charges d'entrée 3, une porte d'emmagasinage de charges d'entrée, une paire de portes de division de charges 9 et 11, et une diffusion de réception de charges de sortie 4. Les diffusions et les portes d'emmagasinage et de division de charges sont séparées les unes des autres par des portes de commande respectives 6, 8, 10 et 12. Peut être utilisé dans tous les convertisseurs numériques-analogiques. Serial digital-to-analog converter using load-coupled device technology. The converter comprises an input charge source diffusion 3, an input charge storage gate, a pair of charge dividing gates 9 and 11, and an output charge reception diffusion 4. The broadcasts and the charge storage and dividing gates are separated from each other by respective control gates 6, 8, 10 and 12. Can be used in all digital-to-analog converters.

Current sampling mixer with harmonic rejection

본 발명은 광대역 방송 시스템 등에 적용될 수 있는 전류 샘플링 믹서에 관한 것으로, 본 발명의 전류 샘플링 믹서는, 복수의 커패시터를 포함하는 전류 샘플러 구조를 변경하여, 출력시 웨이트값이 부여된 커패시터를 선택하여 합산함으로써, FIR 필터 기능 및 고조파 제거 기능을 수행할 수 있다. 전류 샘플러, 믹서, 고조파 리젝션 믹서, 합산(summing), 웨이트값(weighting)

System and method for digitally calibrating an analog-to-digital converter

A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

D/A conversion circuit and semiconductor device

A D/A conversion circuit comprising n first resistors (A 0 , A 1 ,........A n-1 ), n second resistors (B 0 , B 1 ,........, B n-1 ), a power-supply voltage line L and a power-supply voltage line H being maintained at potentials different from each other, an output line, n first switches (SWa 0 , SWa 1 ,....., SWa n-1 ), and n second switches (SWb 0 , SWb 1 ,........, SWb n-1 ), wherein one end of each of the n first resistors (A 0 , A 1 , ........ A n-1 ) is connected to one end of corresponding one of the n first switches (SWa 0 , SWa 1 ,......., SWa n-1 ) while the other end is connected to the output line, wherein an end of each of the n first switches (SWa 0 , SWa 1 ,...., SWa n-1 ) which is not connected to each of the n first resistors (A 0 , A 1 ,.....A n-1 ) is connected to the power-supply voltage line L, wherein one end of each of the n second resistors (B 0 , B 1 , ....., B n-1 ) is connected to one end of corresponding one of the n second switches (SWb 0 , SWb 1 , ......, SWb n-1 ) while the other end is connected to the output line, wherein an end of each of the n second switches (SWb 0 , SWb 1 ,....., SWb n-1 ) which is not connected to each of the n second resistors (B 0 , B 1 , ........, B n-1 ) is connected to the power-supply voltage line H, and wherein the n first switches SWa 0 , SWa 1 , ....., SWa n-1 and the n second switches SWb 0 , SWb 1 , ......, SWb n-1 are controlled by n-bit digital signals inputted from the outside, characterized in that n stands for a natural number of greater than 1, and R stands for a positive number, respectively, resistance values of the n first resistors (A 0 , A 1 , ......... A n-1 ) and R, 2R, ....., 2 n-1 R, respectively, resistance values of the n second resistors (B 0 , B 1 ,....., B n-1 ) are R, 2R, ....., 2 n-1 R, respectively, wherein inverted signals of the n-bit digital signals which are inputted to the n first switches (SWa 0 , SWa 1 , ....., SWa n-1 ) are respectively inputted to the n second switches ( ...

A/D converting circuit

The present invention has an object to provide an A/D converting circuit with improved accuracy in an output. In this invention, the initial electric charge is given to a capacitive coupling for outputting in a quantizing circuit so as to cancel the dispersion of thresholds of MOS inverter in the quantizing circuit, the supply voltage of the first and the second inverters is higher than the supply voltage of an inverter for quantizing, as well as the initial electric charge is given to a capacitance for input in order to limit the function of the quantizing circuit within the linear area of the first and the second inverters.

Low-power area-efficient SAR ADC using dual capacitor arrays

An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.