Low-miss-rate and low-miss-penalty cache system and method
Номер патента: EP2987085A1
Опубликовано: 24-02-2016
Автор(ы): Kenneth ChengHao Lin
Принадлежит: Shanghai Xin Hao Micro Electronics Co Ltd
Опубликовано: 24-02-2016
Автор(ы): Kenneth ChengHao Lin
Принадлежит: Shanghai Xin Hao Micro Electronics Co Ltd
Реферат: A method for assisting operations of a processor core coupled to a first memory and a second memory includes: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions, and creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the instructions, such that the processor core fetches the instructions from the second memory for execution. Filling the instructions further includes pre-fetching from the first memory to the second memory instruction segments containing the instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.
Low-miss-rate and low-miss-penalty cache system and method
Номер патента: WO2013071868A1. Автор: Kenneth ChengHao Lin. Владелец: Shanghai XinHao Microelectronics Co. Ltd.. Дата публикации: 2013-05-23.