Schaltungsanordnung zur Verarbeitung abgetasteter elektrischer analoger Signale

AKTIVE STROMMODUS-ABTASTSCHALTUNG

Equalising phase for switched capacitor circuit operation

In a switched-capacitor circuit such as a DAC, charges are accumulated by a plurality of sampling capacitors in dependence upon input digital data during a sampling phase. Then, during a sharing phase these charges are shared with a holding capacitor which is connected across an op-amp. In the so-called bipolar charging type switched-capacitor DAC, the signal provided by the sampling capacitors is doubled by connecting their opposite sides to positive and negative reference voltages during the sampling phase. However, parasitic capacitances associated with the sampling capacitors then cause a disturbance to the input of the operational amplifier during the sharing phase. By equalising the input sides of the sampling capacitors to a reference voltage, prior to the sharing phase, this disturbance is avoided thereby allowing a low-power op-amp to be employed in the DAC. This equalising can be achieved by adding a short equalising clock phase between the usual sampling and sharing clock phases ...

CURRENT MEMORY

Current amplifier and current mode analog/digital converter using the same

In a current amplifier, a current obtained by holding an input current from an input terminal by a first current sample/hold circuit is added through a connection to a current obtained by inverting the input current by a current inverter to generate a current twice the input current. This current is alternately sampled and held by second and third current sample/hold circuits and alternately output to an output terminal.

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

CURRENT MODE SAMPLE-AND-HOLD AMPLIFIER

CURRENT DRIVING CIRCUIT

PROBLEM TO BE SOLVED: To easily change the use number of a driving circuit. SOLUTION: A current mirror circuit 12 receives a reference current Irefi input via a reference current input terminal 11 and generates an internal current Irefa. A current mirror circuit 13 receives an internal current Irefa, generates an internal reference current Irefb and generates an output reference current equal in the current value to the reference current Irefi. The output reference current Irefc is output to the outside via a reference current output terminal 14. An output current generation section 15 receives the internal reference current Irefb and generates output currents Iout-1 to Iout-n having the current values meeting the reference current Irefi. The output currents Iout-1 to Iout-n are supplied to the outside via output current output terminals 16-1 to 16-n. COPYRIGHT: (C)2007,JPO&INPIT ...

INTEGRATOR CIRCUIT

An integrator circuit which uses switched current techniques and includes a first current memory cell (T31,T32, S31, C31) a second current memory cell (T33, T34, C32, S32, T35) and a third (correcting) current memory cell (T36, S33, C33). An input current signal is fed to input (30) and a switch (S30) is closed during the phi portion of each sampling period, as is the switch (S31) in the first current memory cell. The other switches (S32, S33) are closed during the phi portion of each sampling period. During the phi portion transistor (T31) acts as a current source producing the current applied to it in the preceding phi portion. This is subtracted from the current produced by the output of the second current memory cell (T34) and the difference is stored in the third current memory cell (T36, S33, C33). During the next phi portion transistor (T36) acts a current source correcting the feedback current fed to the input (T31) of the first current memory cell. This reduces the sensitivity ...

Current memory

CURRENT FOLDING CELL AND CIRCUIT WITH AT LEAST ONE FOLDING CELL

CURRENT DRIVE CIRCUIT AND DRIVE METHOD THEREOF, AND ELECTROLUMINESCENT DISPLAY APPARATUS USING THE CIRCUIT

A current drive apparatus for an active matrix display operates a plurality of loads, e.g. organic or inorganic EL elements, by applying a current thereto. The apparatus includes a plurality of output terminals (Tout) to which the loads are respectively connected. A single current generation circuit (10A) comprising e.g. a digital to analogue converter and a current mirror, outputs an operating current having a predetermined current value. A plurality of current storage circuits (30A) are provided in accordance with the respective output terminals, sequentially sample and hold (40A) the operating current and then simultaneously output (EN) the drive currents based on the sampled operating currents to the respective output terminals. The operating current has a current value according to an input signal. The current storage circuit (30A) includes a voltage component holding section which samples the operating current outputted from the current generation circuit and holds a voltage component ...

Current memory, including device memory current, and combinations thereof

샘플링된 아날로그 전류들을 위한 전류 메모리는 제 1 의 조잡한 전류 메모리 셀(T1,C1,S1)과 제 2 의 정밀한 전류 메모리셀(T2,C2,S2)로 구성되어 있다. 전류 메모리셀은 클락 싸이클의 제 1 주기의 제 1 부분동안( 1a)에는 입력 전류를 감지한다. 반면에, 제 2 전류 메모리셀은, 입력 전류에서, 클락 싸이클의 제 1 주기의 제 2 부분 동안( 1b)에는 제 1 전류 메모리셀에 의해 만들어진 전류를 뺀 전류를 감지한다. 제 1 전류 메모리셀은 메모리 트랜지스터(T1)의 효율(g m )을 증가시키고, 트랜지스터들(T1,T2)의 드레인 전극들의 결합부의 전위를 가상접지 전압과 비슷하게 유지시키는 전압 증폭기(2)를 추가로 포함하고 있다. The current memory for the sampled analog currents consists of a first coarse current memory cell (T1, C1, S1) and a second precise current memory cell (T2, C2, S2). The current memory cell is turned on during the first portion of the first period of the clock cycle 1a detects the input current. On the other hand, the second current memory cell is configured such that, at the input current, during the second portion of the first period of the clock cycle 1b senses a current minus the current produced by the first current memory cell. The first current memory cell adds a voltage amplifier 2 that increases the efficiency g m of the memory transistor T 1 and keeps the potential of the junction of the drain electrodes of the transistors T 1 and T 2 close to the virtual ground voltage .

CLOCK FEEDTHROUGH REDUCTION SYSTEM FOR SWITCHED CURRENT MEMORY CELLS

스위치 전류 회로용 전류 셀은 정전류원(51)과 기준 접지 사이에 직렬로 접속된 제1 및 제2 MOS 트랜지스터를 포함한다. 제1 MOS 트랜지스터(M2)의 드레인(52)은 정전류원(51)에 결합되며 제2 MOS 트랜지스터(M1)의 소오스(64)는 기준 접지에 결합된다. 2개의 MOS 트랜지스터는 각각 제어 게이트가 드레인에 결합된 제1 스위치(59) 및 제2 스위치(63)를 갖는다. 샘플 및 홀드 동작의 샘플 위상은 제1 및 제2 샘플 서브 위상으로 분할되고 입력 전류(I in )는 샘플 서브 위상 동안 전류 셀에 인가되어 유지된다. 제1 샘플 서브 위상 동안 제2 MOS 트랜지스터(M1)은 입력 전류(I in ), 정전류원(51) 및 클록 피드스루 에러에 대응하는 게이트 전압을 기억한다. 채널 효과는 클록 피드스루 에러를 보상 및 보정하기에 충분한 정도로 제2 MOS 트랜지스터(M1)에 의도적으로 유도된다. 변조 전압(V mod )은 채널 효과의 결과로서 제2 트랜지스터(M1)의 드레인(62)에서 유도되고, 제1 MOS 트랜지스터(M2)는 홀드 위상 동안 제2 MOS 트랜지스터(M1)의 드레인(62)에서의 변조 전압(V mod )을 저장 및 유지하는데 사용된다. The current cell for the switch current circuit includes first and second MOS transistors connected in series between the constant current source 51 and the reference ground. The drain 52 of the first MOS transistor M2 is coupled to the constant current source 51 and the source 64 of the second MOS transistor M1 is coupled to reference ground. The two MOS transistors each have a first switch 59 and a second switch 63 with a control gate coupled to the drain. The sample phase of the sample and hold operation is divided into first and second sample subphases and the input current I in is applied to and maintained in the current cell during the sample subphase. During the first sample subphase, the second MOS transistor M1 stores the input current I in , the constant current source 51 and the gate voltage corresponding to the clock feedthrough error. The channel effect is intentionally induced in the second MOS transistor M1 to a degree sufficient to compensate for and correct the clock feedthrough error. The modulation voltage V mod is induced at the drain 62 of the second transistor M1 as a result of the channel effect, and the first MOS transistor M2 is drain 62 of the second MOS transistor M1 during the hold phase. It is used to store and maintain the modulating voltage (V mod ) at.

METHOD AND DEVICE FOR PROCESSING SAMPLED ANALOGUE SIGNALS IN DIGITAL BICMOS PROCESS

디지털 BiCMOS 프로세스에서, MOS 트랜지스터의 기억용량 및 바이폴라 트랜지스터의 커다란 상호 컨덕턴스는 상기 방법으로 결정될 수 있는데, 그 속도는 상기 MOS 트랜지스터(4)의 용량 및 바이폴라 트랜지스터(5)의 상호 콘덕턴스에 의해 본래 결정된다. CMOS에서 종래의 SI 기술상에 장점은 속도가 빠르고, 에러가 적으며, 정확도가 크다는 것이다. BiCMOS에서 다른 기술에 걸친 장점은 에러가 작고 정확도가 크다는 것이다. 본 발명의 기술의 유일한 특징은 상기 MOS 장치의 큰 입력 임피던스 및 바이폴라 장치의 큰 상호 인덕턴스의 결합이고, 이러한 2개의 장치는 BiCMOS 프로세스에서만 이용할 수 있고, 상기 CMOS 프로세스에서는 이용할 수 없다.

Current sampling circuit and method and sensor circuit and signal sensing method

A current sampling circuit including a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provide in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase.

ELECTRIC CIRCUIT

A method and device for processing sampled analogue signals in digital BICMOS process

A method for processing sampled analogue signals in digital BICMOS processes featuring the use of MOS transistors and BICMOS transistors in the manufacturing process of BICMOS, where one voltage is stored temporarily in the port of an MOS transistor and the transconductance of a bi-polarity transistor boosts the pace.

SWITCHED-CURRENT MEMORY

A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (iOr) is produced. The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

OLED DISPLAY WITH PING PONG CURRENT DRIVING CIRCUIT AND SIMULTANEOUS SCANNING OF LINES

A display drive apparatus includes a selection circuit which sets display pixels in a plurality of specific rows of the display panel in a selected state simultaneously with selection signals of said rows at least overlapping each other. A gradation signal generation circuit generates a gradation signal which controls a luminance gradation of each OLED display pixel based on the display data and sequentially supplies the generated gradation signal in a ping pong manner. A plurality of signal distribution circuits sequentially distribute the gradation signal supplied by the gradation signal generation circuit in accordance with the plurality of display pixels in each column at the timing of time-series supply. A plurality of current holding circuits individually hold the distributed gradation signal and simultaneously supply as the gradation current a current having a current value based on the held gradation signal to the display pixels in the plurality of simultaneously scanned rows.

CURRENT MEMORY

A current memory for sampled analogue currents comprises a first, coarse, current memory cell (T1, C1, S1) and a second, fine, current memory cell (T2, C2, S2). The first current memory cell senses the input current during a first portion (ζla) of the first period of the clock cycle, while the second current memory cell senses the input current plus the current produced by the first current memory cell during a second portion (ζlb) of the first period of the clock cycle. The combined outputs of the first and second current memory cells is available during a second period (ζ2) of the clock cycle. The first current memory further comprises a voltage amplifier (2) which increase the effective gm of the memory transistor (T1) and holds the potential at the junction of the drain electrodes of transistors (T1 and T2) close to a virtual earth.

Signal processing arrangements

Switched current circuits include current memory cells which store analogue currents by means of the charge on the gate source capacitance of an MOS transistor. A source of inaccuracy in these circuits is switch charge injection into the gate source capacitance. It has been found that the error current produced by a single such current memory cell has a peak value at one value of stored current, the peak being relatively broad and symmetrical over a significant range of currents (Figure 3b). When two current memory cells (S1,T1,C1; S2,T2,C2) are connected in cascade this error may be cancelled. In order to produce equal errors an optimum bias current needs to be generated which will depend on parameters which are variable in integrated circuit manufacturing processes but which will be relatively constant within an individual integrated circuit. The two cascaded current memory cells (S1,T1,C1; S2,T2,C2) include controllable bias current sources (T16,T17) and a control circuit (10) is provided to control the current sources (T16,T17) so that the current memory cells (S1,T1,C1; S2,T2,C2) operate at the optimum bias current. The control circuit (10) comprises two further current memory cells (S11,T11,C11; S12,T13,C12) connected in cascade. Two different value current sources (T10,T12) are provided and the error current due to switch charge injection is used to charge a capacitor (Cx). The voltage across this capacitor (Cx) provides the control for current sources (T16,T17) and also current sources (T14,T15). The control feedback loop comprising current sources (T14,T15) and capacitor (Cx) causes the bias current to approximate to the optimum value.

Verfahren und Schaltungsanordnung für die Verarbeitungs von abgetasteten analogen elektrischen Signalen.

INTEGRIERTER FUNKTIONSGENERATOR

STROMSPEICHER

Storing sampled analogue electrical currents

An analogue current memory has a current input (1) which is connected to the input branch of a first current mirror circuit formed by two transistors (T4 and T8). The input and output branches of the first current mirror are isolated by a first switch (S1) which is controlled by a clock signal OA. The output branch of the first current mirror is connected to the input branch of a second current mirror formed by two transistors (T9 and T12). The input and output branches of the second current mirror are isolated by a second switch (S2) which is controlled by a clock signal OB which does not overlap the clock signal OA. The first switch (S11) is made during the first half of the sample period and the second switch (S2) is made during the second half. A current fed to input 1 is mirrored by the transistor T8 while the first switch (S1) is closed and a first capacitor (CA) charges to the gate/source voltage of transistor T8. When the first switch (S1) opens the current through transistor T8 ...

INTEGRATOR CIRCUIT

Current comparator arrangement

CURRENT EXPENSIVE CIRCUIT AND STEURVERFAHREN FOR IT, AND ELEKTROLUMINESZENTES INDICATOR WITH THIS CIRCUIT

ACTIVE CURRENT MODE SCANNING CIRCUIT

CURRENT DRIVE CIRCUIT AND DRIVE METHOD THEREOF, AND ELECTROLUMINESCENT DISPALY APPARATUS USING THE CIRCUIT

A current drive apparatus for an active matrix display operates a plurality of loads, e.g. organic or inorganic EL elements, by applying a current thereto. The apparatus includes a plurality of output terminals (Tout) to which the loads are respectively connected. A single current generation circuit (10A) comprising e.g. a digital to analogue converter and a current mirror, outputs an operating current having a predetermined current value. A plurality of current storage circuits (30A) are provided in accordance with the respective output terminals, sequentially sample and hold (40A) the operating current and then simultaneously output (EN) the drive currents based on the sampled operating currents to the respective output terminals. The operating current has a current value according to an input signal. The current storage circuit (30A) includes a voltage component holding section which samples the operating current outputted from the current generation circuit and holds a voltage component ...

SYSTEMS AND METHODS FOR PROGRAMMING FLOATING-GATE TRANSISTORS

A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.

METHOD AND CIRCUIT FOR ELIMINATING CHARGE INJECTION FROM TRANSISTOR SWITCHES

A method for reducing charge injection from a field effect transistor switch in a circuit being controlled by a timing signal having an operation cycle with at least a first phase and a second phase. A charge density is changed in at least one layer in a channel in the switch when the timing signal begins its operational cycle and is in the first phase. A depth of the layer is significantly reduced while the timing signal is still in the first phase before a transition of the timing signal from the first phase to the second phase. The timing signal is transitioned from the first phase to the second phase while the layer is significantly reduced.

Analog current memory

An analogue current memory arrangement includes an input (30) and an output (33). A first (coarse) current memory cell (T31,S31,C31) senses the input current during clock phase phi 1a and reproduces the sensed current during clock phases phi 1b and phi 2. A second (fine) current memory cell (T32,C32,S32) acts as a current source during phase phi 1a when a reference voltage (VR) is applied to the gate of transistor (T32). The second current memory cell senses the difference between the input current and the output of the first current memry cell during phase phi 1b and reproduces the sensed current during phase phi 2. During phase phi 2 the input switch (S30) is opened and the output switch (S34) is closed causing the combined outputs of the first and second current memory cells to be fed to the output (33). (FIGS. 3 and 4).

High dynamic range current-mode track-and-hold circuit

Embodiments of the current-mode track and hold circuit comprise a cascode input stage, a dynamic biasing stage, a cascode output stage, and a switch operable to interconnect the input stage and the output stage. The input stage is connected to receive an input current. The dynamic biasing stage is connected to receive a scaled version of the input current as a dynamic biasing current and dynamically biases the input stage in response to the dynamic biasing current. Dynamically biasing the track-and-hold circuit in response to a dynamic biasing current that is a scaled version of the input current significantly increases the maximum peak-to-peak voltage swing allowed at the input of the track-and-hold circuit and enables a corresponding increase in signal-to-noise ratio. These benefits are obtained at the expense of only a small increase in power consumption.

Current sample / hold circuit, current sample / hold method, demultiplexer using the same, and display device

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

A METHOD AND DEVICE FOR PROCESSING SAMPLED ANALOGUE SIGNALS IN DIGITAL BICMOS PROCESS

In a digital BiCMOS process the storage capability of MOS transistors and the large transconductance of bipolar transistors can be utilized in such a way, that the speed is primarily determined by the capacitance seen by the MOS transistor (4) and the transconductance of the bipolar transistor (5). The advantages over the prior S1 technique in CMOS are higher speed, smaller errors and higher accuracy. The advantages over other techniques in BiCMOS are smaller errors and higher accuracy. The unique feature of the invented technique is the combination of high input impedance of the MOS devices and high transconductance of the bipolar devices, where both devices are only available in BiCMOS process and not in the CMOS process.

INTEGRATED FUNCTION GENERATOR

Integrator circuit

ACOUSTIC SYSTEM Of IMAGERY

A circuit and method for sampling and holding current, de-multiplexer and display apparatus using the same

본 발명은 데이터 전류샘플/홀드 회로에 관한 것이다. 더욱 상세하게는 전류 소스 형태의 입력단과 전류 싱크 형태의 출력단을 가지는 샘플/홀드 회로에 관한 것이다. 본 발명에 따른 샘플/홀드 회로는 데이터 드라이버의 출력단으로 싱크되는 데이터 전류를 샘플링 및 홀딩하는 제 1 트랜지스터와 커패시터와 복수의 스위치를 포함한다. 상기 샘플링 및 홀딩된 데이터 전류가 데이터 라인에 제공될 때, 상기 데이터 전류는 상기 샘플/홀드 회로의 출력단으로 싱크된다. 본 발명의 구성에 의한 샘플/홀드 회로는 출력단이 전류 싱크 형태인 데이터 드라이버와 함께 사용될 수 있다.

INTEGRATOR CIRCUIT

Circuit arrangement for processing analogue electrical signals

A circuit arrangement for processing sampled analogue electrical signals comprises means for combining (9) in predetermined proportions on input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal as or from the combined current produced by the combining means in successive sample periods. The circuit arrangement further comprises means for scaling a current which comprises a first branch (T1) for receiving a current to be scaled, second and third branches (T2,T3) for producing first and second sub-output currents which are proportional to the received current, means for forming the difference (2) between the first and second sub-output currents, and means for feeding the difference current to the output (3) of the current scaling means.

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING THE SAME

The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

CURRENT MODE SAMPLE-AND-HOLD AMPLIFIER

A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output ...

INTEGRATOR CIRCUIT

SIGNAL PROCESSING ARRANGEMENTS

Current memory

CIRCUIT ARRANGEMENT FOR PROCESSING SAMPLED ANALOGUE ELECTRICAL SIGNALS

FUNCTION GENERATOR CIRCUIT

... 1339212 Electric analogue calculating PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 Aug 1972 [21 Aug 1971] 38634/72 Heading G4G [Also in Division G2] A non-linear function generator comprises an amplifier (transistors T 2 , T 3 , T 4 ) provided with a non-linear negative feedback path (diode D, transistor T 1 and voltage source E) connected to the input of the amplifier by a switch S 1 , and a storage capacitor C which is used to maintain the amplifier output unchanged for a certain period after switch S 1 has been opened; that is, the function generator continues to operate as if the input signal immediately prior to the opening of S 1 were still connected. In a more elaborate form, Fig. 2 (not shown), the switch S 1 is replaced by an electronic switching circuit (T 5 , T 6 , T 7 , D 2 ). The circuit is manufactured as an integrated circuit, Fig. 3 (not shown). The circuit can be used in an automatic exposure control system of a camera comprising a photodiode D 1 , amplifier L, integrating ...

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

A current drive apparatus operates a plurality of loads by applying a current thereto. The apparatus includes a plurality of output terminals (Tout) to which the loads are respectively connected. A single current generation circuit (10) outputs an operating current having a predetermined current value. A plurality of current storage circuits (30A) are provided in accordance with the respective output terminals, sequentially fetch and hold the operating current and simultaneously output the drive current based on the operating current to the respective output terminals. The operating current has a current value according to an input signal. The current storage circuit (30A) includes a voltage component holding section which fetches the operating current outputted from the current generation circuit and holds a voltage component corresponding to a current value of the operating current.

INTEGRATOR CIRCUIT

CURRENT MEMORY

A current memory for balanced current inputs comprises two coarse (M1, M11) and two fine (M2, M12) current memory cells each of which comprises a field effect transistor (T1, T11, T2, T12) having a switch (S3, S13, S4, S14) between its gate and source electrodes. Parasitic gate-drain capacitances (C3, C13, C4, C14) are neutralised by capacitors (C31-C34) connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors (C31-C34).

Apparatus for processing sample analog electrical signals

A circuit arrangement for processing sampled analog electrical signals where each sample being in the form of an electrical current. The circuit arrangement includes apparatus for combining, in predetermined proportions, the input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and apparatus for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement consists of a plurality of circuit modules each of which deliver and accept bi-directional signal currents and which contain current sources so that internally only unidirectional currents are processed. The transistors which conduct signal currents are arranged to be of one conductivity type only. This reduces the voltage requirements at the interfaces between modules.

Method and device for processing sampled analogue signals in digital BiCMOS process

In a digital BiCMOS process the storage capability of MOS transistors and the large transconductance of bipolar transistors can be utilized in such a way, that the speed is primarily determined by the capacitance seen by the MOS transistor (4) and the transconductance of the bipolar transistor (5). The advantages over the prior SI technique in CMOS are higher speed, smaller errors and higher accuracy. The advantages over other techniques in BiCMOS are smaller errors and higher accuracy. The unique feature of the invented technique is the combination of high input impedance of the MOS devices and high transconductance of the bipolar devices, where both devices are only available in BiCMOS process and not in the CMOS process.

Circuit arrangement for processing sampled analogue electrical signals

STROMSTEUERSCHALTUNG UND STEURVERFAHREN DAFÜR, UND ELEKTROLUMINESZENTES ANZEIGEGERÄT MIT DIESER SCHALTUNG

Integratorschaltung

CIRCUIT ARRANGEMENT FOR PROCESSING SAMPLED ANALOGUE ELECTRICAL SIGNALS

A method of and a circuit arrangement for processing sampled analogue electrical signals

A sampled analogue electrical signal in the form of sample currents is processed by combining the input sample current in one sample period with sample currents derived from input sample currents in preceding sample periods. The signal processing is performed by scaling, adding, subtracting and storing sample currents. A circuit arrangement for carrying out the signal processing may be constructed from current mirror circuits and a current memory which is capable of reproducing at its output in one sample period the current applied to its input in a previous sample period.

CURRENT MIRROR CIRCUIT

Current memory

Current sampling and holding circuit and signal acquisition system

Current drive apparatus and drive method thereof, and display apparatus using same apparatus

A current drive apparatus operates a plurality of loads by applying a current thereto. The apparatus includes a plurality of output terminals (Tout) to which the loads are respectively connected. A single current generation circuit (10) outputs an operating current having a predetermined current value. A plurality of current storage circuits (30A) are provided in accordance with the respective output terminals, sequentially fetch and hold the operating current and simultaneously output the drive current based on the operating current to the respective output terminals. The operating current has a current value according to an input signal. The current storage circuit (30A) includes a voltage component holding section which fetches the operating current outputted from the current generationcircuit and holds a voltage component corresponding to a current value of the operating current.

ACOUSTIC SYSTEM Of IMAGERY

The invention concerns acoustic imaging systems. It consists in producing delays required for the reception signals of each of the sensors (201) of such a system using a set (203) of cells (207) with current memory. Said cells are posted and read by means of two offset registers (204, 205) wherein circulates a single bit per register. The space between the bits delays the signal introduced in the set, to form channels. The system enables the use of very compact acoustic cameras or ultrasonograph probes.

전류 샘플링 유지 회로 및 신호 수집 시스템

전류 샘플링 유지 회로에 있어서, 상기 전류 샘플링 유지 회로는 VDD단과 전류형 센서 사이에 직렬 연결되고, 제1 인에이블 신호에 따라 턴온되며, 전류를 출력하여 상기 전류형 센서의 직류 전류 성분을 상쇄시키는 상쇄 회로; 직렬 연결되는 상기 상쇄 회로 및 전류형 센서와, 상기 VDD단과 접지 전압 사이에 병렬 연결되고, 상기 제1 인에이블 신호와 상반되는 제2 인에이블 신호에 따라 턴온되며, 션트 전류의 미러 전류 및 상기 전류형 센서의 출력 전력으로 획득한 전류 차이를 이용하여 전류의 전달을 진행하는 미러 회로를 포함한다. 본원 발명은 전류 샘플링 유지 회로의 구축 속도를 향상시키고, 전류 샘플링 유지 회로가 출력하는 소음을 감소시킨다.

ELECTRIC CIRCUIT CAPABLE OF SUPPLYING A SPECIFIC LEVEL VOLTAGE BY CONTROLLING AN INFLUENCE DUE TO THE CHARACTERISTIC CHANGE OF A TRANSISTOR

PURPOSE: An electric circuit is provided to control an influence due to the characteristic change between transistors by inputting a value which is a result of adding a sustain voltage of each capacitor connected to each transistor and a signal voltage. CONSTITUTION: A first transistor(111) and a second transistor(112) are arranged between a first power line and a second power line. A bias electric potential is inputted to the gate electrode of the second transistor. Capacitors(113,114) change a current flowing between the first and the second power line through the first transistor and the second transistor to a voltage. A first switch is electrically connected between the gate electrode of the first transistor and a input terminal. A second switch is electrically connected between the source electrode of the first transistor and a output terminal. Each output terminal and input terminal is electrically connected to the first transistor and the second transistor. COPYRIGHT KIPO 2010 ...

CURRENT MEMORY

A current memory for sampled analogue currents comprises a first, coarse, current memory cell (T1, C1, S1) and a second, fine, current memory cell (T2, C2, S2). The first current memory cell senses the input current during a first portion (ζla) of the first period of the clock cycle, while the second current memory cell senses the input current plus the current produced by the first current memory cell during a second portion (ζlb) of the first period of the clock cycle. The combined outputs of the first and second current memory cells is available during a second period (ζ2) of the clock cycle. The first current memory further comprises a voltage amplifier (2) which increase the effective gm of the memory transistor (T1) and holds the potential at the junction of the drain electrodes of transistors (T1 and T2) close to a virtual earth.

Demultiplexer using current sample/hold circuit, and display device using the same

A demultiplexer using sample/hold circuits, and a display device using the same. The demultiplexer includes a first sample/hold circuit group with first and second sample/hold circuits for sampling the data current according to a first sampling order during a first interval, and programming the current corresponding to the sampled and stored data to at least two signal lines during a second interval. The demultiplexer further includes a second sample/hold circuit group with third and fourth sample/hold circuits for sampling the data current according to a second sampling order during a second interval, and programming the current corresponding to the sampled and stored data to the signal lines during a third interval. The first and second sampling orders in even the even frames are different from the sampling orders in the odd frames.

CURRENT MEMORY

A current memory comprises an input (1) which is connected via a switch (S1) which is closed on a phase 'phi'1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell (M2). The coarse memory cell samples the input current on phase 'phi'1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory (M1) on phase 'phi'1b of the clock. A switch (S2) which is closed on phase 'phi'2 of the clock passes the combined outputs of the coarse (M1) and fine (M2) memories to an output 3. Two further switches (S6, S7) are provided which are closed for a short time (sh1) at the start of phase 'phi'1b. These serve to discharge the stray capacitance (Cn) at the node (2) to the voltage reference source via terminal 4.

Circuit arrangement for processing sampled analogue electrical signals

A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, comprises means for combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement is formed by a plurality of circuit modules, for example scaling, memory, and integrator modules, each of which may be capable only of processing uni-directional currents. To enable easy interconnection of the modules, each module is arranged to receive and deliver bi-directional currents and to generate internally bias currents to enable conversion from bi-directional to uni-directional currents and vice versa.

Circuit for storage of bipolar currents consisting of two basic storage circuits, one with N MOS and another with P MOS transistor contg. current storage cell

From one current storage basic cell transistors (102,101) is obtained a factor-graduated copy of the storage current, from which then a rated current is subtracted by a unit (103). The differential current energises the respective other basic cell by a current-voltage converter (104). The subtraction operation unit, the current-voltage converter, and the basic cell P MOS transistor (101) form a control loop, controlling the drain current of storage transistors at an input current from zero to a defined rated value. Input currents, exceeding the rated value, are stored in the cell with N MOS transistor (102). Otherwise they are stored in the cell with P MOS transistor.

Signalverarbeitungsanordnungen

Verarbeitung von abgetasteten analogen elektrischen Signalen.

INTEGRATOR CIRCUIT

A bilinear integrator comprises a first input (1) and a second input (5). The input (1) is connected to the input of a first current memory cell formed by two transistors (T1, T2), capacitor (C1), and switch (S1). The first current memory cell is arranged to store a current applied to its input during a first portion phi of each sampling period and to reproduce that current at its output during a second portion phi of the succeeding sampling period. The second input (5) is connected to the input of a second current memory cell formed by three transistors (T3, T4 and T5), capacitor (C2) and switch (S3) via the switch (S2). During a second portion phi of each sampling period the current applied to the second input (5) and the current produced at the output of the first current memory cell are applied to the input of the second current memory cell. The second current memory cell has two outputs (from the drain electrodes of transistors (T4, T5)). The first output is fed back to the input of ...

PROCESSING SAMPLED ANALOGUE ELECTRICAL SIGNALS

Switched-current memory

Current memory and circuit arrangement comprising current memories

PROCESSING SAMPLED ANALOGUE ELECTRICAL SIGNALS

A METHOD AND DEVICE FOR PROCESSING SAMPLED ANALOGUE SIGNALS IN DIGITAL BICMOS PROCESS

In a digital BiCMOS process the storage capability of MOS transistors and the large transconductance of bipolar transistors can be utilized in such a way, that the speed is primarily determined by the capacitance seen by the MOS transistor (4) and the transconductance of the bipolar transistor (5). The advantages over the prior S1 technique in CMOS are higher speed, smaller errors and higher accuracy. The advantages over other techniques in BiCMOS are smaller errors and higher accuracy. The unique feature of the invented technique is the combination of high input impedance of the MOS devices and high transconductance of the bipolar devices, where both devices are only available in BiCMOS process and not in the CMOS process.

Device for processing sampled analogue signals

Current memory and circuit arrangement comprising current memories

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING THE SAME

The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

A DEVICE FOR PROCESSING SAMPLED ANALOGUE SIGNALS IN DIGITAL BiCMOS PROCESS

CURRENT MEMORY CIRCUIT FOR MINIMIZING CLOCK-FEEDTHROUGH

The present invention relates to a current memory circuit for minimizing clock-feedthrough, which comprises: a first memory capacitor implemented as a first type MOS; a second memory capacitor implemented as a second type MOS; and a control part connecting the first memory capacitor and the second memory capacitor. The control part includes a plurality of dummy capacitors located in parallel and a plurality of control switches connected to each of the plurality of dummy capacitors in series. The first memory capacitor and the second memory capacitor are current mirrors. According to the present invention, the clock-feedthrough can be minimized, and output degradation of a current memory can be actively compensated.

STROMFALTUNGSZELLE UND SCHALTUNG MIT MINDESTENS EINER FALTUNGSZELLE

A METHOD OF AND A CIRCUIT ARRANGEMENT FOR PROCESSING SAMPLED ANALOGUE ELECTRICALS

INTERGRATOR CIRCUIT

An integrator circuit for input signals in the form of sampled analogue currents has an input connected to a node (2). Also connected to the node (2) are a first current memory cell (C1, T1, S2) and a second current memory cell (C2, T2, T3, S3). The switches (S1, S3) are operated on opposite phases of a clock signal synchronised with the sampling period. The first current memory cell produces an output current when switch (S2) is open while the second current memory cell produces a first output when switch (S3) is open and a second output (T3) which is connected to the output (6) of the integrator and which is continuously available. Forward or Backward Euler mapping is produced by closing switch (S1) on appropriate phases of the clock. A Bilinear mapping can be produced by connecting an inverted version of the input signal to a second input (8) and appropriately clocking the switches (S1, S4). A feedforward function can be added by use of a further input (9) directly connected to the node ...

INTEGRATOR CIRCUIT

Shared sample and convert capacitor architecture

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

Semiconductor device and electronic apparatus using the same

The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

CURRENT MEMORY CIRCUIT FOR MINIMIZING CLOCK-FEEDTHROUGH

The present disclosure relates to a current memory circuit for minimizing clock feedthrough, the circuit including: a first memory capacitor implemented as a first conductive type MOS; a second memory capacitor implemented as a second conductive type MOS; and a dummy capacitor for connecting the first memory capacitor and the second memory capacitor to each other, wherein the first memory capacitor and the second memory capacitor are current mirrors. Accordingly, a current memory circuit with a more accurate performance, low power consumption, and an integration capability can be provided. 1. A current memory circuit , comprising:a first memory capacitor implemented as a first conductive type MOS;a second memory capacitor implemented as a second conductive type MOS; anda dummy capacitor connecting the first memory capacitor and the second memory capacitor to each other,wherein the first memory capacitor and the second memory capacitor are current mirrors.2. The current memory circuit of claim 1 , wherein the dummy capacitor is a MOS capacitor or at least one capacitor element.3. The current memory circuit of claim 1 , wherein the current mirror is driven only by an incoming current without using a bias current.4. The current memory circuit of claim 3 , further comprising a circuit unit supplying the incoming current.5. The current memory circuit of claim 1 , the first conductive type MOS is an N-type MOS and the second conductive type MOS is a P-type MOS.6. The current memory circuit of claim 5 , wherein the dummy capacitor connects a common gate of the first memory capacitor and a common gate of the second memory capacitor to each other.7. The current memory circuit of claim 1 , wherein the first memory capacitor and the second memory capacitor are disposed to allow an incoming current of the first memory capacitor to be equal to an output current of the second memory capacitor.8. A current memory circuit claim 1 , comprising:a first current mirror formed by an N- ...

Analog circuit and display device and electronic device

The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

SAMPLING NETWORK

A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Current sample-and-hold circuit and sensor

A current sample-and-hold circuit and a sensor, are provided. The current sample-and-hold circuit is used for offsetting a background photocurrent of a photodiode, and includes a capacitor and a first transconductance amplifier which has adjustable transconductance and outputs a sampled current to the photodiode to offset the background photocurrent of the photodiode. One end of the capacitor is connected with a power supply, the other end of the capacitor is connected with one end of the first transconductance amplifier; and the other end of the first transconductance amplifier is connected with the photodiode to output the sampled current to the photodiode. When the background photocurrent of the photodiode is increased, a change of a voltage of the capacitor within a large range can be avoided by increasing the transconductance of the first transconductance amplifier, so that the current sample-and-hold circuit can offset a larger background photocurrent.

BOOTSTRAP SAMPLING CIRCUIT WITH ACCURATELY AVERAGING PRE-CHARGE CIRCUIT

A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal. The switch controller may include a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitance immediately prior to each commencement of the sample state. The amount of the pre-charging may be substantially independent of the voltage of the input signal. 1. A sampling circuit comprising:a sampling capacitance; has a control input that controls whether the electronic sampling switch is in a sample state or a hold state;', 'connects the sampling capacitance to an input signal while in the sample state; and', 'disconnects the sampling capacitance from the input signal while in the hold state;, 'an electronic sampling switch that controls the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period;', 'while in the sample state, causes the impedance of the electronic sampling switch that is seen by the ...

SOLID-STATE IMAGE SENSOR AND ELECTRONIC APPARATUS

The present invention relates to a solid-state image sensor including a pixel array section including a plurality of unit pixels each having a photoelectric conversion unit, the plurality of unit pixels being arranged in a matrix, a sample-and-hold unit configured to sample and hold a pixel signal output from the unit pixel through a vertical signal line provided in association with column arrangement of the pixel array section, and an analog-to-digital conversion unit configured to convert a pixel signal output from the sample-and-hold unit into a digital signal. Then, the sample-and-hold unit has two sample-and-hold circuits in parallel for one vertical signal line, and at least one of the two sample-and-hold circuits has at least two sampling capacitors. 1. A solid-state image sensor comprising:a pixel array section including a plurality of unit pixels each having a photoelectric conversion unit, the plurality of unit pixels being arranged in a matrix;a sample-and-hold unit configured to sample and hold a pixel signal output from the unit pixel through a vertical signal line provided in association with column arrangement of the pixel array section; andan analog-to-digital conversion unit configured to convert a pixel signal output from the sample-and-hold unit into a digital signal,wherein the sample-and-hold unit has two sample-and-hold circuits in parallel for one vertical signal line, andat least one of the two sample-and-hold circuits has at least two sampling capacitors.2. The solid-state image sensor according to claim 1 ,wherein the solid-state image sensor has a stacked structure including at least two semiconductor substrates of a first semiconductor substrate and a second semiconductor substrate arranged on top of each other,the pixel array section is formed on the first semiconductor substrate, andthe sample-and-hold unit is formed on a semiconductor substrate other than the first semiconductor substrate.3. The solid-state image sensor according to ...

SHARED SAMPLE AND CONVERT CAPACITOR ARCHITECTURE

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor. 1. A LIDAR detector circuit , comprising:an input node to receive a photodetector signal;an output node to generate an output signal indicating a light intensity value of the photodetector signal; and a single capacitor and a comparator connected in series between the input node and the output node, wherein the single capacitor includes a first plate, includes a second plate coupled to an input of the comparator, and is configured to capture a value of the photodetector signal; a first switch configured to selectively couple the first plate of the single capacitor to receive the photodetector signal at the input node of the detector circuit; and', 'a second switch configured to selectively couple the second plate of the single capacitor to a supply voltage., 'a sample-and-convert circuit including a number of detection channels coupled in parallel with each other between the input node and the output node, each of the detection channels comprising2. The LIDAR detector circuit of claim 1 , wherein:the single capacitor is configured to capture the value of the photodetector signal during a sample mode and to hold the captured value as a differential voltage across the single capacitor during a convert mode; andthe comparator is configured to generate a compare signal based on a comparison between the captured value and a reference value.3. The LIDAR detector circuit of claim 2 , ...

Circuit arrangement for processing sampled analogue electrical signal

내용 없음. No content.

Current memory cell and current mode digital-to-analog converter

본 발명은 전류 메모리 셀 및 이를 포함하는 전류 모드 디지털 아날로그 컨버터에 관한 것으로, 특히 리프레시 기간을 감소시킬 수 있는 전류 메모리 셀 및 이를 포함하는 전류 모드 디지털 아날로그 컨버터에 관한 것이다. 본 발명의 실시 예에 따른 전류 메모리 셀은 제1 입력 단자, 제2 입력 단자 및 출력 단자를 포함하는 증폭기, 소스 전극이 제1 노드에 접속되고 드레인 전극이 접지에 접속되고 게이트 전극이 제2 노드에 접속된 트랜지스터, 상기 제2 노드와 상기 접지 사이에 접속된 제1 커패시터, 제3 노드와 상기 접지 사이에 접속된 제2 커패시터, 제1 기간 동안 기준 전류원과 상기 제1 노드를 접속시키고 제2 기간 동안 출력선과 상기 제1 노드를 접속시키는 제1 스위칭부, 상기 제1 기간 동안 상기 제1 노드와 상기 제2 노드 사이를 접속시키는 제2 스위칭부, 및 상기 제1 기간 동안 상기 제1 입력 단자를 상기 제2 노드에 접속시키고 상기 제2 입력 단자와 상기 출력 단자를 상기 제3 노드에 접속시키며 상기 제2 기간 동안 상기 제1 입력 단자를 상기 제3 노드에 접속시키고 상기 제2 입력 단자와 상기 출력 단자를 상기 제2 노드에 접속시키는 제3 스위칭부를 포함한다. The present invention relates to a current memory cell and a current mode digital analog converter including the same, and more particularly, to a current memory cell capable of reducing a refresh period and a current mode digital analog converter including the same. In the current memory cell according to an embodiment of the present invention, an amplifier including a first input terminal, a second input terminal, and an output terminal, a source electrode is connected to a first node, a drain electrode is connected to ground, and a gate electrode is a second node. A transistor connected to, a first capacitor connected between the second node and the ground, a second capacitor connected between a third node and the ground, a reference current source and the first node for a first period, and a second A first switching unit connecting an output line and the first node during a period, a second switching unit connecting between the first node and the second node during the first period, and the first input terminal during the first period Is connected to the second node, the second input terminal and the output terminal are connected to the third node, the first input terminal is connected to the third node during the second period, and the second input terminal and the And a third switching unit connecting the output terminal to the second node.

A method of and a circuit arrangement for processing sampled analogue electrical signals

내용 없음. No content.

Current sample and hold circuit and display device using the same

전류 샘플/홀드 회로에서, 커패시터가 제1 트랜지스터의 소스와 게이트 사이에 연결되어 있으며, 제2 트랜지스터가 제1 전압을 공급하는 제1 전원과 제1 트랜지스터의 소스 사이에 연결되어 있다. 제3 트랜지스터는 입력단과 제1 트랜지스터의 게이트 사이에 연결되어 있으며, 제4 트랜지스터는 턴온 시에 제3 트랜지스터와 함께 제1 트랜지스터를 다이오드 형태로 연결한다. 제5 트랜지스터는 제1 트랜지스터의 드레인과 제2 전압을 공급하는 제2 전원 사이에 연결되어 있으며, 제6 트랜지스터는 제1 트랜지스터의 소스와 출력단 사이에 연결되어 있다. 여기서, 제2, 제5 및 제6 트랜지스터의 게이트에 동일한 제어 신호가 인가된다. In the current sample / hold circuit, a capacitor is connected between the source and the gate of the first transistor, and the second transistor is connected between the first power source that supplies the first voltage and the source of the first transistor. The third transistor is connected between the input terminal and the gate of the first transistor, and the fourth transistor connects the first transistor in the form of a diode together with the third transistor when turned on. The fifth transistor is connected between a drain of the first transistor and a second power supply for supplying a second voltage, and the sixth transistor is connected between a source and an output terminal of the first transistor. Here, the same control signal is applied to the gates of the second, fifth and sixth transistors. 샘플/홀드, 전류, 트랜지스터, 커패시터, 표시장치 Sample / Hold, Current, Transistor, Capacitor, Display

CURRENT DRIVE DEVICE, ITS DRIVE METHOD, AND DISPLAY DEVICE USING CURRENT DRIVE DEVICE

A current drive apparatus for an active matrix display operates a plurality of loads, e.g. organic or inorganic EL elements, by applying a current thereto. The apparatus includes a plurality of output terminals to which the loads are respectively connected. A single current generation circuit comprising e.g. a digital to analogue converter and a current mirror, outputs an operating current having a predetermined current value. A plurality of current storage circuits are provided in accordance with the respective output terminals, sequentially sample and hold the operating current and then simultaneously output the drive currents based on the sampled operating currents to the respective output terminals. The operating current has a current value according to an input signal. The current storage circuit includes a voltage component holding section which samples the operating current outputted from the current generation circuit and holds a voltage component for driving a drive control current corresponding to a current value of the operating current for driving a second current mirror.

Demultiplexer using current sample/hold circuit, and display apparatus using the same

본 발명은 전류 샘플/홀드 회로를 이용한 역다중화 장치, 및 이를 이용한 디스플레이 장치에 관한 것이다. 본 발명의 일실시예에 따른 역다중화 장치는 제1 구간 동안 데이터 전류를 소정 순서로 샘플링하고, 제2 구간 동안 상기 샘플링하여 저장한 데이터에 해당되는 전류를 적어도 두개의 신호선에 기입하는 제1 및 제2 샘플/홀드 회로를 포함하는 제1 샘플/홀드 회로 그룹, 및 제2 구간 동안 데이터 전류를 소정 순서로 샘플링하고, 제3 구간 동안 상기 샘플링하여 저장한 데이터에 해당되는 전류를 상기 복수의 데이터선에 기입하는 제3 및 제4 샘플/홀드 회로를 포함하는 제2 샘플/홀드 회로 그룹을 포함한다. 본 발명의 일실시예에 따른 디스플레이 장치는 이러한 역다중화 장치를 포함하고, 짝수번째 프레임과 홀수번째 프레임에서 제1 샘플/홀드 회로 그룹의 샘플링 순서와 제2 샘플/홀드 회로 그룹의 샘플링 순서 중 적어도 하나가 서로 다르도록 설정된다.

Current sampling method and circuit

Current memory

Integrator circuit

A bilinear integrator comprises a first input (1) and a second input (5). The input (1) is connected to the input of a first current memory cell formed by two transistors (T1, T2), capacitor (C1), and switch (S1). The first current memory cell is arranged to store a current applied to its input during a first portion  of each sampling period and to reproduce that current at its output during a second portion  of the succeeding sampling period. The second input (5) is connected to the input of a second current memory cell formed by three transistors (T3, T4 and T5), capacitor (C2) and switch (S3) via the switch (S2). During a second portion  of each sampling period the current applied to the second input (5) and the current produced at the output of the first current memory cell are applied to the input of the second current memory cell. The second current memory cell has two outputs (from the drain electrodes of transistors (T4, T5)). The first output is fed back to the input of the first current memory cell while the second output is fed to the integrator output (8).

Switched current memory cell

A switched current memory cell includes a current source 100 having one end connected to an operation power source (Vdd) stage, a current memory circuit unit 200 that stores an input current; which is inputted in a sampling mode of the current from the current source 100 , during a hold mode, maintains the current value stored in the hold mode, and outputs the stored current in an output mode, an input switch SW 10 that is turned on in the sampling mode to transfer an input current to the current memory circuit unit 200 , and turned off in the hold mode, an output switch SW 20 that is turned on in the output mode to output current from the current memory circuit unit 200 , and a current cut circuit unit 300 that connects a current path between the operation power source Vdd stage and the current source 100 in the input mode and output mode, and separates the current path between the operation power source Vdd stage and the current source 100 in the hold mode.

Current amplifier and current mode a/d converter using the same

(57)【要約】 【課題】回路の動作速度に対する要求を増大させること なく高精度化を達成できる、電流を２倍に増幅する電流 増幅装置を提供する。 【解決手段】入力端子１５１からの入力電流を第１の電 流サンプルホールド回路１０１により所定周期でサンプ ルしてホールドした電流と、入力電流を電流反転回路１ １０で反転させた電流を結線で加算することによって、 入力電流の２倍の電流を生成し、この電流を第２および 第３の電流サンプルホールド回路１０２，１０３により 交互にサンプルしてホールドし、かつ交互に出力端子１ ５２へ出力する電流増幅装置。

Sampled analog current storage circuit

Circuit

由于制造过程或所采用的基片中的差别而引起的门极绝缘薄膜中的变化，以及沟道区域晶体状态中的变化，这两种因素的结合产生的阈值电压的变化或变动性困扰着晶体管。本发明提供了一种电路，该电路具有一种配置，使得电容元件的两个电极能够保持一个特定晶体管的门极－源极电压。本发明提供了一种电路，该电路能够通过使用一种恒流源来在所述电容元件的两个电极之间设定一个电位差。

Current memory and circuit arrangement comprising current memories

Current memory cell

Current memory cell

본원은 샘플 간격동안에 전류 단자(5)상에서 전류를 샘플링하고 홀드 간격 동안에는 전류 단자(5)에 전류를 공급하기 위한 전류 메모리 셀에 관한 것이다. 제1스위치(S1)는 샘플 간격동안에는 다이오드로서 홀드 간격동안에는 전류원으로서 PMOS 트랜지스터(P1)를 스위치한다. 샘플 간격동안에 상기 전류 단자(5)의 전류는 PMOS 트랜지스터(P1)에 카피된다. 홀드 간격 동안에는 PMOS 트랜지스터(P1)의 전류는 전류 단자(5)에 카피된다. 미러링은 2개의 NMOS 트랜지스터(N1, N2) 및 하나의 반전 스위치(S2)에 의해 영향받으며, 샘플 간격과 홀드 간격동안에 전류 미러 회로의 입력과 출력을 반전한다. 상기 전류 미러 회로(N1, N2) 및 PMOS 전류원(P1)은 바디 효과에 의해 발생된 기판 전압에 민감한 전류 싱크로서 동작한다. The present application relates to a current memory cell for sampling current on current terminal 5 during a sample interval and for supplying current to current terminal 5 during a hold interval. The first switch S1 switches the PMOS transistor P1 as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current at the current terminal 5 is copied to the PMOS transistor P1. During the hold interval, the current of the PMOS transistor P1 is copied to the current terminal 5. Mirroring is affected by two NMOS transistors N1 and N2 and one inverting switch S2, inverting the input and output of the current mirror circuit during the sample interval and the hold interval. The current mirror circuits N1 and N2 and the PMOS current source P1 operate as current sinks sensitive to the substrate voltage generated by the body effect.

Acoustic imaging system

The invention concerns acoustic imaging systems. It consists in producing delays required for the reception signals of each of the sensors (201) of such a system using a set (203) of cells (207) with current memory. Said cells are posted and read by means of two offset registers (204, 205) wherein circulates a single bit per register. The space between the bits delays the signal introduced in the set, to form channels. The system enables the use of very compact acoustic cameras or ultrasonograph probes.

Current copiers with improved accuracy

A current copier (10) is disclosed having a reduced transconductance at the output (18) to reduce the corresponding amount of deviation of the current sample. The disclosed current copier may be implemented on an integrated circuit and includes a residue circuit (12) for receiving an input current (I IN ) at an input node (16) during a first operating cycle, for generating an estimate current (I EST ) corresponding to the input current, and for generating a residue current (IRES) from the input current and the estimate current; and a first current copier (14) for storing the residue current during the first operating cycle, and for generating an output current (at 18) from the stored residue current during a second operating cycle.

Display drive apparatus in which display pixels in a plurality of specific rows are set in a selected state with periods at least overlapping each other, and gradation current is supplied to the display pixels during the selected state, and display apparatus

A display drive apparatus includes a selection circuit which sets display pixels in a plurality of specific rows of the display panel in a selected state with periods at least overlapping each other. A gradation signal generation circuit generates a gradation signal which controls a luminance gradation of each display pixel based on the display data and sequentially supplies the generated gradation signal in time series. A plurality of signal distribution circuits sequentially distribute the gradation signal supplied by the gradation signal generation circuit in accordance with the plurality of display pixels in each column at the timing of time-series supply. A plurality of current holding circuits individually hold the distributed gradation signal and simultaneously supply as the gradation current a current having a current value based on the held gradation signal to the display pixels in the plurality of specific rows.

Current sample and hold circuit and display device using the same

전류 샘플/홀드 회로에서, 커패시터가 제1 트랜지스터의 소스와 게이트 사이에 연결되어 있으며, 제2 트랜지스터가 제1 전압을 공급하는 제1 전원과 제1 트랜지스터의 소스 사이에 연결되어 있다. 제3 트랜지스터는 입력단과 제1 트랜지스터의 게이트 사이에 연결되어 있으며, 제4 트랜지스터는 턴온 시에 제3 트랜지스터와 함께 제1 트랜지스터를 다이오드 형태로 연결한다. 제5 트랜지스터는 제1 트랜지스터의 드레인과 제2 전압을 공급하는 제2 전원 사이에 연결되어 있으며, 제6 트랜지스터는 제1 트랜지스터의 소스와 출력단 사이에 연결되어 있다. 여기서, 제2, 제3, 제4 및 제6 트랜지스터는 PMOS 트랜지스터이며, 제5 트랜지스터는 NMOS 트랜지스터이다. In the current sample / hold circuit, a capacitor is connected between the source and the gate of the first transistor, and the second transistor is connected between the first power source that supplies the first voltage and the source of the first transistor. The third transistor is connected between the input terminal and the gate of the first transistor, and the fourth transistor connects the first transistor in the form of a diode together with the third transistor when turned on. The fifth transistor is connected between a drain of the first transistor and a second power supply for supplying a second voltage, and the sixth transistor is connected between a source and an output terminal of the first transistor. Here, the second, third, fourth and sixth transistors are PMOS transistors, and the fifth transistor is an NMOS transistor. 샘플/홀드, 전류, 트랜지스터, 커패시터, 표시장치 Sample / Hold, Current, Transistor, Capacitor, Display

Current amplifier and current mode analog/digital converter using the same

In a current amplifier, a current obtained by holding an input current from an input terminal by a first current sample/hold circuit is added through a connection to a current obtained by inverting the input current by a current inverter to generate a current twice the input current. This current is alternately sampled and held by second and third current sample/hold circuits and alternately output to an output terminal.

Frequency voltage conversion circuit, semiconductor device, and memory system

【課題】回路内で発生するリーク電流を抑制するとともに、定電流源に印加される正弦波ノイズ等の影響を受けた場合でも、一定の出力電圧を出力することができる周波数電圧変換回路を提供する。 【解決手段】周波数電圧変換回路は、第１の電流を出力する定電流源と、定電流源に直列接続された第１のスイッチと、第１のスイッチとグランドとの間に直列接続された第１の容量と、第１のスイッチ及び第１の容量間の第１のノードと出力ノードとの間に設けられた第２のスイッチと、第１のノードとグランドとの間に設けられた第３のスイッチと、第１のスイッチに並列に接続された第４のスイッチと、第４のスイッチとグランドとの間に直列接続された第２の容量と、第４のスイッチ及び第２の容量間の第２のノードと出力ノードとの間に設けられた第５のスイッチと、第２のノードとグランドとの間に設けられた第６のスイッチと、を有する。 【選択図】図８

Current sample and hold circuit and method and demultiplexer and display device

一种数据采样和保持电路，具有电流源型的输入端和电流宿型的输出端。该采样和保持电路包括第一晶体管，电容，以及多个开关，用于采样和保持吸收到数据驱动器输出端的数据电流。当所采样和保持的数据电流施加到数据线上时，数据电流吸收到采样和保持电路的输出端上。该采样和保持电路与具有电流宿型输出端的数据驱动器一起使用。

Signal processing arrangements

Switched current circuits include current memory cells which store analogue currents by way of the charge on the gate source capacitance of an MOS transistor. A source of inaccuracy in these circuits is switch charge injection into the gate source capacitance. It has been found that the error current produced by a single current memory cell is relatively flat over a current range centered above a peak value of stored current. When two current memory cells are connected in cascade this error may be cancelled. In order to produce equal errors an optimum bias current is generated which depends on parameters variable in integrated circuit manufacturing processes but which are relatively constant within an individual integrated circuit. The two cascaded current memory cells include controllable bias current sources and a control circuit controls the current sources so that the current memory cells operate at the optimum bias current. The control circuit includes two further current memory cells connected in cascade and two different value current sources are provide. The error current due to switch charge injection charges a capacitor (Cx). The voltage across this capacitor controls current sources (T16,T17) and also current sources (T14, T15). The current sources (T14,T15) and capacitor form a control feedback loop that causes the bias current to approximate the optimum value.

Differential circuits

一种单晶体管电流镜像与适当的负载相接合，其中结合了适当的开关集合，以实现比较器功能。具体地，差分电路包括单晶体管电流镜像，所述单晶体管电流镜像包括通过开关与晶体管相连的电容器以及通过各自独立的开关与电流镜像相连的两个电流源，与电容器开关一起操作电流源之一的开关，以便充电电容器，并且操作另一个电流源的开关，以便所述电路作为具有电流源负载的源极跟随放大器进行操作。因此，晶体管特性的空间分布不会影响比较器功能。

Switched-current memory

A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (i¿Or) is produced. The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

A circuit arrangement for storing sampled analogue electrical currents

Voltage buffer for capacitive loads

A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory.

Current memory

Integrator circuit.

Device for limiting power loss during digital signal sampling

本发明涉及用于在数字信号采样时限制损耗功率的装置。所述装置包括布置在数字信号的信号路径中的电路，其中，所述电路设置成，响应于表明采样暂停的控制信号，减小沿着信号路径的电流。

Current driving circuit

A current driving circuit includes: a reference input terminal to which a first reference current is given; a current mirror circuit for receiving the first reference current and outputting a first internal current corresponding to the first reference current; a bias voltage generation section for receiving the first internal current and generating a bias voltage corresponding to the first internal current; an output reference current generation section for receiving the bias voltage and generating a second reference current corresponding to the bias voltage; a reference current output terminal for outputting the second reference current; an internal current generation transistor for receiving at a gate thereof the bias voltage and generating a second internal current corresponding to the bias voltage; and an output current generation section for receiving the second internal current and generating n output currents corresponding to the second internal current.

Current sampling method and circuit

A current sampling circuit including a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for sampling a gate source voltage in a first sampling phase and a second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase.

Integrator circuit

Differential circuits

A single transistor current-mirror is interfaced with a suitable load in combination with a suitable set of switches to accomplish a comparator function. In particular, the differential circuit comprises a single transistor current mirror, including a capacitor connected to the transistor by a switch, and two current sources connected to the current mirror by respective and independent switches, the switch of one of the current sources being operated together with the capacitor switch so as to charge the capacitor and the switch of the other current source being operated so that the circuit operates as a source-follower amplifier with a current-source load. The comparator function is, thus, not influenced by the spatial distribution of the characteristics of the transistors used to implement the circuit.

CROSS-THROUGH REDUCTION SYSTEM FOR POWERED STORAGE CELLS

POWERED MEMORY

Differential circuits

Detection circuit and signal detection method

一种检测电路及信号检测方法。该检测电路包括具有电流取样晶体管、电容组、放大器以及开关组的电流取样电路及检测器。电容组设置在栅极与源极之间，用以储存栅极与源极之间的压差，栅极与源极之间的压差对应于欲取样电流。放大器具有输入端以及输出端，并且在栅极与源极之间，提供回授路径。开关组用以对电容值所储存的栅源电压进行取样，栅源电压对应于欲取样电流。电容组具有第一以及第二电容电路。在第一取样期间，第一电容电路对栅极与该源极之间的压差进行取样。在第二取样期间，第一及第二电容电路对栅极与源极之间的压差进行取样。开关组可根据第一取样期间的取样结果，在第一及第二取样期间，位移放大器的操作点。检测器产生欲取样电流。

Switched-current memory

스위치된 전류 메모리 회로는, 입력 전류(i)가 공급되며 스위치(S1)를 통하여 메모리 트랜지스터(M)의 드레인 전극에 접속된 입력을 갖는다. 제 2 스위치(S3)는 메모리 회로 입력과 그라운드된 게이트 트랜지스터(G)의 소스 전극 사이에 접속되며, 상기 그라운드된 게이트 트랜지스터(G)의 드레인 전극은 메모리 트랜지스터(M)의 게이트 전극에 접속된다. 메모리 트랜지스터(M)의 드레인 전극은, 스위치(S2)를 통해, 출력 전류가 생성되는 출력에 접속된다. 제 2 스위치(S3)는 저장된 전류의 전하 주입 효과를 감소시키는 제로 전압 스위칭을 제공한다. The switched current memory circuit has an input supplied with an input current i and connected to the drain electrode of the memory transistor M through the switch S1. The second switch S3 is connected between the memory circuit input and the source electrode of the grounded gate transistor G, and the drain electrode of the grounded gate transistor G is connected to the gate electrode of the memory transistor M. The drain electrode of the memory transistor M is connected to the output through which the output current is generated via the switch S2. The second switch S3 provides zero voltage switching which reduces the charge injection effect of the stored current.

Integrator circuit

An integrator circuit for input signals in the form of sampled analogue currents has an input connected to a node (2). Also connected to the node (2) are a first current memory cell (C1, T1, S2) and a second current memory cell (C2, T2, T3, S3). The switches (S1, S3) are operated on opposite phases of a clock signal synchronised with the sampling period. The first current memory cell produces an output current when switch (S2) is open while the second current memory cell produces a first output when switch (S3) is open and a second output (T3) which is connected to the output (6) of the integrator and which is continuously available. Forward or Backward Euler mapping is produced by closing switch (S1) on appropriate phases of the clock. A Bilinear mapping can be produced by connecting an inverted version of the input signal to a second input (8) and appropriately clocking the switches (S1, S4). A feedforward function can be added by use of a further input (9) directly connected to the node (2). Various higher performance current memory cells are also disclosed together with fully differential versions of the integrator.

Processing sampled analogue electrical signals

The invention relates to a circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of an electrical current, the circuit arrangement comprising means for combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample curent(s) in one or more preceding sample periods, and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement is formed by a plurality of modules which each generate and accept bi-directional signal currents and which contain current sources so that internally only unidirectional currents are processed. The transistors which conduct signal currents are arranged to be of one conductivity type only. This reduces the voltage requirements at the interfaces between modules.

Differential circuits

A single transistor current-mirror is interfaced with a suitable load in combination with a suitable set of switches to accomplish a comparator function. In particular, the differential circuit comprises a single transistor current mirror, including a capacitor connected to the transistor by a switch, and two current sources connected to the current mirror by respective and independent switches, the switch of one of the current sources being operated together with the capacitor switch so as to charge the capacitor and the switch of the other current source being operated so that the circuit operates as a source-follower amplifier with a current-source load. The comparator function is, thus, not influenced by the spatial distribution of the characteristics of the transistors used to implement the circuit.

Active current mode sampling circuit

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

本发明涉及一种电流驱动装置、电流驱动方法及使用该装置的显示装置，该电流驱动装置通过向多个负载施加电流来操作该多个负载，包括：分别与这些负载连接的多个输出端子(Tout)；单电流产生电路(10)，输出具有预定电流值的操作电流；多个电流存储电路(30A)按照各个输出端子设置，顺序读取和保存操作电流，并且根据该操作电流同时输出驱动电流给上述输出端子。所述操作电流具有对应输入信号的电流值。电流存储电路(30A)包括一个电压分量保存单元，读取从电流产生电路输出的操作电流并保存对应于操作电流的电流值的电压分量。

Circuit arrangement for processing sampled analogue electrical signals

A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, comprises means for combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement is formed by a plurality of circuit modules, for example scaling, memory, and integrator modules, each of which may be capable only of processing uni-directional currents. To enable easy interconnection of the modules, each module is arranged to receive and deliver bi-directional currents and to generate internally bias currents to enable conversion from bi-directional to uni-directional currents and vice versa. In order to increase the accuracy of current summing at inputs to the modules the input circuit of the module is provided as a current conveyor circuit which has a very low input impedance.

Current sample-and-hold-circuit, a/d converter and a method for operating a current sample-and-hold circuit

The invention relates to a current sample-and-hold circuit comprising, several sub-circuits, in which a current signal is stored. At least one of said sub-circuits contains a switch. The inventive current hold-and-sample circuit is characterised in that each of the sub-circuits contains a linear resistor, which is connected in such a way that the current signal generates a voltage drop across the resistor, that each of the sub-circuits contains at least one inverting control amplifer, which sets an initial current of the circuit in a hold operational mode, thus inducing a voltage drop across the resistor, said voltage drop being substantially as great as the voltage drop across the resistor before the hold operational mode.

Circuit arrangement for storing sampled electrical analog currents.

Oled display with ping pong current driving circuit and simultaneous scanning of lines

A display drive apparatus includes a selection circuit which sets display pixels in a plurality of specific rows of the display panel in a selected state simultaneously with selection signals of said rows at least overlapping each other. A gradation signal generation circuit generates a gradation signal which controls a luminance gradation of each OLED display pixel based on the display data and sequentially supplies the generated gradation signal in a ping pong manner. A plurality of signal distribution circuits sequentially distribute the gradation signal supplied by the gradation signal generation circuit in accordance with the plurality of display pixels in each column at the timing of time-series supply. A plurality of current holding circuits individually hold the distributed gradation signal and simultaneously supply as the gradation current a current having a current value based on the held gradation signal to the display pixels in the plurality of simultaneously scanned rows.

Display drive apparatus, display apparatus and drive control method thereof

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit

Clock feedthrough reduction system for switched current memory cells

Sampling Analog Signal Processing Apparatus and Method in Digital BiCMOS Process

디지털 BiCMOS 프로세스에서, MOS 트랜지스터의 기억 기능 및 바이폴라 트랜지스터의 큰 트랜스컨덕턴스를 이용하면, 속도는 주로 MOS 트랜지스터에 의한 커패시턴스 및 바이폴라 트랜지스터의 트랜스컨덕턴스에 의해 결정된다. CMOS를 이용하는 종래의 SI 기술에 비해 본 발명이 우수한 점은 속도가 빠르고, 에러가 적으며, 정확도가 높다는 것이다. BiCMOS를 이용하는 다른 기술에 비해 본 발명이 우수한 점은 에러가 적고, 정확도가 높다는 것이다. 본 발명의 방식의 독특한 특징은, MOS 소자의 고 입력 임피던스 및 바이폴라 소자의 트랜스컨덕턴스를 조합시키는 것이며, 여기서, 양방의 소자는 BiCMOS 프로세스에서만 이용 가능하고, CMOS 프로세스에서는 이용할 수 없다. In the digital BiCMOS process, using the memory function of the MOS transistor and the large transconductance of the bipolar transistor, the speed is mainly determined by the capacitance by the MOS transistor and the transconductance of the bipolar transistor. The advantage of the present invention over conventional SI technology using CMOS is that it is fast, low in error, and high in accuracy. The advantage of the present invention over other techniques using BiCMOS is that it has fewer errors and higher accuracy. A unique feature of the scheme of the present invention is the combination of the high input impedance of the MOS device and the transconductance of the bipolar device, where both devices are available only in the BiCMOS process and not in the CMOS process.

Aktive strommodus-abtastschaltung

램프 생성기 및 이를 포함하는 이미지 센서

작은 면적으로 구현되고 글리치 없는 램프 생성기는 로우 디코더, 컬럼 디코더, 전류 셀 매트릭스 및 전류-전압 변환기를 포함한다. 로우 디코더는 복수의 행 선택 신호들을 생성한다. 컬럼 디코더는 복수의 열 선택 신호들을 생성한다. 전류 셀 매트릭스는 순차적으로 턴-온되며 복수의 단위 전류들을 제공하는 복수의 전류 셀들을 포함하고, 복수의 단위 전류들을 합산하여 출력 전류를 생성한다. 전류-전압 변환기는 전류 셀 매트릭스의 출력 전류를 램프 전압으로 변환한다. 복수의 전류 셀들 각각은 상응하는 행 선택 신호 및 상응하는 열 선택 신호가 활성화될 때 턴-온되고, 상기 상응하는 행 선택 신호 또는 상기 상응하는 열 선택 신호가 비활성화되더라도 단위 전류를 지속적으로 제공한다. 글리치 발생을 방지할 수 있다.

Image sensing device and operating method thereof

Disclosed is an image sensing device including a plurality of current cells whose total number to be used is adjusted based on a plurality of enable signals, and which are sequentially controlled based on a reset signal and a plurality of selection signals; a current-voltage conversion circuit suitable for converting a plurality of unit currents, which are supplied from current cells used among the plurality of current cells, into a ramp signal; and a first control circuit suitable for generating the plurality of enable signals based on a maximum conversion code value corresponding to a slope of the ramp signal.

샘플/홀드 회로 및 이를 이용한 표시 장치

본 발명의 샘플/홀드 회로는 제1 스위치, 제1 저장소자, 제2 스위치, 제2 저장소자, 제3 스위치, 및 제4 스위치를 포함한다. 제1 스위치는 제1 기간에서 제1 전압을 전달한다. 제1 저장소자는 출력단에 연결되며, 제1 스위치로부터 전달되는 제1 전압을 저장한다. 제2 스위치는 제1 기간 이전의 제2 기간에서 제1 제어신호에 응답하여 제1 레벨 또는 제2 레벨을 선택적으로 가지는 입력 데이터를 전달한다. 제2 저장소자는 제2 스위치로부터 전달되는 입력 데이터를 저장한다. 제3 스위치는 제2 저장소자에 저장된 제1 레벨의 입력 데이터에 응답하여 제2 전압을 전달하며, 제2 저장소자에 저장된 상기 제2 레벨의 입력 데이터에 응답하여 턴오프된다. 제4 스위치는 제1 기간 이후의 제3 기간에서 출력단과 제3 스위치를 전기적으로 연결한다. 출력단은 제3 기간에서 출력데이터를 출력한다. 샘플, 홀드, 샘플/홀드 회로, 데이터 구동부

Analog Circuit and Display Device and Electronic Device

The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the/effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

半導体装置、表示装置、及び電子機器

Computing circuitry

This application relates to computing circuitry ( 200, 500, 600 ) for analogue computing. A plurality of current generators ( 201 ) are each configured to generate a defined current (I D1 , I D2 , . . . I Dj ) based on a respective input data value (D 1 , D 2 , . . . D j ). A memory array ( 202 ), having at least one set ( 204 ) of programmable-resistance memory cells ( 203 ), is arranged to receive the defined currents from each of the current generators at a respective signal line ( 206 ). Each set ( 204 ) of programmable-resistance memory cells ( 203 ) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module ( 207 ) is coupled to each of the signal lines to generate a voltage at an output node ( 210 ) based on the sum of the voltages on each of the signal lines.

Bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station and a mobile device

The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

图像感测装置及其操作方法

本申请公开了图像感测装置及其操作方法。公开了一种图像感测装置，该图像感测装置包括：多个电流单元，基于多个使能信号来调节要使用的电流单元的总数，并且基于重置信号和多个选择信号来依次控制所述多个电流单元；电流‑电压转换电路，其被设置为将从所述多个电流单元当中的使用的电流单元供应的多个单位电流转换为斜坡信号；以及第一控制电路，其被设置为基于与斜坡信号的斜率对应的最大转换码值来生成所述多个使能信号。

이미지 센싱 장치 및 그의 동작 방법

본 발명의 일실시예는, 복수의 인에이블신호에 기초하여 사용되는 총 개수가 조절되고, 리셋신호와 복수의 선택신호에 기초하여 순차적으로 제어되는 복수의 전류 셀; 상기 복수의 전류 셀 중 사용되는 전류 셀들로부터 공급되는 복수의 단위 전류를 램프신호로 변환하기 위한 전류-전압 변환회로; 및 상기 램프신호의 기울기에 대응하는 최대 변환 코드값에 기초하여 상기 복수의 인에이블신호를 생성하기 위한 제어회로를 포함하는 이미지 센싱 장치를 제공한다.

Current comparator arrangement

A current comparator arrangement has first and second inputs (100, 103) and an output (105) and comprises cross-coupled transistors (MP1, MP2). The arrangement also includes current stores (MP3, MP4) and is arranged so that the input currents to be compared are fed to the current stores during a first portion of a clock period during which the cross-coupled latch is reset. The input current connections are then reversed and the input currents are added to the stored currents for feeding to the latch. This cancels common mode and offset currents.

スイッチト・エミッタ・フォロワ回路

딥 러닝 인공 신경망에서의 아날로그 뉴럴 메모리를 위한 입력 회로

딥 러닝 인공 신경망에서 아날로그 뉴럴 메모리에 대한 입력 회로에 대해 다양한 실시예가 개시된다.

Stromsteuerschaltung und steurverfahren dafür, und elektrolumineszentes anzeigegerät mit dieser schaltung

共享采样转换电容器架构

一种LIDAR设备包括输入节点、输出节点和采样转换电路。输入节点接收光电检测器信号，输出节点生成指示光电检测器信号的光强度值的输出信号。采样转换电路包括并联耦接在输入节点和输出节点之间的若干个检测通道。在一些方面，每个检测通道可以被配置为使用单个电容器在采样模式期间对光电检测器信号的值进行采样并且在转换模式期间保持采样的值。

Current folding cell and circuit comprising at least one folding cell

A current folding cell has current inputs and current outputs. Input currents are transferred from one current path to another and finally leading to the current outputs to establish a continuous folding characteristic. The signal current through one of the current paths often does not need to be substantially zero around the folding point in the folding characteristic. Comparator outputs in the cell provide digital outputs corresponding to the currents at the current inputs. An A/D converter can be constructed utilizing such current folding circuit cells in cascade and/or in parallel. The well-determined relationship between folder outputs can be used in a feedback loop to reduce or eliminate mismatch contributions. A mixer can be constructed using such current folding cells.

Switched emitter follower circuit

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

トラック・アンド・ホールド回路