Verfahren zum Erzeugen einer Schutzschicht auf einer Halbleiteranordnung mit mindestens einem p-n-UEbergang

VERFAHREN ZUR HERSTELLUNG EINER SCHICHT

NIEDRIG-TEMPERATUR-VERFAHREN ZUR HERSTELLUNG VON GESCHICHTETEN SUPERGITTERMATERIALEN

Herstellungsmethode eines Bi enthaltenden dünnen Films mit Schichtstruktur

Vorrichtung mit Zr-Ge-Ti-O oder Hf-Ge-Ti-O als dielektrisches Material und Verfahren zur Herstellung

Thin film formation method

Preparing PbTiO3 thin films and sols

A PbTiO3 film is prepared by applying a PbTiO ý sol coating onto a substrate, and annealing the substrate. The PbTiO3 sol may be prepared by reacting tetrapropyl orthotitanate, lead acetate trihydrate and acetic acid. The substrate such as glass, SiO2/Si, Pt/Ti/SiO2/Si and SrTiO3 may be preheated prior to annealing. The sol may be applied by spin coating.

Improvements relating to annealing

SEMICONDUCTOR COMPONENT WITH SUPERPARAELEKTRI GATE INSULATOR

DIELECTRIC FILMS AND THEIR MANUFACTURING PROCESSES

USE OF SCHICHTIGEM OVER LATTICE MATERIAL

Hybrid semiconductor structure and device

Zirconium-doped bst materials and mocvd process for forming same

Catio₃ interfacial template structure on superconductor

Semiconductor structure

METHOD FOR FORMING FILM

In a film-forming process comprising depositing a molecule composed of a plurality of atoms on a substrate or reacting the molecule with an atom in the substrate to produce a compound, an improvement which comprises generating plasma in an atmosphere of a mixed gas of the molecule with an inert gas having a metastable energy level higher than the energy required for transferring the molecule to an atomic state, to thereby dissociate the molecule into atoms in advance prior to forming a film. This eliminates the need for dissociation of the molecule on the substrate and allows the practice of the film-forming process at a low temperature.

Crystallographically Aligned Ferroelectric Films Usable in Memories and Method of Crystallographically Aligning Perovskite Films

THIN FILM CAPACITORS ON GALLIUM ARSENIDE SUBSTRATE AND PROCESS FOR MAKING THE SAME

A silicone nitride barrier layer (12) is deposited on a gallium arsenide substrate (11) to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer (14) is deposited on the barrier layer. A first electrode (16) comprising an adhesion layer (18) and a second layer (20) is formed on the stress reduction layer. An essentially anhydrous alkoxycarboxylate liquid precursor is prepared, just before use a solvent exchange step is performed, then the precursor is spun on the first electrode, dried at 400 .degree.C, and annealed at between 600 .degree.C and 850 .degree.C to form a BST capacitor dielectric (22). A second electrode (24) is deposited on the dielectric and annealed.

Strontium ruthenium oxide interface

Structure formation method

Dielectric Devices using multi layer oxide artificial superlattice

STRONTIUM RUTHENIUM OXIDE INTERFACE

METHOD OF FORMING FERROELECTRIC FILM, FERROELECTRIC MEMORY, PROCESS FOR PRODUCING FERROELECTRIC MEMORY, SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE

A method of forming a ferroelectric film, comprising exposing amorphous oxide film (30) superimposed on substrate (10) to pulsed laser beams or lamp light so as to create oxide microcrystal nuclei (40). Light transmission/absorption film (22) is formed on the oxide film containing microcrystal nuclei (40). Further, the light transmission/absorption film (22) on its upper side is exposed to pulsed laser beams or lamp light so as to crystallize the oxide. Thus, ferroelectric material (50) is provided. © KIPO & WIPO 2007 ...

ＰＮｂＺＴ 박막의 제조 방법

... 본 발명은, 막 중의 각 조성이 대략 균일해지고, 보다 압전 특성 및 유전 특성이 높은 PNbZT 박막의 제조 방법을 제공한다. 본 발명의 PNbZT 박막의 제조 방법은, 조성식 PbzNbxZryTi1-yO3 (0 ＜ x ≤ 0.05, 0.40 ≤ y ≤ 0.60 및 1.05 ≤ z ≤ 1.25) 을 만족하고 지르코늄 및 티탄의 농도비 Zr/Ti 가 상이한 복수 종류의 졸겔액을 준비하는 공정과, 농도비 Zr/Ti 가 단계적으로 작아지도록 복수 종류의 졸겔액 중에서 소정의 졸겔액을 선택하여 기판 상에 졸겔액의 도포 및 예비 소성을 2 회 이상 반복함으로써, 기판 (12) 상에 농도비 Zr/Ti 가 단계적으로 작아지는 2 층 이상의 예비 소성막 (11a ∼ 11c) 을 적층하는 공정과, 복수의 예비 소성막 (11a ∼ 11c) 을 일괄적으로 소성함으로써 단일의 PNbZT 박막 (11) 을 얻는 공정을 포함한다.

SEMICONDUCTOR DEVICE USING Pt FILM FOR IMPROVING ORIENTATION OF CRYSTALS IN LOWER ELECTRODE AND MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and its manufacturing method are provided to acquire the high reliability from the device by improving the orientation of crystals in a lower electrode using a Pt film. CONSTITUTION: An interlayer dielectric is formed on a silicon substrate(11), wherein the interlayer dielectric is uniformly planarized. An SiO2 layer(15) is formed on the interlayer dielectric. An Al2O3 layer(18) is formed on the SiO2 layer. A ferroelectric capacitor structure is formed on the Al2O3 layer. The ferroelectric capacitor structure comprises a lower electrode, a ferroelectric film and an upper electrode. At this time, the lower electrode(22) is made of a Pt film. © KIPO 2006 ...

METHOD FOR FORMING THIN FILM

A method for forming a thin film, characterized in that it comprises a surfactant film formation step of forming a film containing a surfactant on the surface of a substrate for forming the thin film, a vapor phase film growth step of contacting the resultant substrate with a gas containing a silica derivative, to form a thin film containing the silica derivative, and a step of firing the substrate having the thin film containing a silica derivative to decompose and remove the substrate. The method allows the production of a dielectric thin film which has a high porosity and also a high mechanical strength with good productivity. © KIPO & WIPO 2007 ...

Gas feeding device, treating device, treating method, and storage medium

Provided is a gas feeding device (3) comprising a body portion (31) forming a substantially conical gas passage space (32) for passing gases from the side of a radially reduced end (32a) to the side of a radially enlarged end (32b), gas introduction ports (61a to 63a, 61b to 63b and 64) formed in the gas passage space (32) on the side of the radially reduced end (32a), for introducing the gases into the gas passage space (32), and a plurality of partition members (41 to 46) disposed in the gas passage space (32) and defining the gas passage space (32) concentrically. The diverging degree of one of the partition members (42 to 46) is larger than the diverging degree of that of the partition members (41 to 45), which is adjacent, on the radially inner side, to the former. As a result, the conductance in the gas passage inside of the gas feeding device can be made larger than that of the gas shower head of the prior art, thereby improving the replaceability of the gases in the gas passage.

Acceptor doped barium titanate based thin film capacitors on metal foils and methods of making thereof

The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002 - 0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.

Method of fabricating a hard mask

The present invention involves fabrication of a hard mask. An embodiment involves the conversion of a precursor into a top-surface imaging layer during a direct patterning step. Another embodiment of the present invention is a method of forming an etched pattern in a substrate. A further embodiment of the present invention is a method of forming an implanted region in a substrate. Preferred precursors are formed from a metal complex selected from those comprising acac, carboxylato, alkoxy, azide, carbonyl, nitrato, amine, and nitro complexes of Ba, Sr, Ti, Zr, Nb, Ta, Cr, Mo, W, Ru, Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Pb, and mixtures thereof.

Low temperature CVD processes for preparing ferroelectric films using Bi aryls

PROCESS FOR FABRICATION OF A FERROCAPACITOR

A process for fabricating a ferrocapacitor comprises etching a layer of amorphous PZT (5) formed over a layer (3) having a low concentration of nucleation centres for PZT crystallisation. The etching step forms individual PZT elements. The side surfaces of the PZT elements are then coated with a layer (9) of a material which promotes crystallisation of the PZT, such as one having a high concentration of PZT crystallisation centres (e.g. TiO2), and a PZT annealing step is carried out. The result is that the PZT has a high degree of crystallisation, with grain boundaries extending substantially horizontally through the PZT elements.

Dielectric devices having multi-layer oxide artificial lattice and method for fabrication the same

Disclosed are dielectric devices having a multi-layer oxide artificial lattice and a method for manufacturing the same. The method is adapted for a dielectric device having a substrate, a dielectric film coated on the substrate so as to be selectively patterned thereon, and a top electrode deposited and patterned on the dielectric film, a dielectric device having a substrate, a bottom electrode deposited on the substrate so as to be patterned thereon, a dielectric film coated on an upper portion of the lower electrode so as to be selectively patterned thereon, and a top electrode deposited and patterned on the dielectric film, or a dielectric device having a substrate, a bottom electrode deposited on the substrate and selectively patterned thereon, and a dielectric film coated on an upper portion of the bottom electrode so as to be selectively patterned thereon. The dielectric film is deposited at a single atomic layer thickness or at a unit lattice thickness. The dielectric film is formed ...

Method of manufacturing a high dielectric constant capacitor

This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device. This is accomplished by the invention of a capacitor element consisting of a substrate of semiconductor integrated circuit, a first electrode selectively deposited on the surface of said substrate, a capacitor insulation layer having a high dielectric constant deposited selectively on the surface of said first electrode, and a second electrode deposited on the surface of said capacitor insulation layer avoiding the contact with the first electrode, of which average grain diameters ...

High charge storage density integrated circuit capacitor

An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

Semiconductor device having a hydrogen barrier layer

A consolidated LSI including a logic circuit section and a FeRAM section formed on a single chip has a hydrogen barrier layer covering the cell array of the FeRAM section. The hydrogen barrier layer is made of plasma CVD SiON and has an excellent hydrogen barrier function. The hydrogen barrier layer protects the ferroelectric film of a ferroelectric capacitor an against the hydrogen-annealing process in the fabrication a process for the consolidated LSI.

Method for fabricating capacitor and method for fabricating semiconductor device

A method for fabricating a capacitor according to the present invention includes the steps of: forming a lower-level electrode layer over a structure having thermally deteriorative properties; depositing an insulating film, containing a titanium oxide, on the lower-level electrode layer at a deposition temperature of 400° C. or less; conducting a heat treatment at a temperature higher than the deposition temperature and lower than 500° C. after the insulating film has been deposited; and depositing an upper-level electrode layer on the insulating film after the heat treatment has been conducted.

Method for producing low thermal budget ferroelectric thin films for integrated device structures using laser-crystallization of spin-on sol-gel films

A method for developing large area highly oriented polycrystalline ferroelectric thin films using spin-on sol-gel deposition and laser crystallization techniques that allow for precise control of temperature distribution. The present invention improves quality, reliability, performance and cost effective production of ferroelectric non-volatile random access memory (FNVRAM) on thermally sensitive silicon and gallium arsenide semiconductor substrates compatible with very large scale integrated circuit technologies. The method is time effective, as crystallization is performed in three seconds as compared to thirteen hours in a conventional furnace for 1 cmx1 cm wafer. In addition, crystallization of the film is further achieved without exposing the underneath device structure to detrimental high temperature annealing conditions. The present invention results in minimization of thermal budget, interdiffusion of substrates/electrodes/films and phase segregation, and increased compatibility ...

Methods and apparatus for material deposition

The present invention discloses methods and apparatus for depositing thin films of complex (compound) materials, including ferroelectrics, superconductors, and materials with high dielectric constants through a technique which is hereby entitled photo-enhanced chemical vapor deposition and activation (PECVDA). The technique involves the use of multiple heating sources including a resistive heat bias heater, a tuned optical source (UV or laser) and a source (halogen lamps or microwave sources) for applying high energy, rapid thermal pulses in a precise time sequence.

Method of manufacturing ferroelectric capacitor using a sintering assistance film

Provided is a method of manufacturing a ferroelectric capacitor capable of manufacturing a ferroelectric capacitor with lower unevenness on a ferroelectric film surface, and thereby with excellent electric characteristics. By sputtering method, a PZT film is formed on a first conductive film, which constitutes a lower electrode of the ferroelectric capacitor. Thereafter, the PZT film is subjected to crystallization treatment (annealing). Next, a silicate solution is coated on the PZT film as a sintering assistance and then dried. Subsequently, sintering treatment is performed at the temperature of about 700° C. In this way, crystals constituting the PZT film are sintered, unevenness on the surface of PZT film is reduced, and tiny pores in grain boundaries are also reduced.

Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers

Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved ...

METHOD FOR PRODUCING A THIN FILM MADE OF LEAD ZIRCONATE TITANATE

The invention relates to a method for producing the thin film made of lead zirconate titanate in a 111-oriented perovskite structure, comprising the following steps: providing a substrate having a substrate temperature above 450° C. and a lead target, a zirconium target, and a titanium target; applying the thin film by sputtering lead, zirconium, and titanium from the respective targets onto the substrate, wherein the total deposition rate of lead, zirconium, and titanium is greater than 10 nm/min, the deposition rate of zirconium is selected in such a way that the atomic concentration of zirconium with respect to the atomic concentration of zirconium together with titanium in the thin film is between 0.2 and 0.3, and the deposition rate of lead is selected to be sufficiently low, depending on the substrate temperature and the total deposition rate of lead, zirconium, and titanium, for an X-ray diffractometer graph of the 111-oriented lead zirconate titanate to have a significant peak value ( 19 ) in a diffraction angle range from 33 to 35.5°; and completing the thin film.

Capacitor element and production thereof

A capacitor element includes a lower electrode, a ferroelectric film, and an upper electrode that are formed on a substrate. In the capacitor element, the ferroelectric film is formed by a reaction rate-determining method, and the lower electrode has a thickness of not more than 100 nm, and variation of the thickness of not more than 10%. With this, a capacitor element in which the composition variation of the ferroelectric film is suppressed, and a method for producing the same, are provided.

Field-effect transistor

A field-effect transistor is provided, which includes an organic thin film and which can realize a low threshold voltage while a stable, high field-effect mobility is ensured at the same time. In a field-effect transistor provided with a gate electrode, a source electrode, a drain electrode, a semiconductor film, a gate insulating film, and a substrate, the gate insulating film is formed from a plurality of insulating layers. Here, a first insulating layer in contact with the semiconductor film is formed from poly-p-xylylene formed into a film by a CVD method. A second insulating layer is formed from, for example, cyanoethylpullulan, and the dielectric constant is specified to be higher than that of the first insulating layer.

Ceramic film and method of manufacturing the same, semiconductor device, and piezoelectric device

A method of manufacturing a ceramic film includes a step of forming a ceramic film 30 by crystallizing a raw material body 20 . The raw material body 20 contains different types of raw materials in a mixed state. The different types of raw materials differ from one another in at least one of a crystal growth condition and a crystal growth mechanism in the crystallization of the raw materials. According to this manufacturing method, a surface morphology of the ceramic film can be improved.

Method of forming high dielectric constant thin film and method of manufacturing semiconductor device

A method of forming a (Ba, Sr) TiO3 high dielectric constant thin film with sufficient coverage is provided. A Ba material, an Sr material and a Ti material including bis (t-butoxy) bis (dipivaloylmethanate) titanium are dissolved in an organic solvent to obtain a solution material. The solution material is vaporized, so that material gas is obtained. A (Ba, Sr) TiO3 thin film is formed on a substrate by CVD reaction using the material gas.

Microelectronic piezoelectric structure and method of forming the same

A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.

HIGH-DENSITY LOW VOLTAGE NON-VOLATILE DIFFERENTIAL MEMORY BIT-CELL WITH SHARED PLATE-LINE

Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric). 1. A differential bit-cell comprising:a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;a first non-volatile structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL); anda second non-volatile structure coupled to one of the drain or source of the second transistor, and further coupled to the PL; a first layer comprising a first refractive inter-metallic, wherein the first layer is adjacent to the drain or source of the first or second transistor;', 'a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;', 'a third layer comprising a perovskite, wherein the third layer is adjacent to the second layer;', 'a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer; and', 'a fifth layer comprising a second refractive inter-metallic, wherein the fifth layer is ...

Method of forming haze- free BST films

Described herein is a method for producing a haze-free (Ba, Sr)TiO3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a substantially uniform desired crystal orientation, for example, (100), preferably by forming the film by metal-organic chemical vapor deposition at a temperature greater than about 580° C. at a rate of less than about 80 Å/min, to result in a film having about 50 to 53.5 atomic percent titanium. In another embodiment, where the BST film serves as a capacitor for a DRAM memory cell, a desired {100} orientation is induced by depositing the bottom electrode over a nucleation layer of NiO, which gives the bottom electrode a preferential {100} orientation. BST is then grown over the {100} oriented bottom electrode also with a {100} orientation. A nucleation layer of materials such as Ti, Nb and Mn can also be provided over the bottom electrode and beneath the BST film to induce smooth, haze-free BST ...

Ferroelectric Thin Films and Devices Comprising Thin Ferroelectric Films

A method of producing a device with a ferroelectric crystal thin film on a first substrate including the steps of providing a ferroelectric crystal, of irradiating a first surface of the ferroelectric crystal with ions so that a damaged layer is created underneath the first surface, of bonding a block of material including the first substrate to the ferroelectric crystal to create a bonded element, wherein an interface is formed between the first surface and a second surface of the block, and of heating the bonded element and separating it at the damaged layer, so that a ferroelectric crystal layer remains supported by the first substrate. By this method, very thin films-down to thicknesses of a fraction of a micrometer-of ferroelectric crystals may be fabricated without jeopardizing the monocrystalline structure.

Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof

Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.

Enhanced perovskite materials for photovoltaic devices

A perovskite material that has a perovskite crystal lattice having a formula of CxMyXz, and alkyl polyammonium cations disposed within or at a surface of the perovskite crystal lattice; wherein x, y, and z, are real numbers; C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine; M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr, and combinations thereof and X comprises one or more anions each selected from the group consisting of halides, pseudohalides, chalcogenides, and combinations thereof.

METHOD OF PRODUCING INORGANIC COMPOUND SOLID SUBSTANCE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of forming a more satisfactory inorganic compound solid (ferroelectric film or the like) out of organic compound materials containing metal elements by annealing at a relatively low temperature. In order to form a ferroelectric film, a solution of organic compound materials containing metal elements is coated over a semiconductor substrate (S41) and dried (S42), after which precalcining is carried out (S43). After this process is repeated until a predetermined film thickness is achieved, organic substance removing treatment is carried out (S45). The organic substance removing treatment is carried out by, for example, heat treatment (approximately at 550ºC) in a low-pressure atmosphere (approximately at 50 Torr). Post calcining is carried out to inorganic compound materials obtained by the organic substance removing treatment (S46). The post calcining is carried out at a temperature of approximately 550ºC, for example, whereby the inorganic compound materials are crystallized.

薄膜製造方法

SPUTTER FILM FORMING METHOD, SPUTTER FILM FORMING DEVICE AND PRODUCTION OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To form a compd. film having a stable compsn. and to facilitate the compositional control in the compd. film by using stable plasma wide in a process window as for a high frequency sputter film forming method. SOLUTION: In a high frequency sputter film forming method, a part or the whole part of a wall positioned at the outside of a space formed by a wafer and a target 14 is applied with A.C. voltage or A.C. current, or high frequency electric power is pulse-oscillated to reduce the temp. of electrons in plasma, or as the gas for sputtering, at least one kind of gas among helium, neon, xenon and krypton is contained. Otherwise, a part or the whole part of the wall positioned at the outside of the space formed by the wafer and the target is applied with minus voltage. COPYRIGHT: (C)1999,JPO ...

Halbleiter-Bauelement aus einem Material mit hoher Bandlücke und Dielektrizitätskonstante

Preparation of ferroelectric lead-zirconium-titanium oxide film comprises preparing pre-mixed reagent solution, evaporating to form precursor vapor, and introducing vapor into chemical vaporization chamber containing the substrate

Preparation of a ferroelectric lead-zirconium-titanium oxide (PZT) film on a substrate (22) comprises: (1) preparing a pre-mixed reagent solution containing a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium; (2) evaporating the reagent solution to form a precursor vapor; and (3) introducing the vapor into a chemical vaporization chamber (12) containing the substrate.

VERFAHREN ZUR HERSTELLUNG DOTIERTER BST-SCHICHTEN UND KONDENSATOREN FÜR INTEGRIERTE SCHALTUNGEN MIT MAGNESIUM DOTIERTEN BST SCHICHTEN

DÜNNSCHICHTKONDENSATOREN ÜBER EINEM GALLIUMARSENIDSUBSTRAT UND HERSTELLUNGSVERFAHREN

Dünne ferroelektrische Schicht von höchster Reinheit

Fabrication of ceramic films

Improvements in or relating to sol gel processing of lead zirconate titanate thin films

DEVICE ON BASIS FROM ORGANIC MATERIAL TO THE COLLECTION OF A PROBENANALYTS

SOURCES ASYMMETRICAL LEAGUE GENES, METALLIFEROUS CONNECTIONS WITH REDUCED SYMMETRY AND SYSTEM AND PROCEDURE, WITH THOSE THESE BEGUN

EVAPORATOR AND THE BESCHICTUNGSVORRICHTUNG WITH THE EVAPORATOR

ATOMIC POSITION SEPARATION SYSTEMS AND - PROCEDURES WITH METAL BETA DIKETIMINAT CONNECTIONS

FORERUNNER SOLUTION, PROCEDURE FOR YOUR PRODUCTION AND USE

Improvements to oxide films

Enhanced perovskite materials for photovoltaic devices

A perovskite material that has a perovskite crystal lattice having a formula of C ...

Semiconductor devices

Low temperature chemical vapor deposition process for forming bismuth-containingceramic thin films useful in ferroelectric memory devices

NASO-GASTRIC TUBE HOLDER

... 2130898 9316750 PCTABS00025 A tube holding clamp (14) in the form of a cylinder open at both ends is attached at one end to a connection (16) which is attached to an adhesive member for attachment to the nose of a patient. The cylinder is slit (32) along its length to permit the tube (18) free entry and to resiliently hold the tube. The connecting member (16) is angular to hold the clamp forward of and in line with the nostrils.

LOW TEMPERATURE PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME

A liquid precursor containing a metal is applied to a first electrode, RTP backed at a temperature of 700 ~C, and annealed at the same temperature from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700 ~C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8 <= u <= 1.0, 2.0 <= v <= 2.3, and 1.9 <= w <= 2.1.

Formation Method of FeRAM having BLT ferroelectric layer

Ferroelectric/paraelectric multiple thin film, method for forming the same, and high frequency tunable device using the same

엑시톤 버퍼층을 포함하는 페로브스카이트 발광 소자 및 이의 제조방법

... 엑시톤 버퍼층을 포함하는 페로브스카이트 발광 소자 및 이의 제조방법을 제공한다. 본 발명의 발광 소자는 제1 전극, 상기 제1 전극 상에 배치되고, 전도성 물질을 포함하는 도전층 및 상기 전도성 물질보다 낮은 표면 에너지를 갖는 불소계 물질을 포함하는 표면 버퍼층이 순차적으로 적층된 엑시톤 버퍼층, 상기 엑시톤 버퍼층 상에 배치되며 유무기 하이브리드 페로브스카이트 발광체를 포함하는 발광층, 및 상기 발광층 상에 배치된 제2 전극을 포함함에 따라 나노입자 발광체 안에 FCC와 BCC를 합친 결정구조를 갖는 유무기 하이브리드 페로브스카이트가 형성되며, 유기평면과 무기평면이 교대로 적층이 되어있는 라멜라 구조를 형성하고 있으며, 무기평면에 엑시톤이 구속되어 높은 색순도를 낼 수 있다.

PEROVSKITE-TYPE MANGANESE OXIDE THIN FILM

PZT-BASED FERROELECTRIC THIN FILM AND METHOD OF FORMING THE SAME

METHOD OF FORMING SPUTTERING LAYER, EQUIPMENT FOR FORMING SPUTTERING LAYER AND FABRICATING METHOD OF EQUIPMENT

PURPOSE: Method of forming sputtering layer and equipment for forming sputtering layer and fabricating method of the equipment are provided to control a composition of a chemical compound easily. CONSTITUTION: The method of forming sputtering layer comprises the steps of: supplying alternating voltage or alternating current to all or part of the wall, which is placed external of space between a wafer and a target; generating a high frequency power to reduce electron temperature of plasma; including at least a kind of gas of helium, neon, xenon and krypton as sputter gas; supplying minus voltage to all or part of the wall, which is placed external of space between a wafer and a target. COPYRIGHT 2000 KIPO ...

FERROELECTRIC FILM, FERROELECTRIC CAPACITOR, FERROELECTRIC MEMORY, PIEZOELECTRIC DEVICE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING FERROELECTRIC FILM, AND METHOD FOR MANUFACTURING FERROELECTRIC CAPACITOR

A ferroelectric film is composed of an oxide represented by a general formula of ABNbO. The component A comprises at least Pb, and the component B comprises at least one of Zr, Ti, V, W, Hf, and Ta. The ferroelectric film contains Nb in an amount of 0.05 <= x < 1. This ferroelectric film can be used in any of 1T1C, 2T2C and simple matrix ferroelectric memories.1-xx 3 © KIPO & WIPO 2007 ...

COMPOSITION FOR FERROELECTRIC THIN FILM FORMATION, METHOD FOR FERROELECTRIC THIN FILM FORMATION, AND FERROELECTRIC THIN FILM FORMED BY THE METHOD

Barium titanate thin films with titanium partially substituted by zirconium, tin or hafnium

Disclosed are high permittivity (dielectric constant), thin film CSD barium titanate based dielectric compositions that have titanium partially substituted by zirconium, tin or hafnium. The compositions show capacitance as a function of temperature that better satisfies the X7R requirements.

Semiconductor device and method of manufacturing same

A semiconductor device having a stacked capacitor is provided. A dielectric film (81) formed of BST by a sputtering process is entirely provided to cover upper part of a plurality of storage node electrodes (SN2). A dielectric film (82) formed of BST by a CVD process is entirely provided to cover the dielectric film (81). The dielectric films (81, 82) constitute a dielectric layer (80). A conductive layer made of platinum covers an entire surface of the dielectric film (82) to constitute a counter electrode (9) to the storage node electrodes. The dielectric layer has good step coverage, reduced dependence upon its underlying layer, and good crystallinity.

Semiconductor device and production thereof

In forming a metal oxide dielectric film of perovskite type for capacitor, an array of lower electrodes and a crystallization-assisting conductive film are simultaneously formed. The crystallization-assisting conductive film is formed outside the lower electrode array, at a distance of about 10 m or less from the outermost lower electrodes, in a width of 20 m or more. Then, a metal oxide dielectric film is formed thereon. Since the crystallization-assisting conductive film assists the crystallization of metal oxide dielectric film, capacitor elements which are superior in properties and reliability even when the capacitor elements are produced in a fine structure is obtained.

Integrated method and apparatus for forming an enhanced capacitor

A novel method and apparatus for forming a capacitor is described. According to the present invention, a substrate having a bottom electrode is provided. A metal-oxide dielectric film is then formed on the bottom electrode. The metal-oxide dielectric film is annealed with remotely generated radicals. A metal-nitride layer is then formed on the annealed metal-oxide dielectric film. A top electrode is then formed on the metal-nitride barrier layer.

Method for forming thin film and apparatus for forming thin film

This invention provides a method for forming thin film and an apparatus for forming thin film to ensure good composition of the thin film, film thickness uniformity and increased film formation rate. A shower head (9) having a plurality of ejection holes for supplying an organic metal gas at uniform density to the surface of a substrate (10) and a plurality of ejection holes for supplying an oxidizing gas at uniform density is provided in a reaction furnace (8) of an MOCVD system. A heater for heating the inside at a temperature higher than the thermal decomposition point of the organic metal gas but lower than the film forming temperature is provided in the vicinity of the substrate-side surface of the shower head (9).

Low-temperature crystallization of ceramic films by high-pressure processing

A process is disclosed for reducing the crystallization temperature of amorphous or partially crystallized ceramic films by providing a higher pressure under which the crystallization of the amorphous or partially crystallized ceramic films can be significantly enhanced. The present invention not only improves quality, performance and reliability of the ceramic films, but also reduces the cost for production. By lowering the crystallization temperature, the cost for thermal energy consumed during the crystallization process is greatly reduced. In addition, the interaction or interdiffusion occurring between films and substrates is significantly suppressed or essentially prevented, avoiding the off-stoichiometry and malfunction of thin films, which usually occur in the conventional high-temperature crystallization processes. The process of present invention also decreases the grain size of formed films, thus reducing the roughness of films and producing relatively smooth, good quality films ...

SEMICONDUCTOR FERROELECTRIC STORAGE TRANSISTOR AND METHOD FOR MANUFACTURING SAME

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME

A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode separation caused by the formation of the passivation film (insulating film) of a capacitor using a high ferroelectric material by plasma processing at a relatively low temperature and a method for manufacturing the memory. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode (105), a lower electrode (102), and a high ferroelectric oxide thin film (103) which is held between electrodes (105 and 102) and serves as a capacitor insulating film and an insulating protective film (106) which covers the capacitor structure and is formed by plasma processing. An oxygen introducing layer (104) is further formed on the surface of the thin film (103) constituting the capacitor insulating film. In the manufacturing process of the memory, for example, the oxygen introducing layer (104) is ...

Decoupling capacitor for high frequency noise immunity

Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al₂O₃. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.

DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Apparatus for stabilizing high pressure oxidation of a semiconductor device

A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N20 and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

Method for preparation of ferroelectric single crystal film structure using deposition method

A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric and electronic parts and devices is prepared by forming an electrode layer having a perovskite crystal structure on a substrate made of a silicon or ferroelectric single crystal optionally polished to have a off-axis crystal structure, and epitaxially growing a layer of a ferroelectric single crystal thereon by pulsed laser deposition (PLD) or metallorganic chemical vapor deposition (MOCVD).

Sputtering method for forming dielectric films

A method for forming a dielectric film having a desired composition comprising sputtering a dielectric material onto a substrate to produce an intermediary film, the intermediary film incorporating one or more elements in addition to those elements included in the desired composition of the dielectric film; and removing the one or more additional elements from the intermediary film to produce the dielectric film having the desired composition.

Misted precursor deposition apparatus and method with improved mist and mist flow

A substrate is located within a deposition chamber, the substrate defining a substrate plane. A liquid precursor is misted by ultrasonic or venturi apparatus, to produce a colloidal mist. The mist is generated, allowed to settle in a buffer chamber, filtered through a system up to 0.01 micron, and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film of solid material on the substrate, which is then incorporated into an electrical component of an integrated circuit.

Ferroelectric thin-film device and method for producing the same

A ferroelectric thin-film device comprises: a single crystal substrate; a conductive thin film formed on the single crystal substrate; and an oriented ferroelectric oxide thin film having a perovskite structure formed on the conductive thin film. The oriented ferroelectric thin film comprises a first layer having a composition changing from the interface with the conductive thin film in the thickness direction and a second layer having a constant composition formed on the first layer. The composition of the first layer and the composition of the second layer are substantially the same at the boundary between the first layer and the second layer.

Ferroelectric thin film and device including the same

A composition for forming a ferroelectric thin film includes: a PZT sol-gel solution including at least one of: a whole or partial hydrolysate of a lead precursor and a whole or partial hydrolyzed and polycondensated product thereof; a whole or partial hydrolysate of a zirconium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a zirconium complex having at least one hydroxy ion and at least one non-hydrolyzable ligand; and a whole or partial hydrolysate of a titanium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a titanium complex having at least one hydroxyl ion and at least one non-hydrolyzable ligand; and a Bi2SiO5 sol-gel solution including at least one of: a whole or partial hydrolysate of a silicon precursor and a whole or partial hydrolyzed and polycondensated product thereof, and a resultant obtained by refluxing triphenyl bismuth as a bismuth precursor.

Process for producing a semiconductor device

In forming a metal oxide dielectric film of perovskite type for capacitor, an array of lower electrodes and a crystallization-assisting conductive film are simultaneously formed. The crystallization-assisting conductive film is formed outside the lower electrode array, at a distance of about 10 mum or less from the outermost lower electrodes, in a width of 20 mum or more. Then, a metal oxide dielectric film is formed thereon. Since the crystallization-assisting conductive film assists the crystallization of metal oxide dielectric film, capacitor elements which are superior in properties and reliability even when the capacitor elements are produced in a fine structure is obtained.

COMPOSITION FOR FERROELECTRIC THIN FILM FORMATION, METHOD FOR FORMING FERROELECTRIC THIN FILM, AND FERROELECTRIC THIN FILM FORMED BY THE METHOD THEREOF

Disclosed is a composition for ferroelectric thin film formation which is used in the formation of a ferroelectric thin film of one material selected from the group consisting of PLZT, PZT, and PT. The composition for ferroelectric thin film formation is a liquid composition for the formation of a thin film of a mixed composite metal oxide formed of a mixture of a composite metal oxide (A) represented by general formula (1): (PbxLay)(ZrzTi(1-z))O3 [wherein 0.9 Подробнее

Integrated Capacitor Comprising an Electrically Insulating Layer Made of an Amorphous Perovskite-Type Material and Manufacturing Process

An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided.

Showerhead for cvd depositions

A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Thin film manufacturing apparatus, thin film manufacturing method and method for manufacturing semiconductor device

In an apparatus for manufacturing a ceramic thin film by employing a thermal CVD method, an internal jig, which is provided with a heat radiation material film on the surface, is provided at a position that faces a substrate (S) on which the film is to be formed. The thin film and a semiconductor device are manufactured using such apparatus.

Methods for producing a thin film consisting of nanosheet monolayer film(s) by spin coat methods, and hyperhydrophilized materials, substrates for an oxide thin film and dielectric materials obtained therefrom

To provide a method for producing a thin film consisting of nanosheet monolayer film(s) and use of the thin film obtained thereby. The method for producing a thin film consisting of nanosheet monolayer film(s) by a spin coat method according to the invention comprises a step for preparing an organic solvent sol formed by allowing nanosheets obtained by the exfoliation of an inorganic layered compound to be dispersed in an organic solvent; and a step for dropping the organic solvent sol onto a substrate and rotating the substrate using a spin coater. Preferably, the nanosheet size, the organic solvent sol concentration and the spin coater rotation speed are controlled.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

Perovskite oxide film and ferroelectric film using the same, ferroelectric device, and method for manufacturing perovskite oxide film

A perovskite oxide film is formed on a substrate, in which the perovskite oxide film has an average film thickness of not less than 5 μm and includes a perovskite oxide represented by a general formula (P) given below: (K 1−w−x , A w , B x )(Nb 1−y−z , C y , D z )O 3 - - - (P), where: 0<w<1.0, 0≦x≦0.2, 0≦y<1.0, 0≦z≦0.2, 0<w+x<1.0, A is an A-site element having an ionic valence of 1 other than K, B is an A-site element, C is a B-site element having an ionic valence of 5, D is a B-site element, each of A to D is one kind or a plurality of kinds of metal elements.

DIELECTRIC THIN FILM, METHOD OF MANUFACTURING SAME, AND APPLICATIONS THEREOF

A dielectric thin film and a method of manufacturing the same, wherein the manufacture of a dielectric thin film having a composition represented by BaSrTiO(wherein 0≦x≦1 and 0.9≦y≦1.1) includes applying a precursor to the thin film to a substrate and performing drying, and subsequently performing calcination by raising the temperature of the dried thin film at a rate of not more than 30° C./minute, thereby forming a dielectric thin film having an average primary particle size of not less than 70 nm, for which no cracks with a continuous linear length of 1.5 μm or greater exist at the surface of the thin film. 112-. (canceled)13. A method for manufacturing a dielectric thin film having a composition represented by BaSrTiO(wherein 0.1≦x≦0.5 and 0.9≦y≦1.1) , comprising the steps of:{'sub': n', '2n+1, 'preparing a precursor solution by dissolving an organic barium compound, an organic strontium compound, and a titanium alkoxide dissolved in an organic solvent such that a molar ratio of Ba:Sr:Ti is (1−x):x:y (wherein 0.1≦x≦0.5 and 0.9≦y≦1.1), and the organic barium compound and the organic strontium compound being metal salts of carboxylic acids represented by a formula CHCOOH (3≦n≦7);'}applying the precursor solution to a substrate to form a coating and drying the coating at a temperature of 150° C. to 400° C.;repeating the step of applying and drying to form a dried coating; andperforming calcination treatment by heating the dried coating to a temperature of not less than 450° C. and not more than 800° C. at a rate of temperature increase of 5 to 20° C./minute to form the dielectric thin film, which is formed by dielectric crystal particles having an average primary particle size of not less than 70 nm and not more than 300 nm, and{'sup': −1', '2, 'the dielectric thin film having no cracks which have a width of not less than 5 nm and not more than 60 nm and a continuous linear length of 1.5 μm or greater at a surface of the dielectric thin film, and the dielectric ...

SEMICONDUCTOR FERROELECTRIC STORAGE TRANSISTOR AND METHOD FOR MANUFACTURING SAME

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body () and a gate electrode conductor () are sequentially laminated in this order on a semiconductor base () that has a source region () and a drain region (). The insulating body () is configured by laminating a first insulating body () and a second insulating body () in this order on the base (), and the second insulating body () is mainly composed of an oxide of strontium, calcium, bismuth and tantalum. 112-. (canceled)13. A semiconductor ferroelectric memory transistor comprising a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order ,wherein the insulator includes a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, andwherein in the oxide of strontium, calcium, bismuth, and tantalum, a ratio of a calcium element to a strontium element is larger than 0 and not more than two-thirds.14. The semiconductor ferroelectric memory transistor according to claim 13 ,wherein the insulator is comprised of a first insulator and a second insulator stacked on the body in that order, andwherein the second insulator is mainly comprised of the oxide of strontium, calcium, bismuth, and tantalum.15. The semiconductor ferroelectric memory transistor according to claim 13 , wherein the oxide of strontium claim 13 , calcium claim 13 , bismuth claim 13 , and tantalum has a bismuth layered perovskite-type crystal structure.16. The semiconductor ferroelectric memory transistor according to claim 14 , wherein the oxide of strontium claim 14 , calcium claim 14 , bismuth claim 14 , and tantalum has a bismuth layered perovskite-type crystal structure.17. The ...

ANTIFERROELECTRIC PEROVSKITE GATE OXIDE FOR TRANSISTOR APPLICATIONS

An integrated circuit structure comprises a substrate. An antiferroelectric gate oxide is above the substrate, the antiferroelectric gate oxide comprising a perovskite material. A gate electrode is over at least a portion of the gate oxide. 1. An integrated circuit structure , comprising:a substrate;an antiferroelectric gate oxide above the substrate, the antiferroelectric gate oxide comprising a perovskite material; anda gate electrode over at least a portion of the gate oxide.2. The integrated circuit structure of claim 1 , wherein the integrated structure is selected from a group comprising: a transistor claim 1 , a capacitance stack; and a gate capacitance stack.3. The integrated circuit structure of claim 2 , wherein the transistor includes a configuration selected from a group comprising: planar claim 2 , fin-FET claim 2 , nanowire claim 2 , and silicon on insulator (SOI).4. The integrated circuit structure of claim 1 , wherein the gate electrode comprises a material selected from a group comprising: SrPbO claim 1 , LaSrMnO claim 1 , and LaSrCoO.5. The integrated circuit structure of claim 1 , wherein the integrated structure comprises a fin-FET transistor claim 1 , and wherein the antiferroelectric gate oxide comprising the perovskite material is approximately 1-10 nm in thickness claim 1 , and a width of the gate electrode matches the configuration of the transistor.6. The integrated circuit structure of claim 1 , wherein the antiferroelectric perovskite material is stoichiometry controlled to obtain a tunable gate leakage.7. The integrated circuit structure of claim 6 , wherein the antiferroelectric perovskite material comprises ABOtype perovskites having sub-lattices that include an A-site and a B-site claim 6 , wherein the A-site is doped with a rare earth material for first site ferroelectricity.8. The integrated circuit structure of claim 7 , wherein the B-site is doped with a 3d block transition metal for second site ferroelectricity.9. The integrated ...

SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES

A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. 1. A method of forming a semiconductor structure , the method comprising:etching a trench into a semiconductor substrate;forming a crystalline oxide layer in the trench, wherein the crystalline oxide fills an entire volume of the trench to form an epitaxial oxide structure, wherein said epitaxial oxide structure does not extend above a topmost planar surface of said semiconductor substrate; andforming a first semiconductor structure and a second semiconductor structure on the semiconductor substrate, wherein the epitaxial oxide structure is located between the first semiconductor structure and the second semiconductor structure, and wherein the epitaxial oxide structure substantially electrically isolates the first and the second semiconductor structure.2. The method of claim 1 , wherein the crystalline oxide comprises rare earth oxides.3. The method of claim 2 , wherein the rare earth oxide is selected from the group consisting of cerium oxide (CeO) claim 2 , lanthanum oxide (LaO) claim 2 , yttrium oxide (YO) claim 2 , gadolinium oxide (GdO) claim 2 , europium oxide (EuO) claim 2 , and terbium oxide (TbO).4. The method of claim 1 , wherein the crystalline oxide comprises a combination of rare earth oxides.5. The method of claim 4 , wherein the combination of rare earth oxides is a binary oxide having the chemical formula ABO claim 4 , wherein A is a rare earth metal atom and B is a different rare earth metal atom.6. The method of claim 1 , wherein the crystalline oxide comprises a perovskite material.7. The method of claim 6 , wherein the perovskite material is selected from the group consisting of strontium titanate (SrTiO) and barium ...

Crystallization of amorphous multicomponent ionic compounds

A method for crystallizing an amorphous multicomponent ionic compound comprises applying an external stimulus to a layer of an amorphous multicomponent ionic compound, the layer in contact with an amorphous surface of a deposition substrate at a first interface and optionally, the layer in contact with a crystalline surface at a second interface, wherein the external stimulus induces an amorphous-to-crystalline phase transformation, thereby crystallizing the layer to provide a crystalline multicomponent ionic compound, wherein the external stimulus and the crystallization are carried out at a temperature below the melting temperature of the amorphous multicomponent ionic compound. If the layer is in contact with the crystalline surface at the second interface, the temperature is further selected to achieve crystallization from the crystalline surface via solid phase epitaxial (SPE) growth without nucleation.

CRYSTALLINE STRONTIUM TITANATE AND METHODS OF FORMING THE SAME

Methods of forming a crystalline strontium titanate layer may include providing a substrate with a crystal enhancement surface (e.g., Pt), depositing strontium titanate by atomic layer deposition, and conducting a post-deposition anneal to crystallize the strontium titanate. Large single crystal domains may be formed, laterally extending greater distances than the thickness of the strontium titanate and demonstrating greater ordering than the underlying crystal enhancement surface provided to initiate ALD. Functional oxides, particularly perovskite complex oxides, can be heteroepitaxially deposited over the crystallized STO. 1. (canceled)2. A method of forming a layer comprising crystalline oxide on a substrate , the method comprising:depositing a layer comprising strontium oxide on the substrate by atomic layer deposition; andsubjecting the strontium oxide layer to a post-deposition anneal (PDA) under conditions selected to produce large crystal grains in the strontium oxide layer, the crystal grains having lateral dimensions exceeding the thickness of the strontium oxide layer by at least a factor of two.3. The method of claim 2 , wherein the crystalline oxide comprises a dopant.4. The method of claim 2 , wherein the strontium oxide is strontium titanate.5. The method of claim 2 , wherein the crystal grains have lateral dimensions exceeding the thickness of the strontium oxide layer by a factor of five.6. The method of claim 2 , wherein the layer comprising strontium oxide is deposited on a substrate comprising an exposed crystal enhancement layer over a wafer.7. The method of claim 6 , wherein the crystal enhancement layer comprises a noble metal layer.8. The method of claim 7 , wherein the crystal enhancement layer comprises a platinum layer.9. The method of claim 2 , wherein the layer comprising strontium oxide is deposited on a substrate comprising a self-assembled monolayer with periodic openings exposing an underlying Pt layer.10. The method of claim 2 , ...

Methods of Forming A Semiconductor Device

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.

Method for fabrication of crack-free ceramic dielectric films

The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 μm to about 20.0 μm and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 μm to about 20.0 μm.

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate. 1. An integrated circuit , comprising:a first insulation layer, wherein a first trench penetrates the first insulation layer;a bottom plate partly disposed on the first insulation layer and partly disposed in the first trench;a first patterned dielectric layer disposed on the bottom plate, wherein at least a part of the first patterned dielectric layer is disposed in the first trench;a medium plate disposed on the first patterned dielectric layer, wherein at least a part of the medium plate is disposed in the first trench, and wherein the bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor;a second patterned dielectric layer disposed on the medium plate; anda top plate disposed on the second patterned dielectric layer, wherein the medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor, and the bottom plate is electrically connected with the top plate, wherein the top plate is electrically separated from the medium ...

DRAM INTERCONNECT STRUCTURE HAVING FERROELECTRIC CAPACITORS

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells. 1. A method of making a microelectronic structure , the method comprising:forming transistors on a semiconductor substrate;forming a first set of electrodes overlying the transistors;depositing a dielectric layer in contact with the first set of electrodes;forming a second set of electrodes in contact with the dielectric layer;depositing a ferroelectric layer in contact with the second set of electrodes; andforming a third set of electrodes in contact with the ferroelectric layer.2. The method of claim 1 , further comprising depositing the dielectric layer in contact with the ferroelectric layer to form a capacitive bi-layer.3. The method of claim 2 , further comprising depositing a metal layer in contact with the capacitive bi-layer.4. The method of wherein the ferroelectric layer includes Pb(ZrTi)O.5. The method of wherein forming the first set of electrodes claim 1 , depositing the dielectric layer claim 1 , and forming the second set of electrodes comprises forming an array of positive capacitors claim 1 , each positive capacitor in the ...

Method of Etching Ferroelectric Capacitor Stack

A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained. 1. A method of fabricating an integrated circuit including ferroelectric capacitors , comprising the steps of:depositing a first conductive layer comprising iridium near a semiconducting surface of a body;depositing a ferroelectric layer comprising lead-zirconium-titanate over the first conductive film;depositing a second conductive layer comprising iridium overlying the ferroelectric layer;depositing a hard mask layer over the second conductive layer;patterning and etching the hard mask layer to define mask elements at one or more locations at which capacitors are to be formed; andthen removing portions of the first and second conductive films, and the ferroelectric material, at the location defined by the mask elements;wherein the removing step comprises:removing exposed portions of the second conductive layer by exposing the body to a plasma of a plurality of gases comprising a fluorine-bearing species to;then removing exposed portions of the ferroelectric layer by exposing the body to a plasma of a non-fluorine-bearing plurality of gases;then removing exposed portions of the first conductive layer by exposing the body to a plasma of a plurality of gases comprising a fluorine-bearing ...

METHOD FOR MANUFACTURING FERROELECTRIC THIN FILM DEVICE

This method for manufacturing a ferroelectric thin film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a ferroelectric thin film made of a sodium potassium niobate on the lower electrode film; an upper electrode film formation step of forming an upper electrode film on the ferroelectric thin film; and an upper electrode film etching step of shaping the upper electrode film into a desired micro-pattern by performing a reactive ion etching process on the upper electrode film. The upper electrode film etching step is a step of calculating a rate of change of sodium emission intensity in an ion plasma generated by the reactive ion etching process and determining that the etching process is completed when the rate of change falls below a predetermined threshold. 1. A method for manufacturing a ferroelectric thin film device , the method comprising:a lower electrode film formation step of forming a lower electrode film on a substrate;{'sub': 1-x', 'x', '3, 'a ferroelectric thin film formation step of forming a ferroelectric thin film made of a sodium potassium niobate (typical chemical formula of (KNa)NbO, 0.4≦x≦0.7) on the lower electrode film;'}an upper electrode film formation step of forming an upper electrode film on the ferroelectric thin film; andan upper electrode film etching step of shaping the upper electrode film into a desired micro-pattern by performing a reactive ion etching process on the upper electrode film, whereinthe upper electrode film etching step is a step of calculating a rate of change of sodium emission intensity in an ion plasma generated by the reactive ion etching process and determining that the etching process is completed when the rate of change falls below a predetermined threshold.2. The method for manufacturing a ferroelectric thin film device according to claim 1 , whereinthe predetermined threshold is 1.0 after the rate of ...

Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process. 1. A method of manufacturing an integrated circuit , comprising:forming at least one circuit element comprising a layer of a ferroelectric material near a semiconducting surface of a body;then forming at least one level of conductors overlying the element, each level comprising patterned metal conductors and a dielectric layer;forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors;then depositing a passivation layer over the protective overcoat layer; andheating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes.2. The method of claim 1 , wherein the ferroelectric material is lead-zirconium-titanate.3. The method of claim 2 , wherein the heating step heats the passivation layer to a curing temperature at or below about 390° C.4. The method of claim 1 , wherein the at least one circuit element comprises a plurality of ferroelectric capacitors; 'before the heating step, polarizing the ...

SHELLING OF HALIDE PEROVSKITE NANOPARTICLES FOR THE PREVENTION OF ANION EXCHANGE

A core/shell semiconductor nanoparticle structure comprises a core comprising a halide perovskite semiconductor and a shell comprising a semiconductor material that is not a halide perovskite (and that is substantially free of halide perovskites). The halide perovskite semiconductor core may be of the form AMX, wherein: A is an organic ammonium such as CHNH, (CH)(CHNH), PhCHNH, CHCHNH or 1-adamantyl methyl ammonium, an amidinium such as CH(NH), or an alkali metal cation such as Li, Na, K, Rbor Cs; M is a divalent metal cation such as Mg, Mn, Ni, Co, Pb, Sn, Zn, Ge, Eu, Cuor Cd; and X is a halide anion (F, Cl, Br, I) or a combination of halide anions. 1. A core/shell semiconductor nanoparticle comprising:a core comprising a halide perovskite semiconductor; anda shell substantially surrounding the core and comprising a semiconductor material that is not a halide perovskite,wherein the shell is substantially free of halide perovskites.2. The core/shell semiconductor nanoparticle of claim 1 , wherein the shell comprises BaTiO claim 1 , SrTiO claim 1 , BiFeO claim 1 , LaNiO claim 1 , CaTiO claim 1 , PbTiOor LaYbO.3. The core/shell semiconductor nanoparticle of claim 1 , wherein the shell comprises a group IIB-VIB semiconductor material or a group IV-VI semiconductor material.4. The core/shell semiconductor nanoparticle of claim 1 , wherein the shell comprises ZnS or PbS.5. The core/shell semiconductor nanoparticle of claim 1 , wherein the core comprises a halide perovskite semiconductor of the form AMX claim 1 , wherein A is an organic ammonium claim 1 , an anidinium or alkali metal cation claim 1 , M is a divalent metal cation claim 1 , and X is a halide anion.6. The core/shell semiconductor nanoparticle of claim 5 , wherein A is CHNH claim 5 , (CH)(CHNH) claim 5 , PhCHNH claim 5 , CHCHNH claim 5 , 1-adamantyl methyl ammonium claim 5 , CH(NH) claim 5 , Li claim 5 , Na claim 5 , K claim 5 , Rbor Cs.7. The core/shell nanoparticle of claim 5 , wherein M is Mg claim 5 , Mn ...

Method for producing ferroelectric thin film

A method for producing a ferroelectric thin film comprising: coating a composition for forming a ferroelectric thin film on a base electrode of a substrate having a substrate body and the base electrode that has crystal daces oriented in the (111) direction, calcining the coated composition, and subsequently performing firing the coated composition to crystallize the coated composition, and thereby forming a ferroelectric thin film on the base electrode, wherein the method includes formation of an orientation controlling layer by coating the composition on the base electrode, calcining the coated composition, and firing the coated composition, where an amount of the composition coated on the base electrode is controlled such that a thickness of the orientation controlling layer after crystallization is in a range of 5 nm to 30 nm, and thereby controlling the preferential crystal orientation of the orientation controlling layer to be in the (110) plane.

METHOD AND APPARATUS FOR A THIN FILM DIELECTRIC STACK

A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed. 1. A thin film capacitor comprising:a silicon substrate having a silicon dioxide layer;an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric;a first electrode layer on the adhesion layer;a dielectric layer on the first electrode layer;a second electrode layer on the dielectric layer; andconnections for the first electrode layer, the second electrode layer, or both.2. The thin film capacitor of claim 1 , further comprising another adhesion layer between the adhesion layer and the first electrode layer.3. The thin film capacitor of claim 1 , wherein the other adhesion layer is a thin film of Ti claim 1 , Ta claim 1 , TiOx or TaOx.4. The thin film capacitor of claim 1 , wherein the dielectric layer comprises:a first dielectric layer on the first electrode layer, wherein the first dielectric layer has a columnar-oriented grain structure; anda group of second dielectric layers stacked on the first dielectric layer, wherein each of the group of second dielectric layers has a randomly-oriented grain structure, wherein at least one of the group of second dielectric layers is formed from a different material from at least one other of the group of second dielectric layers.5. The thin film capacitor of claim 1 , wherein the adhesion layer is between 50 to 500 Angstroms thick.6. A thin film capacitor comprising:a silicon substrate with a silicon dioxide layer;an adhesion layer on the silicon dioxide layer of the silicon substrate, wherein the adhesion layer comprises a polar dielectric selected from ...

COMPOSITION FOR FORMING FERROELECTRIC THIN FILM, AND METHOD FOR MANUFACTURING SAME

A composition containing a precursor of a ferroelectric thin film, a solvent, and a reaction control substance, can form a ferroelectric thin film by temporary firing and permanent firing of a coating film. The composition contains the reaction control substance in such an amount that a Young's modulus of a film formed in a step of temporary firing at a temperature of 200° C. to 300° C. becomes equal to or less than 42 GPa, and a Young's modulus of a film formed in a step of permanent firing at a temperature of 400° C. to 500° C. becomes equal to or greater than 55 GPa. Thus a thin film having high crystallinity can be formed which substantially does not crack at the time of permanent firing even if the thickness of the coating film formed per single coating operation is increased. 1. A composition for forming a ferroelectric thin film that forms a ferroelectric thin film by temporary firing and permanent firing of a coating film , comprising:a precursor of the ferroelectric thin film;a solvent; anda reaction control substance,wherein the reaction control substance is contained in such an amount that a Young's modulus of a film formed in a step of temporary firing at a temperature of 200° C. to 300° C. becomes equal to or less than 42 GPa, and a Young's modulus of a film formed in a step of permanent firing at a temperature of 400° C. to 500° C. becomes equal to or greater than 55 GPa.2. The composition for forming a ferroelectric thin film according to claim 1 ,wherein the reaction control substance is polyvinyl pyrrolidone (PVP), polyacrylamide, or polyvinyl acetamide.3. The composition for forming a ferroelectric thin film according to claim 1 ,wherein the reaction control substance is contained in an amount of 0.0025 mol to 0.25 mol with respect to 1 mol of the precursor of the ferroelectric thin film.4. The composition for forming a ferroelectric thin film according to that is a composition for forming a PZT thin film claim 1 ,wherein the precursor of PZT is ...

Reduced capacitance coupling effects in devices

A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

LIQUID AND METHOD FOR REMOVING CSD COATED FILM, FERROELECTRIC THIN FILM AND METHOD FOR PRODUCING THE SAME

Coated film is removed at an outer peripheral edge of a substrate before heat-treating in CSD method by spraying or dropping liquid for removing CSD coated film including water and organic solvent mixed in a weight ratio of 50:50 to 0:100, in which the organic solvent is one or more selected from the group consisting of β-diketones, β-ketoesters, polyhydric alcohol, carboxylic acids, alkanolamines, α-hydroxy carboxylic acid, α-hydroxy carbonyl derivatives, and hydrazone derivatives. 15-. (canceled)6. A method for removing CSD coated film formed by applying material solution on a substrate in CSD method , whereina liquid for removing CSD coated film is sprayed or dropped on an outer peripheral edge of the substrate while rotating the substrate, andthe coated film is removed at the outer peripheral edge thereof;wherein the liquid for removing CSD coated film comprises water and organic solvent,wherein the organic solvent is one or more selected from the group consisting of β-diketones, β-ketoesters, polyhydric alcohol, carboxylic acids, alkanolamines, α-hydroxy carboxylic acid, α-hydroxy carbonyl derivatives, and hydrazone derivatives,and wherein the organic solvent and the water are mixed in a weight ratio of 50:50 to 0:100.7. A method for producing ferroelectric thin film in CSD method comprising the steps of:forming a coated film by applying material solution comprising organic metallic compound for forming ferroelectric thin film on a substrate;removing the coated film at an outer peripheral edge of the substrate by spraying or dropping a liquid for removing CSD coated film at the outer peripheral edge of the rotating substrate; andforming ferroelectric thin film by heat-treating the coated film;wherein the liquid for removing CSD coated film comprises water and organic solvent,wherein the organic solvent is one or more selected from the group consisting of β-diketones, β-ketoesters, polyhydric alcohol, carboxylic acids, alkanolamines, α-hydroxy carboxylic acid, ...

Gas supply device, processing apparatus, processing method, and storage medium

A gas supply device 3 includes a device body 31 forming a substantially conical gas-conducting space 32 for conducting gases therethrough from a diametrally reduced end 32 a of the space 32 to a diametrally enlarged end 32 b thereof, gas introduction ports 61 a to 63 a, 61 b to 63 b , and 64 , each provided near the diametrally reduced end 32 a of the gas-conducting space 32 in the device body 31 to introduce the gases into the gas-conducting space 32 , and a plurality of partitioning members 41 to 46 provided in the gas-conducting space 32 of the device body 31 to partition the gas-conducting space 32 concentrically. The partitioning members 42 to 46 arranged adjacently to each other at a radially outer side of the gas-conducting space 32 are greater than the adjacently arranged partitioning members 41 to 45 at a radially inner side in dimensionally diverging rate per partitioning member. Thus, internal gas flow channels of the gas supply device have high gas conductance and enhanced gas replaceability, compared with those of the conventional gas showerhead.

THIN-FILM STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A thin-film structure includes a support layer and a dielectric layer on the support layer. The support layer includes a material having a lattice constant. The dielectric layer includes a compound having a Ruddlesden-Popper phase (ABX). where A and B each independently include a cation, X is an anion, and n is a natural number. The lattice constant of the material of the support layer may be less than a lattice constant of the compound. 1. A thin-film structure comprising:a support layer including a material having a lattice constant; and {'sub': n+1', 'n', '3n+1, 'the dielectric layer including a compound having a Ruddlesden-Popper phase (ABX), where A and B each independently include a cation, X is an anion, and n is a natural number, the lattice constant of the material of the support layer being less than a lattice constant of the compound.'}, 'a dielectric layer on the support layer,'}2. The thin-film structure of claim 1 , whereinA includes an alkali metal, an alkaline earth metal, or a rare earth metal, andB is a transition metal.3. The thin-film structure of claim 1 , whereina compressive strain occurs in the dielectric layer at an interface between the dielectric layer and the supporting layer,the compressive strain in the dielectric layer occurs in an in-plane direction that is in-plane with the interface between the dielectric layer and the supporting layer,the compressive strain in the dielectric layer induces a tensile strain in the dielectric layer, andthe tensile strain occurs in an out-of-plane direction that is out-of-plane with the interface between the dielectric layer and the supporting layer.4. The thin-film structure of claim 3 , whereinthe tensile strain in the dielectric layer that occurs in the out-of-plane direction varies with the n value of the compound and the lattice constant of the material of the support layer.5. The thin-film structure of claim 4 , whereinthe lattice constant of the material included in the support layer is capable ...

FERROELECTRIC DEVICE AND METHOD FOR MANUFACTURING SAME

A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity. 1. A method of making a ferroelectric device having a semiconductor on which there is a multi-layered structure having an insulator , a ferroelectric and a conductor built up in this order or a multi-layered structure having a ferroelectric and a conductor built up in this order , the method being characterized in that it comprises making a layer of said ferroelectric by a metal organic chemical vapor deposition process which comprises the steps of: preparing a raw material liquid solution having complex compounds each dissolved in a solvent , the complex compounds containing strontium , calcium , bismuth and tantalum; dispersing the raw material liquid solution into a carrier gas to form a raw material gaseous medium in a state of gas and liquid two phases; introducing the raw material gaseous medium while in the state of gas and liquid two phases into a vaporizing chamber to form a vapor thereof; and introducing the vapor into a film forming chamber; wherein the complex compound is Ca[Ta(OCH)(OCHOCH)].2. A method of making a ferroelectric device as ...

Method for manufacturing ferroelectric film

To provide a method for manufacturing a ferroelectric film formed of a lead-free material. The method for manufacturing a ferroelectric film according to an aspect of the present invention is a method for manufacturing a ferroelectric film including the steps of pouring a sol-gel solution for forming (K 1-X Na X )NbO 3 into a mold 3, calcining the sol-gel solution to form a (K 1-X Na X )NbO 3 material film inside the mold 3, heat-treating and crystallizing the (K 1-X Na X )NbO 3 material film in an oxygen atmosphere to form a (K 1-X Na X )NbO 3 crystallized film inside the mold 3 and removing the mold 3 through etching, and is characterized in that the mold 3 is more easily etched than the (K 1-X Na X )NbO 3 crystallized film and the X satisfies a formula below 0.3≦X≦0.7.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABOwhere ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDOwhere ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer. 1. A semiconductor device comprising:a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode,{'sub': '3', 'wherein the lower electrode includes ABOwhere ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element;'}{'sub': '3', 'the dielectric layer includes CDOwhere ‘C’ is a third metal element and ‘D’ is a fourth metal element;'}the lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked;the first layer includes the first metal element and oxygen;the second layer includes the second metal element and oxygen; andthe dielectric layer is in contact with the lower electrode at a first contact surface, the first contact surface corresponding to the second layer.2. The semiconductor device of claim 1 , wherein the first contact surface has a {100} crystal plane.3. The semiconductor device of claim 1 , wherein each of the lower electrode and the dielectric layer have a perovskite crystal structure.4. The semiconductor device of claim 1 , wherein the dielectric layer ...

Enhanced Perovskite Materials for Photovoltaic Devices

A perovskite material that has a perovskite crystal lattice having a formula of CMX, where x, y, and z, are real numbers, and 1,4-diammonium butane cation cations disposed within or at a surface of the perovskite crystal lattice. C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine. M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr and combinations thereof. X comprises one or more anions each selected from the group consisting of halides, sulfides, selenides, and combinations thereof. 1. A perovskite material comprising:{'sub': x', 'y', 'z, 'a perovskite crystal lattice having a formula of CMX; and'} x, y, and z, are real numbers;', 'C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine;', 'M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr and combinations thereof; and', 'X comprises one or more anions each selected from the group consisting of halides, pseudohalides, chalcogenides, and combinations thereof., '1,4-diammonium butane cation cations disposed within or at a surface of the perovskite crystal lattice; wherein2. The perovskite material of claim 1 , wherein the 1 claim 1 ,4-diammonium butane cations have a concentration between 1 mol % and 20 mol % in the perovskite material.3. The perovskite material of claim 1 , wherein the 1 claim 1 ,4-diammonium butane cations have a concentration between 1 mol % and 5 mol % in the perovskite material.4. The perovskite material of claim 1 , wherein the 1 claim 1 ,4-diammonium butane cations have a concentration of approximately 5 mol % in the ...

METHOD FOR PRODUCING FERROELECTRIC THIN FILM

A method for producing a ferroelectric thin film comprising: coating a composition for forming a ferroelectric thin film on a base electrode of a substrate having a substrate body and the base electrode that has crystal faces oriented in the (111) direction, calcining the coated composition, and subsequently performing firing the coated composition to crystallize the coated composition, and thereby forming a ferroelectric thin film on the base electrode, wherein the method includes formation of a orientation controlling layer b coating the composition on the base electrode, calcining the coated composition, and firing the coated composition, where an amount of the composition coated on the base electrode is controlled such that a thickness of the orientation controlling layer after crystallization is in a range of 35 nm to 150 nm, and thereby controlling the preferential crystal orientation of the orientation controlling layer in the (100) plane. 113-. (canceled)14. A ferroelectric thin film that has preferred crystal orientation in the (100) plane that is produced by a method comprising:coating a composition for forming a ferroelectric thin film on a base electrode of a substrate having a substrate body and the base electrode that has crystal faces oriented in the (111) direction,performing calcination of the coated composition, and subsequently performing firing of the coated composition to crystallize the coated composition, and thereby forming a ferroelectric thin film on the base electrode,wherein the method includes performing formation of a orientation controlling layer by a process including coating the composition for forming a ferroelectric thin film on the base electrode, performing calcination of the coated composition, and performing firing of the coated composition,where an amount of the composition for forming a ferroelectric thin film coated on the base electrode is controlled such that a thickness of the orientation controlling layer after ...

FERROELECTRIC-MODULATED SCHOTTKY NON-VOLATILE MEMORY

Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element. 1. A resistive memory element , comprising:a semiconductive material comprising a first portion and a second portion;a first metal element positioned adjacent to the first portion to form a first Schottky junction with the semiconductive material;a second metal element positioned adjacent to the second portion to form a second Schottky junction with the semiconductive material; anda ferroelectric material adjacent to the semiconductive material, the ferroelectric material configured to generate an electric field into the semiconductive material based on a voltage applied to the ferroelectric material to change a Schottky barrier height and a resistance associated with the semiconductive material.2. The resistive memory element of claim 1 , further comprising:a first metal terminal coupled to and proximate the first Schottky junction;.a second metal terminal coupled to and proximate the second Schottky junction; anda third metal terminal coupled to and proximate the ferroelectric material.3. The resistive memory element ...

PIEZOELECTRIC THIN FILM PROCESS

A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature. 1: A process of forming an integrated circuit containing a piezoelectric thin film , comprising the steps of:dispensing a first portion of a sol gel solution onto a top surface of a wafer which will contain said integrated circuit;spinning said wafer so as to distribute said first portion of said sol gel solution across said top surface of said wafer so as to form a first sol gel layer on said top surface of said wafer;drying said first sol gel layer by spinning said wafer in a non-reducing ambient;baking said first sol gel layer in a non-reducing ambient to remove solvent in the first sol gel layer; and providing an oxidizing ambient to said first sol gel layer;', 'baking said wafer and said first sol gel layer at a temperature between 250° C. and 350° C. for at least 30 seconds, while ramping a pressure of said oxidizing ambient from less than 100 torr to between 700 torr and 1000 torr at a ramp rate greater than 10 torr per second, and while flowing an oxidant in said ambient between 3 and 7 standard liters per minute (slm);', 'ramping up said temperature of said wafer and said first sol gel layer to between 425° C. and 475° C. over a time period of at least 20 seconds, while maintaining said ambient pressure between 700 torr and 1000 torr, and while maintaining ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor. 1. A method of manufacturing a semiconductor device , the method comprising:forming an insulating film over a semiconductor substrate;forming a conductive film over the insulating film;forming a first ferroelectric film over the conductive film;forming an amorphous second ferroelectric film containing iridium and ruthenium over the first ferroelectric film;forming a first conductive metal oxide film over the second ferroelectric film;annealing and crystallizing the second ferroelectric film after forming the first conductive metal oxide film;patterning the first conductive metal oxide film to form a top electrode of a ferroelectric capacitor;patterning the first ferroelectric film and the second ferroelectric film to form a capacitor dielectric film of the ferroelectric capacitor; andpatterning the conductive film to form a bottom electrode of the ferroelectric capacitor.2. The method of manufacturing a semiconductor device according to claim 1 , wherein in the forming the second ferroelectric film claim 1 , the second ferroelectric film is formed by sputtering using a sputter target to which iridium and ruthenium are added.3. The method of manufacturing a semiconductor device according to claim 1 , wherein a material ...

PEROVSKITE MATERIAL WITH ANION-CONTROLLED DIELECTRIC PROPERTIES, THIN FILM CAPACITOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME

A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO)-(ABON). A represents a divalent element, B represents a tetravalent element, γ satisfies 0.005≦γ≦1.0, 1−α satisfies 0.05≦1−α≦0.9, and 1−α is an area ratio between the regions containing rich N anions and the matrix of remaining oxide perovskite material. 1. (canceled)2. A thin film capacitor comprising:a substrate;an adhesion layer disposed on the substrate;a lower electrode layer disposed on the adhesion layer;a lower buffer layer of dielectric perovskite material disposed on the lower electrode layer;a main dielectric layer of crystalline oxynitride composite paraelectric material disposed on the lower buffer layer;an upper oxide buffer layer disposed on the main dielectric layer; andan upper electrode film of electrically conductive material disposed on top of the upper oxide buffer layer.3. The thin film capacitor according to claim 2 , wherein a dielectric stack including the main dielectric layer of crystalline oxynitride composite paraelectric material claim 2 , the lower buffer layer claim 2 , and the upper oxide buffer layer has an effective dielectric constant of about 800 to about 1100 and a thickness of about 90 nm to about 100 nm.4. A thin film capacitor made by a fabrication process comprising the steps of:{'sub': 2', '3, 'depositing an adhesion layer on a substrate material, the adhesion layer containing at least one of TiN, TiOx, Ti, HfN, and AlO, or a combination thereof;'}depositing a lower electrode layer of electrically conductive material on the adhesion layer, the lower electrode layer containing at least one of Pt, Ni, Cu, and Al or a combination thereof and being separated from the adhesion layer by a barrier layer;depositing a lower oxide buffer layer of a paraelectric high dielectric constant material so as to be in direct contact ...

PBNZT FERROELECTRIC FILM, SOL-GEL SOLUTION, FILM FORMING METHOD AND METHOD FOR PRODUCING FERROELECTRIC FILM

To provide a PBNZT ferroelectric film capable of preventing sufficiently oxygen ion deficiency. The PBNZT ferroelectric film according to an embodiment of the present invention is a ferroelectric film including a perovskite-structured ferroelectric substance represented by ABO, wherein the perovskite-structured ferroelectric substance is a PZT-based ferroelectric substance containing Pb as A-site ions and containing Zr and Ti as B-site ions, and the A-site contains Bi as A-site compensation ions and the B-site contains Nb as B-site compensation ions. 1. A method for producing a ferroelectric film comprising the steps of:preparing a sol-gel solution including a raw material solution including: a hydrolysis condensation polymerization of an alkoxide raw material including Pb, Bi, Nb, Zr and Ti and heteropolyacid; and polar solvents and unsaturated fatty acids;coating said sol-gel solution on a substrate to form a coated film on said substrate;subjecting said coated film to temporary burning at a temperature of 25 to 450° C. to form a ferroelectric material film on said substrate; andheat-treating said ferroelectric material film at a temperature of 450 to 800° C. to produce a ferroelectric film including a perovskite-structured ferroelectric substance obtained by crystallizing said ferroelectric material film.2. The method for producing a ferroelectric film according to claim 1 , wherein said ferroelectric film is a PBNZT ferroelectric film comprising a perovskite-structured ferroelectric substance represented by (PbBi)((TiZr)Nb)O claim 1 , wherein:X is 0.05 to 0.1; andY is 0.05 to 0.1.3. The method for producing a ferroelectric film according to claim 1 , wherein said ferroelectric film has a relative permittivity of 400 or more.4. A ferroelectric film being formed by the method for producing a ferroelectric film according to and having a relative permittivity of 400 or more. The present invention relates to a PBNZT ferroelectric film, a sol-gel solution, a film ...

Mxene layers as substrates for growth of highly oriented perovskite thin films

The present disclosure is directed to using MXene compositions as templates for the deposition of oriented perovskite films, and compositions derived from such methods. Certain specific embodiments include methods preparing an oriented perovskite, perovskite-type, or perovskite-like film, the methods comprising: (a) depositing at least one perovskite, perovskite-type, or perovskite-like composition or precursor composition using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) onto a film or layer of a MXene composition supported on a substrate to form a layered composition or precursor composition; and either (b) (1) heat treating or annealing the layered precursor composition to form a layered perovskite-type structure comprising at least one oriented perovskite, perovskite-type, or perovskite-like composition; or (2) annealing the layered composition; or (3) both (1) and (2).

Reduced capacitance coupling effects in devices

A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

DRAM INTERCONNECT STRUCTURE HAVING FERROELECTRIC CAPACITORS EXHIBITING NEGATIVE CAPACITANCE

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells. 1. A method , comprising:forming a thin dielectric layer on a substrate;forming openings in the thin dielectric layer;forming an array of lower electrodes in the thin film dielectric layer by filling the openings in the thin dielectric layer with a conductive material;planarizing the thin dielectric layer and array of lower electrodes;forming a thick dielectric layer over the thin dielectric layer and the array of lower electrodes;forming openings in the thick dielectric layer;forming an array of middle electrodes in the thick dielectric layer by filling the openings in the thick dielectric layer with a first conductive material;forming a ferroelectric layer over the thick dielectric layer and the array of middle electrodes, the ferroelectric layer having an upper surface opposite the array of middle electrodes;forming openings in the upper surface of the ferroelectric layer; andforming an array of upper electrodes in the upper surface of the ferroelectric layer by filling the openings in the upper surface of the ferroelectric layer with a ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell. 110-. (canceled)11. A method of manufacturing a semiconductor device , comprising the steps of:(a) depositing a first conductor film over a semiconductor substrate;{'b': '0', '(b) depositing, over the first conductor film, a metal oxide film having and at least one of Hf and Zr as a main component;'}(c) depositing a second conductor film over the metal oxide film; and(d) subjecting the metal oxide film to microwave heat treatment.12. The method of manufacturing a semiconductor device according to claim 11 ,wherein the step (d) is performed after the step (b) and before the step (c).13. The method of manufacturing a semiconductor device according to claim 11 ,wherein the step (d) is performed after the step (c).14. The method of manufacturing a semiconductor device according to claim 11 ,wherein the second conductor film in the step (c) has TiN as a main component.15. The method of manufacturing a semiconductor device according to claim 14 ,wherein the second conductor film is deposited by RF sputtering.16. The method of manufacturing a semiconductor device according to claim 11 ,wherein at least any one of elements Si, N, C and F is added to the metal oxide film.17. The method of manufacturing a semiconductor ...

High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

HIGH-DENSITY LOW VOLTAGE NON-VOLATILE MEMORY WITH UNIDIRECTIONAL PLATE-LINE AND BIT-LINE AND PILLAR CAPACITOR

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms. 1. A capacitive structure comprising:a first structure comprising refractive inter-metallic, wherein the first structure is adjacent to the source or drain of the transistor;a second structure comprising a first conductive oxide, wherein the second structure comprises first, second, and third sections, wherein the first section extends in a second direction orthogonal to the first direction, wherein the second section is parallel to the first section, and wherein the third section is adjacent to the first and second sections such that the third section extends in the first direction, wherein a portion of the first section and a portion of the second section are adjacent to the first structure; anda third structure comprising ferroelectric material, wherein the third structure comprises first, second, and third sections, wherein the first section is adjacent to the first section of the second structure, wherein the second section is adjacent to the second section of the second structure, and wherein the third section is adjacent to the third section of the second structure, wherein the first and the second sections of the third structure are parallel to one another extends along the second direction.2. The capacitive structure of comprising a fourth structure comprising a second conductive oxide claim 1 , wherein the fourth structure is between the first and second sections of the third structure claim 1 , and wherein a portion of the fourth structure is adjacent to a portion of ...

METHOD OF MAKING SEMICONDUCTOR FERROELECTRIC MEMORY ELEMENT, AND SEMICONDUCTOR FERROELECTRIC MEMORY TRANSISTOR

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm Подробнее

SEMICONDUCTOR DEVICE

There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film. 1. A semiconductor device comprising:first and second electrodes apart from each other; anda capacitor dielectric film between the first electrode and the second electrode and including a first dielectric film and a second dielectric film,wherein the first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film,the first dielectric film has an orthorhombic crystal system,the second dielectric film includes a paraelectric material, anda dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.2. The semiconductor device of claim 1 , wherein each of the first dielectric film and the second dielectric film is a single film.3. The semiconductor device of claim 1 , wherein the first dielectric film includes a first sub-dielectric film and a second sub-dielectric film claim 1 , andthe first sub-dielectric film is between the second sub-dielectric film and the second dielectric film.4. The semiconductor device of claim 3 , wherein the second dielectric film includes a third sub-dielectric film and a fourth sub ...

Dram interconnect structure having ferroelectric capacitors

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

METHOD OF MAKING SEMICONDUCTOR FERROELECTRIC MEMORY ELEMENT, AND SEMICONDUCTOR FERROELECTRIC MEMORY TRANSISTOR

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm Подробнее

VEHICLE LAMPS

A vehicle includes a body and a lamp assembly coupled to the body. The lamp assembly includes a housing and a first metal conductor coupled to the housing. A semiconductor layer is coupled to the first metal conductor, wherein the semiconductor layer includes a plurality of perovskites configured to emit light. A second conductor is coupled to the semiconductor layer and a lens is coupled to the housing. 1. A vehicle , comprising:a body; and a housing;', 'a first metal conductor coupled of the housing;', 'a semiconductor layer coupled to the first metal conductor, wherein the semiconductor layer comprises a plurality of perovskites configured to emit light;', 'a second conductor coupled to the semiconductor layer; and', 'a lens coupled to the housing., 'a lamp assembly coupled to the body, the lamp assembly comprising2. The vehicle of claim 1 , wherein the lamp assembly comprises a center high mount stop lamp.3. The vehicle of claim 1 , wherein the lamp assembly comprises a decorative light bar coupled to a vehicle-rearward portion of the body.4. The vehicle of claim 1 , wherein the first metal conductor comprises a vacuum metalized layer positioned on an inner surface of the housing.5. The vehicle of claim 1 , wherein an electrical connection couples the first conductor to at least one of the body and a power source.6. The vehicle of claim 1 , wherein the semiconductor layer is configured to emit light in response to an electrical potential being generated between the first metal conductor and the second conductor.7. The vehicle of claim 1 , wherein the second conductor comprises at least one of indium tin oxide claim 1 , aluminum doped zinc oxide claim 1 , nickel oxide claim 1 , tungsten oxide claim 1 , and silver nanowires.8. A vehicle lamp claim 1 , comprising:a substrate;a first conductor coupled to the substrate;a semiconductor layer coupled to the first conductor, wherein the semiconductor layer comprises a plurality of perovskites configured to emit a first ...

METHOD FOR MANUFACTURING PEROVSKITE-BASED DEVICES IN AMBIENT AIR

A method for manufacturing perovskite-based devices, such as solar cells. In ambient air includes steps of forming a perovskite film on a substrate by spin-coating, the perovskite film having a turbid point when the perovskite film transitions from transparent to turbid in appearance, and dropping an antisolvent on the perovskite film during an antisolvent window having a start time five seconds before the turbid point and an end time one second before the turbid point. The method also includes the step of measuring the current relative humidity of the ambient air at the time of manufacture and adjusting the antisolvent window or optimum drop time of the antisolvent based upon the current relative humidity. 1. A method for manufacturing of a perovskite-based device in ambient air , comprising:forming a perovskite film on a substrate by spin-coating, the perovskite film having a turbid point when the perovskite film transitions from transparent to turbid in appearance; anddropping an antisolvent on the perovskite film during an antisolvent window having a start time 3-8 seconds before the turbid point and a stop time one second before the turbid point.2. The method of claim 1 , including identifying timing of the turbid point for the ambient air at different relative humidities.3. The method of claim 2 , including measuring a current relative humidity of the ambient air at a current time of the manufacturing of the perovskite-based device and basing timing of the antisolvent window upon the identified timing of the turbid point for the current relative humidity.4. The method of claim 3 , including measuring the timing of the turbid point from starting of the spin-coating.5. The method of claim 4 , including dropping the antisolvent onto the perovskite film between 4-8 seconds after the starting of the spin-coating when the current relative humidity is 0%.6. The method of claim 4 , including dropping the antisolvent onto the perovskite film between 10-14 seconds after ...

SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES

A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. 1. A method of forming a semiconductor structure , the method comprising:etching a trench into a semiconductor substrate;forming a crystalline oxide layer in the trench, wherein the crystalline oxide fills an entire volume of the trench to form an epitaxial oxide structure; andforming a first semiconductor structure and a second semiconductor structure on the semiconductor substrate, wherein the epitaxial oxide structure is located between the first semiconductor structure and the second semiconductor structure, the epitaxial oxide structure substantially electrically isolating the first and the second semiconductor structure.2. The method of claim 1 , wherein the crystalline oxide comprises rare earth oxides.3. The method of claim 2 , wherein the rare earth oxide is selected from the group consisting of cerium oxide (CeO) claim 2 , lanthanum oxide (LaO) claim 2 , yttrium oxide (YO) claim 2 , gadolinium oxide (GdO) claim 2 , europium oxide (EuO) claim 2 , and terbium oxide (TbO).4. The method of claim 1 , wherein the crystalline oxide comprises a combination of rare earth oxides.5. The method of claim 4 , wherein the combination of rare earth oxides is a binary oxide having the chemical formula ABO claim 4 , wherein A is a rare earth metal atom and B is a different rare earth metal atom.6. The method of claim 1 , wherein the crystalline oxide comprises a perovskite material.7. The method of claim 6 , wherein the perovskite material is selected from the group consisting of strontium titanate (SrTiO) and barium titanate (BaTiO).8. The method of claim 1 , wherein the crystalline oxide is aluminum oxide (AlO).9. The method of claim 1 , wherein ...

METHOD FOR FABRICATION OF CRACK-FREE CERAMIC DIELECTRIC FILMS

The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 μm to about 20.0 μm and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 μm to about 20.0 μm. 1. A process for forming a crack-free barium strontium titanate (BST) dielectric comprising:providing a substrate;depositing a first dielectric precursor BST sol-gel layer having a thickness from about 0.3 μm to about 1.0 μm on a substrate;heating the first dielectric precursor BST sol-gel layer at a preheat temperature from about 100° C. to about 200° C. for a preheat temperature heating time from about 1 minute to about 30 minutes;initiating a step-wise preheat treatment using three distinct temperatures comprising increasing the temperature from about 275° C. to about 325° C. in a pre-pyrolysis step and maintaining the temperature at the pre-pyrolysis temperature for a pre-pyrolysis period of time;increasing the temperature from about 375° C. to about 425° C. in a first pyrolysis step and maintaining the temperature at the first pyrolysis temperature for a first pyrolysis period of time;increasing the temperature from about 425° C. to about 475° C. in a second pyrolysis step and maintaining the temperature at the second pyrolysis temperature for a second pyrolysis period of time;initiating a crystallization treatment comprising increasing the ...

Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process. 1. An integrated circuit , comprising:at least one circuit element comprising a layer of a ferroelectric material, and disposed near a semiconducting surface of a body;at least one layer of insulating material disposed over the surface and overlying the at least one circuit element;at least one level of conductors disposed near the surface;a protective overcoat layer, comprising an insulating material, disposed over the ferroelectric circuit element, the at least one layer of insulating material, and the at least one level of conductors; and 'heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes.', 'a passivation layer overlying the protective overcoat layer, the passivation layer having a tensile stress state, and formed by a process comprising2. The integrated circuit of claim 1 , further comprising:a plurality of solder halls near the surface, in contact with conductors through openings in the passivation layer.3. The integrated circuit of claim 1 , wherein the ...

MATERIAL HAVING SINGLE CRYSTAL PEROVSKITE, DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers. 1. A method for manufacturing a transistor , the method comprising:forming source and drain regions;alternately growing, on a channel region disposed between the source and drain regions, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers;forming a gate insulating layer having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers to convert the plurality of first layers and the plurality of second layers alternately stacked on each other to a material having a Perovskite single crystal structure containing elements of the plurality of first layers and the plurality of second layers; andforming a gate electrode covering the gate insulating layer.2. The method of claim 1 , wherein the annealing is performed in a temperature range from about 300° C. to about 1500° C.3. The method of claim 1 , wherein the gate insulating layer includes materials having a chemical formula ABX claim 1 , in which:{'sub': 3', '3, 'A is a rare earth element selected from the group consisting of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, or A is an alkaline earth element selected from the group consisting of Be, Mg, Ca, Sr, and Ba, or A is organic compound CHNH,'}B is a non-rare earth element selected from the group consisting of Ti, Zr, Hf, Al, Ga, In, Tl, Ge, Sn, and Pb, or B is a rare-earth element or a transition metal, andX is a nonmetal element selected from the group consisting of O, S, Se, Te, F, Cl, Br ...

Metalorganic chemical vapor deposition of layered structure oxides

A method of fabricating high quality layered structure oxide ferroelectric thin films. The deposition process is a chemical vapor deposition process involving chemical reaction between volatile metal organic compounds of various elements comprising the layered structure material to be deposited, with other gases in a reactor, to produce a nonvolatile solid that deposits on a suitably placed substrate such as a conducting, semiconducting, insulating, or complex integrated circuit substrate. The source materials for this process may include organometallic compounds such as alkyls, alkoxides, β-diketonates or metallocenes of each individual element comprising the layered structure material to be deposited and oxygen. Preferably, the reactor in which the deposition is done is either a hot wall or a cold wall reactor and the vapors are introduced into this reactor either through a set of bubblers or through a direct liquid injection system. The ferroelectric films can be used for device applications such as in capacitors, dielectric resonators, heat sensors, transducers, actuators, nonvolatile memories, optical waveguides and displays.

Sol-gel precursor and method for formation of ferroelectric materials for integrated circuits

A sol-gel precursor mixture for forming a perovskite ferroelectric material and a method for forming a ferroelectric material are provided. The precursor solution comprises a sol-gel formulation of a mixture of an inorganic salt of at least one metal, and metal-organic compounds of other constituent metals in a suitable pH controlled aqueous solvent mixture to form a stable, clear sol-gel mixture. The precursor solution and method provides for formation of thin layers of other ferroelectric dielectrics and piezoelectric materials, particularly lead containing materials, for application including non-volatile DRAMs, optoelectronic devices relying on non-linear optical properties, and piezoelectric devices, and is compatible with processing for submicron device structures for bipolar, CMOS or bipolar CMOS circuits.

Low temperature seeding process for ferroelectric memory device

A process for producing a ferroelectric lead zirconate titanate dielectric for a semiconductor device by applying a lead titanate seeding layer to a substrate before applying the lead zirconate titanate film, and a semiconductor device produced in accordance with the process. The lead titanate seeding layer allows the subsequent lead zirconate titanate to be annealed at a significantly lower seeding temperature, to lessen interdiffusion among the films, electrodes and substrate and to lessen thermal stresses.

薄膜电容元件用组合物、绝缘膜、薄膜电容元件和电容器

本发明是在基板(4)上依次形成下部电极(6)、电介质薄膜(8)和上部电极(10)的薄膜电容器(2)。电介质薄膜(8)由薄膜电容元件用组合物构成，该薄膜电容元件用组合物具有c轴相对于基板面垂直取向的铋层状化合物，该铋层状化合物用组成式：(Bi 2 O 2 ) 2+ (A m-1 B m O 3m+1 ) 2- 或Bi 2 A m-1 B m O 3m+3 表示，上述组成式中的符号m为偶数，符号A为选自Na、K、Pb、Ba、Sr、Ca和Bi的至少1种元素，符号B为选自Fe、Co、Cr、Ga、Ti、Nb、Ta、Sb、V、Mo和W的至少1种元素。电容率的温度特性优良，同时即使变薄也具有较高的电容率且损耗低，漏电特性优良，耐电压提高，表面平滑性也优良。

Acceptor doped barium titanate based thin film capacitors on metal foils and methods of making thereof

The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002-0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.

Insulation layer, organic thin film transistor using the same and manufacturing method

An insulation layer, an organic thin film transistor having the same and a forming method thereof are provided to make a thin film at a low temperature by adding inorganic material into vinyl polymer. A gate electrode(110) is formed in one region on a substrate(100), and a gate insulation layer(120) is formed on the gate electrode and the substrate. An organic semiconductor layer(130) is located at a position corresponding to the organic semiconductor layer on the region of the gate insulation layer. At least a part of source/drain electrodes(140,140') is formed on the organic semiconductor layer. The gate insulation layer contains vinyl polymer and inorganic material.

強誘電体薄膜の製造方法

Metalorganic chemical vapor deposition of layered structure oxides

A method of fabricating high quality layered structure oxide ferroelectric thin films. The deposition process is a chemical vapor deposition process involving chemical reaction between volatile metal organic compounds of various elements comprising the layered structure material to be deposited, with other gases in a reactor, to produce a nonvolatile solid that deposits on a suitably placed substrate such as a conducting, semiconducting, insulating, or complex integrated circuit substrate. The source materials for this process may include organometallic compounds such as alkyls, alkoxides, β-diketonates or metallocenes of each individual element comprising the layered structure material to be deposited and oxygen. Preferably, the reactor in which the deposition is done is either a hot wall or a cold wall reactor and the vapors are introduced into this reactor either through a set of bubblers or through a direct liquid injection system. The ferroelectric films can be used for device applications such as in capacitors, dielectric resonators, heat sensors, transducers, actuators, nonvolatile memories, optical waveguides and displays.

Chemical vapor deposition process for fabricating layered superlattice materials

A substrate is prebaked in an oxygen furnace. A thin film of layered superlattice oxide is formed on the substrate by a chemical vapor deposition process. The film is RTP baked to provide grains with a mixed phase of A-axis and C-axis orientation. The film may be treated by ion implantation prior to the RTP bake and oxygen furnace annealed after the RTP bake. An electrode is deposited on the layered superlattice thin film and then the film and electrode are oxygen furnace annealed.

Low imprint ferroelectric material for long retention memory and method of making the same

Thin film ferroelectric materials for use in integrated memory circuits, such as FERAMS and the like, contain strontium bismuth niobium tantalate having an empirical formula SrBi 2+E (Nb X Ta 2-X )O 9+3E/2 , wherein E is a number representing an excess amount of bismuth ranging from zero to 2; and X is a number representing an excess amount of niobium ranging from 0.01 to 0.9. The thin films demonstrate an exceptional resistance to polarization imprinting when challenged with unidirectional voltage pulses.

High dielectric constant thin film structure method for forming high dielectric constant thin film and apparatus for forming high dielectric contact thin film

There is provided a (Ba, Sr) TiO 3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM) 2 /THF, Sr(DPM) 2 /THF and TiO(DPM) 2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO 3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

High dielectric constant thin film structure, method for forming high dielectric constant thin film, and apparatus for forming high dielectric constant thin film

There is provided a (Ba, Sr) TiO 3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM) 2 /THF, Sr(DPM) 2 /THF and TiO(DPM) 2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO 3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

Method for selectively depositing bismuth based ferroelectric films

A method is described for the selective deposition of bismuth based ferroelectric films by selective chemical vapor deposition on a substrate. Selectivity in the deposition process is attained by selection of substrate-precursor combinations which assure high bismuth deposition efficiency in certain areas and low bismuth deposition efficiency in other areas in combination with specific process parameters.

Method for deposition of ferroelectric thin films

A method is discribed for the nucleation controlled deposition of ferroelectric thin films by chemical vapor deposition in a novel processing sequence wherein a higher density of bismuth nucleation sites is achieved either by the use of a substrate member which has been treated in a manner to yield a controllably and reproducible rough surface on which SBT films with excellent properties may be produced or by using a chemically modified substrate surface upon which surface chemical properties are modified. Typical techniques for achieving surface roughening include reactive ion etching, inert ion milling and chemical mechanical polishing, each of which may be used to delineate patterned bottom electrodes. The chemical properties of the substrate may be modified by alloy deposition, deposition of seed layers which are then partially or completely in-diffused and ion implantation with or without heat treatment and changing the chemistry of the surface by a pre-exposure to chemical agents prior to deposition. The resultant oxide feroelectric thin films are suitable for use in capacitors, memory devices and the like.

Method of manufacturing bi-layered ferroelectric thin film

A method of forming a Bi-layered ferroelectric thin film on a substrate with good reproducibility, using a mixed composition of a Bi-containing organic compound and a metal polyalkoxide compound by at least one technique selected from the group consisting of molecular deposition such as CVD, and spincoat-sintering.

Method for manufacturing oxide dielectric device, and memory and semiconductor device usign the device

The temperature at which an oxide dielectric thin film is formed can be made bottom than conventional by reducing the concentration of oxygen in an atmosphere for forming the thin film. As a result, there can be formed an oxide dielectric thin film which has a crystal structure preferentially oriented at a crystal plane allowing a polarization axis to be directed in the vertical direction, eliminates any reaction with an electrode material, and controls the growth of crystal grains. The use of such an oxide dielectric thin film can provide an oxide dielectric element having a high spontaneous polarization and a small coercive field. Consequently, it is possible to achieve a dielectric element having a high density of integration for detecting reading and writing operations, and a semiconductor device using the same.

Method for preparing dielectric thin film and semiconductor device using same

A process for preparing a semiconductor device using a dielectric thin film includes the steps of forming a first electrode on a base plate; forming a dielectric film on the first electrode, the dielectric film including a Perovskite structure oxide; forming a second electrode on the dielectric film; and annealing the first and second electrodes so that metal components of the first and second electrodes are oxidized and diffused into a crystal system of the dielectric film.

Cvd processes using bi aryl

Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides adjacent to the substrate. The precursor of Bi oxide is a Bi complex which includes at least one aryl group and is decomposed at a decomposition temperature lower than 450 °C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.

Low temperature CVD processes for preparing ferroelectric films using Bi amides

Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides at the surface of the substrate. The precursor of Bi oxide is a Bi complex which includes at least one amide group and is decomposed and deposited at a temperature lower than 450° C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.

Low temperature CVD processes for preparing ferroelectric films using Bi carboxylates

Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides at the surface of the substrate. The precursor of Bi oxide is a Bi complex which includes at least one carboxylate group and is decomposed and deposited at a temperature lower than 450° C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.

Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory

A method of making a ferroelectric thin film includes the step of forming a ferroelectric thin film with a randomly oriented layered structure on a surface of a conductor layer. At least the surface of the conductor layer has a spherical crystal structure.

Method of forming high dielectric constant thin film and method of manufacturing semiconductor device

A method of forming a (Ba, Sr) TiO 3 high dielectric constant thin film with sufficient coverage is provided. A Ba material, an Sr material and a Ti material including bis (t-butoxy) bis (dipivaloylmethanate) titanium are dissolved in an organic solvent to obtain a solution material. The solution material is vaporized, so that material gas is obtained. A (Ba, Sr) TiO 3 thin film is formed on a substrate by CVD reaction using the material gas.

Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory

To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6 , lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.

Low temperature chemical vapor deposition process for forming bismuth-containing ceramic films useful in ferroelectric memory devices

A low temperature CVD process using a tris (beta-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Reduced degradation of metal oxide ceramic due to diffusion of a mobile specie therefrom

Reduced diffusion of excess mobile specie from a metal oxide ceramic is achieved by tailoring the composition an/or deposition parameters. A barrier layer which reacts with the excess mobile specie is provided below the metal oxide ceramic to prevent or reduce the diffusion of the excess mobile specie through the bottom electrode and into the substrate.

Method for stabilizing oxide-semiconductor interface by using group 5 element and stabilized semiconductor

The present invention provides a method for stabilizing an oxide-semiconductor interface, which is free from the formation of an interface layer (reactive layer) between a semiconductor and an interface oxide and which thereby allows satisfactory exhibition of performance capabilities of a functional oxide and achievement of the stability of oxide-semiconductor interface, yet independent of temperature; it also provides a stabilized semiconductor.

Low temperature CVD processes for preparing ferroelectric films using Bi alcoxides

Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides at the surface of the substrate. The precursor of Bi oxide is a Bi complex which includes at least one alkoxide group and is decomposed and deposited at a temperature lower than 450° C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.

Forming ferroelectric Pb(Zr,Ti)O3 films

Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer uniformity, high throughput and at a relatively low deposition temperature. In one aspect, a source reagent solution comprising a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium is provided. The source reagent solution is vaporized to form a precursor vapor. The precursor vapor is introduced into a chemical vapor deposition chamber containing the substrate. In another aspect, before deposition, the substrate is preheated during a preheating period. After the preheating period, the substrate is disposed on a heated susceptor during a heating period, after which a PZT film is formed on the heated substrate.

Systems and methods for forming strontium-and/or barium-containing layers

A method of forming (and system for forming) layers, such as calcium, barium, strontium, and/or magnesium, tantalates and/or niobates, and optionally titanates, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.

Precursor mixtures for use in preparing layers on substrates

Methods of forming a layer on a substrate using complexes of Formula I. The complexes and methods are particularly suitable for the preparation of semiconductor structures. The complexes are of the formula L y MY z (Formula I) wherein: M is a metal; each L group is independently a neutral ligand containing one or more Lewis-base donor atoms; each Y group is independently an anionic ligand; y=a nonzero integer; and z=a nonzero integer corresponding to the valence state of the metal.

High dielectric constant thin film structure, method for forming high dielectric constant thin film, and apparatus for forming high dielectric constant thin film

There is provided a (Ba, Sr) TiO3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM)2/THF, Sr(DPM)2/THF and TiO(DPM)2/THF solutions which are used as source material solutions. A (Ba, Sr) TiO3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

High dielectric constant thin film structure, method for forming high dielectric constant thin film and apparatus for forming high dielectric constant thin film

There is provided a (Ba, Sr) TiO 3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM) 2 /THF, Sr(DPM) 2 /THF and TiO(DPM) 2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO 3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

High dielectric constant thin film structure, method for forming high dielectric constant thin film, and apparatus for forming high dielectric constant thin film

There is provided a (Ba, Sr) TiO 3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM) 2 /THF, Sr(DPM) 2 /THF and TiO(DPM) 2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO 3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.

Method of producing oxide dielectric element, and memory and semiconductor device using the element

The temperature at which an oxide dielectric thin film is formed can be made lower than conventional by reducing the concentration of oxygen in an atmosphere for forming the thin film. As a result, there can be formed an oxide dielectric thin film which has a crystal structure preferentially oriented at a crystal plane allowing a polarization axis to be directed in the vertical direction, which eliminates any reaction with an electrode material, and controls the growth of crystal grains. The use of such an oxide dielectric thin film can provide an oxide dielectric element having a high spontaneous polarization and a small coercive field. Consequently, it is possible to achieve a dielectric element having a high density of integration for detecting reading and writing operations, and a semiconductor device using the same.

Patent EP0957516A4

The forming temperature of an oxide dielectric thin film can be lowered from the conventional forming temperature by lowering the oxygen concentration of the forming atmosphere of the thin film. Since the forming temperature is lowered, the oxide dielectric device has a crystal structure in which the polarizing axis is preferentially oriented in the plane orientation the structure has in the vertical direction, and does not react with the material of the electrodes. The growth of crystal grains can be controlled, the spontaneous polarization is high and the resistive electric field is weak. Therefore, a highly integratable dielectric device for detecting readout and writting and a semiconductor device using the device can be obtained.

Cvd processes using bi aryl

Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides adjacent to the substrate. The precursor of Bi oxide is a Bi complex which includes at least one aryl group and is decomposed at a decomposition temperature lower than 450 °C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.

Method of forming high dielectric constant thin film and method of manufacturing semiconductor device

A method of forming a (Ba, Sr) TiO 3 high dielectric constant thin film with sufficient coverage is provided. A Ba material, an Sr material and a Ti material including bis (t-butoxy) bis (dipivaloylmethanate) titanium are dissolved in an organic solvent to obtain a solution material. The solution material is vaporized, so that material gas is obtained. A (Ba, Sr) TiO 3 thin film is formed on a substrate by CVD reaction using the material gas.

Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory

A method of making a ferroelectric thin film includes the step of forming a ferroelectric thin film with a randomly oriented layered structure on a surface of a conductor layer. At least the surface of the conductor layer has a spherical crystal structure.

Method of making ferroelectric thin film having a randomly oriented layer and spherical crystal conductor structure

A method of making a ferroelectric thin film includes the step of forming a ferroelectric thin film with a randomly oriented layered structure on a surface of a conductor layer. At least the surface of the conductor layer has a spherical crystal structure.

Method for stabilizing oxide-semiconductor interface by using group 5 element and stabilized semiconductor

Systems and methods for forming layers that contain niobium and/or tantalum

A method of forming (and system for forming) layers, such as calcium, barium, strontium, and/or magnesium, tantalates and/or niobates, and optionally titanates, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.

Systems and methods for forming strontium-and/or barium-containing layers

A method of forming (and system for forming) layers, such as calcium, barium, strontium, and/or magnesium, tantalates and/or niobates, and optionally titanates, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.

Chemical vapor deposition process for fabricating layered superlattice materials

Capacitor and high-capacitance capacitor manufacturing method

Semiconductor device and its manufacturing method

강유전체막의 제조방법 및 이 막을 사용한 소형이고 대용량인 콘덴서를 갖는 반도체장치에 관한 것으로서, 0.1㎛정도의 박막에 있어서도 강유전체와 전극간의 계면에 의한 영향이 없고 균일한 특성을 갖는 유전체 박막을 구비하고 또 계면에 존재하는 산화물의 용량으로의 영향을 없애기 위해서, 박막퇴적용 원료로서 강자성막 조성에 포함되는 1종류 이상의 금속원자를 함유하는 유기분자를 사용하고 또 콘덴서의 전극으로서 산화에 의해서도 도전성이 손실되지 않는 금속 또는 화합물을 채용하는 구성으로 하였다. A method of manufacturing a ferroelectric film and a semiconductor device having a small and large-capacity capacitor using the film, wherein the thin film having a thickness of about 0.1 μm is provided with a dielectric thin film having uniform characteristics without affecting the interface between the ferroelectric and the electrode. In order to eliminate the influence of the oxide present in the capacitor, organic molecules containing at least one metal atom included in the ferromagnetic film composition are used as the raw material for thin film deposition, and the conductivity of the capacitor is not lost even by oxidation. It was set as the structure which employ | adopts a metal or a compound. 이것에 의해, 0. 1㎛정도의 박막에 있어서도 계면의 영향이 없는 균일한 특성을 갖는 유전체 박막을 형성할 수 있고 또 콘덴서의 전극과 강유전체간의 계면에 존재하는 유전율이 낮은 유전체막에 의한 실효적인 용량의 저하를 방자할 수 있으므로, 소형대용량의 콘덴서 및 반도체기억장치를 실현할 수 있다. This makes it possible to form a dielectric thin film having a uniform characteristic without the influence of the interface even in a thin film having a thickness of about 0.01 μm, and is effective by a dielectric film having a low dielectric constant present at the interface between the electrode of the capacitor and the ferroelectric. Since the capacity can be reduced, a small capacitor and a semiconductor storage device can be realized.