Nichtflüchtige Halbleiterspeicheranordnung und Verfahren zur Herstellung

Verfahren zur Bearbeitung eines Trägers, Verfahren zur Herstellung einer Ladungsspeicherzelle, Verfahren zur Bearbeitung eines Chips und Verfahren zum elektrischen Kontaktieren einer Abstandhalterstruktur

Ein Verfahren (100) zur Bearbeitung eines Trägers gemäß verschiedenen Ausführungsformen kann enthalten: Bilden einer Struktur über dem Träger, wobei die Struktur mindestens zwei benachbarte Bauelemente aufweist, die mit einem ersten Abstand zueinander angeordnet sind (110); Abscheiden einer Abstandhalterschicht über der Struktur, wobei die Abstandhalterschicht mit einer Dicke größer als eine Hälfte des ersten Abstandes abgeschieden werden kann, wobei die Abstandhalterschicht elektrisch leitendes Abstandhaltermaterial enthalten kann (120); Entfernen eines Teils der Abstandhalterschicht, wobei Abstandhaltermaterial der Abstandhalterschicht in einem Bereich zwischen den mindestens zwei benachbarten Bauelementen verbleiben kann (130); und elektrische Kontaktierung des verbleibenden Abstandhaltermaterials (140).

EEPROM-Zelle

Es wird ein Verfahren zur Herstellung eines Bauelements offenbart. Das Verfahren umfasst das Bereitstellen eines Substrats, das mit einem Zellenbereich versehen ist, der von anderen aktiven Bereichen durch Isolationsgebiete getrennt ist. Es werden ein erstes und ein zweites Gate eines ersten eines zweiten Transistors in dem Zellenbereich hergestellt. Das erste Gate enthält ein erstes und ein zweites Teil-Gate, die durch eine erste dielektrische Zwischen-Gate-Schicht voneinander getrennt. Das zweite Gate enthält ein zweites Teil-Gate, das ein erstes Teil-Gate gibt. Das erste und das zweite Teil-Gate des zweiten Gates sind durch eine zweite dielektrische Zwischen-Gate-Schicht voneinander getrennt. Es werden ein erster und zweiter Übergänge des ersten und des zweiten Transistors hergestellt. Das Verfahren umfasst ferner das Bilden eines ersten Gateanschlussest, der mit dem zweiten Teil-Gate des ersten Transistors verbunden ist, und das Bilden eines zweiten Gateanschlusses, der mit mindestens ...

NON VOLATILE INTEGRATED MULTI-CONDITION MEMORY SYSTEMS, THE DIELECTRIC MEMORY ELEMENTS USING

Method for forming high quality oxide layers of different thickness in one processing step

NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES

A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

EEPROM CELL WITH ASYMMETRIC THIN WINDOW

A nonvolatile memory cell (80) is constructed with a charge transfer window (101) having a charge transfer region (101A) smaller than the minimum resolution feature size of used to construct the cell. The window (101) is constructed to the minimum feature size, but its layout position places it partly within the channel region of the cell and partly within a field oxide barrier wall (85b). The part of the window (101A) that lies within the channel region does not reach across the width of the channel to an apposing field oxide barrier wall (85a) and does not reach along the length of the channel region to either of opposedly laid source (91) and drain (93) regions. The oxide within the window (101) is evenly etched back to reveal the substrate (111) within the channel region. A thin tunneling oxide is then grown within the window (101), including the part of the window (101B) encompassing the field oxide barrier wall (85b).

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH

The overlapping margin of with improved gate-splitting type non-volatile memory unit and its method

ELECTRICALLY ERASABLE PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE

STRUCTURE OF CELL EEPROM HAVING A THICKNESS OF DIELECTRIC OF CHANNEL NONUNIFORM AND MANUFACTORING PROCESS

PROTECTED INTEGRATED CIRCUIT AGAINST SHORT CIRCUITS CAUSED BY THE SILICIDE.

TWIN MEMORY CELLS INDIVIDUALLY ACCESSIBLE READ

L'invention concerne une mémoire non volatile (MA2) sur substrat semi-conducteur , comprenant : une première cellule mémoire comportant un transistor à grille flottante (TRi,j) et un transistor de sélection (ST) ayant une grille de contrôle verticale enterrée (CSG), une seconde cellule mémoire (Ci,j+i) comportant un transistor à grille flottante (TRi,j+i) et un transistor de sélection (ST) ayant la même grille de contrôle (CSG) que le transistor de sélection de la première cellule mémoire, une première ligne de bit (RBLj) reliée au transistor à grille flottante (TRi,j) de la première cellule mémoire, et une seconde ligne de bit (RBLj+1) reliée au transistor à grille flottante (TRi,j+i) de la seconde cellule mémoire (Ci,j+i).

non-volatile memory device and manufacturing method thereof

Semiconductor device having multi bit nonvolatile memory cell and fabrication method thereof

FLASH MEMORY WITH RECESSED FLOATING GATE

NON-VOLATILE MEMORY DEVICES AND METHDOS OF FORMING THE SAME

NONVOLATILE MEMORY DEVICE USING THE THERMAL ASSISTED GATE - INDUCED DRAIN LEAKAGE, METHOD OF ERASING DATA IN THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME

플래시 메모리와 집적하기 위한 교차전극형 커패시터

... 일부 실시예가 집적 회로(IC)에 관한 것이다. 그러한 IC는, 플래시 메모리 영역 및 커패시터 영역을 포함하는 반도체 기판을 포함한다. 플래시 메모리 셀이 플래시 메모리 영역 위에 배치되고, 플래시 메모리 셀의 제1 및 제2 소스/드레인 영역 사이에 배치되는 폴리실리콘 선택 게이트를 포함한다. 플래시 메모리 셀이 또한 선택 게이트를 따라서 배치되고 제어 게이트 유전체 층에 의해서 선택 게이트로부터 분리되는 제어 게이트를 포함한다. 커패시터가 커패시터 영역 위에 배치되고, 서로 교차전극화되고 커패시터 유전체 층에 의해서 서로로부터 분리되는, 폴리실리콘 제1 커패시터 플레이트 및 폴리실리콘 제2 커패시터 플레이트를 포함한다. 커패시터 유전체 층 및 제어 게이트 유전체 층이 동일한 재료로 제조된다.

3차원 메모리 구조

... 3차원 메모리 구조를 제조하는 방법은, 어레이 스택을 형성하는 단계, 어레이 스택 위에 희생 재료의 층을 생성하는 단계, 희생 재료의 층 및 어레이 스택을관통하여 홀을 에칭하는 단계, 홀에 반도체 재료의 필러(pillar)를 생성하여, 필러를 공통 바디로서 사용하는 적어도 2개의 수직 스택형(stacked) 플래시 메모리 셀들을 형성하는 단계, 필러 주위의 희생 재료의 층의 적어도 일부를 제거하여, 필러의 일부를 노출시키는 단계, 및 이러한 필러의 부분을 FET(Field Effect Transistor)의 바디로서 사용하는 FET를 형성하는 단계를 포함한다.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Non-volatile memory device and method of forming the same

INTEGRATED CIRCUIT DEVICE WITH LAYERED TRENCH CONDUCTORS

MEMORY SYSTEM WITH SWITCH ELEMENT

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR DEVICE INCLUDING SOURCE STRUCTURE

Provided is a semiconductor device. The semiconductor device comprises a semiconductor substrate having a memory cell region and a pad region adjacent to the memory cell region. The pad region includes a first pad region, a second pad region closer to the memory cell region than the first pad region, and a buffer region between the first pad region and the second pad region. A separation source structure including a first portion and a second portion parallel to each other is arranged. A first source structure and a second source structure are disposed between the first and second portions of the separation source structure. The first and second source structures have end portions facing each other, the first source structure is disposed on the second pad area, and the second source structure is disposed on the second pad area. A gate group is disposed on the memory cell region and the pad region between the first and second portions of the separation source structure. The end portions, ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE TO MOUNT PLURAL SEMICONDUCTOR MEMORIES WITHOUT CAUSING INCREASE OF FABRICATING COST

PURPOSE: A semiconductor integrated circuit device is provided to mount plural semiconductor memories without causing an increase of fabricating cost by forming an NVM(non-volatile memory) device and a logic circuit on the same semiconductor substrate. CONSTITUTION: A memory cell which includes the first and second select transistors and a plurality of the first memory cell transistors having a current path serially connected between the first and second select transistors is disposed as a matrix type in the first NVM. A memory cell that includes the third select transistor and the second memory cell transistor is disposed as a matrix type in the second NVM. The first memory cell transistor has the first stack gate including the first floating gate and the first control gate. The first floating gate is formed on a substrate by interposing the first gate insulation layer. The first control gate is formed on the first floating gate by interposing the second inter-gate dielectric. The second ...

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE CAPABLE OF UNIFORMLY RECESSING A LINER INSULATING LAYER WHICH IS LOCATED ON THE SURFACE OF A GATE PATTERN

PURPOSE: The manufacturing method of a semiconductor device is provided to form metal silicide of uniform thickness on the surface of a plurality of gate patterns using the thickness difference of a liner insulating layer. CONSTITUTION: A plurality of gate patterns(101a,101b) is formed on a substrate(100). A liner insulating layer(160) having a first thickness(t1) is formed in the surface of a plurality of gate patterns. A gap fill layer capable of burying the interval of gate patterns is formed on the liner insulating layer. Metal layers(180a,180b) are formed on the liner insulating layer and the gap fill layer. Metal silicide is formed using the metal layer. A first insulation layer is formed on the substrate. First silicon is formed on the substrate. A second insulation layer is formed on the first silicon. Second silicon is formed on the second insulation layer. A plurality of gate pattern is formed by etching the first insulation layer, the first silicon, the second insulation layer ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE STORAGE LAYERS AND A MANUFACTURING METHOD THEREOF

PURPOSE: A nonvolatile semiconductor memory device having charge storage layers and a manufacturing method thereof are provided to improve the driving reliability by restraining the diffusion of the hydrogen atom from the insulating layer during annealing. CONSTITUTION: A tunnel insulation layer(104) is interposed to form a charge storing layer(105) on a semiconductor substrate(100). A control gate electrode(107) is formed on the charge storing layer. A second gate electrode and a third gate electrode are positioned to oppose in longitudinal direction of the gate. COPYRIGHT KIPO 2011 ...

기판 스트레서 영역을 갖는 스플릿 게이트 메모리 셀, 및 이를 제조하는 방법

... 제1 도전형의 반도체 물질의 기판, 기판 내의 제2 도전형의 이격된 제1 영역 및 제2 영역 - 이들 사이의 기판 내에 채널 영역이 있음 -, 기판 위에 있으면서 그로부터 절연되는 도전성 플로팅 게이트 - 플로팅 게이트는 적어도 부분적으로 제1 영역 및 채널 영역의 제1 부분 위에 배치됨 -, 플로팅 게이트에 측방향으로 인접하면서 그로부터 절연되는 도전성 제2 게이트 - 제2 게이트는 적어도 부분적으로 채널 영역의 제2 부분 위에 배치되면서 그로부터 절연됨 -, 및 제2 게이트 아래의 기판 내에 형성되는 임베디드된 탄화규소의 스트레서 영역을 포함하는 메모리 디바이스 및 이를 형성하는 방법.

NAND-TYPE FLASH MEMORY DEVICE INCLUDING SELECT TRANSISTORS WITH AN IMPURITY REGION FOR RESTRAINING PUNCH-THROUGH AND A FABRICATING METHOD THEREOF TO IMPROVE SHORT CHANNEL EFFECT OF SELECT TRANSISTORS WITHOUT DETERIORATING MAGNETIC BOOSTING EFFECT OF A NON-SELECTED STRING

PURPOSE: A NAND-type flash memory device including select transistors with an impurity region for restraining punch-through is provided to prevent a non-selected string from being programmed by restraining short channel effect and hot carrier effect of a string select transistor and a ground select transistor using gate patterns. CONSTITUTION: First and second impurity regions(69b,69s) are formed in a semiconductor substrate(51). First and second select gate patterns(SGP1,SGP2) are disposed on the semiconductor substrate between the first and second impurity regions, adjoining the first and second impurity regions. A plurality of cell gate patterns(WP1,WP2,WP3,WP4) are disposed between the first and the second select gate patterns. A first anti-punchthrough impurity region(67b) comes in contact with the first impurity regions, overlaying a first edge of a first select gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region(67s) comes in contact with ...

소스들의 에지들에 인접한 소스 접촉부들을 갖는 메모리 어레이들을 포함하는 장치들

... 3-차원(3D) 메모리 디바이스들 및 이를 포함하는 시스템들을 포함하는, 다양한 장치가 본 출원에 설명된다. 일 실시예에서, 3D 메모리 디바이스는 적어도 두 개의 소스; 각각 적어도 두 개의 소스 위에 형성되고 적어도 두 개의 소스에 결합되는 적어도 두 개의 메모리 어레이; 및 각각 소스의 하나 이상의 에지에 인접한 소스 접촉부들을 사용하여 적어도 두 개의 소스에 전기적으로 결합되는 소스 전도체를 포함할 수 있다. 적어도 두 개의 메모리 어레이의 각각은 메모리 셀들, 제어 게이트들, 및 데이터 라인들을 포함할 수 있다. 소스의 에지 및 에지에 인접한 소스 접촉부들 사이에는 데이터 라인이 없다.

SEMICONDUCTOR MEMORY DEVICE WITH MOS TRANSISTOR INCLUDING FLOATING GATE AND CONTROL GATE, CONTROL METHOD THEREOF AND MEMORY CARD INCLUDING THE SAME TO MINIATURIZE FLASH MEMORY

PURPOSE: A semiconductor memory device with a MOS transistor including a floating gate and a control gate is provided to improve reliability of reading and writing operations by latching a potential supplied to a bitline for corresponding writing in a reading operation by a latch circuit corresponding to a writing bit connected to a memory cell in which data 0 is to be written. CONSTITUTION: A plurality of memory cells include the first MOS transistor having a charge accumulation layer and a control gate. Data are written in the plurality of memory cells by a transfer of electrons between the charge accumulation layer and the memory cells due to FN(Fowler-Nordheim) tunneling. An end of a current path of the plurality of the first MOS transistors is electrically connected to each of a plurality of writing bitlines. An end of a current path of the plurality of the first MOS transistors is electrically connected to each of a plurality of reading bitlines. A latch circuit retains writing data ...

Non-Volatile memory device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF UNIFORMLY CONTROLLING PARASITIC CAPACITANCE BETWEEN CONDUCTIVE PATTERNS

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to improve interference effect generated on a conductive pattern by forming an interference preventive groove between an insulating film and the conductive pattern. CONSTITUTION: A damascene patter is formed on an insulating film, and the insulating film is formed on a semiconductor substrate. A conductive pattern(109a) is formed to be higher than the height of the insulating film and to be lower than the height of the damascene pattern. An interference preventive groove(111) is formed between the sidewall of the conductive pattern and the insulating film. The damascene pattern includes a first damascene pattern. COPYRIGHT KIPO 2010 ...

SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING

SEMICONDUCTOR DEVICE

Semiconductor memory device and method of manufacturing the same

THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

The present invention relates to a three-dimensional non-volatile memory device and a manufacturing method thereof. According to an embodiment of the present invention, the three-dimensional non-volatile memory device comprises: a substrate; semiconductor pillars arranged at prescribed intervals in a first direction parallel with a main surface of the substrate and a second direction different from the first direction; a string separation film arranged between semiconductor pillars arranged in the first direction among the semiconductor pillars, and extended in a direction perpendicular to the first direction and the main surface of the substrate; first sub-electrodes repeatedly deposited on the substrate in the perpendicular direction; second sub-electrodes electrically separated from the first sub-electrodes by the string separation film, and repeatedly deposited on the substrate in the perpendicular direction; and an information storage film between the first sub-electrodes and the semiconductor ...

NON-VOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF TO SUFFICIENTLY GUARANTEE INTERVAL MARGIN BETWEEN COMMON SOURCE REGION AND CHANNEL REGION AND AVOID SHORT-CHANNEL EFFECT

PURPOSE: A non-volatile memory device is provided to improve an operation characteristic by reducing the area of a tunneling window. CONSTITUTION: A gate insulation layer is formed on a semiconductor substrate, having a predetermined width in a direction parallel with a longitudinal direction of a channel and a predetermined length in a direction parallel with the longitudinal direction of the channel. A lower floating gate is formed on the gate insulation layer, including a first lower floating gate and a second lower floating gate separated from the first lower floating gate by a predetermined interval having substantially the same width as a tunneling window(22). In the lower floating gate, the tunnel window and the gate insulation layer in the periphery of the tunnel window are partially exposed to a region between the first and second lower floating gates. A tunneling insulation layer is formed on the tunneling window. A region between the first and second floating gates is filled ...

MULTI-STATE NON-VOLATILE INTEGRATED CIRCUIT MEMORY SYSTEMS THAT EMPLOY DIELECTRIC STORAGE ELEMENTS

Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element (107) that is sandwiched between a control gate (109, 110, 111) and the semiconductor substrate surface (101) over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions (103, 104, 105) in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines (110) and the semiconductor substrate (100). COPYRIGHT KIPO & WIPO 2010 ...

METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY DEVICE, TO INCREASE A DEGREE OF INTEGRATION BY ARRANGING AN UPPER CONTROL GATE ELECTRODE ACROSS A LOWER CONTROL GATE ELECTRODE

PURPOSE: A method for manufacturing a non-volatile memory device is provided to increase the degree of integration of the non-volatile memory device by eliminating source/drain regions in memory transistors. CONSTITUTION: A semiconductor layer(115) is formed on a substrate(105). A plurality of lower charge storage layers are formed on the substrate to cover a lower part of the semiconductor layer. A plurality of lower control gate electrodes are formed on the substrate to cover the lower charge storage layers. A plurality of upper charge storage layers are formed on the substrate to cover an upper part of the semiconductor layer. A plurality of upper control gate electrodes(190) are formed on the substrate to cover the upper charge storage layers. © KIPO 2008 ...

NAND TYPE FLASH MEMORY DEVICE USING DIRECT CONNECTION STRUCTURE BETWEEN FLOATING GATE AND CONTROL GATE IN SELECT LINE FOR PREVENTING FALL-DOWN OF PREDETERMINED PATTERNS AND MANUFACTURING METHOD THEREOF

PURPOSE: A NAND type flash memory device and its manufacturing method are provided to prevent fall-down of predetermined patterns and to restrain the predetermined pattern from becoming thin by connecting directly electrically a floating gate with a control gate in a select line. CONSTITUTION: A plurality of wordlines(WLa1,WLb1) are formed on a semiconductor substrate(401), wherein each wordline is composed of a first floating gate(403), a first dielectric film(404) and a first control gate(411). A plurality of select lines(DSL) are formed on the substrate. Each select line includes a second floating gate, a second dielectric film and a second control gate. The second dielectric film is smaller than the first dielectric film, so that the second control gate is directly connected with the second floating gate. The wordlines and the select lines are spaced apart from each other on the substrate. © KIPO 2006 ...

NOR FLASH MEMORY AND A MANUFACTURING METHOD THEREOF TO PROVIDE A SEMICONDUCTOR MEMORY CELL ARRAY

PURPOSE: An NOR flash memory and a manufacturing method thereof are provided to enhance the manufacturing method newly by a semiconductor memory cell array and the manufacturing method thereof. CONSTITUTION: A memory cell array includes a substrate of a first conductivity type. In the substrate, a first and a second region of a second conductivity type are defined with an uniform distance, and a first and a second word line(14) are formed adjacent to the first and the second region, and a third region of a second conductivity type is defined on the substrate between the first and the second region. The memory cell array further comprises an erase gate(17) on the third region, a first and a second floating gate between the erase gates, coupling gates(16) for covering the floating gates, bit lines(12) and bit line contacts(22) for interconnecting the first and the second region and the bit lines. © KIPO 2008 ...

Split-gate, non-volatile memory cell with floating,gate one-word-line-one erase gate

A method for fabricating semiconductor device

INTER-STACK PLUG IN THREE-DIMENSIONAL MEMORY ELEMENT AND METHOD OF FORMING SAME

Erasable programmable nonvolatile memory

Semiconductor device and manufacturing method therefor

A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Semiconductor device

A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j-1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.

Independently programmable memory segments within an NMOS electrically erasable programmable read only memory array achieved by P-well separation and method therefor

An array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

Production method of non-volatile memory device

The invention relates to a production method of non-volatile memory device. Steps as follows: Form the gate oxide layer on the base. Form the stacked capacitor of the memory cell after logic gates polysilicon passing through at least two sedimentary processes. Then the redundant logic gates polysilicon is removed by an etching process to form the memory transistor and the periphery logic transistor. According to the method of the present invention, the stacked capacitor of the memory cell is formed by at least two sedimentary processes, and the memory device is fabricated in a standard logic process, so that the memory manufacturing process is simpler, the compatibility with the logic process is good, and the cost is low.

Storage device

A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.

Substrate processing method and device manufactured by using the same

Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

Steam oxidation initiation for high aspect ratio conformal radical oxidation

A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

Semiconductor memory

THREE-DIMENSIONAL (3D) MEMORY DEVICE AND METHOD OF OPERATING THE SAME

METAL FILL PROCESS FOR THREE-DIMENSIONAL VERTICAL NAND WORDLINE

Memory cell and memory array

Method for forming contact window

Antifuse otp memory cell with performance improvement and operating method of memory

Flash memory structure and method of making the same

PROVIDING LOCAL BOOSTING CONTROL IMPLANT FOR NON-VOLATILE MEMORY

A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation may also be made to set a threshold voltage of storage elements of the NAND string.

METHOD OF FILLING A HIGH ASPECT RATIO TRENCH ISOLATION REGION AND RESULTING STRUCTURE

A method of filling a high aspect ratio trench isolation region, which allows for better gap-fill characteristics and avoids voids and seams in the isolation region. The method includes the steps of forming a trench, forming an oxide layer on the bottom and sidewalls of the trench, etching the oxide layer to expose the bottom of the trench, providing an epitaxial silicon layer on the bottom of the trench, and providing a high quality oxide chemical vapor deposition layer over the epitaxial silicon layer.

NOR STRUCTURE FLASH MEMORY AND MANUFACTURING METHOD THEREOF

The present invention relates to the technical field of flash memories, and provides a NOR structure flash memory and a manufacturing method thereof. In the manufacturing method, a mask dielectric layer is formed and covered on a second polysilicon layer of a gate laminated structure, a part of the mask dielectric layer is patterned and etched to expose a part of the second polysilicon layer on one side that is relatively closer to a source of the NOR structure flash memory, and self-alignment is performed on the exposed second polysilicon layer to form a metal silicide layer. Therefore, in the manufactured NOR structure flash memory, the mask dielectric layer that is not etched can be approximately disposed between the metal silicide layer and a drain contact hole of the NOR structure flash memory. The leakage current between the gate and the drain of the NOR structure flash memory is small, the processing procedure of the manufacturing method is not complex, the process window is large ...

INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS

A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Semiconductor memory device

A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Gate fringing effect based channel formation for semiconductor device

A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Methods for manufacturing semiconductor devices having three-dimensionally arranged memory cells

Methods for manufacturing semiconductor devices may include forming a stack structure including layers stacked on a substrate, forming a mask pattern on the stack structure, and patterning the stack structure using the mask pattern such that the stack structure has an end portion with a stepped profile. The patterning of the stack structure may include performing a pad etching process of etching the stack structure using the mask pattern as an etch mask, and performing a mask etching process of etching a sidewall of the mask pattern. The performing of the mask etching process may include irradiating an ion beam onto the mask pattern, which may be irradiated at a first tilt angle with respect to the sidewall of the mask pattern and at a second tilt angle with respect to a top surface of the mask pattern. The first tilt angle may be different from the second tilt angle.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.

NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE

A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Semiconductor device of non- volatile memory

A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS

An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Fabrication method and structure for providing a recessed channel in a nonvolatile memory device

A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Single poly EE cell with separate read/write paths and reduced product term coupling

A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

Method of fabricating a high density EEPROM cell

A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide+544 nitride+544 oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO+544 poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Non-volatile memory devices and methods of forming the same

A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Flash memory cell with contactless bit line, and process of fabrication

Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

NON-VOLATILE MEMORY CELL, NAND-TYPE NON-VOLATILE MEMORY, AND METHOD OF MANUFACTURING THE SAME

A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps. An insulating layer, a first conductive layer, an inter-gate insulating layer, a second conductive layer, and a hard mask layer are formed on a substrate in order. The hard mask layer, the second conductive layer, the inter-gate insulating layer, and the first conductive layer are patterned to form a stacked gate structure. The insulating layer on the substrate at two sides of the stacked gate structure is removed until the surface of the substrate is exposed. A portion of the substrate at two sides of the stacked gate structure is removed to form two recesses in the substrate, and each of the recesses is extended below the stacked gate structure. A source/drain region is formed in the substrate below the recesses.

Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Three-dimensional memory device including wrap around word lines and methods of forming the same

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

Source/drain zones with a delectric plug over an isolation region between active regions and methods

Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Devices and memory arrays including bit lines and bit line contacts

Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.

NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF

A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

Semiconductor memory device including multi-layer gate structure

A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

MEMORY DEVICE WITH VPASS STEP TO REDUCE HOT CARRIER INJECTION TYPE OF PROGRAM DISTURB

Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass level such as Vpass, and in a second step from Vpass to a peak program level of Vpgm. A voltage on an adjacent unselected word line can be increased from the initial level to Vpass and then temporarily increased to an elevated level of Vpass_el during the second step increase on the selected word line. This helps reduce the magnitude of a channel gradient between the selected word line and the adjacent word line. The increase to Vpass_el may be implemented for program loops in the later part of a program operation, when Vpgm and the risk of program disturb is relatively high.

Nonvolatile semiconductor memory

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, VgVd is a value of a potential difference required for generating a tunnel current between the bands or higher, and VsubVd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Nonvolatile semiconductor memory device

A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate.wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate.wiring.

NAND Memory Constructions and Methods of Forming NAND Memory Constructions

Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions. 122-. (canceled)23. A NAND memory construction , comprising:dielectric regions extending into a semiconductor material, the semiconductor material comprising pillars extending upwardly between the dielectric regions; individual pillars having a pair of opposing vertically-extending sides along a cross-section, said opposing vertically-extending sides being a first side and a second side;electrically conductive interconnect lines along and directly against the dielectric regions, the interconnect lines extending primarily along a horizontal direction;first conductivity type regions within the semiconductor material pillars along the first sides of the individual pillars within the semiconductor material; the first conductivity type regions being directly against first portions of the dielectric regions;second conductivity type regions within the semiconductor material pillars along the second sides of the individual pillars; the second conductivity type regions being directly against second portions of the dielectric regions and directly contacting the interconnect lines;a plurality of vertical ...

3-D NAND Control Gate Enhancement

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. 1. A method of forming a NAND memory structure , the method comprising:depositing a plurality of alternating layers of a nitride material and an oxide material separated by a silicon layer;etching a memory hole through the plurality of alternating layers to form an exposed surface of the plurality of alternating layers;selectively etching laterally through the memory hole from the exposed surface a portion of the nitride material;depositing a blocking oxide layer in the memory hole to form a conformal oxide liner on the exposed surface of the plurality of alternating layers, the conformal oxide layer having a first side adjacent to the plurality of alternating layers of nitride material and oxide material, and second adjacent to the memory hole;depositing a floating gate metal into the memory hole to form a floating gate adjacent the conformal oxide liner, the floating gate material having a first side, a second side, a third side, and a fourth side, the conformal oxide layer surrounding the floating gate on the first side, the second, side, and the third side, and the fourth side facing the memory hole channel;depositing a gate oxide material into the memory hole to form a layer of gate oxide material adjacent the floating gate, the gate oxide material conformally extending along the fourth side of the floating gate material and conformally extending along the conformal blocking oxide liner adjacent the face of the first and second insulating layers facing the memory hole channel;depositing a silicon material in the memory hole to form a silicon channel ...

SEMICONDUCTOR MEMORY DEVICE

A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction. 1. A method of controlling a memory device comprising:receiving a write instruction;starting a write operation to a first address in response to the write instruction;receiving a first read instruction of the first address;suspending the write operation; andapplying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction.2. The method according to claim 1 , further comprising:transmitting write data of a first memory cell held by a latch circuit to a data register as read data;wherein the first memory cell is connected to the word line and the writing of the write data to the first memory cell is not completed.3. The method according to claim 1 , further comprising:transmitting data read from a second memory cell to a data register as read data;wherein the second memory cell is connected to the word line and the writing of write data to the second memory cell is completed.4. The method according to claim 1 , further comprising:transmitting write data of a first memory cell held by a latch circuit to a data register as read data; andtransmitting data read from a second memory cell to the data register as read data;wherein the first memory cell and the second memory cell are connected to the word line, the writing of the write data to the first memory cell is not completed and the writing of the write data to the second memory cell is completed.5. The method according to claim 1 , further comprising:resuming the write operation after the first read operation.6. The method according to claim 1 , ...

3d nand flash memory

A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.

METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described. 1. A method comprising:forming a material in a substrate;forming pedestals from a portion of the substrate, such that the pedestals are separated from each other and each of the pedestals includes a base contacting the material; andforming memory cell strings overlying the pedestals.2. The method of claim 1 , further comprising:forming at least a portion of a gate of a select transistor in a location between at least two of the pedestals.3. The method of claim 2 , wherein forming at least a portion of a gate of a select transistor in a location between at least two of the pedestals comprises forming portions of two gates of two select transistors between the at least two of the pedestals.4. The method of claim 1 , wherein forming the memory cell strings includes forming bodies of the memory cell strings claim 1 , such that each of the bodies contacts a respective one of the pedestals.5. The method of claim 1 , wherein the material in the substrate comprises a first material claim 1 , the substrate includes a second material of a first conductivity type claim 1 , and forming the first material includes inserting impurities of a second conductivity type into the substrate.6. The method of claim 1 , wherein the portion of the substrate includes a monocrystalline semiconductor material.7. A method comprising:forming a first material in a substrate comprising a second material;removing the second material from a first location of a portion of the substrate overlying the first material and from a second location of the portion of the substrate overlying the ...

SHALLOW TRENCH AIR GAPS AND THEIR FORMATION

A method of forming a NAND flash memory includes etching between word lines to expose isolation material in shallow trench isolation (STI) trenches while active areas between word lines remain covered, then forming protective sleeves at locations over exposed isolation material. Subsequently, with the protective sleeves in place, isotropic etching of isolation material forms an air gap extending continuously between the protective sleeves along an individual STI trench. 1. A NAND flash memory comprising:a plurality of active areas extending along a first direction in a substrate;a plurality of shallow trench isolation (STI) trenches extending along the first direction in the substrate between the plurality of active areas;a plurality of word lines extending over the plurality of active areas and over the plurality of STI trenches along a second direction that is perpendicular to the first direction, the plurality of word lines separated from the plurality of STI trenches by a plurality of dielectric strips that extend under the plurality of word lines;an air gap extending under the plurality of word lines along an individual STI trench of the plurality of STI trenches;a plurality of portions of an isolating material located along undersides of the plurality of dielectric strips where the plurality of dielectric strips overlie the individual STI trench, the isolating material filling a remaining portion of the individual STI trench that extends from the air gap to the bottom of the trench; andwherein the air gap has a profile along a word line direction at a location under an individual word line that has a first width at a first height above a bottom surface of the individual STI trench and has a second width at a second height above the bottom surface that is greater than the first height, the second width being less than the first width.2. The NAND flash memory of wherein the isolating material is polysilazane (PSZ).3. (canceled)4. The NAND flash memory of further ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars. 1. A semiconductor memory device comprising:a first semiconductor pillar extending in a first direction;a second semiconductor pillar extending in the first direction, the first semiconductor pillar and the second semiconductor pillar being arranged in a second direction intersecting the first direction;a first electrode film extending in a third direction intersecting the first direction and the second direction;a second electrode film extending in the third direction, the first electrode film and the second electrode film being arranged in the second direction;a first memory portion provided between the first semiconductor pillar and the first electrode film;a second memory portion provided between the second semiconductor pillar and the second electrode film;a first connection member being electrically connected in common to an upper portion of the first semiconductor pillar and an upper portion of the second semiconductor pillar;a first contact, a lower portion of the first contact being electrically connected to the first connection member; anda first upper interconnect extending in the second direction and electrically connected to an upper portion of the first contact.2. The device according to claim 1 , whereinthe first semiconductor pillar and the second semiconductor pillar are disposed between the first electrode film and the second electrode film.3. The device according to claim 1 , further comprising:a conductive layer containing silicon, the conductive layer being electrically connected in common to a lower portion of the first semiconductor pillar and a lower portion of the second semiconductor pillar.4. The device according to claim 1 , whereinthe first semiconductor ...

Reduced Size Semiconductor Device And Method For Manufacture Thereof

A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided. 1. A nonvolatile semiconductor device comprising:a substrate;a plurality of blocks forming a string, wherein each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate;a single ground select line associated with the string, wherein the single ground select line is disposed at one side of the plurality of blocks; anda single string select line associated with the string, wherein the single string select line is disposed at another side of the plurality of blocks.2. The nonvolatile semiconductor device of claim 1 , wherein the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string.3. The nonvolatile semiconductor device of claim 1 , wherein a dummy word line is disposed in a gap between a first block and a second block of the plurality of blocks of the string.4. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line is a floating dummy word line.5. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line has a voltage bias.6. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line is connected to a ground.7. The ...

THREE-DIMENSIONAL MEMORY DEVICES HAVING HYDROGEN BLOCKING LAYER AND FABRICATION METHODS THEREOF

Embodiments of three-dimensional (3D) memory devices have a blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic devices, a pad-out interconnect layer above the semiconductor layer, and a blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen. 1. A memory device , comprising:a memory array;a plurality of logic devices above the memory array;a semiconductor layer above and in contact with the logic devices;a pad-out interconnect layer above the semiconductor layer; anda blocking layer vertically between the semiconductor layer and the pad-out interconnect layer,wherein the semiconductor layer is vertically between the plurality of logic devices and the blocking layer.2. The memory device of claim 1 , wherein the blocking layer comprises a high dielectric constant (high-k) dielectric material.3. The memory device of claim 1 , wherein a thickness of the blocking layer is between about 1 nm and about 100 nm.4. The memory device of claim 1 , wherein the blocking layer extends laterally to cover the semiconductor layer.5. The memory device of claim 1 , wherein the blocking layer is configured to block outgassing of the hydrogen from the logic devices into or beyond the pad-out interconnect layer during fabrication of the memory device.6. The memory device of claim 1 , further comprising:a first bonding layer above the memory array and comprising a plurality of first bonding contacts;a second bonding layer below the logic devices and above the first bonding layer and comprising a plurality of second bonding contacts; anda ...

Semiconductor Device Having Electrically Floating Body Transistor, Semiconductor Device Having Both Volatile and Non-Volatile Functionality and Method of Operating

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided. 1199-. (canceled)200. A single polysilicon floating gate semiconductor memory cell comprising:a substrate;a floating body region exposed at a surface of said substrate and configured to store volatile memory;a single polysilicon floating gate configured to store nonvolatile data;an insulating region insulating said floating body region from said single polysilicon floating gate; andfirst and second regions exposed at said surface at locations other than where said floating body region is exposed;wherein said floating gate is configured to receive transfer of data stored by the volatile memory.201. The single polysilicon floating gate semiconductor memory cell of claim 200 , wherein said first and second regions are asymmetric claim 200 , wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface claim 200 , and wherein said first area is unequal to said second area.202. The single polysilicon floating gate semiconductor memory cell of claim 200 , wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.203. The single polysilicon floating gate semiconductor memory cell of claim 200 , further comprising a buried layer at a bottom portion of the substrate claim 200 , said buried layer ...

Structure and method for single gate non-volatile memory device

The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. 1. A three-dimensional semiconductor memory device , comprising:a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;a selection structure including a plurality of selection conductive patterns stacked on the stacked structure;a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;an upper interconnection line crossing the selection structure; anda conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,wherein a bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the plurality of selection conductive patterns.2. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top surfaces of two adjacent selection conductive patterns in a vertical direction.3. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the uppermost selection conductive pattern.4. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned below a bottom surface of the uppermost ...

Data Line Arrangement and Pillar Arrangement in Apparatuses

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). 124-. (canceled)25. An apparatus , comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement; the hexagonally closest packed arrangement comprising a repeating pillar pattern , with the repeating pillar pattern having at least portions of 7 different pillars , wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines; and wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD); the pillars and SGD being supported by a base comprising monocrystalline silicon.26. The apparatus of claim 25 , wherein said each of the pillars in a respective one of the repeating pillar patterns being encompassed by a single drain-side select gate (SGD) comprises each of the pillars in the respective one of the repeating pillar patterns being at least partially surrounded by the single SGD claim 25 , and wherein activation of the single SGD electrically couples the 7 different pillars to 7 different data lines.27. The apparatus of claim 26 , wherein a drain-side ...

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. 1. (canceled)2. A semiconductor memory device comprising: a first well of a first conductively type being formed in the substrate;', 'a second well of a second conductively type being formed in the first well;, 'a substrate,'}a plurality of bit lines, the plurality of bit lines including a first bit line and a second bit line adjacent to the first bit line;a source line; a first NAND string connected between the first bit line and the source line,', 'a second NAND string connected between the second bit line and the source line', 'a third NAND string connected between the first bit line and the source line, and', 'a fourth NAND string connected between the second bit line and the source line;, 'a plurality of NAND strings, each of the NAND strings including a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first select transistor and the second select transistor, the plurality of NAND strings includinga first line connected between the source line and a first node;a sense amplifier;a first transistor connected at a first end to the sense amplifier and connected at a second end to a second node; and a first bit line select transistor connected at a first end to the first node and connected at a second end to the first bit line,', 'a second bit line select transistor connected at a first end to the first node and connected ...

FLOATING DATA LINE CIRCUITS AND METHODS

A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node. 1. A write line circuit comprising:a power supply node configured to carry a power supply voltage level;a reference node configured to carry a reference voltage level;a first input node configured to receive a first data signal;a second input node configured to receive a second data signal;a third input node configured to receive a control signal; andan output node, output one of the power supply voltage level or the reference voltage level on the output node, or', 'float the output node., 'wherein the write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either2. The write line circuit of claim 1 , whereinwhen the first data signal and the second data signal have a same logical state, the write line circuit is configured to float the output node, andwhen the first data signal and the second data signal have different logical states, the write line circuit is configured to output one of the power supply voltage level or the reference voltage level on the output node.3. The write line circuit of claim 2 , wherein the same logical state is a low logical state.4. The write line circuit of claim 1 , wherein an inverter responsive to the first data signal; and', 'a switching device coupled with the inverter, and, 'the write line circuit further comprisesthe write line circuit is configured to ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers. 113-. (canceled)14. A semiconductor device , comprising:first, second, fifth and sixth vertical channel layers vertically coupled between a semiconductor substrate and a bit line;third, fourth, seventh and eighth vertical channel layers vertically coupled between the semiconductor substrate and a common source line;first, third, fifth and seventh multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the first, third, fifth and seventh vertical channel layers, respectively;second, fourth, sixth and eighth multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the second, fourth, sixth and eighth vertical channel layers, respectively;charge storage layers formed between the first to eighth vertical channel layers and the first to eighth multilayer conductive layers;a first pipe channel layer formed in the semiconductor substrate to couple lower portions of the first and eighth vertical channel layers;a second pipe channel layer formed in the semiconductor substrate to couple lower portions of the second and third vertical channel layers;a third pipe channel layer ...

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. 1. A three-dimensional semiconductor memory device , comprising:a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;a selection structure including a plurality of selection conductive patterns stacked on the stacked structure;a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;an upper interconnection line crossing the selection structure; anda conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,wherein a bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the plurality of selection conductive patterns,wherein the conductive pad has impurities of a first conductivity type, and the channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to at least one of the plurality of selection conductive patterns, andwherein bottom surfaces of the channel impurity region and the conductive pad are positioned at different vertical levels.2. The device of claim 1 , wherein the bottom surface of the conductive pad is ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING ON-PITCH DRAIN SELECT GATE ELECTRODES AND METHOD OF MAKING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;an array of memory opening fill structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory opening fill structures comprises a memory film and a memory-level channel portion;an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion, a drain region contacting an upper end of the drain-select-level channel portion, and a gate dielectric laterally surrounding the drain-select-level channel portion;a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies; anda drain-select-level ...

SEMICONDUCTOR DEVICE INCLUDING GATE LAYER AND VERTICAL STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern. 1. A semiconductor device , comprising:a first vertical structure on a substrate;a second vertical structure on the substrate; andinterlayer insulating layers and gate layers alternately and repeatedly stacked on the substrate,wherein:the gate layers are sequentially stacked in a memory cell array area of the substrate and extend into an extension area of the substrate adjacent to the memory cell array area of the substrate,the gate layers have pad regions arranged to have a staircase structure in the extension area,the first vertical structure has a side surface facing the gate layers in the memory cell array area,the second vertical structure has a side surface facing at least one of the gate layers in the extension area,the first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern,the second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, ...

Source structure of three-dimensional memory device and method for forming the same

Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

MEMORY CELL STRUCTURE OF A THREE-DIMENSIONAL MEMORY DEVICE

Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction. 1. A three-dimensional (3D) memory device , comprising:an alternating conductor/dielectric stack disposed on a substrate; anda plurality of channel structures extending vertically through the alternating conductor/dielectric stack, wherein the plurality of channel structures are arranged in a hexagonal lattice.2. The 3D memory device of claim 1 , further comprising:a slit extending vertically through the alternating conductor/dielectric stack, wherein the slit is arranged in a zigzag pattern extending laterally in a first direction.3. The 3D memory device of claim 2 , wherein the hexagonal lattice comprises a plurality of hexagons claim 2 , each having three pairs of sides claim 2 , wherein:a first pair of side is perpendicular to the first direction; anda second pair and a third pair of sides are parallel to the slit in the zigzag pattern.4. The 3D memory device of claim 2 , wherein the slit is configured to divide the 3D memory device into multiple memory blocks and/or multiple memory fingers.5. The 3D memory device of claim 2 , wherein the slit is configured as a common source contact for the plurality of channel structures.6. The 3D memory device of claim 2 , further comprising:a top select gate, parallel to the slit, wherein the top select gate is arranged in a zigzag pattern extending in the first direction ...

METHOD FOR ETCHING BOTTOM PUNCH-THROUGH OPENING IN A MEMORY FILM OF A MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE

First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film. 1. A method of forming a three-dimensional memory device comprising:forming a first alternating stack of first insulating layers and first spacer material layers over a semiconductor material layer;forming first memory openings through the first alternating stack, wherein a top surface of the semiconductor material layer is physically exposed at a bottom of each of the first memory openings;filling each of the first memory openings with a first memory film, a sacrificial liner, and a first-tier opening fill material portion;forming a second alternating stack of second insulating layers and second spacer material layers over the first alternating stack and the first-tier opening fill material portions;forming second memory openings through the second alternating stack, wherein a top surface of a respective one of the first-tier opening fill material portions is physically exposed at a bottom of each of the second memory openings;forming a second memory film within each of the second memory openings;removing the first-tier opening fill material portions selective to the sacrificial liners;removing the sacrificial liners selective to the second memory films and the first memory films; ...

SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS

Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications. 1. A VLSI semiconductor device , comprising:a substrate of a first doping type at a first doping level having a surface;a first active region disposed adjacent the surface with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed;a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed;transistors formed in at least one of the first active region or second active region;at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first and second active regions towards an area of the substrate where there are no active regions; andat least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the surface towards the area of the substrate where there are no active regions, wherein at least some of the transistors form digital logic of the VLSI semiconductor device.2. The VLSI semiconductor device of claim 1 , wherein the substrate is a p-type substrate.3. The VLSI semiconductor device of ...

Assemblies Having Conductive Structures with Three or More Different Materials

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions. 1. A memory cell , comprising:a conductive gate; the conductive gate including at least three different materials; said at least three different materials including a first material having an outer perimeter in a cross-section, a second material directly adjacent the first material and compositionally different than the first material, and a third material directly adjacent the second material and compositionally different than each of the first and second materials; the first and third materials comprising metal and being electrically conductive, the third material being present along an entirety of the outer perimeter of the first material in the cross-section;a charge-blocking region adjacent the conductive gate;a charge-storage region adjacent the charge-blocking region;tunneling material adjacent the charge-storage region; andchannel material adjacent the tunneling material, the tunneling material being between the channel material and the charge-storage region.2. The memory cell of wherein the first material comprises one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.3. The memory cell of wherein the first material consists of one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.4. The memory cell of wherein the second material comprises one or more compositions selected from the group consisting of metal nitrides claim 1 , metal carbides claim 1 , metal borides claim 1 , metal oxides and metal carbonitrides.5. The memory cell of wherein the second material comprises one or more of AlO claim 1 , ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact. 1. A semiconductor memory device comprising:a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate, a first dielectric layer which covers the peripheral circuit elements, and a plurality of first pads which are coupled to the peripheral circuit elements, on one surface thereof;a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate, a second dielectric layer which covers the memory cell array, and a plurality of second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip;a contact passing through the base dielectric layer and the second dielectric layer; andone or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.2. The semiconductor memory device according to claim 1 , wherein the contact and the dummy contacts are formed of the same material.3. The semiconductor memory device ...

Erasable programmable non-volatile memory

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ALUMINUM-SILICON WORD LINES AND METHODS OF MANUFACTURING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; andmemory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, and extends through each of the electrically conductive layers and is laterally surrounded by each of the electrically conductive layers,wherein each of the electrically conductive layers comprises a respective conductive fill material structure including an aluminum-containing portion surrounded on at least three sides by a silicon-containing portion.2. The three-dimensional memory device of claim 1 , wherein at least 85% of all atoms within the aluminum-containing portions comprise aluminum atoms.3. The three-dimensional memory device of claim 1 , wherein at least 95% of all atoms within the silicon-containing portions comprise silicon atoms.4. The three-dimensional memory device of claim 1 , wherein each of electrically conductive layers further comprises a metallic barrier layer embedding the conductive fill material structure.5. The three-dimensional memory device of claim 4 , wherein the metallic barrier ...

NONVOLATILE MEMORY STRUCTURE AND ARRAY

A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction. 1. A nonvolatile memory structure , comprising:a substrate comprising an oxide defined (OD) region and an erase region;a select transistor disposed on the OD region; anda floating-gate transistor disposed on the OD region between the select transistor and the erase region, wherein the floating-gate transistor comprises a floating gate having an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction, the nonvolatile memory structure being characterized in thatthe OD region has at least one addition region protruding in a second direction and partially overlapped with the floating gate, wherein the second direction is vertical to the first direction.2. The nonvolatile memory structure according to claim 1 , wherein the addition region is disposed at one side of the OD region.3. The nonvolatile memory structure according to claim 1 , wherein the addition regions are disposed at two sides of the OD region.4. The nonvolatile memory structure according to claim 1 , wherein an area of the at least one addition region is A1 claim 1 , an overlap area between the floating gate and the addition region is A2 claim 1 , and a ratio of A2 to A1 is 0.5 or more.5. The nonvolatile memory structure ...

Memory system and method for controlling nonvolatile memory

According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING HYDROGEN DIFFUSION BARRIER LAYER FOR CMOS UNDER ARRAY ARCHITECTURE AND METHOD OF MAKING THEREOF

A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer. 1. A semiconductor structure , comprising:at least one semiconductor device;a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer comprising a hydrogen diffusion barrier, and at least one second dielectric material layer overlying the at least one semiconductor device;lower metal interconnect structures embedded within the dielectric layer stack, the lower metal interconnect structures comprising a lower metal line structure located below the silicon nitride layer;a three-dimensional memory array overlying the dielectric layer stack and including an alternating stack of insulating layers and electrically conductive layers, and including memory stack structures vertically extending through the alternating stack in a memory array region;a through-stack contact via structure extending through the alternating stack, through the at least one second dielectric material layer, and through the silicon nitride layer, and contacting the lower metal line structure; anda through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack and through the at least one second dielectric material layer, but not extending ...

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor. 1. A semiconductor structure , comprising:a stack of memory cells, anda CMOS structure, located below the stack of memory cells, wherein the CMOS structure comprises a source line transistor and a bit line transistor.2. The semiconductor structure according to claim 1 , wherein the source line transistor is adjacent to the bit line transistor.3. The semiconductor structure according to claim 1 , wherein the stack of memory cells does not overlap the source line transistor and the bit line transistor.4. The semiconductor structure according to claim 1 , further comprising:a local bit line, located above the stack of memory cells, anda first pillar element, located between the local bit line and the bit line transistor, wherein the local bit line is electrically connected to the bit line transistor through the first pillar element.5. The semiconductor structure according to claim 4 , further comprising:an insulating stack, adjacent to the stack of memory cells,wherein the first pillar element penetrates the insulating stack, and the first pillar element transmits a signal in the local bit line to the bit line transistor.6. The semiconductor structure according to claim 1 , further comprising:a first metal layer, located above the bit line transistor,a second pillar element, located above the first metal layer, anda global bit line, located above the stack of memory cells,wherein the bit line transistor is electrically connected to the global bit line through the first metal layer and the second pillar element.7. The semiconductor structure according to claim 6 , further comprising:a second metal layer, located between the first metal layer and the second pillar element, wherein the bit line transistor is electrically connected to the global bit ...

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed. 1. A method used in forming a memory array comprising strings of memory cells , comprising: (a): of a thickness greater than that of the upper first tier and that of the upper second tier immediately-above the intervening tier and greater than that of the lower first tier and that of the lower second tier immediately-below the intervening tier;', '(b): at least predominantly polysilicon and of different composition from compositions of the upper first tier and the upper second tier immediately-above the intervening tier and of different composition from compositions of the lower first tier and the lower second tier immediately-below the intervening tier; and', '(c): at least predominantly conductive and of different composition from the compositions of the upper first tier and the upper second tier immediately-above the intervening tier and of different composition from the compositions of the lower first tier and the lower second tier immediately-below the intervening tier;, 'forming an upper stack above a lower stack, the lower stack comprising vertically-alternating lower first tiers and lower second ...

MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. 1. An apparatus comprising:a memory device; and a first pillar;', 'first memory cells and associated control gates located in different levels of the memory device and along a first portion of the first pillar;', 'a first select gate, a control line, and a second select gate located in different levels of the memory device and along a second portion of the first pillar;', 'a second pillar, and second memory cells located in different levels of the memory device and along a first portion of the second pillar;', 'third memory cells located in different levels of the memory device and located along a third pillar;', 'a first conductive material coupled to the first pillar and the second pillar, wherein the first select gate, the control line, and the second select gate are between the first conductive material and the first memory cells;', 'a second conductive material coupled to the third memory cells; and', 'a first coupling component located along the second portion of the first pillar, the first coupling component being between the first select gate and the second select gate;', 'a second coupling component located along a second portion of the second pillar; and', 'a third coupling component coupled to the second conductive material and the third memory cells and located between the second conductive material and the third memory cells., 'an external device coupled to the memory device, the memory device including2. The apparatus of claim 1 , wherein the external device includes a memory controller.3. The apparatus of claim 1 , wherein the external device includes a processor.4. The ...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region. 125.-. (canceled)26. A three-dimensional semiconductor device , comprising:a semiconductor layer including first, second, third, and fourth well regions doped with first conductivity impurities, the first and second well regions that are adjacent to each other in a first direction, the first and third well regions that are adjacent to each other in a second direction crossing the first direction, and the second and fourth regions that are adjacent to each other in the second direction; andfirst, second, third, and fourth cell array structures disposed on the first, second, third, and fourth well regions, respectively; a stack structure including a plurality of stacked electrodes stacked in a vertical direction on a top surface of the semiconductor layer; and', 'a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region,, 'wherein each of the first, second, third, and fourth cell array structure compriseswherein the semiconductor layer further includes a separation impurity region doped with second conductivity impurities, and a first region continuously extending along the second direction between the first and second well regions and between the third and fourth well region; and', 'a second ...

METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEMORY STRINGS

A process for manufacturing a -D NOR memory array provides thin-film storage transistors of each NOR memory string in either shafts or portions of a trench between adjacent shafts. 1. A process , comprising:providing over a planar surface of a semiconductor substrate a semiconductor structure which comprises a plurality of active multi-layers which are stacked one on top of another along a first direction that is substantially normal to the planar surface, wherein adjacent active multi-layers are electrically isolated from each other by a layer of dielectric material, and wherein each active multi-layer comprises first and second semiconductor layers of a first conductivity type separated by a dielectric material;providing a plurality of shafts arrayed in a regular pattern along both a second direction and a third direction, the second and third directions being substantially orthogonal to each other and each being orthogonal to the first direction, each shaft extending in depth along the first direction through the semiconductor structure and having a predetermined extent along the second direction;providing a plurality of trenches in the semiconductor structure each extending in depth along the first direction and in length along the third direction, each trench (a) intersecting a plurality of the shafts in the second direction, and (b) having a width along the second direction that is less than the extent of each shaft; andforming, in either (i) each shaft, or (ii) portions of each trench between adjacent shafts: (a) a third semiconductor layer of a second conductivity type opposite the first conductivity type, the third semiconductor layer being formed adjacent to and in contact with the first and second semiconductor layers of each active multi-layer, (b) a charge-trapping layer adjacent the third semiconductor layer; and (c) a conductor layer in contact with the charge-trapping layer.2. The process of claim 1 , wherein the first and second semiconductor layers ...

Vertical memory devices

In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.

SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE

A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed. 1. (canceled)2. A method of manufacturing a memory device comprising:creating a stackup of at least three tier insulating layers alternating with at least two circuit layers, the circuit layers individually include a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer to allow selective etching of the sacrificial layers without etching the tier insulating layers;creating a hole through the stackup;etching the conductive layers back from the hole;etching the sacrificial layers back from the hole;forming a blocking dielectric film inside at least a portion of the hole, the blocking dielectric film no thicker than an individual sacrificial layer of the sacrificial layers;creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, the floating gates separated from the conductive layers and the tier insulating layers by the blocking dielectric film;forming a tunneling dielectric film inside the hole; andfilling the hole with semiconductor material, the semiconductor material separated from the floating gates by the tunneling dielectric film.3. The method of claim 2 , the conductive layers claim 2 , the floating gates and the semiconductor material comprise polysilicon claim 2 , and the tier insulating layers and the sacrificial layers comprise an oxide or a nitride.4. The method of claim 2 , further comprising:creating an outer oxide film on an ...

Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate. 1. A memory device , comprising:a silicon semiconductor substrate;spaced apart source and drain regions formed in the silicon semiconductor substrate with a channel region there between;a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region; a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and', 'a second portion that extends up and over, and is insulated from, the floating gate;, 'a conductive erase gate that includesa conductive word line gate disposed over and insulated from a second portion of the channel region, wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate;wherein a thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate.2. The memory device of claim 1 , wherein the erase gate second portion is the only conductive gate or ...

Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells. 113-. (canceled)14. A method of forming vertically-stacked memory cells , comprising:forming a first insulative material over a stack of alternating dielectric levels and conductive levels;forming a first opening through the first insulative material and through the stack of alternating dielectric levels and conductive levels;forming cavities extending into the conductive levels along sidewalls of the first opening;forming a silicon nitride liner within the first opening and extending into the cavities;forming a second insulative material over the silicon nitride liner and over the first insulative material, the second insulative material covering the first opening and not extending downwardly into the first opening to an uppermost level of the stack, a remaining portion of the first opening being beneath the second insulative material;forming select gate material over the second insulative material;forming a second opening the through the select gate material and the second insulative material, and to the remaining portion of the first ...

SALICIDED STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates. A silicide contact pad is arranged over a top surface of the first memory cell gate. The silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate. A method of manufacturing the integrated circuit is also provided. 1. An integrated circuit for an embedded flash memory device , said integrated circuit comprising:a semiconductor substrate including a memory region and a logic region adjacent to the memory region;a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;a flash memory cell device arranged over the memory region, wherein the flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates; anda silicide contact pad arranged over a top surface of the first memory cell gate, wherein the silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate.2. The integrated circuit according to claim 1 , wherein the first memory cell gate is a memory gate claim 1 , the second memory cell gate is a select gate claim 1 , and the dielectric region includes a charge trapping dielectric arranged ...

RECESSED SALICIDE STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided. 1. An integrated circuit for an embedded flash memory device , said integrated circuit comprising:a semiconductor substrate including a memory region and a logic region adjacent to the memory region;a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;a flash memory cell device arranged over the memory region, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions; anda silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions.2. The integrated circuit according to claim 1 , wherein the memory cell gate is one of a memory gate claim 1 , a select gate claim 1 , an erase gate claim 1 , a word line claim 1 , and a control gate.3. The integrated circuit according to claim 1 , wherein the flash memory cell ...

HIGHLY SCALABLE SINGLE-POLY NON-VOLATILE MEMORY CELL

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region. 1. A nonvolatile memory (NVM) cell , comprising:a semiconductor substrate;a first OD region and a second OD region;an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth;a PMOS select transistor disposed on the first OD region;a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region;a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region; anda memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region.2. The NVM cell according to claim 1 , wherein the PMOS select transistor and the PMOS floating gate transistor commonly share the memory N well.3. The NVM cell according to claim 1 , ...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs. 1. A semiconductor device comprising:a substrate including a first region and a second region;a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;an etch stop layer on the lower layer structure;an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure; anda first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; anda second contact plug filling a second opening, the ...

SEMICONDUCTOR DEVICE

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion. 1. (canceled)2. A semiconductor device comprising a circuit , the circuit comprising: a first semiconductor layer;', 'a first gate insulating layer over the first semiconductor layer; and', 'a first gate electrode over the first gate insulating layer;, 'a first transistor comprisingan insulating layer over the first semiconductor layer; a second gate electrode;', 'a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer;', 'a second semiconductor layer over the second gate insulating layer; and', 'a third gate electrode over the second semiconductor layer;, 'a second transistor comprising a first electrode; and', 'a second electrode over the first electrode,, 'a capacitor comprisingwherein the first semiconductor layer comprises silicon,wherein the second semiconductor layer comprises an oxide semiconductor,wherein the first electrode comprises silicon,wherein the second gate electrode is over and in contact with the first gate insulating layer,wherein the second electrode is electrically connected to the first ...

APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described. 1. An apparatus comprising:a first deck including alternating levels of first conductor materials and levels of first dielectric materials;first memory cells located in the first deck, each of the first memory cells located in a respective level of the levels of first conductor materials;a second deck including alternating levels of second conductor materials and levels of second dielectric materials;second memory cells located in the second deck, each of the second memory cells located in a respective level of the levels of second conductor materials;a level of third conductor material located between the first and second decks;a level of fourth conductor material located between the first and second decks; anda level of a dielectric material located between the level of third conductor material and the level of fourth conductor material.2. The apparatus of claim 1 , wherein the first conductor materials have a first conductivity type and each of the third and fourth conductor materials has a second conductivity type.3. The apparatus of claim 1 , wherein the first conductor materials have a conductivity of n-type and each of the third and fourth conductor materials has a conductivity of p-type.4. The apparatus of claim 1 , wherein each of the third and fourth conductor materials includes conductively doped semiconductor material.5. The apparatus of claim 4 , wherein the conductively doped semiconductor has a p-type conductivity.6. The ...

NAND Memory Arrays, Devices Comprising Semiconductor Channel Material and Nitrogen, and Methods of Forming NAND Memory Arrays

Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays. 1. (canceled)2: The device of wherein the semiconductor channel material further comprises one or more of germanium claim 3 , GaAs claim 3 , InP claim 3 , GaP and GaN.3: A device claim 3 , comprising:a gate spaced from a semiconductor channel material by a dielectric region;a nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region; and wherein:the semiconductor channel material comprises conductively doped polycrystalline silicon,the nitrogen-containing material comprises silicon nitride;the semiconductor channel material joining to the silicon nitride along an interface;a volume of the semiconductor channel material comprising nitrogen to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent; said volume of the semiconductor channel material being within a distance of no greater than about 10 Å from said interface; andsaid volume of the semiconductor channel material comprising fluorine.4: ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other. 1. A semiconductor device , comprising:a first cell structure including first channel layers;a second cell structure including second channel layers;a pad structure located between the first cell structure and the second cell structure and including a first stepped structure and a second stepped structure, the first stepped structure including first pads electrically connected to the first and second cell structures and stacked on top of each other;a circuit vertically arranged with the first cell structure, the second cell structure and the pad structure;an interconnection electrically connecting the first pads to the circuit.2. The semiconductor device of claim 1 , further comprising an opening passing through the pad structure to expose the circuit.3. The semiconductor device of claim 2 , wherein the interconnection is electrically connected to the circuit through the opening.4. The semiconductor device of claim 1 , wherein the pad structure includes a dummy structure including wiring lines stacked on top of each other claim 1 , the wiring lines electrically connecting the first cell structure and the second cell ...

ELECTRONIC DEVICES AND SYSTEMS WITH CHANNEL OPENINGS OR PILLARS EXTENDING THROUGH A TIER STACK, AND METHODS OF FORMATION

Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack. 1. A method of forming a semiconductor device , the method comprising:forming a stack of vertically-alternating tiers of insulative material and other material over a base material, a sacrificial material disposed in the base material, and a soft plug material disposed in the sacrificial material;forming an opening extending through the stack and through the soft plug material, leaving remnants of the soft plug material along sidewalls of the opening;forming a liner in the opening;exposing, through the liner, a portion of the sacrificial material;without removing the liner, removing the sacrificial material and the remnants of the soft plug material to define a gap between the liner and a sidewall of the base material, the gap exposing a portion of a lower tier of the stack;etching into the portion of the lower tier of the stack to define an undercut portion in the lower tier of the stack; andremoving the liner to form a channel opening extending through the stack and into the base material, the channel opening exposing a source region of the base material at a base of the channel opening, the channel opening defined by sidewalls comprising the undercut portion.2. The method of claim 1 , wherein forming a liner in the opening comprises conformally forming polysilicon in the opening.3. The method of claim 1 , wherein etching into the portion of the lower tier of the stack to define an undercut portion in the lower tier of the stack comprises isotropically etching into the portion of the lower tier of the stack.4. The method of claim 1 , ...

Split Gate Non-Volatile Memory Cells With Three-Dimensional FINFET Structure, And Method Of Making Same

A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins. 1. A memory device , comprising:a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface; spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a control gate that extends along and is insulated from the floating gate, and', 'an erase gate that extends along and is insulated from the source region;, 'a memory cell formed on a first fin of the plurality of fins, comprisinga second fin of the plurality of fins has a ...

NON-VOLATILE MEMORY DEVICE

A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. 1. A non-volatile memory , comprising:an upper semiconductor layer vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region,the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.2. The non-volatile memory of claim 1 , further comprising:a control logic that generates a connection control signal, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.3. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor including a first source/drain region and a second source/drain region claim 1 , and a first contact plug extending from the first source/drain region through the separation region to connect the first bit line; and', 'a second contact plug extending from the second source/drain region through the separation region to connect the second bit line., 'the non-volatile memory device further comprises4. (canceled)5. The non-volatile memory of claim 1 , wherein a portion of the lower semiconductor layer underlying the first memory group includes a first portion of a first row decoder claim 1 , a second portion ...

Method Of Making Split Gate Non-Volatile Memory Cells With Three-Dimensional FINFET Structure, And Method Of Making Same

A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins. 1. A method of forming a memory device , comprising:forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface; forming spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'forming a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'forming a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'forming a control gate that extends along and is insulated from the floating gate, and', 'forming an erase gate that extends along and is insulated from the source region;, 'forming a memory cell on a first fin of the plurality ...

Integrated Assemblies Having Anchoring Structures Proximate Stacked Memory Cells, and Methods of Forming Integrated Assemblies

Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Method for in situ Preparation of Antimony-doped Silicon and Silicon Germanium films

A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane 1. A process , comprising:exposing a surface of a semiconductor structure; andflowing over the surface of the semiconductor structure an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas, so as to deposit by chemical vapor deposition an antimony-doped silicon-containing layer at a temperature no greater than 900° C.2. The process of claim 1 , wherein the antimony source gas comprises one or more of: trimethylantimony (TMSb) and triethylantimony (TESb).3. The process of claim 1 , wherein the silicon source gas comprises one or more of: silane claim 1 , disilane claim 1 , trichlorosilane claim 1 , (TCS) claim 1 , dichlorosilane (DCS) claim 1 , monochlorosilane (MCS) claim 1 , methylsilane claim 1 , and silicon tetrachloride.4. The process of claim 1 , wherein the germanium source gas comprises germane.5. The process of claim 1 , wherein the antimony-doped silicon-containing layer is deposited into a cavity formed by removal of a sacrificial layer.1. process of claim 1 , further comprising:forming an n-type semiconductor layer above the semiconductor structure; andannealing the n-type semiconductor layer at a temperature higher than 800° C., prior to annealing the ...

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a plurality of memory strings including a plurality of memory transistors connected in series and a selection transistor disposed on either end of the plurality of memory transistors, which together form a memory cell. The memory transistors and the selection transistors each include a polysilicon layer formed on an insulating film as a channel region thereof. A drain region is in a first diffusion layer region in the polysilicon layer in a location adjacent to a selection transistor at a first end of the memory string, and a source region is in a second diffusion layer region in the polysilicon layer in a location adjacent to a selection transistor at a second end of the memory string. In at least one of the first and the second diffusion regions, the grain size of the polysilicon is smaller than in other portions of the polysilicon.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes stacked above a substrate;a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda first insulating layer positioned between the semiconductor layer and the control gate electrode,part of the first insulating layer being a charge accumulation layer, andpart of the first insulating layer being an oxide layer positioned upwardly of the charge accumulation layer.2. The semiconductor memory device according to claim 1 , further comprising:a second insulating layer positioned between the semiconductor layer and the first insulating layer; anda third insulating layer provided between the first insulating layer and the control gate electrode.3. The semiconductor memory device according to claim 1 , whereinthe plurality of control gate electrodes include a first control gate electrode and a second control gate electrode positioned more upwardly than the first control gate electrode, anda boundary of the charge accumulation layer and the oxide layer is positioned more upwardly than the first control gate electrode and more downwardly than an upper surface of the second control gate electrode.4. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes provided as a stack above a substrate;a semiconductor layer having as its longitudinal direction a direction crossing the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda charge accumulation layer positioned between the control gate electrode and the semiconductor layer,a gap being provided between the semiconductor layer and a lower end portion of the charge accumulation layer.2. The semiconductor memory device according to claim 1 , further comprising:a first insulating layer covering a sidewall of the semiconductor layer; anda second insulating layer covering a sidewall of the charge accumulation layer,wherein the lower end portion of the charge accumulation layer has a recess portion which is recessed with respect to lower end portions of the first insulating layer and the second insulating layer.3. The semiconductor memory device according to claim 1 , further comprisinga first insulating layer provided between the semiconductor layer and the charge accumulation layer,wherein a distance, via the gap, between the semiconductor layer and the lower end portion of the charge accumulation layer, when converted to an electrical resistance value, is not less than a distance equivalent to a film thickness of the first insulating layer.4. The ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes provided as a stack above a substrate;a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda charge accumulation layer positioned between the control gate electrode and the semiconductor layer,a lower end of the charge accumulation layer being positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.2. The semiconductor memory device according to claim 1 , whereinthe plurality of control gate electrodes include: a first control gate electrode; and a plurality of second control gate electrodes positioned more upwardly than the first control gate electrode, andthe lower end of the charge accumulation layer is positioned between the first control gate electrode and the plurality of second control gate electrodes.3. The semiconductor memory device according to claim 2 , further comprising:a memory string including a plurality of memory cells connected in series; anda select gate transistor connected to one end of the memory string,wherein the first control gate electrode functions as a control gate electrode of the select gate transistor, andthe second ...

CARBON LAYER COVERED MASK IN 3D APPLICATIONS

Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer. 1. A method , comprising:forming a mask on a feature layer;forming a first opening in the mask to expose a portion of the feature layer;forming a carbon layer on the mask and the exposed portion of the feature layer; andremoving portions of the carbon layer and a portion of the exposed portion of the feature layer to form a second opening in the feature layer.2. The method of claim 1 , wherein the mask comprises doped carbon.3. The method of claim 2 , wherein the feature layer comprises silicon claim 2 , germanium claim 2 , silicon germanium claim 2 , silicon oxide claim 2 , aluminum oxide claim 2 , silicon oxide nitride claim 2 , or silicon nitride.4. The method of claim 2 , wherein the feature layer comprises a metal.5. The method of claim 2 , wherein the carbon layer comprises a graphene layer.6. The method of claim 2 , wherein the carbon layer comprises a plurality of graphene layers.7. The method of claim 6 , wherein the plurality of graphene layers is formed by a microwave-assisted chemical vapor deposition process.8. A method claim 6 , comprising:forming a mask on alternating layers;forming a first plurality of openings in the mask to expose portions of the alternating layers;forming a carbon layer on the mask and the exposed portions of the alternating layers; andremoving portions of the carbon layer and portions of the exposed portions of the alternating layers to form a second plurality of openings in the ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patters overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction. 1. A semiconductor memory device comprising:a substrate extending in a first direction and a second direction intersecting with the first direction;a plurality of input/output pads disposed at one side of the substrate;a first circuit adjacent to the input/output pads in the first direction;a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit;a first memory cell array overlapping the first circuit;a second memory cell array overlapping the second circuit;first metal source patters overlapping the first memory cell array, wherein the first metal source patterns are spaced apart from each other in the second direction; anda second metal source pattern overlapping the second memory cell array, wherein the second metal source pattern has a width wider than a width of each of the first metal source patterns in the second direction.2. The semiconductor memory device of claim 1 , further comprising a transmission line overlapping the first memory cell array between the first metal source patterns claim 1 ,wherein the transmission line is configured to transmit an ...

THREE-DIMENSIONAL MEMORY DEVICE WITH HYDROGEN-RICH SEMICONDUCTOR CHANNELS

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen. 1. A three-dimensional (3D) memory device , comprising:a memory stack comprising interleaved stack conductive layers and stack dielectric layers;a semiconductor layer;a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer; andan insulating structure extending vertically through the memory stack and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.2. The 3D memory device of claim 1 , wherein an atomic percent of the at least one of hydrogen or an isotope of hydrogen in the dielectric layer is not greater than about 50%.3. The 3D memory device of claim 2 , wherein the atomic percent of the at least one of hydrogen or an isotope of hydrogen in the dielectric layer is between about 1% and about 10%.4. The 3D memory device of claim 1 , wherein the dielectric layer comprises silicon nitride.5. The 3D memory device of claim 1 , wherein the insulating structure further comprises a first silicon oxide layer laterally between the dielectric layer and the stack conductive layers of the memory stack.6. The 3D memory device of claim 5 , wherein the insulating structure further comprises a second silicon oxide layer claim 5 , wherein the dielectric layer is laterally between the first and second silicon oxide layers.7. The 3D memory device of claim 5 , wherein the insulating structure further comprises a polysilicon layer claim 5 , wherein the dielectric layer is ...

UV-ERASABLE MEMORY DEVICE WITH UV TRANSMITTING WINDOW AND FABRICATION METHOD THEREOF

A UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate; an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window. 1. A method for fabricating a UV-erasable memory device with a UV transmitting window , comprising:providing a substrate;forming two serially connected MOS transistors on said substrate;covering said two MOS transistors with an interlayer dielectric (ILD) layer;depositing a first intermetal dielectric (IMD) layer on said ILD layer;depositing an intermediate layer on said first IMD layer;forming a UV transmitting window in said intermediate layer; anddepositing a second intermetal dielectric (IMD) layer on said first IMD layer and into said UV transmitting window.2. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said two serially connected MOS transistors comprise a select transistor and a floating gate transistor.3. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 2 , wherein said floating gate transistor comprises a polysilicon gate for charge storage.4. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 3 , wherein said UV transmitting window is positioned directly above said polysilicon gate for charge storage.5. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said substrate is a P type silicon substrate with an N well.6. The method for fabricating a UV-erasable memory device with a UV transmitting window according ...

NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region. 1. A nonvolatile memory (NVM) cell , comprising:a semiconductor substrate of a first conductivity type;a first oxide define (OD) region in the semiconductor substrate;a second oxide define (OD) region for forming an erase gate (EG) region being spaced apart from the first OD region;a trench isolation region separating the first OD region from the second OD region;a select transistor disposed on the first OD region;a floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the floating gate transistor comprises a floating gate overlying the first OD region;a floating gate extension continuously extending from the floating gate to the second OD region; anda shallow junction diffusion region of a second conductivity type situated directly under the floating gate extension within the second OD region.2. The NVM cell according to claim 1 , wherein the select transistor and the floating gate transistor are PMOS transistors and the select transistor and the floating gate transistor are disposed within an N well.3. The NVM cell according to claim 2 , wherein the first conductivity type is P type and the second conductivity type is N type.4. The NVM cell according to further comprising an isolation ion well of the first conductivity ...

NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME

Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. 18-. (canceled)9. A nonvolatile memory device comprising:a substrate;a ground select line on the substrate;a plurality of word lines vertically stacked on the ground select line;a string select line on the plurality of word lines;a first dummy word line between the ground select line and a first word line, wherein the first word line is nearest to the ground select line among the word lines; anda second dummy word line between the string select line and a second word line, wherein the second word line is nearest to the string select line among the word lines,wherein a first distance between a bottom surface of the ground select line and a bottom surface of the first dummy word line is greater than a second distance between the bottom surface of the first dummy word line and a bottom surface of the first word line, andwherein a third distance between bottom surfaces of adjacent ones of the word lines is less than the second distance.10. The nonvolatile memory device of claim 9 ,wherein a bottom surface of the second dummy word line is vertically spaced apart from a bottom surface of the second word line by a fourth distance, andwherein the fourth distance is greater than the third distance and is less than the first distance.11. The nonvolatile memory device of claim 9 ,wherein a bottom surface of the string select line is vertically spaced apart from a bottom surface of the second dummy word line by a fifth distance, andwherein the fifth distance is greater than the second distance and the third distance.12. The nonvolatile memory device of claim 9 , wherein each ...

MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device and an operating method thereof are provided. A memory device may include a plurality of source lines coupled to a memory block. The memory device may include a plurality of strings coupled to each of the source lines. The memory device may include a row decoder configured to selectively transmit voltages to local lines corresponding to a selected source line among the source lines. 1. A memory device comprising:a plurality of source lines coupled to a memory block;a plurality of strings coupled to each of the source lines;a source decoder configured to selectively apply voltages to the source lines; anda row decoder configured to selectively transmit voltages to local lines corresponding to a selected source line among the source lines.2. The memory device of claim 1 , wherein the strings are coupled between bit lines and the source lines.3. The memory device of claim 1 , wherein the source decoder includes source switch circuits claim 1 , and the number of the source switch circuits corresponds to the number of the source lines.4. The memory device of claim 3 , wherein the source switch circuits are coupled to the respective source lines claim 3 , and each selectively operates in response to a row address.5. The memory device of claim 3 , wherein each of the source switch circuits transmits a voltage supplied from different voltage sources to a source line in response to the row address claim 3 , or interrupts the transmission of the voltage.6. The memory device of claim 1 , wherein the row decoder includes:global switch circuits configured to transmit voltages supplied to global lines to sub-global lines in response to the row address; andlocal switch circuits configured to commonly receive voltages applied to the sub-global lines, and selectively transmit the voltages applied to the sub-global lines to local lines corresponding to the source lines.7. The memory device of claim 6 , wherein each of the global switch circuits is configured to ...

MEMORY SYSTEM AND METHOD FOR READ OPERATION OF MEMORY SYSTEM

According to one embodiment, a peripheral circuit of a first memory executes a read operation to acquire first data programmed to a first memory cell transistor of the first memory on the basis of a comparison between a threshold voltage of the first memory cell transistor and a determination voltage. An error corrector circuit corrects error in second data being the first data acquired by the read operation. When the error corrector circuit fails in the error correction in the second data, a memory controller acquires first history information, changes the determination voltage to a second voltage value in accordance with first history information, and causes the peripheral circuit to re-execute the read operation. The first history information includes second history information on elapsed time since the first data is programmed and third history information on the number of executed program operations on the first memory cell transistor. 1. A memory system , comprising:a first memory including a memory cell array and a peripheral circuit, the memory cell array including a first memory cell transistor, the peripheral circuit executing a read operation to acquire, on the basis of a comparison between a threshold voltage of the first memory cell transistor and a determination voltage, first data programmed to the first memory cell transistor;an error corrector circuit that corrects error in second data, the second data being the first data acquired by the read operation; anda memory controller that, when the error corrector circuit has failed to correct the error in the second data, acquires first history information, and changes the determination voltage from a first voltage value to a second voltage value in accordance with the first history information to cause the peripheral circuit to re-execute the read operation, the first history information including second history information on an elapsed time from programming of the first data, and third history ...

SEMICONDUCTOR DEVICE INCLUDING GATES

A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction. 1. A semiconductor device comprising:first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode; andsecond gate electrodes including a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode,wherein the second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region along a direction orthogonal to an upper surface of the first upper electrode,the first lower electrode extends by a first length, further than the first upper electrode, in a first direction, andthe second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.2. The ...

VERTICAL MEMORY DEVICE

A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer. 1. A vertical memory device comprising:a substrate;a plurality of gate electrode layers stacked on the substrate;a channel layer penetrating through the plurality of gate electrode layers and having an external diameter;a first epitaxial layer in contact with a lower portion of the channel layer and having a first epitaxial diameter; anda second epitaxial layer disposed between the first epitaxial layer and the substrate and having a second epitaxial diameter,wherein the channel layer covers an entire upper surface of the first epitaxial layer,the second epitaxial diameter is greater than the external diameter of the channel layer, and the external diameter of the channel layer is greater than or equal to the first epitaxial diameter.2. The vertical memory device of claim 1 , further comprising a gate dielectric layer disposed between the channel layer and the plurality of gate electrode layers claim 1 , and extended below the lower portion of the channel layer claim 1 ,wherein the first epitaxial layer penetrates through at least a portion of the gate dielectric layer and has an upper surface protruding beyond the gate dielectric layer.3. The vertical memory device of claim 1 , wherein an upper surface of the first epitaxial layer has an upwardly convex curved surface.4. The vertical memory device of claim 1 , wherein an upper surface of the first epitaxial layer has inclined surfaces.5. The vertical memory device of claim 1 , wherein a lower surface of the first epitaxial layer has a downwardly convex curved surface.6. The vertical memory device of claim 1 , wherein a lower ...

Memory Cell Comprising First and Second Transistors and Methods of Operating

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

INTERCONNECTIONS FOR 3D MEMORY

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step. 120-. (canceled)21. An apparatus , comprising:a memory array comprising a plurality of access lines; and select a first access line or a second access line for performance of a memory operation;', 'cause performance of the memory operation; and', 'cause the first access line and the second access line of the memory array to be equalized subsequent to performance of the memory operation., 'a controller coupled to the memory array, the controller to22. The apparatus of claim 21 , wherein claim 21 , when the memory operation comprises a program operation claim 21 , the controller is to cause the first access line to be selected and the second access line to be deselected.23. The apparatus of claim 21 , wherein claim 21 , when the memory operation comprises a read operation claim 21 , the controller is to cause the first access line to be deselected and the second access line to be selected.24. The apparatus of claim 21 , wherein the first access line and the second access line of the memory array are equalized to a potential that is different than a ground reference potential.25. The apparatus of claim 21 , wherein the controller is claim 21 , subsequent to causing the first access line and the second access line of the memory array to be equalized claim 21 , to cause the first access line or the second access line claim 21 , or both claim 21 , to be discharged to ...

CELL-LIKE FLOATING-GATE TEST STRUCTURE

Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device. 1. An integrated circuit (IC) comprising:a semiconductor substrate; anda floating gate test device on the semiconductor substrate, wherein the floating gate test device comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode, wherein the floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges, and wherein the bridges interconnect the islands.2. The IC according to claim 1 , wherein the array is limited to a single row or column.3. The IC according to claim 1 , wherein the array comprises a plurality of rows and a plurality of columns.4. The IC according to claim 1 , wherein the plurality of bridges comprises a bridge for each pair of neighboring islands in the array claim 1 , and wherein the bridge extends from direct contact with a first island of the pair to a second island of the pair.5. The IC according to claim 1 , wherein the islands have substantially the same top layout claim 1 , and wherein the bridges have substantially the same top layout.6. The IC according to claim 1 , wherein the floating gate electrode comprises a floating gate array of ...

SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor memory device includes a substrate including a cell region on which memory sells are disposed and a connection region on which conductive patterns are disposed, the conductive patterns electrically connected to the memory cells; a first word line stack including a plurality of first word lines that are stacked on the substrate in the cell region and extend to the connection region; a second word line stack including a plurality of second word lines that are stacked on the substrate in the cell region and extend to the connection region, the second word line stack being adjacent to the first word line stack; vertical channels disposed on the cell region of the substrate, the vertical channels being connected to the substrate and respectively coupled with the plurality of first and second word lines; a bridge connecting one of the plurality of first word lines in the first word line stack to a corresponding word line of the second word line stack. 1. A semiconductor memory device comprising:a substrate including a cell region on which memory cells are disposed and a connection region on which conductive patterns are disposed, the conductive patterns electrically connected to the memory cells;a first word line stack comprising a plurality of first word lines that are stacked on the substrate in the cell region and extend to the connection region;a second word line stack comprising a plurality of second word lines that are stacked on the substrate in the cell region and extend to the connection region, the second word line stack being adjacent to the first word line stack;vertical channels disposed on the cell region of the substrate, the vertical channels being connected to the substrate and respectively coupled with the plurality of first and second word lines;a bridge connecting one of the plurality of first word lines in the first word line stack to a corresponding word line of the second word line stack; anda first pattern formed between a first ...

FERROELECTRIC NON-VOLATILE MEMORY

A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer. 1. A non-volatile memory system comprising: a control gate;', 'a tunneling layer;', 'a floating gate; and', 'a blocking layer comprising a ferroelectric material,, 'a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element comprisingwherein the tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.2. The non-volatile memory system of claim 1 , wherein the blocking layer comprises hafnium oxide.3. The non-volatile memory system of claim 1 , wherein the blocking layer comprises hafnium oxide doped with one or more of silicon claim 1 , aluminum claim 1 , zirconium claim 1 , yttrium claim 1 , gadolinium claim 1 , calcium claim 1 , cerium claim 1 , dysprosium claim 1 , erbium claim 1 , germanium claim 1 , scandium claim 1 , and tin.4. The non-volatile memory system of claim 1 , wherein the blocking layer comprises a combination of a ferroelectric dielectric material and one or more non-ferroelectric dielectric materials.5. The non-volatile memory system of claim 1 , further comprising a three-dimensional memory array claim 1 , wherein the plurality of NAND strings reside in the three-dimensional memory array.6. The non-volatile memory system of claim 1 , further comprising a two-dimensional memory array claim 1 , wherein the plurality of NAND strings reside in the two-dimensional memory array.7. A monolithic three-dimensional memory structure comprising: a control gate;', 'a tunneling layer;', 'a ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING A SLIMMED ALUMINUM OXIDE BLOCKING DIELECTRIC AND METHOD OF MAKING SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer. 2. The method of claim 1 , wherein the etch process comprises an isotropic etch process that reduces a thickness of a vertical portion of the in-process polycrystalline aluminum oxide blocking dielectric layer by a percentage in a range from 15% to 85%.3. The method of claim 1 , wherein:the amorphous aluminum oxide layer is deposited directly on physically exposed surfaces of the insulating layers;the in-process polycrystalline aluminum oxide blocking dielectric layer comprises an edge at which a physically exposed vertical surface of the in-process polycrystalline aluminum oxide blocking dielectric layer directly adjoins a physically exposed horizontal surface of the in-process polycrystalline aluminum oxide blocking dielectric layer; andthe etch process forms removes the edge and forms a concave surface having a uniform radius of curvature within a region in which a physically exposed vertical surface of the polycrystalline aluminum oxide blocking dielectric layer indirectly adjoins a physically exposed horizontal surface of the ...

Using Metal Gate First Method to Build Three-Dimensional Non-Volatile Memory Devices

A three-dimensional NAND memory system and method of making is disclosed. The three-dimensional NAND memory system may comprise a stack of horizontal layers and a vertical structure. The stack of horizontal layers may be formed on a semiconductor substrate. The stack of horizontal layers may comprise a plurality gate electrode layers alternating with a plurality of insulating layers. The gate electrode layer may comprise conductive lines alternate with insulating lines. The insulating lines may be formed of insulating materials. The conductive lines are formed of a metal comprising W. The vertical structure may extend vertically through the stack of horizontal layers. The vertical structure may comprise a blocking dielectric layer, a charge storage layer, a tunnel dielectric layer, and a vertical channel structure. The charge storage layer may be formed over the blocking dielectric layer. The tunnel dielectric layer may be formed over the charge storage layer. The tunnel dielectric layer may be sandwiched between the vertical channel structure and the charge storage layer. There is no metal nitride layer in the vertical structure between the stack of horizontal layers and blocking dielectric layer. 1. A method of fabricating a three-dimensional NAND , comprising:forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises an insulating material and wherein the second material comprises a conductive material;forming through the stack of horizontal layers a vertical opening thereby exposing the semiconductor substrate and exposing the stack of horizontal layers on a sidewall of the vertical opening;forming a blocking dielectric layer along the sidewall of the vertical opening;forming a charge storage layer over the blocking dielectric layer in the vertical opening;forming a tunnel dielectric layer over the charge storage layer in the vertical opening;forming a semiconductor layer over the tunnel ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view. 1. A semiconductor memory device comprising:a substrate;a first conductive layer provided above the substrate;a second conductive layer provided above the first conductive layer;a third conductive layer and a fourth conductive layer provided above the second conductive layer, the third conductive layer and the fourth conductive layer being separated from each other in a first direction;a fifth conductive layer provided in the same level of a layered structure as the third conductive layer above the second conductive layer, the fifth conductive layer being separated from the third conductive layer;a sixth conductive layer provided in the same level of the layered structure as the fourth conductive layer above the second conductive layer, the sixth conductive layer being separated from the fourth conductive layer;a plurality of first insulating regions provided between the third conductive layer and the fifth conductive layer and between the fourth conductive layer and the sixth conductive layer, along a second direction intersecting the first direction;a first pillar provided between the first insulating regions and penetrating the second conductive layer along the first direction, the first pillar ...

THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width. 1. A three-dimensional (3D) semiconductor memory device comprising:a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions; anda first block structure on the substrate,wherein the first block structure has a first width on the cell array region,wherein the first block structure has a second width on the first connection region,wherein the first block structure has a third width on the second connection region,wherein the first width, the second width and the third width are parallel to a second direction intersecting the first direction, andwherein the first width is less than the second width and is greater than the third width.2. The 3D semiconductor memory device of claim 1 , further comprising:a second block structure and a third block structure spaced apart from the first block structure in the second direction;a first block separation region separating the first block structure and the second block structure from each other; anda second block separation region separating the second block structure and the third block structure from each other,wherein the first block separation region is spaced apart from the second block separation region.3. The 3D semiconductor ...

Method of manufacturing flash memory cell

A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

THREE-DIMENSIONAL JUNCTION MEMORY DEVICE AND METHOD READING THEREOF USING HOLE CURRENT DETECTION

Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type. 1. A monolithic three-dimensional memory device comprising:a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate; anda memory stack structure extending through the stack and comprising a memory film and a semiconductor junction structure vertically extending through the stack substantially perpendicular to a top surface of the substrate;wherein the semiconductor junction structure comprises a semiconductor channel portion, a lower doped semiconductor source portion having a doping of a first conductivity type, and an upper doped semiconductor drain portion having a doping of a second conductivity type such that a junction is located between the semiconductor channel portion and an upper doped semiconductor drain portion; andwherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type.2. The monolithic three-dimensional memory device of claim 1 , wherein:the first conductivity type is p-type and the second ...

Select Gates with Central Open Areas

A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.

Select Gates with Conductive Strips on Sides

A NAND flash memory array includes a select line that is formed from a portion of a first conductive layer and a portion of second conductive layer separated by dielectric, and a connecting portion of a third conductive layer, the connecting portion extending in contact with a side of the portion of the first conductive layer and a side of the portion of the second conductive layer 114-. (canceled)15. A NAND flash memory array comprising:a plurality of floating gates formed of a first conductive layer;a plurality of word lines formed of a second conductive layer extending along a first direction over the plurality of floating gates;a dielectric between word lines and floating gates; anda select line extending along the first direction, the select line formed from a portion of the first conductive layer that has a top surface and sides, a portion of the second conductive layer, and a connecting portion of a third conductive layer, the connecting portion extending in contact with a side of the portion of the first conductive layer and a side of the portion of the second conductive layer.16. The NAND flash memory array of wherein the first conductive layer and the second conductive layer are formed of doped polysilicon and the third conductive layer is formed of doped amorphous silicon or metal.17. The NAND flash memory array of further comprising an insulating layer between the connecting portion and a substrate surface.18. The NAND flash memory array of further comprising a portion of the dielectric extending to cover the entire top surface of the portion of the first conductive layer between the sides so that there is no direct contact between the portion of the first conductive layer and the portion of the second conductive layer.19. The NAND flash memory array of further comprising a dielectric layer overlying the connecting portion.20. The NAND flash memory array of wherein the second conductive layer is formed of a doped polysilicon layer and a tungsten layer on ...

Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation. 1. A method of forming a memory device , comprising:providing a semiconductor substrate having a memory cell area, a core device area and an HV device area;forming spaced apart source and drain regions in the memory cell area of the substrate, with a channel region extending there between;forming a conductive floating gate disposed over and insulated from a first portion of the channel region and a portion of the source region;forming a conductive control gate disposed over and insulated from the floating gate;forming a first conductive layer in the memory cell area that at least extends over and is insulated from the source region and a second portion of the channel region;forming a first insulation layer that extends over the first conductive layer in the memory cell area, a surface portion of the substrate in the core device area and a surface portion of the substrate in the HV device area;removing the first insulation layer from the core device area; a layer of high K dielectric material, and', 'a layer of metal material on the layer of high K dielectric material;, 'forming an HKMG layer that extends over the first insulation layer in the memory cell area and the HV device area, and over the surface portion of the substrate in the core device area, wherein the HKMG layer includesforming a second conductive layer that extends over the HKMG layer in the memory cell area, the core device area and ...

SEMICONDUCTOR DEVICE

Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern. 1. A semiconductor device comprising:a stack comprising conductive layers and insulating layers that are alternately stacked; anda slit insulating layer passing through the stack in a stacking direction, the slit insulating layer comprising a first main pattern extending in a first direction and a first protruding pattern protruding from an end of the first main pattern in a second direction crossing the first direction.2. The semiconductor device according to claim 1 , wherein the first protruding pattern has a polygonal cross section.3. The semiconductor device according to claim 1 , wherein the first protruding pattern has a circular or elliptical cross section.4. The semiconductor device according to claim 1 , wherein the first protruding pattern comprises a stepped edge.5. The semiconductor device according to claim 1 , wherein the first protruding pattern comprises a curved edge and a straight line edge.6. The semiconductor device according to claim 1 , wherein the first main pattern has a first width claim 1 , an end of the slit insulating layer has a second width greater than the first width claim 1 , an outermost end of the slit insulating layer has a third width less than the second width and greater than the first width.7. The semiconductor device according to claim 1 , wherein a cross-sectional area of a lower surface of the slit insulating layer is less than that of an upper surface of the slit insulating layer.8. The semiconductor device according to claim 1 , wherein an upper surface of the slit insulating layer comprises ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure. 1. A semiconductor device comprising:a substrate including a cell array region and a peripheral circuit region;a stack structure disposed on the cell array region, the stack structure including a plurality of electrodes and a plurality of insulating layers alternately stacked;a plurality of peripheral gate structures disposed on the peripheral circuit region, the plurality of peripheral gate structures spaced apart from each other in one direction; anda plurality of residual spacers disposed on sidewalls of the plurality of peripheral gate structures, a peripheral gate pattern disposed on the substrate; and', 'a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern,, 'wherein each of the plurality of peripheral gate structures comprises a sacrificial pattern and', 'an insulating pattern that are stacked, and, 'wherein each of the plurality of residual spacers compriseswherein the insulating pattern includes substantially the same material as the plurality of insulating layers of the stack structure.2. The semiconductor device of claim 1 , wherein the sacrificial pattern includes a material having etch ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions. 1. A semiconductor memory device , the device comprising:a plurality of word lines stacked in a first direction;a semiconductor pillar extending through the plurality of word lines in the first direction;a source line electrically connected to the semiconductor pillar; anda transistor arranged in the first direction with the plurality of word lines and including a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively,the source line being positioned between the transistor and the plurality of word lines, and being electrically connected to one of the source and drain regions.2. The device according to claim 1 , further comprising:a first interconnect wire provided between the transistor and the source line,the source line being electrically connected to the one of the source and drain regions via the first interconnect wire.3. The device according to claim 2 , further comprising:a first contact plug electrically connecting the first interconnect wire and the source line.4. The device according to claim 1 , further comprising:a second contact plug extending in the first direction through the source line and the plurality of word lines, and electrically connected to the other of the source and drain regions; anda second interconnect wire electrically connected to the second contact plug,the plurality of word ...

Semiconductor Devices with Vertical Channel Structures

Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width. 1. A method of manufacturing a semiconductor device , comprising:alternately forming a plurality of sacrificial layers and a plurality of insulating layers on a substrate, the plurality of sacrificial layers including a first sacrificial layer and a plurality of second sacrificial layers on the first sacrificial layer, the plurality of second sacrificial layers including a material different from that of the first sacrificial layer;forming a channel hole through the plurality of sacrificial layers and the plurality of insulating layers to expose a top surface of the substrate;forming a sidewall protection layer on a sidewall of the channel hole;forming a channel contact layer filling a bottom of the channel hole;removing the sidewall protection layer;forming a channel layer in contact with the channel contact layer on an inner wall of the channel hole;removing the first sacrificial layer; andforming a first gate electrode at a position where the first sacrificial layer is removed.2. The method according to claim 1 , further comprising converting the plurality of second sacrificial layers into a plurality of second gate electrodes by a silicidation process.3. The method according to claim 2 ...

Integrated Assemblies and Methods of Forming Integrated Assemblies

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies. 1. A method of forming an integrated assembly , comprising:forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;forming an opening to extend through the stack;forming charge-storage material, tunneling material and channel material within the opening;forming slits to extend through the stack;flowing etchant into the slits to remove the second material and leave first voids between the first levels;forming conductive structures within the first voids; the conductive structures having proximal ends adjacent the channel material, and having distal ends adjacent the slits;removing the first material to leave second voids between the conductive structures;forming insulative liners within the second voids to line the second voids, regions of the insulative liners being along the distal ends of the conductive structures;forming sacrificial material within the lined second voids and over the regions of the insulative liners along the distal ends of the conductive structures;recessing the sacrificial material to expose the regions of the insulative liners along the distal ends of the conductive ...

INTEGRATED CIRCUIT STRUCTURES AND METHODS OF THEIR FORMATION

Integrated circuit structures, as well as methods for their formation, might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth. 1. An integrated circuit structure , comprising:a semiconductor material;a first active area in the semiconductor material;a second active area in the semiconductor material; and a first edge portion extending below a surface of the semiconductor material to a first depth;', 'a second edge portion extending below the surface of the semiconductor material to the first depth; and', 'an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth., 'an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area, the isolation structure further comprising2. The integrated circuit structure of claim 1 , further comprising:a first transistor in the first active area;a second transistor in the second active area;a first conductor forming a control gate of the first transistor; anda second conductor forming a control gate of the second transistor;wherein the isolation structure has an orientation that is parallel to the first conductor ...

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor storage device includes a stacked portion including an insulating layer and a conductor layer that are alternately stacked, and a plurality of memory pillars extending into the stacked portion. When viewed along a direction perpendicular to a surface of the stacked portion, the stacked portion includes a first area in which the plurality of memory pillars are provided, and a second area adjacent to the first area and free of the memory pillars. The first memory pillar of the plurality of memory pillars formed at a position closest to a boundary between the first area and the second area and a second memory pillar of the plurality of memory pillars that is adjacent to the first memory pillar have the same width. 1. A semiconductor storage device comprising:a stacked portion including an insulating layer and a conductor layer that are alternately stacked; anda plurality of memory pillars extending into the stacked portion,wherein, when viewed along a direction perpendicular to a surface of the stacked portion, the stacked portion includes a first area in which the plurality of memory pillars are provided, and a second area adjacent to the first area and free of the memory pillars, anda first memory pillar of the plurality of memory pillars formed at a position closest to a boundary between the first area and the second area and a second memory pillar of the plurality of memory pillars that is adjacent to the first memory pillar have the same width.2. The semiconductor storage device according to claim 1 , wherein claim 1 , when viewed along the direction perpendicular to the surface of the stacked portion claim 1 ,a third memory pillar of the plurality of memory pillars adjacent to the second memory pillar on a side opposite to the first memory pillar has the same shortest distance from an edge of the second memory pillar on the surface of the stacked portion, as a shortest distance of the second memory pillar from the edge of the first memory pillar ...

THREE-DIMENSIONAL MEMORY DEVICE WITH HIGH MOBILITY CHANNELS AND NICKEL ALUMINUM SILICIDE OR GERMANIDE DRAIN CONTACTS AND METHOD OF MAKING THE SAME

A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion. 1. A memory device comprising:a strained single-crystalline silicon layer;an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer;a memory opening vertically extending through the alternating stack; anda memory opening fill structure located in the memory opening and comprising an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer, a vertical semiconductor channel, a vertical stack of memory elements located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers, and a drain region.2. The memory device of claim 1 , further comprising a single-crystalline silicon-germanium compound semiconductor layer claim 1 , wherein the strained single-crystalline silicon layer is located on and in epitaxial alignment with the single-crystalline silicon-germanium compound semiconductor layer.3. The memory device of claim 2 , wherein:the strained single-crystalline silicon layer and the epitaxial silicon-containing pedestal channel portion have a doping of a first conductivity type; anda source region having a doping of a second conductivity type opposite to the first conductivity type is in contact with the strained single-crystalline silicon layer and is located ...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A COMPOSITE SEMICONDUCTOR CHANNEL AND A HORIZONTAL SOURCE CONTACT LAYER AND METHOD OF MAKING THE SAME

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein. 2. The three-dimensional memory device of claim 1 , wherein the composite semiconductor channel further comprises a pillar channel portion contacting a top surface of the pedestal channel portion and a bottom surface of the vertical semiconductor channel.3. The three-dimensional memory device of claim 2 , wherein:{'sup': 18', '3', '21', '3, 'each of the pillar channel portion and the pedestal channel portion includes n-type dopant atoms at a respective average atomic concentration in a range from 1.0×10/cmto 2.0×10/cm; and'}{'sup': 17', '3, 'the vertical semiconductor channel is intrinsic or includes electrical dopants at an atomic concentration not greater than 1.0×10/cm.'}4. The three-dimensional memory device of claim 2 , wherein: source-select-level electrically conductive layers located below a horizontal plane including a bottom surface of the vertical semiconductor channel, and', 'word-line-level electrically conductive layers located above the ...

SEMICONDUCTOR MEMORY DEVICES

A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer. 1. A semiconductor memory device comprising:a word line extending in a vertical direction on a substrate;a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width;a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction; anda cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.2. The semiconductor memory device of claim 1 , wherein an inner surface of the lower electrode layer comprises an electrode hole extending along a perimeter of the upper electrode layer and having a concave shape.3. The semiconductor memory device of claim 1 , wherein the lower electrode layer comprises a vertical cross-sectional surface having a U-shape rotated by 90 degrees.4. The semiconductor memory device of claim ...

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device is disclosed. The device may include an electrode structure including electrodes, the electrodes stacked on a substrate, a source semiconductor layer between the substrate and the electrode structure, and a vertical channel structure penetrating the electrode structure. The vertical channel structure includes a vertical insulating pattern, a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor pattern and the electrode structure; and a barrier pattern spaced apart from the electrode structure with the vertical semiconductor pattern interposed between the barrier pattern and the electrode structure. The vertical semiconductor pattern comprises a recess region, the source semiconductor layer extending in the recess region. The barrier pattern includes an insulating layer including carbon. 1. A semiconductor memory device , comprising:an electrode structure including electrodes, the electrodes stacked on a substrate;a source semiconductor layer between the substrate and the electrode structure; anda vertical channel structure penetrating the electrode structure, a vertical insulating pattern,', 'a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor pattern and the electrode structure; and', 'a barrier pattern spaced apart from the electrode structure with the vertical semiconductor pattern interposed between the barrier pattern and the electrode structure,, 'wherein the vertical channel structure includes,'}the vertical semiconductor pattern comprises a recess region, the source semiconductor layer extending in the recess region, andthe barrier pattern includes an insulating layer including carbon.2. The semiconductor memory device of claim 1 , further comprising:an insulating gapfill pattern spaced apart from the vertical semiconductor ...

INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME

Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof. 1. A method of manufacturing an integrated circuit device , the method comprising:forming, on a substrate, a structure comprising a plurality of first films and a plurality of second films alternately stacked with the plurality of first films;forming a channel hole that extends through the structure;forming, in the channel hole, a plurality of indented spaces by removing portions of the plurality of first films through the channel hole;forming, in the channel hole, a blocking dielectric film comprising a plurality of first grooves that are on the plurality of indented spaces, respectively, a preliminary charge storage film comprising a plurality of second grooves that are on the plurality of first grooves, respectively, and a first cover sacrificial layer comprising a plurality of third grooves that are on the plurality of second grooves, respectively, a plurality of first cover layers in the plurality of third grooves, respectively, and a second cover layer on the first cover sacrificial layer;exposing portions of the first cover sacrificial layer by removing the plurality of first ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate comprising storage transistors in a storage region;forming a plurality of stacked gates for the storage transistors in the storage region on the substrate;forming side walls on two sides of each of the plurality of stacked gates, wherein a height of one of the side walls is lower than a top surface of said stacked gate;performing ion implantation in the storage region defined by the side walls; andperforming an ashing process followed by a wet cleaning process using the side walls as protective layers for the plurality of stacked gates to remove a photoresist remaining after the ion implantation.2. The manufacturing method according to claim 1 , wherein the plurality of stacked gates comprises:a floating gate film, an interlayer dielectric layer and a control gate film sequentially formed from bottom to top over the substrate, whereina top surface of one of the side walls is arranged to be higher than the interlayer dielectric layer.3 ...

INTERCONNECTIONS FOR 3D MEMORY

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step. 1. An apparatus , comprising:a memory array including a plurality of access lines;an equalization circuit coupled to the array; and a first voltage to be applied to a selected one of the access lines;', 'a second voltage to be applied to a non-selected one of the access lines; and', 'the selected one of the access lines and the non-selected one of the access lines to be discharged to an equalization potential subsequent to performance of a program operation., 'a controller coupled to the memory array, wherein the controller is configured to cause2. The apparatus of claim 1 , wherein the controller is further configured to cause the selected access line and the non-selected access line to be discharged to a ground reference potential subsequent to discharge of the selected access line and the non-selected access line to the equalization potential.3. The apparatus of claim 1 , wherein the equalization potential is different than a ground reference potential.4. The apparatus of claim 1 , wherein the controller is further configured to cause the equalization circuit to be enabled while discharging the selected access line and the non-selected access line to the equalization potential.5. The apparatus of claim 1 , further comprising:a first global control line coupled to the selected access line; anda second global control line coupled to the non-selected access line ...

3d nand array with divided string architecture

A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

NAND String Utilizing Floating Body Memory Cell

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 123-. (canceled)24. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;wherein each said at least one of said plurality of semiconductor memory cells has only one gate; andwherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.25. The NAND string configuration of claim 24 , wherein all serial connections between said semiconductor memory cells are not connected to any terminals claim 24 , so that only said select gate drain device and said select gate source device are connected ...

MEMORY ARRANGEMENT

A memory arrangement having a memory cell array, wherein each column is associated with a bit line and each row is associated with a word line, wherein the columns have first columns of memory cells that store useful data, and columns of memory cells of a second column type that store prescribed verification data, wherein during a read access operation the memory cells of at least the columns of memory cells of the second column type set the associated bit line to a value that corresponds to a logic combination of the values stored by the memory cells of the column of the second column type that belong to rows of memory cells addressed during the read access operation, and a detection circuit that is configured to, during a read access operation, detect whether a bit line associated with a column of memory cells of the second column type is set to a value that corresponds to the logic combination of values stored by memory cells of the column of the second column type of memory cells and whose values belong to different rows of memory cells. 1. A memory arrangement , comprising:a memory cell array having columns and rows of memory cells, bit lines and word lines, wherein each column is associated with a bit line and each row is associated with a word line;wherein the columns of memory cells have columns of memory cells of a first column type that are configured to store useful data, and have columns of memory cells of a second column type that are configured to store prescribed verification data;wherein the memory cells of at least the columns of memory cells of the second column type are configured, and connected to the bit lines, such that during a read access operation the memory cells of a column of memory cells set the bit line associated with the column to a value that corresponds to a logic combination of the values stored by the memory cells of the column that belong to rows of memory cells addressed during the read access operation; anda detection circuit ...