DISPLAY DEVICE

Hereinafter, with reference to the drawing objects, a preferred embodiment of the present invention examples are described as follows. Throughout the specification the same reference number are substantially the same big components. The description hereinafter, the present invention specifically associated with publicly known technology or configuration description is the subject matter of invention can be judged that a breach of haze when, description and the V-shaped substrate. In addition, components which are used in the description hereinafter specification name may ease the TdSS are controlled by the one or more database comprised of, chamber number number article component name each of the disclosed.

The present invention according to display on display device includes a glass substrate (glass substrate) part of the plastic display device are disclosed. Examples of the display device, organic light emitting display device, liquid crystal display device, is used as the enabled device electrically connected, organic light emitting display device as an example in the present invention are described as follows. It is a child node number 1 and number 2 electrode it digs up and it is a cow [tu organic light emitting display device includes a light emitting layer comprises organic material. The, number 1 number 2 supplied from an electrode and the electrons supplied from an electrode in the emissive layer the electron hole pair (exciton) - combine in the exciton is formed, messenger by energy produced bottom light self-luminous display device back state are disclosed. However the present invention according to organic light emitting display device includes a glass substrate in addition to the Y disapproval.

Hereinafter, with reference to the drawing objects, of the present invention in the embodiment describes the on-sensors other.

Figure 1 shows a schematic diagram of the organic light emitting display device also blocks degrees and, Figure 2 of a sub pixel circuit configuration example [...] indicating number 1, number 2 example Figure 3 indicating sub-pixel circuit arrangement are disclosed.

The reference also 1, organic light emitting display device is Image processing unit (10), timing number control unit (20), data driver (30), the gate driving unit (40) and display panel (50) comprises.

Image processing unit (10) is also together with a data signal supplied from the data enable signal (DE) (DATA) on outputs or the like. Image processing unit (10) includes a data enable signal (DE) in addition vertical synchronous signal, horizontal synchronizing signal and a clock signal output one or more signals are descriptions but omitting [...] shown substrate. Image processing unit (10) has a circuit board IC (Integrated Circuit) formed form.

Timing number control unit (20) includes Image processing unit (10) from data enable signal (DE) or vertical synchronous signal, horizontal synchronizing signal and a clock signal with a data signal including driving signal like LIFD (DATA).

Timing number control unit (20) a drive signal based on the gate driving unit (40) for timing the operation of gate timing number hu when it freezes (GDC) number data and drive (30) for the operation of timing data timing number (DDC) and outputs a number hu when it freezes. Timing number control unit (20) is formed in the form IC number to the circuit board.

Data driver (30) the TV receiver number control unit (20) in response to number hu when it freezes (DDC) number data timing supplied from the timing control section (20) for sampling a data signal that is supplied from (DATA) into voltage to gamma reference the latched outputs. Data driver (30) is a data signal over the data lines (DL1 - DLn) (DATA) and outputs a. Data driver (30) are in the form of IC on the substrate.

The gate driving unit (40) the TV receiver number control unit (20) in response to a gate voltage supplied from the gate timing number hu when it freezes (GDC) 30 outputs a gate signal outputs. The gate driving unit (40) and outputs a gate signal through the gate lines (GL1 - GLm). The gate driving unit (40) is shaped in the form of IC circuit device substrate or display panel (50) (Gate In Panel) gate the panel which is formed manner.

Display panel (50) the data driver (30) driving unit (40) (DATA) supplied from the data signal corresponding to and gate signals to display an Image substrate. Display panel (50) comprises the first container sub-pixels (SP).

The reference 2 also, one sub-pixels switching transistor (SW), drive transistor (DR), and organic light-emitting diode (OLED) comprising the compensation circuit (CC). Organic light emitting diode (OLED) (DR) a drive transistor formed by the drive current provided to light emitting and operate.

Switching transistor gate lines (GL1) number 1 (SW) is fed via the data lines (DL1) number 1 gate signal in response to a data signal that is fed through the capacitor (Cst) to be stored in the data voltage switching and operate. Drive transistor (DR) data stored in a capacitor (Cst) high potential and low potential power supply line (GND) power line voltage (VDD) between the drive current to flow therein. Compensation circuit (CC) (DR) like a drive transistor threshold voltage for compensating circuit are disclosed. In addition, switching transistor (SW) (DR) of the drive transistor connected to a capacitor (Cst) has a compensation circuit (CC) in an inner can.

Compensation circuit (CC) consists of one or more of the thin-film transistors and capacitors. Compensation circuit according to the configuration of the compensation method (CC) wide variety of bar, for the specific example described and dispensed to each other.

In addition, as shown in fig. 3, compensation circuit (CC) is included in addition to the complementary thin-film transistor of the sub-pixels when a particular signal or signal line for driving the power supply and power line more like multiple myelomas are included. In addition to the added signal line is sub-pixel number 1 - 1 gate line (GL1a) comprising a compensation thin film transistor for driving gate lines (GL1b) number 1 - 2 can be defined. The added power line specifying a particular node for initializing sub pixel voltage initialization (INIT) power line can be defined. However this is not limited to only one example.

On the other hand, 2 and in Figure 3 is also one of sub-pixel compensation circuit (CC) is set to one example as polyester. However, subject of compensation data drive (30) is located outside of a sub pixel when compensation circuit (CC) such as may be omitted is disapproval. I.e., one of the subpixel essentially relates to a switching transistor (SW), drive transistor (DR), organic light emitting diode (OLED) (Transistor) a capacitor and including 2T of the tree but 1C (Capacitor), compensation circuit (CC) added when 3T 1C, 4T 2C, 5T 2C, 6T 2C, 7T 2C adapted or solid material may be filled.

In addition, compensation circuit is also 2 and in Figure 3 (SW) (CC) switching transistor and a drive transistor (DR) located between shown but, on organic light emitting diode (OLED) may be positioned between the can drive transistor (DR) disapproval. Compensation circuit (CC) also is not limited to the position of structure 2 are symmetrically 3.

Figure 4 shows a plane view of the present invention number 1 in the embodiment according to organic light emitting display device and also indicating, organic light emitting display device cross-sectional drawing indicating which sub-pixels of Figure 5, Figure 6 of the present invention number 1 in the embodiment according to which data pad part indicating the plane view, Figure 7 shows a perforation I a-I ' of Figure 6 according to cross-sectional cutting are disclosed

The reference also 4, organic light emitting display device substrate (110), display unit (A/A) and the display unit (A/A) (GP) (DP) data pad part on a gate pad part having a predetermined wavelength. (A/A) disposed on the display unit has a plurality of subpixel (SP), R, G, B or R, G, B, W the full color light emitting to realize. Gate pad part (GP) is one side of the color display unit (A/A) e.g. right or disposed on the left side (not shown) extending from the gate signal line (A/A) GIP or second scan can be connected to the plurality of thin film transistors. However, only one example of the present invention includes a gate pad part (GP), data pad part carry FOG equal to film with disapproval. The data pad part (DP) display unit (A/A) extending from one side of the color (A/A) e.g. can be located under the plurality of signal line (SL) are disposed thereon. A plurality of signal line (SL) can be data line and power line, only sensing line may be filled. A plurality of signal line (SL) are attached to the data pad part (DP) FOG film (FOG) applied to communicate data over a channel.

Hereinafter, with reference to the 5 also of the present invention, organic light emitting display device of the subpixel (SP) for automobile herein disclosed.

The reference also 5, organic light emitting display device of the present invention in the embodiment according to number 1 on one substrate (SUB) buffer layer (BUF1) located therein. Substrate (SUB) consisting of glass (glass). (BUF1) buffer layer number 1 substrate (SUB) from impurities such as alkali ion from flowing out into a thin film transistor formed and protecting could be bonded each other. A buffer layer of silicon (SiOx) number 1 (BUF1), silicon nitride (SiNx) or multiple-seed layer disclosed.

Number 1 (LS) shield layer on the buffer layer (BUF1) is the lungs. The shield layer (LS) light incident from outside the gate line could be bonded each other to prevent leakage current occurs. Shield layer (LS) number 2 on buffer layer (BUF2) located therein. The shield layer (LS) number 2 buffer layer (BUF2) from impurities such as alkali ion from flowing out into a thin film transistor formed and protecting could be bonded each other. Silicon buffer layer (BUF2) number 2 (SiOx), silicon nitride (SiNx) or multiple-seed layer disclosed.

(BUF2) number 2 buffer layer on semiconductor layer (ACT) located therein. (ACT) can be silicon semiconductor layer is an oxide semiconductor. Silicon semiconductor amorphous silicon crystal can be polycrystalline silicon. Wherein, polycrystalline silicon is mobility and high (100 cm2/Vs or more), low in power consumption energy has excellent reliability, driver and/or multiplexer (MUX) gate drive element in driving TFT can be applied to applied to except a. On the other hand, oxide semiconductor selected from off - current, on (On) signal from off (Off) suitable application in which a time switching TFT. In addition, off current slow drive and/or low power consumption in small pixel voltage retention complete requiring suitable display device. In addition, edge of the semiconductor layer (ACT) p or n channel transistor includes a floating gate electrode has an including therebetween comprising.

A gate insulating film (GI) semiconductor layer (ACT) is the lungs. A gate insulating film of silicon (GI) (SiOx), silicon nitride (SiNx) or multiple-seed layer disclosed. A gate insulating film on said semiconductor layer a predetermined region (GI) (ACT), i.e. that the gate electrode when impurities are implanted into channels (GA) is the lungs. The molybdenum (Mo) gate electrode (GA), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) alloy selected from the group consisting of one or both of formed. In addition, the molybdenum (Mo) gate electrode (GA), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) alloy selected from the group consisting of one or both of multi-seed layer disclosed. For example, neodymium or molybdenum/aluminum/molybdenum gate electrode (GA)- 2 be a oxidation-reduction is of aluminum.

Gate electrode (GA) (GA) gate electrode on the insulating interlayer dielectric (ILD) is the lungs. The interlayer dielectric (ILD) silicon oxide (SiOx), silicon nitride (SiNx) or multiple-seed layer disclosed. Interlayer dielectric (ILD) (GI) through the bottom part of the gate electrode contact hole exposing a portion of the semiconductor layer (ACT) (CH) is the lungs.

Interlayer dielectric (ILD) drain electrode (DE) on point (SE) is the lungs. Drain electrode (DE) through a contact hole exposing a drain region of semiconductor layer (ACT) (CH) connected to the semiconductor layer (ACT), a source electrode (SE) through a contact hole exposing the source region of the semiconductor layer (ACT) (CH) semiconductor layer (ACT) coupled with each other. A source electrode and a drain electrode (DE) (SE) and can be single layer or multi-layer, said source electrode and a drain electrode (DE) molybdenum (Mo) in the case where the single (SE), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) can be selected from the group consisting of one or both of alloy. In addition, said source electrode and a drain electrode (SE)- 2 in the case where the molybdenum/aluminum neodymium (DE) multi-layered, titanium/aluminum/titanium, molybdenum or molybdenum/aluminum/molybdenum/aluminum/molybdenum can be an oxidation-reduction property of neodymium - 3.

The, semiconductor layer (ACT), gate electrode (GA), including thin film transistor (TFT) is consists of a drain electrode (DE) and source electrode (SE).

The passivation layer including a thin film transistor (TFT) on a substrate (SUB) (PAS) is the lungs. (PAS) passivation layer including a first diode to the buried oxide layer, silicon oxide (SiOx), silicon nitride (SiNx) or multiple-seed layer disclosed. An overcoat layer on the passivation layer (PAS) (OC) is the lungs. Overcoat layer (OC) for applanating a lower step of the main, polyimide (polyimide), benzo gap claw issue [thin total resin (benzocyclobutene series resin), acrylate (acrylate) consisting of lamp of. The overcoat layer (OC) SOG (spin on glass) coating said organic matter in liquid form and then curing method such as can be formed.

Overcoat layer (OC) (DE) (VIA) via hole exposing part of the gate is the lungs. (OC) organic light-emitting diode (OLED) on the overcoat layer is the lungs. More particularly, electrode on the overcoat layer (OC) number 1 (ANO) located therein. The detecting electrode number 1 (ANO) act, drain electrode of the thin film transistor through the via hole (VIA) (DE) (TFT) coupled with each other. The ITO electrode number 1 (ANO) PMOS regions (Indium Tin Oxide), IZO (Indium Zinc Oxide) or ZnO (Zinc Oxide) before material such as transparency can be. (ANO) number 1 electrode when the reflective electrode, the reflective layer further comprises electrode number 1 (ANO). The reflective layer (Al) aluminum, copper (Cu), is (Ag), nickel (Ni) or an alloy thereof can be made, preferably APC (is/palladium/copper alloy) can be made.

(SUB) number 1 (ANO) substrate including a pixel electrode defining a bank layer (BNK) is located on the substrate. Bank layer (BNK) polyimide (polyimide), benzo gap claw issue [thin total resin (benzocyclobutene series resin), acrylate (acrylate) consisting of lamp of. The bank layer (BNK) exposing electrode number 1 (ANO) pixel definition part (OP) is the lungs. (BNK) pixel definition part number 1 (ANO) (OP) bank layer is light-emitting layer (EML) contact to electrode located substrate. The light-emitting layer emit light (EML) electron binding layer, light emitting layer (EML) and number 1 can be a chemical formula or hole injection layer between the electrode (ANO) comprising, on the light emitting layer (EML) comprising metal-containing fullerene or injecting layer can be.

Light emitting layer (EML) number 2 on electrode (CAT) located therein. The display (A/A) number 2 electrode (CAT) to exchange, the workfunction of a cathode electrode low magnesium (Mg), calcium (Ca), aluminum (Al), is (Ag) or an alloy thereof can be made. (CAT) electrode number 2 is the transmissive electrode when a jacket is composed of a thin holes, when the reflective electrode consisting of a jacket thickness can be reflective.

On the other hand, organic light emitting display device of the present invention data pad part of carefully the residual as follows.

<Number 1 in the embodiment>

6 Also reference surface, a display part on substrate (SUB) (A/A) (VL1, VL2, VL3, VL4, VL5) are extending from the plurality of power line is disposed, (VL1, VL2, VL3, VL4, VL5) some of the plurality of power line at the beginning and end pad hole (PCH) are each coupled through electrode power supply pads (VPE1, VPE2) disposed thereon. (VL1, VL2, VL3, VL4, VL5) and a plurality of power line extending from between a plurality of data line of the display unit (A/A) (DL1, DL2, DL3, DL4, DL5 provided DLn) are disposed, (DL1, DL2, DL3, DL4, DL5 provided DLn) a plurality of data line data at the beginning and end of each through hole (DCH) connected by wires and data pad electrode (DPE1 provided DPEn) are disposed thereon. (VL1, VL2, VL3, VL4, VL5) are plurality of power line (VL1, VL2, VL3, VL4, VL5) is divided into a plurality of power line disposed bridge electrode (LSP) by contact respectively connected thereto.

More carefully, 7 also reference surface, substrate (SUB) number (BUF1) located on the buffer layer, the buffer layer (BUF1) number 1 (LSP) bridge electrode on the lungs. The bridge electrode (LSP) shield layer having sub-pixel is situated on the same layer consists of the same. Bridge electrode (LSP) number 2 on buffer layer (BUF2) located therein. The plurality of holes with a bridge electrode part number 2 buffer layer (BUF2) (LSP) to expose the substrate. A gate insulating film (GI) number 2 buffer layer (BUF2) is the lungs. The gate insulating film with a plurality of holes (GI) part number 2 buffer layer (BUF2) (LSP) the bridge electrode exposed through the exposed substrate. A gate insulating film on the first oxide layer (ILD) (GI) is the lungs. The interlayer dielectric (ILD) portion of the gate electrode with a plurality of holes (GI) number 2 buffer layer (BUF2) bridge electrode (LSP) exposed by the exposing the substrate. These number 2 (BUF2) buffer layer, a gate insulating film (GI) and insulating interlayers (ILD) (LSP) so that bridge electrode consists of exposing the hole is to bridge hole (VCH1).

A plurality of power line (VL1, VL2) interlayer dielectric (ILD) (DL1, DL2, DL3, DL4, DL5) and a plurality of data line is the lungs. The plurality of power line (VL1, VL2) (VCH1) (LSP) through bridge electrode bridge hole respectively contact in order to connect electrically with each other. In the present invention (DL1, DL2, DL3, DL4, DL5) bridge electrode (LSP) data drivers for preventing short circuit between, number 2 buffer layer (BUF2) therebetween, a gate insulating film formed mp3. margin (GI) and insulating interlayers (ILD).

A plurality of power line (VL1, VL2) (DL1, DL2, DL3, DL4, DL5) and a plurality of data line on the passivation layer (PAS) located within the data pad part (DP) constituting other. Figure 7 shows a (VL1, VL2, VL3, VL4) during one electric power source line also in Figure 6 4 2 (VL1, VL2) in cross section are described by corresponding to one electric power source line. However, other power line drawing (VL3, VL4, VL5) do not appear (LSP) are also bridge electrode coupled with each other.

6 Also again reference surface, causes the line of the present invention number 1 in the embodiment 5 (VL1, VL2, VL3, VL4, VL5) exposed one electric power source for at least one bridge electrode (LSP) (VL1, VL2, VL3, VL4, VL5) one electric power source line 5 and are both ends of one electric power source line (VL1, VL5) among 2 respectively (VPE1, VPE2) was disclosure as having a power pad electrode. I.e., 5 (VL1, VL2, VL3, VL4, VL5) one electric power source line electrode and both ends of each power supply pads not having a pad electrode connected to one electric power source 2 (VPE1, VPE2), power supply pads 2 can be formed as separated at the lower electrode 5. The present invention refers to one power line circuit includes a pad electrode structure with alternatively, fewer than the number of plurality of power line power line electrode power supply pads with a disclosure as follows. The, power pad electrode exposed to area (MA) as there are power supply pads of pad electrodes or data electrodes can be increasing pitch.

(VL1, VL2, VL3, VL4, VL5) 5 of the present invention in the embodiment one electric power source line in one bridge electrode (LSP) located one electric power source line (VL1, VL5) 2 end and both connected to each power pad electrodes (VPE1, VPE2) the locking arm to go up. However, only a portion of the portion shown in the drawing and, likewise not shown one electric power source line one bridge electrode 5 remaining nodes are coupled with each other. In addition, the present invention refers to 5 each one bridge electrode one electric power source line to which a cache but, do not limited to at least two power line coupled each one bridge electrode may be filled. In addition, one bridge electrode is electrically connected to at least one plurality of power lines are 1 insulating layer electrode disapproval.

<Number 2 in the embodiment>

Figure 8 shows a plane view indicating which data pad part of the present invention number 2 in the embodiment according to also, Figure 9 shows a perforation II a-II ' of Figure 8 cross cutting according are disclosed.

8 Also reference surface, a display part on substrate (SUB) (A/A) (VL1, VL2, VL3, VL4, VL5) are extending from the plurality of power line is disposed, (VL1, VL2, VL3, VL4, VL5) some of the plurality of power line at the beginning and end pad hole (PCH) are each coupled through electrode power supply pads (VPE1, VPE2) disposed thereon. (VL1, VL2, VL3, VL4, VL5) and a plurality of power line extending from between a plurality of data line of the display unit (A/A) (DL1, DL2, DL3, DL4, DL5 provided DLn) are disposed, (DL1, DL2, DL3, DL4, DL5 provided DLn) a plurality of data line data at the beginning and end of each through hole (DCH) connected by wires and data pad electrode (DPE1 provided DPEn) are disposed thereon.

(VL1, VL2, VL3, VL4, VL5) are plurality of power line (VL1, VL2, VL3, VL4, VL5) is divided into a plurality of power line disposed bridge electrode (LSP) by contact respectively connected thereto. (DL1, DL2, DL3, DL4, DL5 provided DLn) of the present invention in the embodiment the pluralities of data line (DL2, DL3, DL4) each data line between some of the further auxiliary electrode (VAE) with each other.

More carefully, the reference also 9, substrate (SUB) number (BUF1) located on the buffer layer, the buffer layer (BUF1) number 1 (LSP) bridge electrode on the lungs. The bridge electrode (LSP) shield layer having sub-pixel is situated on the same layer consists of the same. Bridge electrode (LSP) number 2 on buffer layer (BUF2) located therein. The plurality of holes with a bridge electrode part number 2 buffer layer (BUF2) (LSP) to expose the substrate. A gate insulating film (GI) number 2 buffer layer (BUF2) is the lungs. The gate insulating film with a plurality of holes (GI) part number 2 buffer layer (BUF2) (LSP) the bridge electrode exposed through the exposed substrate. A gate insulating film on the first oxide layer (ILD) (GI) is the lungs. The interlayer dielectric (ILD) portion of the gate electrode with a plurality of holes (GI) number 2 buffer layer (BUF2) bridge electrode (LSP) exposed by the exposing the substrate. These number 2 (BUF2) buffer layer, a gate insulating film (GI) and insulating interlayers (ILD) so that bridge electrode (LSP) (VCH1) and auxiliary (VCH2) consists of exposing the hole is bridge hole to hole.

A plurality of power line (VL1, VL2) interlayer dielectric (ILD), (DL1, DL2, DL3, DL4, DL5) a plurality of data line and an auxiliary electrode (VAE) are located therein. The plurality of power line (VL1, VL2) (VCH1) (LSP) through bridge electrode bridge hole respectively contact in order to connect electrically with each other. Auxiliary electrode (VAE) are auxiliary hole (VCH2) (LSP) through each contact to bridge electrode electrically connected thereto. The power line (VL1, VL2) such as auxiliary electrode (VAE), (DL1, DL2, DL3, DL4, DL5) on the same layer with a plurality of data line to the lungs. A plurality of power line (VL1, VL2), (DL1, DL2, DL3, DL4, DL5) a plurality of data line and an auxiliary electrode on the passivation layer (PAS) located within the data pad part (DP) (VAE) constituting other.

The reference also 6 again, in the present invention the first power line (VL1) number (LSP) bridge electrode located one right and one left number five (VL5) located th power line voltage is for applying reduced voltage from a third power line located among (VL3). Thus, in the present invention auxiliary electrode (VAE) (LSP) by further electrically connected with the electrode bridges, bridge electrode (LSP) prevent voltage can be reduced.

<Number 3 in the embodiment>

Figure 10 shows a plane view and also indicating the data pad part of the present invention number 3 in the embodiment according to, Figure 11 shows a perforation III a-III ' cross cutting according of Figure 10 are disclosed.

10 Also reference surface, a display part on substrate (SUB) (A/A) (VL1, VL2, VL3, VL4, VL5) are extending from the plurality of power line is disposed, (VL1, VL2, VL3, VL4, VL5) some of the plurality of power line at the beginning and end pad hole (PCH) are each coupled through electrode power supply pads (VPE1, VPE2) disposed thereon. (VL1, VL2, VL3, VL4, VL5) and a plurality of power line extending from between a plurality of data line of the display unit (A/A) (DL1, DL2, DL3, DL4, DL5 provided DLn) are disposed, (DL1, DL2, DL3, DL4, DL5 provided DLn) a plurality of data line data at the beginning and end of each through hole (DCH) connected by wires and data pad electrode (DPE1 provided DPEn) are disposed thereon.

(VL1, VL2, VL3, VL4, VL5) are plurality of power line (VL1, VL2, VL3, VL4, VL5) is divided into a plurality of power line disposed bridge electrode (LSP) by contact respectively connected thereto. (VL1, VL2, VL3, VL4, VL5) can cause some of the pluralities of power line of the present invention in the embodiment power line (VL1, VL2, VL4, VL5) are 2 consisting of one or more patterns.

More carefully, 11 also reference surface, substrate (SUB) number (BUF1) located on the buffer layer, the buffer layer (BUF1) number 1 (LSP) bridge electrode on the lungs. Bridge electrode (LSP) number 2 on buffer layer (BUF2) located therein. The plurality of holes with a bridge electrode part number 2 buffer layer (BUF2) (LSP) to expose the substrate. A gate insulating film (GI) number 2 buffer layer (BUF2) is the lungs. The gate insulating film with a plurality of holes (GI) part number 2 buffer layer (BUF2) (LSP) the bridge electrode exposed through the exposed substrate. A gate insulating film on the first oxide layer (ILD) (GI) is the lungs. The interlayer dielectric (ILD) portion of the gate electrode with a plurality of holes (GI) number 2 buffer layer (BUF2) bridge electrode (LSP) exposed by the exposing the substrate. These number 2 (BUF2) buffer layer, a gate insulating film (GI) and insulating interlayers (ILD) (LSP) so that bridge electrode consists of exposing the hole is to bridge hole (VCH1).

Interlayer dielectric (ILD) number 1 and number 2 (VL1) on power line power line power line pattern of pattern (VLP1) (VLP2) located therein. Number 1 and number 2 power line power line pattern (VLP1) (VCH1) (LSP) through the bridge hole pattern (VLP2) bridge electrode respectively contact in order to connect electrically with each other. (VL1) and power line (PAS) is located on the passivation layer, the passivation layer (PAS) (VL1) number 2 of some voltages of power line is exposing the pad hole pattern (VLP2) (PCH) combined with each other. Pad hole (PCH) (VPE) located within the power line (VL1) number 2 of electrode power supply pads on power line pattern (VLP2) coupled with each other.

The reference 10 and 11 also together, the display (A/A) located adjacent to the first power line (VL1) power line pattern (VLP1) number 1, number 2 (VPE1) positioned adjacent to the pad electrode and power supply comprises a power line pattern (VLP2). Number 1 and number 2 power line pattern (VLP1) (VLP2) builds up a bridge electrode (LSP) the power line pattern connecting the being separated from one another even if electrical connected thereto. Number 1 and number 2 power line pattern (VLP1) located at a distance of each other to adjust power line pattern (VLP2), bridge electrode number 1 (LSP) and by reducing the output voltage of the first power line (VL1) [khen area of power line pattern (VLP1) can be control.

In addition, the display (A/A) (VL2) integral with a second power line power line pattern (VLP1) number 1, number 2 (VLP2) power line pattern comprises adjacent substrate (SUB) end. Number 1 and number 2 power line pattern (VLP1) (VLP2) builds up a bridge electrode (LSP) the power line pattern connecting the being separated from one another even if electrical connected thereto. Number 1 and number 2 power line pattern (VLP1) located at a distance of each other to adjust power line pattern (VLP2), bridge electrode number 1 (LSP) and by reducing the output voltage of the second power line (VL2) [khen area of power line pattern (VLP1) can be control.

As aforementioned, the first power line (VL1) number (LSP) bridge electrode located one right and one left number five (VL5) located th power line voltage is for applying reduced voltage from a third power line located among (VL3). Thus, the power source of the present invention in the embodiment applied (VL1) differ from the resistance of the first power line and a third power line the front and five power line (VL5) centrally located (VL3) etching has a meshed structure. To this end, power is applied (VL1) and five first power line power line power line power line number 1 and number 2 in th (VL5) pattern (VLP1) (VLP2) furthest from the rest contact in contact resistance pattern formed much barrier film. And, power line and a second power line (VL2) differ from the number 1 and number 2 (VL4) you in power line pattern (VLP1) distance (VLP2) power line pattern of the dielectric layer to contact area relatively less reducing relatively slightly resistance barrier film. (VL3) may then holds the third located among power line. I.e., power lines with number 1 and number 2 (LSP) bridge electrode contact area adjustment is power line pattern (VLP1) power line pattern (VLP2) or increase the distance between the spaced apart by reducing the control substrate. The, voltage is applied (VL1) one right and one left number located first power line number five (VL5) th power line located from third power line voltage from a power line bridge electrode (VL3) furthest delivered (LSP) contact area can be smaller than the width of the thin film transistor.

Of the present invention number 3 in the embodiment applied a voltage from the first power line (VL1) number one right and one left number located located five doors above the output voltage of the second power line (VL5), th (VL2, VL3, VL4) output voltage of third and four power line can be similar to control. The pixel emission luminance of a display unit (A/A) each subset of the support member can be copyright 2001.

<Number 4 in the embodiment>

Figure 12 shows a data pad part of the present invention number 4 in the embodiment according to indicating plane also are disclosed.

The reference also 12, a display part on substrate (SUB) (A/A) (VL1, VL2, VL3, VL4, VL5) are extending from the plurality of power line is disposed, (VL1, VL2, VL3, VL4, VL5) some of the plurality of power line at the beginning and end pad hole (PCH) are each coupled through electrode power supply pads (VPE1, VPE2) disposed thereon. (VL1, VL2, VL3, VL4, VL5) and a plurality of power line extending from between a plurality of data line of the display unit (A/A) (DL1, DL2, DL3, DL4, DL5 provided DLn) are disposed, (DL1, DL2, DL3, DL4, DL5 provided DLn) a plurality of data line data at the beginning and end of each through hole (DCH) connected by wires and data pad electrode (DPE1 provided DPEn) are disposed thereon.

(VL1, VL2, VL3, VL4, VL5) are plurality of power line (VL1, VL2, VL3, VL4, VL5) is divided into a plurality of power line disposed bridge electrode (LSP) by contact respectively connected thereto. The bridge electrode (LSP) of the present invention in the embodiment of bridge comprising a plurality of opening multiple (OPP) (BRP) effected.

More carefully, bridge electrode (LSP) and a plurality of data lines (DL1 provided DLn) where multiple lines in the first plurality of openings (OPP) of bridge (BRP) is the lungs. A plurality of bridge sections (BRP) and a plurality of opening (OPP) comprises a plurality of data lines (DL1 provided DLn) direction transverse to the axis perpendicularly disposed thereon. A plurality of bridge sections (BRP) and a plurality of opening (VL1, VL2, VL3, VL4, VL5) (OPP) comprises a plurality of power line disposed thereon are positioned. Bridge electrode (LSP) with multiple apertural areas (OPP) and a plurality of bridge (BRP) is short occurs with the data line repair apparatus configuration when they are disclosed. For example, a first power line and a second power line (VL2) (VL1) between a plurality of data lines (DL1 provided DLn) with any one of a bridge electrode (LSP) the short the, which are bridged by a different power line voltage of the power supply electrode (LSP) shot is not supplying. Thus, in the present invention includes a plurality of bridge sections (BRP) and short upon any one data line, a stand-alone mode so that a corresponding bridge (BRP) disconnected and the other bridge (BRP) number short laser amplifier is transmitted to a substrate. Therefore, the bridge electrode (LSP) of the present invention number 4 in the embodiment (BRP) having opening (OPP) on the bridge, bridge electrode (LSP) can improve the reliability of actuation by a short and prevent.

The aforementioned of the present invention number 1 to number 4 in the embodiment are various data pad part indicating the structure of but, in the embodiment of the present invention number 1 to number 4 in the embodiment are each them each other disclosure disclosure or these can be combined. For example, number 2 in the embodiment structure and power line structure are number 3 in the embodiment can be combined, as well as bridges electrode structures are number 3 in the embodiment can be combined.

On the other hand, number 1 in the embodiment of the present invention 6 also shown in fig. 13 according to voltage of the power line data pad part of structure of measuring has been shown, also 10 number 3 in the embodiment shown in fig. 14 according to measuring the voltage of the power line data pad part of structure shown.

13 Figure 14 of the present invention number 3 in the embodiment of effectiveness and also implemented for certification of reduced power line voltage to effect the simulation result are disclosed. The reference also 13, power supply voltage and power line 5 is applied a voltage from the power line 1 23. 45V exhibits a, transmitted via the bridge voltage power line 2, 3, and 4 is constructed by 23 illuminates a lowest voltage. 3V exhibits. I.e., highest voltage 23. 45V on resistor 23. 3V value between 0. 15V exhibits. While, the reference also 14, power supply voltage and power line 5 is applied a voltage from the power line 1 23. 37V exhibits a, transmitted via the bridge voltage power line 2, 3, and 4 is the lowest 23. 29V exhibits. I.e., highest voltage 23. 37V on resistor 23. 29V value between 0. 07V exhibits.

Through the result, the output voltage of the power lines and power-lines of the present invention number 3 in the embodiment resistance of the surfaces can be cylindrical.

Such as said, in the embodiment according to display device includes a bridge electrode of the present invention one of a plurality of power line power line by fewer than insulating layer electrode, power pad electrode exposed area as field power supply pads of pad electrodes or data electrodes can be increasing pitch. The, uniform-pitch pad electrodes can occur short-circuited can be prevented such as copyright 2001. In addition, the present invention refers to bridge the plurality of the first data lines insulating layer is formed, the first data bridge device preventing short circuit between lines can be copyright 2001.

In addition, in the embodiment according to display device of the present invention is included in the voltage transmitted through each of the bridge electrode can prevent copyright 2001. In addition, power line bridge electrode contact and the liquid, and the output voltage of the power line voltage is applied between a power line and the unlicensed copyright 2001 can be uniform. In addition, in the embodiment according to display device includes a bridge electrode by forming a bridge one of the present invention, bridge the first data line of shot regions even if copyright 2001.

Thus, in the embodiment according to display device of the present invention is to prevent one capable of actuation by a short and improves reliability.

The device of the present invention to such an extent that it departs from the content feature if one skilled through various modified can be connected can be ascertained not alter it will rain. The, technical range of the present invention a content specification description are limited to patent the following is claimed but should be defined by will.