[Title of the invention] Semiconductor integrated circuit device and manufacturing method [Brief explanation of the drawings] Number 1 or number 3 degrees to represent one embodiment of the present invention each pattern plane view. Number 4 or conventional pattern of device is plane view. Description of the sign for major part * of the drawings 2 wiring layer 1: number 1 : number 2 wiring layer 3, 31, 32: connection hole 4, 41, 42: dummy line 5: cell 51: dedicated cell 6, 7: internal power supply wiring 8 : [...] 11:12, 22 cuts: additional wiring 131, 132, 21: wiring [Detailed description of the invention] [During industrial applications] The present invention refers to semiconductor integrated circuit having a dummy line device and manufacturing method relates to, in particular standard pherocene this held gate error method has the second wiring such as made by semiconductor pipe of multiple layers. for use in integrated circuits. [Of the existing method technique and the resulting problem] Conventional, types of method 2 of the dummy line been used hereinafter. First a, wiring density within wiring layer same other interlocking with in apparatus of subscriber on a density difference of a wiring of the step by prevention and a wide range can be two 1 wiring is [...]former cutting wiring is erode away ([...] loading) are prevented from being loading effect to cope with a dicing device is provided with a dummy line (Japanese patent disclosure bovine 60-119749 call). A second, dummy line using the modifying a reproduces, modified target only a specified wiring Image signals input from the outside is layer, a semiconductor device the dummy line, the portable telephone sends modification using (Japanese patent disclosure bovine 59-198796 call, Japanese patent disclosure bovine 61-125045 call, call 62-206855 bovine patent disclosure Japanese). Number 4 or with dummy line of the existing method to pattern of an integrated circuit, a plane view, references 1 the number 1 wiring layer, the number 2 wiring layer 2, the connection hole (contact hole) 3, the dummy line 4, the cell 5 (constitution: an adjustable current stand dozen the method which it will count formed of wet liquid to flow down fix). 6 is an internal power supply (VDD) wiring, 7 is an internal power supply (VSS) wiring, [...] is the 8. The dummy line of the existing method, and preventing stepped difference between doors and a apparatus of subscriber to cope loading effect or provided, for modifying a five it wired when using a case of using the first method was the PMOS transistor. Said loading effect and preventing stepped difference between doors and a apparatus of subscriber to cope: after forming a, , as shown on the first aluminum layer to the number 4 installing a dummy line (4) width of after the tailored to an installation location, the mobile has a means for change. To this end, having a non-constant width of dummy line part even in the case, for purposes other than thereof is never used in tower-mounted dummy line thing cancer was may with only once. Also, in the case where the using modifying a reproduces, dummy line Image signals input from the outside previously installed the second semiconductor integrated circuit manufacturing highly when the head cannot reach a modified using dummy line for this by not link the above-mentioned also used to prevent its contacted with the lower as well as when only tower-mounted dummy line there was a problem that the unit assists the main control unit. [Purpose of the invention] The present invention refers to said inputted into an analog multiplexer been made to, provided in the interior of the dummy line voltage stabilizing power, wiring for repairing an active matrix substrate, , delay correction according a semiconductor integrated circuit device manufacturing method and heat exchanger. is provided to. [Constitution of the invention] Said end of the semiconductor integrated circuit of the present invention a device, the semiconductor substrate, potential is supplied to the substrate, the semiconductor substrate formed a plurality of cells, a plurality of base station controllers to reduce the number of [...] and, by refrigerant delivered from the lower stage said implanted into the semiconductor substrate by said substrate potential and other which a potential forming a semiconductor integrated circuit having a power supply interconnection in device, said it will count, between with wiring same width and the same wiring pitch formed dummy line, and said said dummy wirings are connected the power supply interconnection further comprises a dedicated cell is characterized in that the. Also, the manufacturing method of semiconductor integrated circuit device of the present invention, the semiconductor substrate, potential is supplied to the substrate, the semiconductor substrate formed a plurality of cells, a plurality of base station controllers to reduce the number of [...] , by refrigerant delivered from the lower stage said implanted into the semiconductor substrate by said substrate potential and other potential is supplied to the power supply lines, said it will count, between with wiring same width and the same wiring pitch formed dummy line and, said power supply interconnection dummy wirings are connected the and a dedicated cells a step of preparing a semiconductor integrated circuit device, said dummy line selectively by severing an in-said dummy line said energy mode and for electrically isolating the supply wiring, process and, said dummy line said plurality of cells with step of reacting a carboxylic acid component connection is characterized in that the. Also, the manufacturing method of semiconductor integrated circuit device of the present invention, the semiconductor substrate, potential is supplied to the substrate, the semiconductor substrate formed a plurality of cells, a plurality of base station controllers to reduce the number of [...] , by refrigerant delivered from the lower stage said implanted into the semiconductor substrate by said substrate potential and other potential is supplied to the power supply lines, said it will count, between with wiring same width and the same wiring pitch formed dummy line and, said power supply interconnection and said dummy wirings are connected a dedicated the semiconductor integrated circuit cells a step of preparing a device, said dummy line selectively by severing an in-said dummy line said energy mode and for electrically isolating the supply wiring, process and, said dummy line said [...] selectively coupling the process is characterized in that the with. [Action] The present invention refers to said groove, and at least one, e.g. multilayer structure semiconductor integrated circuit in by the cell internal power supply connected to dummy line and, this dummy wiring an integrated circuit and by capacitor is formed between, internal power supply voltage the sway of a stable voltage in the integrated circuit apparatus is to supply. Yet, said dummy line it will count, between with wiring same width and the same wiring pitch is removed by reacting the sacrificial, wiring for repairing an active matrix substrate, , signal delay of correction is enabled. As a result, internal power supply, dummy wiring internal power supply electrically from by by using the, rear of the modified by shortening processes, is enabled. [In the embodiment] Hereinafter, the described thereby, the cold air flows of the present invention 1 embodiment by referring to a drawing. Number 1 or 1 embodiment but the first deoxygenator pattern plane view, the number 4, in this case, the help and a portion corresponding to the since the to the same references by the friction with the explanation which, which does not require a, to illustrate the only point characterized by time as large as that of. I.e., the present embodiment the first deoxygenator characterized by dummy line (4) the [...] (8) and the same wiring width [...] formed in each of pitch endorsement (8) is electrically connected with the wiring layers same without is provided. Number 1 in the dummy line (4) an internal power supply display is an example used for the sake of. In the present in the embodiment, provided all dummy line (4) the connection hole (3) for use in mediating an of the substrate potential (VDD) internal power supply reverse from (VSS) wiring (7) is connected to the. Also, dummy line (4) and the internal power supply voltage in (VSS) wiring (7) connection connecting openings on dedicated cell for (51) using of wet liquid to flow down. Dedicated cells (51) lowest in ten which it will count 1 (layout) when the pattern forming the included. when the DAC receives a grayscale voltage. Also, a semiconductor integrated circuit is the pads of the, the above-mentioned power a dummy wiring to be used for display (4) power supply interconnection therein (7) electrically from cutting the using for modifying a. is capable of being. The wiring for fertilization using dummy line at a moment when a described a number 2. An a suitable length modifying a defective portion in the vicinity of dummy line (4 ; same 41 together with audience rating) motion compensated frame interpolation, select a, salt therein power (VSS) wiring (7) electrically from by severing an in-cuts (11) by forming a structure of wiring (41) a is created. Next, wiring connected wrong (81) for electrically isolating the, original jetting condition is appropriately controlled to connected the above-mentioned structure of wiring (41) and newly added to the wiring (12) and connection hole (31) so as to drive the word to. The, is a long wiring modifying a plurality of dummy if needed the wirings are connected the. can be used in the form. They are not being used for fertilization the dummy line (4) substrate potential chip all (VDD) great man reverse from internal power supply (VSS) wiring (7) book welded part in a state of being connected to. Yet, power supply interconnection therein dummy line (7) electrically from of internal circuits by severing an in-signal delay correction for. can be used in the form. Using dummy line to delay correction is examples described a at number 3. E.g., wants to connect to a burn-in according to delay output (21) suitable delay correction in the vicinity a length of the dummy line (4 ; same 42 together with audience rating) motion compensated frame interpolation, select a, salt therein power endorsement (7) electrically from by severing an in-cuts (11) is carried out by installing a delay correction wiring (42) a is created. Next, correction created by the wiring (42) output of with logic (21) is newly added to the wiring (22), connection hole (32) so as to drive the word to. Adjustment of delay time is connected to dummy line (42). is made by adjusting appropriately length wiring. Delay correction is installed at a dummy wiring (4) all potential readable chip (VDD) great man reverse from internal power supply (VSS) wiring (7) is connected to. Said embodiment according to the example, a chip dummy line such help number 1 substrate potential of reverse from great man internal power supply wiring (7) to and integrated circuit substrate by connecting the dummy line (4) capacity is formed between, the capacity the first internal power supply wiring (7) connected to internal power supply voltage by preventing the shaking arrester is combined oil to produce a stable voltage in the integrated circuit apparatus is enabled. Also, dummy line [...] (8) the same width as the width, a wiring forming pitch the same time by for repairing an active matrix substrate, formed, even if the delay correction is enabled. Wiring for modifying a: after forming a, on the first aluminum layer to the number 2 power supply interconnection as, as shown (7) connected to internal power supply dummy line by using electrically from easily avoided by being improved the working sodium citrate dehydrate for buffering effect, it is possible to includes a bolt and a, they are not being used for fertilization also the dummy line is an internal power supply wiring (7) power is connected to is to display. Yet, number 3 help when the use in delay correction such as, additional new and conventional the cell pattern forming each order to the n bit parallel data inputted must again from, and essentially all of data is performed for mask fabrication method to produce TCC in again from a deck unit easily although plural, the present invention by dummy line (42) for adding cells by using a and need not be, modified data is performed for mask fabrication method to produce TCC in result for use in a of data after an wiring layer that is again it will dance only process transfers heat to the. member is installed. Delay correction is installed at a the dummy line is an internal power supply wiring (7) internal power supply is connected to is to display. Also, by the present invention by mounting a dummy line within wiring layer same uniform than when each of only [...] density wiring in and that makes it possible to to, wiring a density difference of a on reducing a step of a device is enabled. Furthermore, a wide range can be two 1 wiring is, the wiring being cut out at the erosion [...] coverage loading effect even for dummy line (4) is provided the same time by density of the outgoing light of and effectively since is emitted from the emission. Furthermore, the present invention refers to the present embodiment is not limited aspect. application various indicia. E.g., the present in the embodiment the present invention to an integrated circuit by a in the method which it will count standard in applying but, basic cells gate array manner the integrated circuit-proof packing. to be capable of application to the present invention. While, a data section results in a reference weapon requirements includes all of control of the present invention patent the following is claimed a to facilitate understanding of the present invention for, drawing reach techniques of the present invention shown in embodiment aspect weapon in concrete terms, define the not. [Effect of the invention] As taught or more according to the present invention, with several dummy line can be use in the and the shortening of process; a, unit reduce manufacturing costs, yet the active area of. is reduced. Copyright 1997. Substrate power (VDD) the semiconductor substrate, is supplied, the semiconductor substrate formed a plurality of cells (5), a plurality of cell (5) [...] the each of the electrode pads (8) and, by refrigerant delivered from the lower stage implanted into the semiconductor substrate by said substrate potential said (VDD) and the other potential (VSS) power supply interconnection which is supplied with (7) in semiconductor integrated circuit having a device, said [...] (8) the same width as the width and the same wiring pitch the PCB by forming a dummy wiring (4) and, said power supply interconnection (7) and said dummy line (4) dedicated cell for connecting (51) to of characterized by semiconductor integrated circuit device. Substrate potential (VDD) the semiconductor substrate, is supplied, the semiconductor substrate formed a plurality of cells (5), a plurality of cell (5) [...] the each of the electrode pads (8), by refrigerant delivered from the lower stage implanted into the semiconductor substrate by said substrate potential said (VDD) and the other potential (VSS) power supply interconnection which is supplied with (7), said [...] (8) the same width as the width and the same wiring pitch the PCB by forming a dummy wiring (41) and, said power supply interconnection (7) and said dummy line (41) dedicated cell for connecting (51) semiconductor integrated circuit having a a step of preparing a device, said dummy line (41) selectively by severing an in-said dummy line (41) and said power supply interconnection (7) for electrically isolating a process and, said dummy line (41) and said plurality of cells (5) for connecting to with process characterized by manufacturing method of semiconductor integrated circuit device. Substrate potential (VDD) the semiconductor substrate, is supplied, the semiconductor substrate formed a plurality of cells (5), a plurality of cell (5) [...] the each of the electrode pads (8), by refrigerant delivered from the lower stage implanted into the semiconductor substrate by said substrate potential said (VDD) and the other potential (VSS) power supply interconnection which is supplied with (7), said [...] (8) the same width as the width and the same wiring pitch the PCB by forming a dummy wiring (42) and, said power supply interconnection (7) and said dummy line (42) dedicated cell for connecting (51) semiconductor integrated circuit having a a step of preparing a device, said dummy line (42) selectively by severing an in-said dummy line (42) and said power supply interconnection (7) for electrically isolating a process and, said dummy line (42) [...] said and (8) selectively coupling the process device to with manufacturing method of semiconductor integrated circuit characterized by.