КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

ANORDNUNG VERFLOCHTENER UND VERSCHLUNGENER WORTLEITUNGEN FUER HALBLEITERSPEICHER

Halbleitereinrichtung mit Kurzschlußverhinderung in der Verdrahtungsschicht und zugehöriges Herstellungsverfahren

Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Integrierte Halbleiterschaltungsanordnung mit Leiterschichten

Integrierte Vorrichtung in Halbleiterscheibengrösse.

Process for producing a semiconductor device

The process according to the invention for producing a semiconductor device is characterised in that a semiconductor substrate is provided with a first insulating layer on its surface, a first conductive or conductor layer is formed on the first insulating layer, a second insulating layer is formed on the latter in a predetermined pattern, a second conductor layer with a pattern virtually corresponding to that of the second insulating layer is formed by means of etching the part, not covered by the second insulating layer, of the first conductor layer by ion etching by means of gas ions impinging virtually perpendicularly onto the substrate, a third insulating layer is formed on the side face of the second conductor layer by thermal oxidation with the proviso that the second insulating layer remains on the second conductor layer, and the second and third insulating layers are overlapped by a third conductor layer.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A DOUBLE INTERCONNECTION LAYER

Verfahren zur Herstellung einer Leiterbahn

Es ist ein Verfahren zur Herstellung einer abgerundeten Leiterbahn eines Halbleiterbauelements offenbart. Bei diesem Verfahren wird ein teilweise fertig gestelltes Halbleiterbauelement bereitgestellt. Das teilweise fertig gestellte Halbleiterbauelement besitzt eine Unterseite und eine von der Unterseite in einer vertikalen Richtung (v) beabstandete Oberseite (11'). Außerdem wird ein Ätzmittel bereitgestellt. Auf der Oberseite (11') ist eine dielektrische Schicht (2) angeordnet. Die dielektrische Schicht (2) besitzt wenigstens zwei verschiedene Bereiche (21, 22, 23, 24, 25), die, wenn sie mit dem Ätzmittel geätzt werden, unterschiedliche Ätzraten aufweisen. In der dielektrischen Schicht (2) wird ein Graben (13) derart gebildet, dass der Graben (13) einen jeden der verschiedenen Bereiche schneidet (21, 22, 23, 24, 25). Nach der Herstellung des Grabens (13) wird dieser aufgeweitet, indem er bei verschiedenen Ätzraten mit dem Ätzmittel geätzt wird. Nach dem Aufweiten des Grabens (13) wird eine ...

Struktur eines Finnen-Feldeffekttransistorbauelements (FinFET- Bauelement) mit Zwischenverbindungsstruktur

Halbleitervorrichtungsstruktur, die umfasst:eine erste Metallschicht (104), die über einem Substrat (102) gebildet wird;eine dielektrische Schicht (112), die über der ersten Metallschicht (104) gebildet wird;eine Haftschicht (130), die in der dielektrischen Schicht (112) und über der ersten Metallschicht (104) gebildet wird; undeine zweite Metallschicht (142), die in der dielektrischen Schicht (112) gebildet wird, wobei die zweite Metallschicht (142) elektrisch mit der ersten Metallschicht (104) verbunden ist, wobei ein Abschnitt der Haftschicht (130) zwischen der zweiten Metallschicht (142) und der dielektrischen Schicht (112) gebildet wird, und wobei die Haftschicht (130) einen ersten Abschnitt (130a), der einen oberen Abschnitt der zweiten Metallschicht (142) säumt, umfasst und wobei der erste Abschnitt (130a) einen erweiterten Abschnitt entlang einer vertikalen Richtung aufweist;dadurch gekennzeichnet, dass die Haftschicht (130) ferner einen zweiten Abschnitt (130b) unter dem ersten ...

Halbleiter-Die und Antennentuner

Ein Halbleiter-Die (10) umfasst mindestens eine erste Dichtungswand (30) neben einem Rand des Halbleiter-Dies (10), wobei die erste Dichtungswand (30) zumindest teilweise einen periodisch alternierenden Weg aufweist und durch mehrere Durchkontaktierungen (60) gebildet wird.

Elektrische Signalversorgungsschaltung und Halbleiterspeicheranordnung

Ultrafeine Teilchenstruktur und Verfahren zu ihrer Herstellung

Method for the fabrication of a semiconductor device

SEMICONDUCTOR DEVICE

A semiconductor apparatus comprises a step-shaped substrate and a multiple-layered crystal structure formed on the substrate, said multiple-layered crystal structure is of a superlatticed layer which is composed of alternate layers consisting of plural thin layers grown by molecular beam epitaxy.

Auto-contactor system and method for generating variable size contacts

SEMICONDUCTOR DEVICE

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

A method for improving integrated circuit by using a patterned bump layout on a metal layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

A highly integrated semi-conductor wiring structure and a method for manufacturng the same

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

Semiconductor Device and Manufacturing Method Thereof

Integrated circuits

The invention relates to a concept of metallisation for the production of integrated circuit devices in which the components of the integrated circuit are arranged in cells (17) which are all identical, non-functional and assembled in a matrix (14). Components of adjacent cells are interconnected by a metallic sub-network (22) forming blocks (23: 231...2315) representing predetermined logic functions. The blocks (23) have input-output terminals (26) at predetermined points, by which they are interconnected by a metallic sub-network (24:241...). The cells and blocks each have a symmetry with respect to the two axes of the matrix, so that the metallisation is minimal and the distribution may be more concentrated. The invention is applicable more particularly to LSI devices. ...

Aluminium pad power bus and signal routing for integrated circuit device utilizing copper technology interconnect structures

METHOD FOR FORMING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT FORMED BY THE METHOD

PRODUCTION OF AN ELECTRONIC CIRCUIT UNIT, WHICH STACKING CONTAINS IC SITUATIONS WITH BYPASS LINES

PLANAR CONCATENATED CIRCUIT FOR INTEGRATED CIRCUITS.

PROGRAMMABLE CONNECTING ARCHITECTURE

LEITBAHNANORNDUNG FOR MAXIMUMINTEGRATED CIRCUITS

HIGH FREQUENCY SIGNAL TRANSMISSION STRUCTURE

Alternate bump metallurgy bars for power and ground routing

INTEGRATED CIRCUIT CHIP MANUFACTURE

THICK BUS METALLIZATION INTERCONNECT STRUCTURE TO REDUCE BUS AREA

There is disclosed a structure for self aligned and non self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.

NORMALIZED INTERCONNECTION PATTERNS

Herein disclosed is a semiconductor device which includes at least one semiconductor chip forming circuit element thereon and connection patterns being connected to said circuit element or elements. According to the invention, said connection patterns comprise a lower connection pattern, which is normalized and widely applied to many kinds of circuits, and an upper connection pattern, which is positioned on the upper side of said lower connection pattern. Said upper connection pattern and said lower connection pattern are connected in conformity with the circuit to be obtained.

SEMICONDUCTOR INTERCONNECTION STRUCTURE

... 4157-221 An improved field effect transistor utilizes a selfaligned contact structure in which a layer of metal capable of forming silicide is deposited on the source and drain regions as well as external to them. The metal forms metal silicide on the source and drain and, where it extends onto surrounding insulating regions, forms an interconnecting metal contact. In addition, bipolar devices may be formed on the same integrated circuit by employing insulating spacer regions around the edges of polysilicon electrodes to the bipolar devices. Also described are static and dynamic random access memory cells employing the technology.

SEMICONDUCTOR INTERCONNECTION STRUCTURE

IMAGER DEVICE WITH INTEGRAL ADDRESS LINE REPAIR SEGMENTS

An imager array data line repair structure for use in high performance imager arrays includes a first and a second plurality of address lines that are disposed in respective layers with an intermediate layer having at least one insulative material disposed therebetween. The imager device further includes at least one integral address line repair segment that is disposed in the same layer as the first address lines and that is electrically isolated from the first address lines; the integral address line repair segment is disposed so as to underlie a repair portion of the second address line, with the intermediate layer disposed therebetween, and has a width substantially the same as the overlying second address line. In initial fabrication, the integral address line repair segment is electrically isolated from the overlying repair segment of the second address line; in the event a repair has been effected, the repair portion of the second address line is electrically coupled to the underlying ...

METHOD FOR INTEGRATING ANALOG AND DIGITAL FUNCTIONAL COMPONENTS, AND RESULTING SEMICONDUCTOR CHIP INCLUDING AN INTEGRATED DRAM

Fabrication of a processing device and analog and digital components on a semiconductor chip may be performed simultaneously during the integration of a DRAM on the same chip by selectively applying the materials utilized in the integration of the DRAM and other desired materials onto the chip. The interconnections which may be fabricated during the simultaneous fabrication of these components on the chip provide improved data transfer capabilities on the chip and access to data that may be stored in the DRAM. The integration of multiple components together with a DRAM on a chip, furthermore, provides for the reduction of production and testing costs of a DRAM integrated on a semiconductor chip.

Halbleitervorrichtung und Verfahren zur Herstellung derselben

Power supply device for an integrated electronic circuit divided into functional blocks distributed in multidimensional distribution.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor multilayer structure and a manufacturing method thereof

The invention discloses a semiconductor multilayer structure and a manufacturing method thereof. The semiconductor multilayer structure comprises a plurality of layers of first conducting layers, a plurality of layers of first insulating layers and a second conducting layer. The plurality of layers of first conducting layers are arranged at intervals. Each first conducting layer is provided with an upper surface, a lower surface arranged opposite to the upper surface and sidewalls. The first insulating layers surround the peripheries of the first conducting layers, and each first insulating layer at least covers a portion of the upper surface, a portion of the lower surface, and the sidewalls of each first conducting layer. The second conducting layer covers the first conducting layers and the first insulating layers.

Inductor and forming method thereof

The invention relates to an inductor and a forming method thereof, wherein the forming method of the inductor comprises the following steps: sequentially forming at least one metallic insulating layer and at least one dielectric layer on a semiconductor substrate at intervals; forming an electric induction coil which penetrates through the metallic insulating layer in the metallic insulating layer; forming a continuous groove which penetrates through the dielectric layer and is correspondingly connected with the electric induction coil in the dielectric layer, wherein the continuous groove is helical; and filling conducting materials in the continuous groove to form a continuous groove coil. In the invention, the metallic thickness of the inductor is ensured, the resistance in the inductor is reduced, the quality factor of the inductor is improved, and simultaneously the requirement for improving the integration level of a semiconductor device can be met.

A silicon-based vertical interconnection structure and preparation method

Test structure and formation method and test method thereof

Disclosed are a test structure, a formation method and a test method thereof. The test structure comprises a semiconductor substrate, a through-silicone interconnection structure, a medium layer, a first metal interconnection layer, a second metal interconnection layer, a first test end and a second test end, wherein the through-silicone interconnection structure is arranged in the semiconductor substrate, the medium layer covers the semiconductor substrate, the first metal interconnection layer and the second metal interconnection layer are mutually separated in the medium layer and both comprise second diffusion barrier layers and aluminum metal layers arranged on the second diffusion barrier layers, the first metal interconnection layer is connected with the surface of the through-silicone interconnection structure, the second metal interconnection layer is ring-shaped, and the first metal interconnection layer is arranged in the ring; the first test end is connected with the first metal ...

Post-passivation interconnect structure and methods thereof

Wafer -level package structure

Semiconductor device and method for forming pattern for semiconductor device

Contact scheme for landing on different contact area levels

Semiconductor device and semiconductor package comprising the same

Chip structure with rewired circuit layer and manufacturing method thereof

OLED Luminous panel

Semiconductor structure and preparation method thereof

Semiconductor package

With low gate input resistance of the power semiconductor component and method for manufacturing the same

Micro-light-emitting diode growth substrate, display substrate, manufacturing method and display device

Capacitor and metal-oxide-metal capacitor

The invention provides a capacitor and metal-oxide-metal (MOM) capacitor. The MOM capacitor includes a first vertical metal plate, connected to a first terminal; a second vertical metal plate in close proximity to the first vertical metal plate, and connected to a second terminal; a third vertical metal plate in close proximity to the first vertical metal plate, and the third vertical metal platebeing located at the side of the first vertical metal plate opposite to the second vertical metal plate; and at least one oxide layer interposed between the first, second and third vertical metal plates. The inventive improved MOM capacitor is more area efficient, reduces the circuit plane layout and has better electrical performance.

Integrated circuit including nested voltage island

An integrated circuit comprising: a parent terrain; and a hierarchal order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchal structure.

Semiconductor chip manufacturing and wiring design method thereof

Thin film transistor array panel

Interconnection structure and forming method thereof

Semiconductor integrated circuit layout designing apparatus

The invention relates to a layout design device, comprising a memory device for storing the circuit data of a circuit consisting of a plurality of transistors; a search device for searching for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network; an extraction device for extracting a set of routes having the smallest number of routes in sets of route found by searching; a width determination device for determining the layout width according to the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined intoa common electrode, the number of transistors, and the smallest number of routes; and a layout determination device for forming information about the layout, wherein, all the source, drain and gate electrodes ...

Semiconductor device

A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

Signal routing structure and semiconductor device assembly including same

The invention relates to a signal routing structure and a semiconductor device assembly including the same. A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts having a first average pitch; a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts having a second average pitch; and a signal routing structure between the first and second semiconductor devices and including: a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts; a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a parallel conductive line pattern disposed between the first and second plurality of conductive structures. The parallel conductive line pattern ...

MULTIPLE LAYER METAL STRUCTURE AND PROCESSING

POWER MOS TRANSISTOR STRUCTURE

PORTION OF INTEGRATED CIRCUIT

STRUCTURE OF BARRIER FOR CONDUCTING ELECTRODES, AND ITS MANUFACTORING PROCESS

ELECTRICALLY ERASABLE PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE

INTEGRATED CIRCUIT WITH MACROCELLULES NOYEES IN A SEA OF DOORS OF THE TYPE PREDIFFUSEES AND MANUFACTORING PROCESS

DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS

L'INVENTION CONCERNE UN DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS. DANS CE DISPOSITIF QUI COMPORTE UN MICROPROCESSEUR 1 RELIE PAR DES ELECTRODES DE JONCTION P P A DIVERS CAPTEURS ET A DES CIRCUITS PERIPHERIQUES, IL EST PREVU UNE PREMIERE COUCHE DE CABLAGE 103A FORMEE SUR UN SUBSTRAT ET N'INTERSECTANT AUCUNE COUCHE DE CABLAGE ALIMENTEE PAR UN SIGNAL NUMERIQUE, UN PREMIER CIRCUIT ELECTRONIQUE 14, UNE SECONDE COUCHE DE CABLAGE APTE A ETRE ALIMENTEE PAR UN SIGNAL NUMERIQUE ET UN SECOND CIRCUIT ELECTRONIQUE 12 ACCOUPLE A CETTE COUCHE DE CABLAGE. APPLICATION NOTAMMENT A LA COMMANDE DU FONCTIONNEMENT D'UN MOTEUR D'AUTOMOBILE.

STRUCTURE AND PROCEEDED OF REPAIR OF JUST CIRCUITS

STRUCTURE AND PROCEEDED OF REPAIR OF JUST CIRCUITS

L'invention concerne un circuit intégré dont une portion (20) au moins comprend au moins un groupe (21) de cellules de secours destinées à être éventuellement reliées à ladite portion (20) du circuit intégré par des connexions de remplacement dont la longueur ne peut dépasser une valeur prédéterminée (Δ). Les entrées et sorties des cellules de secours sont reliées à des pistes métalliques de secours (WB) dont la disposition sur le circuit est telle que tout point de la portion (20) du circuit est distant au maximum de la valeur prédéterminée (Δ) d'un point de ces pistes.

INDUCTANCE INTEGREE

L'invention concerne une Inductance sous forme monolithique, comportant : dans un premier niveau de métallisation (Mn), des lignes conductrices inférieures parallèles (211, 212, 213) s'étendant le long du motif de l'inductance; dans un deuxième niveau (Vn), des vias (231, 232, 233, 234, 235, 236), chaque ligne conductrice sous-jacente étant associée à au moins deux vias; et, dans un troisième niveau de métallisation (Mn+1), des lignes conductrices supérieures (251, 252, 253, 254) interconnectées aux lignes conductrices sous-jacentes par l'intermédiaire des vias, les lignes conductrices inférieures et supérieures étant décalées les unes par rapport aux autres de façon à assurer la continuité électrique.

CHIP OF CIRCUIT VERY HAS High level Of INTEGRATION WITH REDUCTION OF the SHIFT Of CLOCK

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

ELECTRONIC CIRCUIT DEVICE

다이-대-다이 상호연결을 위한 브리지 모듈을 가지는 반도체 어셈블리

... 일 예에서, 반도체 어셈블리는 제 1 IC 다이(104A), 제 2 IC 다이(104B) 및 브리지 모듈(110)을 포함한다. 제 1 IC 다이는 자신의 최상부 측 상에, 복수의 상호연결부들(108) 중 제 1 상호연결부들(108A) 및 복수의 다이간 접촉부들(608) 중 제 1 다이간 접촉부들(608A)을 포함한다. 제 2 IC 다이는 자신의 최상부 측 상에, 복수의 상호연결부들 중 제 2 상호연결부들(108B) 및 복수의 다이간 접촉부들 중 제 2 다이간 접촉부들(608B)을 포함한다. 브리지 모듈은 제 1 상호연결부들과 제 2 상호연결부들 간에 배치되고 자신의 최상부 측 상에 브리지 상호연결부들(112) ― 브리지 상호연결부들은 복수의 다이간 접촉부들에 기계적으로 그리고 전기적으로 커플링됨 ―, 및 제 1 IC와 제 2 IC 사이에서 신호들을 라우팅하기 위하여 자신의 최상부 상에 배치된 전도성 상호연결부(706)의 층(들)을 포함한다. 브리지 모듈의 후면 측(710)은 복수의 상호연결부들의 높이를 넘어 연장되지 않는다.

INTER-CHIP POWER CONNECTION UNIT IN MULTI-CHIP SYSTEM, POWER DISTRIBUTION NETWORK, AND POWER NOISE MITIGATING METHOD

According to one embodiment, an inter-chip power connection unit in a multi-chip system comprises a transmission line which connects a first on-die power grid of a first die to a second on-die power grid of a second die. The first die and the second die share the same first conductive layer for supplying a power voltage of a power supplier. The transmission line is not directly connected to the first conductive layer. COPYRIGHT KIPO 2017 ...

METHOD FOR FABRICATING PATTERN OF SEMICONDUCTOR DEVICE

PURPOSE: A method for fabricating a pattern of a semiconductor device is provided to reduce fabricating cost and simplify a fabricating process by forming a fine pattern without using a photolithography process, and to overcome the limit of a line width of the photolithography process by making the line width of the pattern determined by the thickness of a material layer for forming the pattern. CONSTITUTION: A sacrificial layer is formed on a semiconductor substrate(100). The sacrificial layer is patterned to form a sacrificial layer pattern(103a). A conformal material layer is formed on the entire surface of the semiconductor substrate including the sacrificial layer pattern. The entire surface of the material layer is dry-etched until the semiconductor substrate is exposed so that a material layer pattern(110a,110b) is formed on both sidewalls of the sacrificial layer pattern. © KIPO 2003 ...

WIRING MANUFACTURING METHOD AND A DISPLAY DEVICE MANUFACTURING METHOD HAVING THE EDGES OF WIRES WITH A TAPER SHAPE

PURPOSE: A wiring manufacturing method and a display device manufacturing method are provided to completely meet the expansion of a pixel member, thereby enhancing the driving property and the reliability. CONSTITUTION: A conductive layer made of aluminum is formed on an insulating substrate. The conductive layer is etched by means of inductively coupled plasma so that a wiring is formed. The wiring structure includes the third conductive layer(18b), the second conducive layer(19b) and the first conducive layer(20b). In another process, a conductive layer including the first layer made of W or Mo and the second layer made of aluminum are also formed on the insulating surface. The conductive layer is etched by means of inductively coupled plasma so that a wiring is formed. The etching is performed by using the gas consisting of BCl3, Cl2 and O2. © KIPO 2007 ...

Thermally isolated ground planes with superconducting electrical couplers

Semiconductor Module Including a Memory Stack Having TSVs

Metal Clip for Semiconductor package

SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURE THEREOF

A semiconductor device includes a semiconductor substrate having an integrated circuit, a first insulating film formed on the semiconductor substrate, at least one power source internal wiring line formed on the first insulating film, and a second insulating film formed on the first insulating film and on the internal wiring line and having a plurality of openings exposing parts of the internal wiring line. At least one wiring line is formed on an upper side of the second insulating film to correspond to the internal wiring line and electrically connected to the internal wiring line via the plurality of openings of the second insulating film. The wiring line has at least one external electrode pad portion whose number is smaller than the number of openings in the second insulating film. © KIPO & WIPO 2007 ...

INSPECTION METHOD, INSPECTION SYSTEM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SAME

Provided are an inspection method and an inspection system which can easily detect a defect. The inspection method comprises: generating first layout data including information on a shape of a first pattern group; generating second layout data including information on a shape of a second pattern group; obtaining a target image including images of the first and second pattern groups; and detecting a defect pattern from the target image by comparing the target image with the first layout data and the second layout data. The first pattern group, the second pattern group, and the defect pattern are provided at different heights from the upper surface of a substrate. COPYRIGHT KIPO 2018 (S10) Providing a substrate including a first pattern group (S20) Generating first layout data including information on a shape of a first pattern group (S30) Providing a substrate including a second pattern group stacked on the first pattern group (S40) Generating second layout data including information on ...

DEVICE, PRINTED CIRCUIT BOARD AND COMMUNICATION APPARATUS

PURPOSE: An integrated circuit is provided to obtain a contact set that includes a specific shielding unit capable of being used independently of a selected power configuration. CONSTITUTION: The integrated circuit is provided with a set of contacts for connecting the integrated circuit to a differential transmission line. The set of contacts includes at least one first pair of contacts intended to receive the first power supply voltage, the second pair of contacts intended to receive the second power supply voltage and the third pair of contacts, referred to as signal contacts, intended to be connected to the transmission lines. Each power supply contact may indifferently receive ground or one of the high or low power supply voltages, realizing two possible power supply configurations, positive or negative. The signal contacts are surrounded by the power supply contacts so as to realize a specific shielding which is independent of the positive or negative power supply configuration. © ...

THIN FILM TRANSISTOR SUBSTRATE

PURPOSE: A thin film transistor substrate is provided to compensate a difference of an RC(Resistance Capacitance) delay value generated due to inequality of the length of lines in a fan-out of a thin film transistor. CONSTITUTION: An insulating substrate is provided. A plurality of gate lines(121) are formed on the insulating film and include pads to be connected with an external circuit. A plurality of data lines(171) cross the plurality of gate lines and include pads to be connected with an external circuit. A conductive pattern(93) is overlapped with the gate lines and the data lines. The length of the conductive pattern overlapped with the gate lines and the data lines decreases as the length of the gate lines or the data lines increases. © KIPO 2004 ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To increase the yield of an embedded conductive layer at the time of forming contact holes without leaving a mechanically damaged layer on the surface of an interlayer insulating layer. CONSTITUTION: A first interlayer insulating layer is formed on a semiconductor substrate layer. Trenches are formed in the first interlayer insulating layer and a conductive layer is formed on the first interlayer insulating layer by filing the trenches with the conductive layer. The surface of the substrate is polished after forming the conductive layer for forming a flat surface from which the first interlayer insulating layer and the conductive layer are exposed. Further, a damaged layer by polishing on the surface of the first interlayer insulating layer is removed by etching. An insulating layer is formed by a coating method on the surface of the substrate after etching. Subsequently, a second interlayer insulating layer exhibiting a high etch selectivity relative to the insulating film is ...

Semiconductor package

에어 갭을 가지는 후면 유전체 층을 갖는 집적 회로 구조체

... 집적 회로(IC) 구조체는 게이트 구조체, 소스 에피택셜 구조체, 드레인 에피택셜 구조체, 전면 상호연결 구조체, 후면 유전체 층 및 후면 비아를 포함한다. 소스 에피택셜 구조체와 드레인 에피택셜 구조체는 제각기 게이트 구조체의 양측에 있다. 전면 상호연결 구조체는 소스 에피택셜 구조체의 전면 및 드레인 에피택셜 구조체의 전면 상에 있다. 후면 유전체 층은 소스 에피택셜 구조체의 후면 및 드레인 에피택셜 구조체의 후면 상에 있으며 내부에 에어 갭을 갖는다. 후면 비아는 후면 유전체 층을 관통하여 소스 에피택셜 구조체 및 드레인 에피택셜 구조체의 첫 번째 것까지 연장된다.

반도체 패키지

... 본 개시의 일 실시예는, 서로 반대에 위치한 제1 및 제2 면을 가지며, 재배선층을 갖는 연결 구조체와, 상기 연결 구조체의 제1 면 상에 배치되며, 상기 재배선층에 연결된 접속 패드를 갖는 반도체 칩과, 상기 연결 구조체의 제1 면 상에 배치되며, 상기 반도체 칩을 봉합하는 봉합재와, 상기 연결 구조체의 제2 면 상에 배치되며, 상기 재배선층의 제1 및 제2 영역을 각각 노출시키는 복수의 제1 및 제2 개구를 갖는 패시베이션층과, 상기 복수의 제1 개구를 통해 상기 재배선층의 제1 영역에 각각 연결되는 복수의 언더범프 금속을 포함하는 반도체 패키지를 제공한다.

STRUCTURE OF TRAVEL TO IMPROVE THE POROSITY OF THE SIGNAL

Nonvolatile semiconductor memory device and method for manufacturing same

In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Semiconductor Device

A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Structure for nano-scale metallization and method for fabricating same

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

Chip structure and process for forming the same

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Wiring structure of semiconductor device

A wiring structure may include a first wiring having a first width that extends in a first direction, and a second wiring intersecting the first wiring, the second wiring extending in a second direction and having a second width that is equal to or less than the first width. Furthermore, the first wiring may have a third width that is smaller than the first width and the second wiring may have a fourth width that is smaller than the second width. Portions of the first and second wirings having the third and fourth widths may extend from an intersecting region in which the first wiring and the second wiring intersect each other.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Semiconductor device and substrate

A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

Distributed Metal Routing

A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Semiconductor device and method of producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Interconnect Structure to Reduce Stress Induced Voiding Effect

An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Backside Power Delivery Using Die Stacking

In a stacked die device having an active circuit die bonded on top of a power delivery die using, circuit components formed on the active circuit die are connected to receive power from a coarse network of low resistance, high capacitance power and ground conductors in the power delivery die through conductive via structures or through silicon vias (TSVs) formed in the active circuit die so that primary power is provided from the backside of the active circuit die, leaving more resources and space in the metal interconnect structure for input/output signal routing.

Wiring structure and method of forming the structure

Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

Discontinuous/non-uniform metal cap structure and process for interconnect integration

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Semiconductor device

In one embodiment, a semiconductor device includes a first wiring provided in a first wiring layer along a first direction, a second wiring provided in a second wiring layer along a second direction orthogonal to the first direction, the second wiring intersecting with the first wiring at a first intersect portion, and a third wiring provided close to and along the second wiring in the second wiring layer, the third wiring intersecting with the first wiring at a second intersect portion, wherein a distance between the second wiring in the first intersection portion and the third wiring in the second intersection portion is narrower than a distance between the second wiring another than the first intersection portion and the third wiring another than the second intersection portion.

Semiconductor Device and Manufacturing Method of the Same

Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR ELEMENT

A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad. 1. A method for manufacturing a semiconductor device , the method comprising:preparing a semiconductor element including a plurality of electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element;preparing a wiring substrate including a plurality of connection pads respectively corresponding to the plurality of electrode pads of the semiconductor element, wherein each of the connection pads is rectangular and elongated in a direction orthogonal to a layout direction of the line of electrode pads including the corresponding electrode pad;applying a solder including a bulging central portion on an upper surface of each of the connection pads;forming a plurality of pillar-shaped electrode terminals respectively on the plurality of electrode pads of the semiconductor element so that each of the electrode terminals has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad; andelectrically connecting ...

SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features. 118-. (canceled)19. A semiconductor device comprising:a plurality of line traces including at least one real trace which includes a gate electrode portion and a protruding portion protruding beyond the gate electrode portion by a predetermined distance, and at least one dummy trace placed in parallel with the at least one real trace,wherein two of multiple ones of the dummy trace, and at least one of the line traces interposed between the two dummy traces and including the at least one real trace form parallel extending line traces extending in parallel so as to be evenly spaced,the parallel extending line traces have an identical width while at least one end portions of the parallel extending line traces form line end portions facing a cell perimeter boundary region and being substantially flush with one another,line end portion uniformization dummy traces are formed on extensions of the line end portions of the parallel extending line traces so that the distances between the line end portions and corresponding line end portions of the line end portion ...

Semiconductor device

A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE

The semiconductor device has insulating films formed over a substrate ; an interconnection buried in at least a surface side of the insulating films ; insulating films formed on the insulating film and including a hole-shaped via-hole and a groove-shaped via-hole having a pattern bent at a right angle; and buried conductors buried in the hole-shaped via-hole and the groove-shaped via-hole . A groove-shaped via-hole is formed to have a width which is smaller than a width of the hole-shaped via-hole . Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented. 1. A semiconductor device comprising:a first insulating film formed above a substrate; a first interconnection buried in the first insulating film;a second insulating film formed above the first insulating film with the first interconnection;two groove-shaped patterns formed in the second insulating film, the groove-shaped patterns including a first pattern which has a first bent portion with a first angle in a plan view, a second pattern which has a second bent portion with a second angle that is larger than the first angle in a plan view and a third bent portion which has a third angle that is larger than the first angle in a plan view; anda conductive layer formed in the first and the second pattern, the conductive layer electrically coupling to the first interconnection.2. The semiconductor device according to claim 1 , wherein the first angle is 90°.3. The semiconductor device according to claim 1 , wherein the second angle and the third angle are 135°.4. The semiconductor device according to claim 1 , wherein the first interconnection has two bent portions with an angle that is larger than 90°.5. The semiconductor device according to claim 1 , wherein the first interconnection has ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first conductive layer over the semiconductor die;depositing an encapsulant around the semiconductor die;forming a first insulating layer over the semiconductor die; andforming an interconnect structure over the first insulating layer and encapsulant, wherein the first insulating layer provides stress relief for the interconnect structure.2. The method of claim 1 , further including:forming a channel in the semiconductor die; andforming the first insulating layer into the channel.3. The method of claim 1 , further including:forming a channel in the encapsulant; andforming the first insulating layer into the channel.4. The method of claim 1 , further including forming a second insulating layer over the semiconductor die prior to forming the first insulating layer.5. The method of claim 1 , further including removing a portion of the first insulating layer by laser direct ablation.6. The method of claim 1 , ...

Power Routing with Integrated Decoupling Capacitance

An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network ( 200 ) which comprises, in a first one (metalz) of the conduction layers, a first mesh structure ( 210 ) of electrically conductive material for distribution of a first electrical potential (POWER) of the power supply. The power-supply distribution network also comprises, in a second one (metalz+1) of the conduction layers, different from the first one of the conduction layers, a second mesh structure ( 220 ) of electrically conductive material for distribution of a second electrical potential (GROUND) of the power supply. In the first one (metalz) of the conduction layers, a first plurality of islands ( 212 ) of electrically conductive material is provided, each island being located in a hole ( 214 ) of the first mesh structure ( 210 ) and being electrically insulated from the first mesh structure with a dielectric material.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. 16-. (canceled)7. A semiconductor device comprising:a first wiring layer disposed in a first level;a second wiring layer formed at a level above the first wiring layers;a third wiring layer formed at a level below the first wiring layers,a contact hole connecting the second wiring layer and the third wiring layer;a first restriction region including the first wiring layer;a second restriction region including the contact hole;a plurality of dummy wiring layers provided in the first level; andwherein the dummy wiring layers are provided in regions other than the first restriction region and the second restriction region.8. The semiconductor device of claim 7 , wherein at least a part of the dummy wiring layer overlaps the second wiring layer in plan view.9. The semiconductor device of claim 7 , wherein at least one of the dummy wiring layers overlaps the second wiring layer in plan view.10. The semiconductor device of claim 7 , wherein the first wiring layer and the second wiring layer are parallel. This application is a continuation application of U.S. Ser. No. 13/485,165 filed May 31, 2012, which is a divisional application of U.S. ...

SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS

A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit. 122-. (canceled)23. A semiconductor device , comprising:a semiconductor substrate;an integrated circuit on the semiconductor substrate;an insulation layer covering the integrated circuit;a barrier layer covering the insulation layer; anda plurality of metal line patterns on the barrier layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit adjacent to the space.24. The semiconductor device as claimed in claim 23 , further comprising an additional insulation layer between the insulation layer and the barrier layer.25. The semiconductor device as claimed in claim 24 , further comprising a resistive layer between the additional insulation layer and the insulation layer.26. The semiconductor device as claimed in claim 23 , wherein the slits are less than about 4 μm from the space.27. The semiconductor device as claimed in claim 23 , wherein the space is less than about 10 μm.28. The semiconductor device as claimed in claim 27 , wherein the space is less than about 1 μm.29. The semiconductor device as claimed in claim 23 , wherein the slits have a width greater than about 1 μm.30. The semiconductor device as claimed in claim 23 , wherein the first and second metal line patterns have a width greater than about 30 μm.31. The semiconductor device as claimed in claim 23 , wherein each metal line pattern of the plurality of metal line patterns having a width greater ...

Stress Reduction Apparatus

A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Semiconductor Package with Integrated Electromagnetic Shielding

There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Interconnect structures

A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE

A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact. 1. A semiconductor device with overlapping contacts comprises:a dielectric layer;a first contact located in the dielectric layer; anda second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.2. The semiconductor device of claim 1 , wherein the second contact completely covers the top surface of the first contact.3. The semiconductor device of claim 1 , wherein the first contact comprises a liner claim 1 , the liner comprising a first outer liner layer located adjacent to the dielectric layer claim 1 , a first inner liner layer located over the first outer liner layer claim 1 , and a first contact fill metal located over the first inner liner layer; andwherein the second contact comprises a second outer liner layer, wherein a first portion of the second outer liner layer is located adjacent to the dielectric layer, and a second portion of the second outer liner layer is located adjacent to the first contact fill metal on the top surface of the first contact, a second inner liner layer located over the second outer liner layer, and a second contact fill metal located over the second inner liner layer.4. The semiconductor device of claim 3 , wherein the first and second outer liner layers comprise titanium claim 3 , the first and second inner liner layers comprises titanium nitride claim 3 , and the first and second contact fill metal comprises tungsten.5. The semiconductor device of claim 1 , wherein the dielectric layer comprises one of an oxide and a nitride.6. The semiconductor device of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. 1. A manufacturing method of a semiconductor device comprising:forming core patterns, onto which a plurality of linear shaped first mask patterns, each of which is offset in three stages by a wiring pitch in an orthogonal direction with respect to a wiring direction, is transferred, on a processing target layer;forming first sidewall patterns on sidewalls of the core patterns;removing the core patterns while leaving the first sidewall patterns on the processing target layer;forming second sidewall patterns on sidewalls of the first sidewall patterns in such a way that sidewalls facing each other with a space between the first sidewall patterns therebetween are brought into contact with each other at a bent portion of the first sidewall patterns; andforming openings in the processing target layer by processing the processing target layer exposed from the first and second sidewall patterns.2. The manufacturing method of a semiconductor device according to claim 1 , wherein the first mask pattern is offset back and forth in an orthogonal direction with respect to the wiring direction of wires.3. The manufacturing method of a semiconductor device according to claim 2 , wherein the first mask ...

NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS

A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device. 1. A method comprising:providing a mask with a semiconductor circuit layout including a plurality of mask lines including at least a first mask line including at least one notch shape;fabricating a portion of said semiconductor circuit using said mask to form a plurality of conductive lines corresponding to said plurality of mask lines and including a first conductive line corresponding to said first mask line and having at least one notch, each of said at least one notch corresponding to one notch shape of said at least one notch shape, wherein said first conductive line is surrounded by an insulator material and interconnects at least two components of said semiconductor circuit and said fabricating results in formation of residual stresses within said plurality of conductive lines and said insulator material; andfurther fabricating further portions of said sera semiconductor circuit to produce said semiconductor circuit,wherein each of said at least one notch generates extra stress components within said first conductive line compared to other conductive lines of said plurality of conductive ...

Optimizing Layout of Irregular Structures in Regular Layout Context

A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch. 1. An integrated circuit , comprising:a plurality of regular wires formed within a given chip level, each of the plurality of regular wires having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction, the plurality of regular wires positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two of the plurality of regular wires is an integer multiple of the fixed pitch; andat least one irregular wire formed within the given chip level and within a region bounded by the plurality of regular wires, the at least one irregular wire having a linear-shape with a length extending in the first direction and a width extending in the second direction, wherein a distance as measured in the second direction between a lengthwise centerline of the at least one irregular wire and any one of the plurality of regular wires is not equal to an integer multiple of the fixed pitch.2. An integrated circuit as recited in claim 1 , wherein the at least one ...

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.

Deformable Network Structure

Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state. 2. The deformable network structure of claim 1 , wherein the connector provides an electrical connection between the first and the second device portions.3. The deformable network structure of claim 1 , wherein a first distance between the first and second centers in the final state varies at least 10% of a second distance between the first and second centers in the initial state contributed by a deformation of the connector.4. The deformable network structure of claim 3 , wherein the first distance between the first and second centers in the final state is less than 90% of the second distance between the first and second centers in the initial state.5. The deformable network structure of claim 3 , wherein the first distance between the first and second centers in the final state is greater than 1.1 fold of the second distance between the first and second centers in the initial state.6. The deformable network structure of claim 1 , wherein the first and second centers are geometric centers claim 1 , mass centers or centers of symmetry.7. The deformable network structure of claim 1 , wherein the first and second device portions and the connector share a common material layer.8. The deformable network structure of claim 1 , wherein the first and second device portions and the ...

Methods for Multi-Wire Routing and Apparatus Implementing Same

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. 1. A semiconductor chip , comprising:a first set of at least two conductors extending in a first direction in a parallel manner, the first set of at least two conductors corresponding to a common electrical node;a second set of at least two conductors extending in a second direction in a parallel manner, the second direction perpendicular to the first direction, the second set of at least two conductors corresponding to the common electrical node, the first and second sets of at least two conductors located on different levels of the semiconductor chip; andat least two interlevel conductors extending between the different levels of the semiconductor chip such that each of the first set of at least two conductors is connected to at least one of the second set of at least two conductors by one or more of the at least two interlevel conductors.2. A semiconductor chip as recited in claim 1 , wherein the at least two interlevel conductors are positioned in a rectangular array defined in accordance with the first and second directions.3. A ...

Elongated via structures

An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Semiconductor device

The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

Method to resolve hollow metal defects in interconnects

A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT

A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described. 1. A method for reducing areas of high field density in an integrated circuit , the method comprising:forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit;forming a second curvilinear wiring structure in a second interconnect layer of the integrated circuit, wherein the second curvilinear wiring structure is substantially vertically aligned with the first curvilinear wiring structure; andelectrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure.2. The method of claim 1 , wherein electrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure comprises:forming a curvilinear conductive via to electrically connect the first curvilinear wiring structure to the second curvilinear wiring structure; andextending the curvilinear conductive via between the first curvilinear wiring structure and the second curvilinear wiring structure.3. The method of claim 2 , wherein forming the first curvilinear wiring structure comprises forming a first set of concentric conductive annular structures having a first electrode and a second electrode.4. The method of claim 3 , wherein forming the second curvilinear wiring structure comprises forming a second set of concentric conductive annular structures having a first electrode and a second ...

Semiconductor chip layout with staggered tx and tx data liness

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. 1. A method of forming a semiconductor structure , comprising:forming a stack of conductive materials, wherein adjacent conductive materials of the stack are separated from each other by a respective insulating material;forming first contact regions over portions of the conductive materials to form a stair step structure extending from a top first contact region to a bottom first contact region; andremoving portions of half of the conductive materials of the stack to form second contact regions, each of the second contact regions being offset from a corresponding first contact region and adjacent to the corresponding first contact region in a direction perpendicular to a direction in which the stair step structure extends.2. The method of claim 1 , wherein forming first contact regions over portions of the conductive materials to form a stair step structure comprises:forming a mask over a topmost insulating material of the stack;removing a portion of the mask to expose a portion of the topmost insulating material;removing at least the exposed ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH FORMATION OF CONDUCTIVE LINES

A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region. 117-. (canceled)18. A semiconductor device comprising:a substrate having a first region and second regions disposed on two sides of the first region;a first group of conductive lines extending from the first region to the second regions on the substrate;a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate;interlayer insulating layers formed over the substrate;insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; andcontact plugs contacting the second group of conductive line formed in second open regions of the interlayer insulating layer in the second region.19. The semiconductor device of claim 18 , wherein the insulating layers and the contact plugs are disposed in a zigzag form.20. The semiconductor device of claim 18 , wherein the first group of the insulating layers is aligned in a first line perpendicular with the extending direction of the conductive lines and the second group of contact plugs is aligned in a second line perpendicular with the extending direction of the conductive lines.21. The semiconductor device of claim 18 , wherein the insulating layers and the contact plugs ...

DIE POWER STRUCTURE

A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles. 19.-. (canceled)10. The method of operating a die , comprising:distributing a first power signal having a first voltage across a first plurality of power tiles arranged in a first array and a first plurality of mesh segments;distributing a second power signal having a second voltage across a second plurality of power tiles arranged in a second array and a second plurality of mesh segments,wherein the first plurality of power tiles encloses the second plurality of mesh segments,wherein the second plurality of power tiles encloses the first plurality of mesh segments, andwherein the first array and the second array are offset on the die; andpropagating the first power signal to a first power rail operatively connected to the first plurality of power tiles and the first plurality of mesh segments by a first plurality of vias.11. The method of claim 10 , further comprising:propagating the second power signal to a second power rail operatively connected to the second plurality of power tiles and the second plurality of mesh segments by a second plurality of vias.12. The method of claim 11 , further comprising:injecting the first power signal into the die using a first bump above the second array and operatively connecting to the first plurality of power tiles using a zipper structure;and injecting the second power signal into the die using a second bump above the first array and operatively connecting to the second plurality of power ...

Semiconductor device

In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.

RF CMOS TRANSISTOR DESIGN

An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line, in an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers. 1. An RF CMOS transistor , the transistor comprising:an active area;a plurality of gate fingers;a plurality of local interconnect lines constrained substantially to above the active area of the transistor; anda source terminal and a drain terminal arranged orthogonally to each of the plurality of local interconnect lines, wherein each terminal is electrically connected to at least one local interconnect line wherein the source terminal and the drain terminal are substantially wider than a local interconnect line and the source terminal and drain terminal are routed above the active region, including above the gate fingers,2. The RF CMOS transistor according to claim 1 , wherein the source terminal and the drain terminal are formed in different metal layers.3. The RF CMOS transistor according to claim 1 , further comprising a second drain terminal and wherein the drain terminals are arranged either side of the source terminal.4. The RF CMOS transistor according to claim 1 , further comprising at least one gate strap claim 1 , and wherein the at least one gate strap is routed in a metal layer avoe the source and drain terminals substantially across a center of the transistor in parallel with the plurality of gate fingers.5. The RF CMOS transistor design according to claim 1 , further comprising:a dummy gate electrode structure; anda well-tap adjacent to the dummy gate electrode structure,and wherein the dummy gate ...

Semiconductor memory devices and methods of fabricating the same

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm. 1. A semiconductor device comprising:a semiconductor substrate;a first active region in the semiconductor substrate;a second active region in the semiconductor substrate;{'sup': '-1', 'a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm.'}2. The semiconductor device of claim 1 , further comprising:a third active region in the semiconductor substrate;a fourth active region in the semiconductor substrate; and{'sup': '-1', 'a second conductive line over the semiconductor substrate electrically connected to the third active region and having a second end face adjacent to the fourth active region, and the second end face having an image log slope of greater than 15 μm, and a distance between the first conductive line and the second conductive line is less than 100 nm.'}3. The semiconductor device of claim 2 , further comprising an isolation region between the first conductive line and the second conductive line.4. The semiconductor device of claim 3 , wherein neither the first conductive line nor the second conductive line substantially overlap the isolation region.5. The semiconductor device of claim 1 , wherein the first conductive line comprises at least one of tungsten claim 1 , aluminum claim 1 , copper claim 1 , or conductive polymer.6. A semiconductor device comprising:a semiconductor substrate;a first active region in the ...

Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer

A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.

Stacked multilayer structure and manufacturing method thereof

A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS

A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. 1. A semiconductor component comprising:a semiconductor substrate; a plurality of elongate first main electrode zones each respectively connected to one of a plurality of overlying first lower islands via at least one through hole,', 'a plurality of elongate second main electrode zones arranged alternately with and parallel to the plurality of elongate first main electrode zones and each respectively connected to one of a plurality of overlying second lower islands via at least another through hole, and', 'a control electrode zone arranged between the first and second main electrode zones;, 'at least one cell formed on the semiconductor substrate and comprising'}a first collective island arranged transversely above the pluralities of overlying first and second lower islands and connected to the plurality of overlying first lower islands;a second collective island arranged transversely above the pluralities of overlying first and second lower islands and connected to the plurality of overlying second lower islands;wherein the pluralities of overlying first and second lower islands and the first and second collective islands comprise sections of metallization layers,wherein longitudinal sections of the overlying first and second lower islands covered by and connected to the first and second collective islands are not more than about four times as wide as the pluralities of elongate first and second main electrode zones respectively connected to the pluralities of overlying first and second lower islands, ...

Semiconductor device

One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer.

Power tsvs of semiconductor device

A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING SAME

Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate. 1. A substrate structure , comprising:a first substrate and a second substrate oppositely arranged,wherein a first surface of the first substrate faces toward a second surface of the second substrate, and a conductive interconnect layer and a bonding layer are provided on the first surface in sequence; andthe first substrate and the conductive interconnect layer are coupled to the second substrate via the bonding layer.2. (canceled)3. The substrate structure according to claim 1 , wherein the conductive interconnect layer comprises at least one conductive layer.4. (canceled)5. The substrate structure according to claim 3 , wherein one of the at least one conductive layer performs a shielding function.6. The substrate structure according to claim 3 , wherein the conductive interconnect layer comprises at least two conductive layers.7. The substrate structure according to claim 1 , further comprising:isolation regions passing through the first substrate, wherein the first substrate is divided into regions mutually insulated by the plurality of isolation regions.8. The substrate structure according to claim 1 , further ...

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor. 1. A semiconductor device comprising:a lower conductor having a lower conductor sidewall;a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall; anda via formed on a top surface of the lower conductor,wherein a top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.2. The semiconductor device of claim 1 , further comprising:a first insulation film surrounding a combination of the lower conductor and the barrier film, wherein a portion of the first insulation film proximate the recessed top portion of the barrier film sidewall is recessed.3. The semiconductor device of claim 2 , wherein the recessed top portion of the barrier film and the recessed portion of the first insulation film collectively form a recessed region having a width that is upwardly increasing from the top surface of the barrier film.4. The semiconductor device of claim 3 , wherein the via extends to completely fill the recessed region.5. The semiconductor device of claim 1 , wherein a width of the top surface of the lower conductor is less than or equal to a width of a bottom surface of the via.6. The semiconductor device of claim 1 , further comprising:a first upper conductor formed directly on the via and having opposing sidewalls that vertically align with respective opposing sidewalls of the via.7. The semiconductor device of claim 6 , further comprising:a second upper conductor arranged in parallel with the first upper conductor and ...

SEMICONDUCTOR DEVICE

A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. 1. A semiconductor device comprising:a substrate;a transistor formed on the substrate;a multilayer interconnect structure having three or more layers which is formed over the substrate and the transistor;a first conductor pattern formed in the n-th layer of the multilayer interconnect structure (n≧1) and coupled to a ground or power supply; anda signal line formed in the (n+2)th layer of the multilayer interconnect structure or an interconnect layer above it and located in a region in which it overlaps the first conductor pattern in a plan view,wherein at least part of a transmission line is formed by the signal line and the first conductor pattern.2. A semiconductor device according to claim 1 ,Wherein the transistor overlaps the first conductor pattern in a plan view.3. A semiconductor device according to claim 2 , further including an organic resin layer formed over the multilayer interconnect structure claim 2 , wherein the signal line is formed over the organic resin layer.4. A semiconductor device according to claim 3 , further including two second conductor patterns which are formed in an interconnect layer above the n-th layer of the multilayer interconnect structure and extend parallel to the signal line with the signal line between them claim 3 , in a plan view claim 3 ,wherein the second conductor patterns are electrically coupled to the ground or the power supply.5. A semiconductor device according to claim 4 ,wherein the second conductor patterns are formed in the same layer as the signal line.6. A semiconductor device according to claim 5 ,wherein the height form the first conductor pattern to the signal line ...

Sensor packaging method and sensor packages

A method ( 80 ) entails providing ( 82 ) a structure ( 117 ), providing ( 100 ) a controller element ( 102, 24 ), and bonding ( 116 ) the controller element to an outer surface ( 52, 64 ) of the structure ( 117 ). The structure includes a sensor wafer ( 92 ) and a cap wafer ( 94 ). Inner surfaces ( 34, 36 ) of the wafers ( 92, 94 ) are coupled together, with sensors ( 30 ) interposed between the wafers ( 92, 94 ). One wafer ( 94, 92 ) includes a substrate portion ( 40, 76 ) with bond pads ( 42 ) formed on its inner surface ( 34, 36 ). The other wafer ( 94, 92 ) conceals the substrate portion ( 40, 76 ). After bonding, methodology ( 80 ) entails forming ( 120 ) conductive elements ( 60 ) on the element ( 102, 24 ), removing ( 126 ) material sections ( 96, 98, 107 ) from the wafers ( 92, 94, 102 ) to expose the bond pads ( 42 ), forming ( 130 ) electrical interconnects ( 56 ), applying ( 134 ) packaging material ( 64 ), and singulating ( 138 ) to produce sensor packages ( 20, 70 ).

Microelectronic packages having trench vias and methods for the manufacture thereof

Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

METHOD FOR FORMING A VERTICAL ELECTRICAL CONNECTION IN A LAYERED SEMICONDUCTOR STRUCTURE

The invention proposes a method for forming a vertical electrical connection () in a layered semiconductor structure (), comprising the following steps: —providing () a layered semiconductor structure (), said layered semiconductor structure () comprising: —a support substrate () including an first surface () and a second surface (), —an insulating layer () overlying the first surface () of the support substrate (), and —at least one device structure () formed in the insulating layer (); and —drilling () a via () from the second surface of the support substrate () up to the device structure (), in order to expose the device structure (); characterized in that drilling () of the insulating layer is at least performed by wet etching (). 23203030. The method of claim 1 , wherein wet etching () is performed during a predetermined time claim 1 , said predetermined time depending on the material of the insulating layer () claim 1 , the etchant and the thickness of the insulating layer () to be drilled.3320. The method of or claim 1 , wherein wet etching () is performed with a solution containing fluorhydric acid claim 1 , and optionally glycerol.4. The method of claim 3 , wherein the etchant comprises between 0.5% and 50% in volume of Fluorhydric acid claim 3 , preferably 1.35%.5. The method of or claim 3 , wherein the etchant further comprises between 0.5 and 50% in volume of glycerol claim 3 , preferably 1.35%.63223201. The method of anyone of to further comprising a pre-wetting step () prior to the wet etching step () claim 3 , wherein the layered semiconductor structure () is plunged in water.73243201. The method of anyone of to further comprising a rinsing step () following the wet etching step () claim 3 , wherein the layered semiconductor structure () is rinsed with water.83263283201328. The method of anyone of to further comprising a vacuum step ( claim 3 , ) following the wet etching step () claim 3 , wherein the layered semiconductor structure () is submitted () ...

Integrated Circuit Formed Using Spacer-Like Copper Deposition

A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer.

RELIABLE PACKAGING AND INTERCONNECT STRUCTURES

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. 1. A semiconductor device , comprising:a substrate; the electrically conductive interconnect structure partially extends within at least one trench in a dielectric region of the substrate; and', 'the electrically conductive interconnect structure has a top surface and at least one sidewall; and', 'a portion of the top surface of the at least one sidewall of the electrically conductive interconnect structure has been removed to create at least one gap between the at least one sidewall of the electrically conductive interconnect structure and at least one wall of the at least on trench; and, 'an electrically conductive interconnect structure disposed on the substrate, whereina dissimilar material disposed on and covering the top surface and a portion of the at least one side of the electrically conductive interconnect structure to at least partially fill the at least one gap.2. The semiconductor device of wherein the dissimilar material is conductive.3. The semiconductor device of wherein the dissimilar material is non-conductive.4. The semiconductor device of wherein the dissimilar material comprises a coupling layer.5. The semiconductor device of wherein the dissimilar material comprises an adhesion layer.6. The ...

CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. 1. A package , comprising:a semiconductor device including an active surface having a contact pad;a redistribution layer (RDL) structure including a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device;an under-bump metallurgy (UBM) layer over and electrically connected to the first PPI line; anda seal ring structure extending around and outside the upper periphery of the semiconductor device, the seal ring structure including a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.2. The package of claim 1 , wherein the seal ring structure includes a top seal layer extending on the same level as and spaced apart from the UBM layer.3. The package of claim 2 , wherein the top seal layer and the UBM layer comprise the same material.4. The package of claim 2 , wherein the seal ring structure further includes a lower seal layer connected to the top seal layer claim 2 , and extended on the same level as the first PPI line.5. The package of claim 4 , wherein the lower seal layer and the first PPI line comprise the same material.6. The package of claim 4 , wherein the lower seal layer extends on the active surface of the semiconductor device.7. The package of claim 4 , whereinthe semiconductor device further includes a chip ...

SEMICONDUCTOR DEVICE

A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential. 1. A semiconductor device comprising:a semiconductor layer of a first conductivity type;an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region;a field insulating film configured to cover a surface of the element isolation well;an interlayer insulating film formed on the semiconductor layer;a wiring formed on the interlayer insulating film; anda conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.2. The semiconductor device of claim 1 , wherein the element formation region includes a low voltage element region in which an element operated with a low reference voltage is formed and a high voltage element region in which an element operated with a high reference voltage is formed claim 1 , the high reference voltage being higher than the low reference voltage claim 1 , the low and high voltage element regions being isolated by the element isolation well claim 1 , andwherein the wiring is electrically connected to the element formed in the high voltage element region.3. The semiconductor device of claim 1 , wherein the wiring intersects the element isolation well when viewed from the top claim 1 , andwherein the conductive film is ...

METHOD TO INCREASE I/O DENSITY AND REDUCE LAYER COUNTS IN BBUL PACKAGES

An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate. 1. An apparatus comprising:a die having a thickness dimension that includes a dielectric material on contact points on a device side of the die, the die also comprising a die area defined by a length dimension and a width dimension;an insulating layer surrounding the die area and embedding the thickness dimension of the die; anda build-up carrier having a carrier area greater than the die area, the build-up carrier comprising a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces and a first level of conductive vias to respective contact points on the die, the traces disposed on a surface defined by the dielectric material and the insulating layer.2. The apparatus of claim 1 , wherein the insulating layer embedding a thickness dimension of the die comprises an epoxy.3. (canceled)4. The apparatus of claim 1 , wherein the dielectric material on the die comprises a thickness profile along its perimeter with an irregular surface.5. A method comprising:disposing ...

STRESSED DECOUPLED MICRO-ELECTRO-MECHANICAL SYSTEM SENSOR

A semiconductor device may include a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device. The stress decoupling structure may include a set of trenches that are substantially perpendicular to a main surface of the semiconductor device. The first region may include a micro-electro-mechanical (MEMS) structure. The semiconductor device may include a sealing element to at least partially seal openings of the stress decoupling structure. 1. A semiconductor device , comprising: wherein the stress decoupling structure includes a set of trenches that are substantially perpendicular to a main surface of the semiconductor device, and', 'wherein the first region includes a micro-electro-mechanical (MEMS) structure; and, 'a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device,'}a sealing element to at least partially seal openings of the stress decoupling structure.2. The semiconductor device of claim 1 , wherein the stress decoupling structure further includes a cavity that at least partially separates the first region from the second region.3. The semiconductor device of claim 1 , wherein the sealing element includes a cap that at least partially seals the openings of the stress decoupling structure.4. The semiconductor device of claim 3 , wherein the cap includes a stress decoupling structure to decouple the first region and the second region.5. The semiconductor device of claim 3 , wherein the cap is formed from silicon or glass.6. The semiconductor device of claim 3 , wherein the cap is affixed to the first region and the second region using a wafer bonding process.7. The semiconductor device of claim 3 , wherein the cap is formed from an elastic material.8. The semiconductor device of claim 7 , wherein the elastic material at least partially fills the set of trenches of the stress ...

Metal via structure

A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

SELF-ALIGNED VIA PROCESS FLOW

A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line. 1. A device , comprising:a first dielectric layer having at least one conductive feature embedded therein;a first plurality of conductive lines embedded in a second dielectric layer disposed above said first dielectric layer, wherein a first conductive line in said first plurality of conductive lines contacts said conductive feature and comprises a conductive via portion and a recessed line portion; anda second plurality of conductive lines embedded in a third dielectric layer disposed above said second dielectric layer, wherein a second conductive line in said second plurality of conductive lines contacts said conductive via portion and said conductive via portion has a first cross-sectional dimension corresponding to a width of said first conductive line and a second cross-sectional dimension corresponding to a width of said second conductive line.2. The device of claim 1 , wherein said second dielectric layer has a reduced thickness in a region disposed beneath each of said second plurality of conductive lines claim 1 , and the device further comprises air gaps disposed in said third dielectric layer between pairs of adjacent second conductive ...

TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension. 1. A test structure of a fin-type field effect transistor (FinFET) comprising:a first conducting layer electrically coupled to a dummy gate of the FinFET;a second conducting layer electrically coupled to a substrate of the FinFET;a third conducting layer electrically coupled to the dummy gate of the FinFET;a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer; anda second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer;wherein the first region comprises a first dielectric having a first dimension; andwherein the second region comprises a second dielectric having a second dimension greater than the first dimension.2. The test structure of claim 1 , wherein the first conducting layer is electrically coupled to the dummy gate by a first local interconnect and a first via.3. The test structure of claim 2 , wherein the second conducting layer is electrically coupled to the substrate by a second local interconnect and a second via.4. The test structure of claim 3 ...

METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING

At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing. 1. A method , comprising:receiving a design for an integrated circuit device, wherein said design comprises at least one functional cell; andproviding a first pair of wide metal formations comprising a first metal formation and a second metal placed about a first cell boundary of said functional cell for providing at least one of additional space for routing, high-drive routing, and power routing.2. The method of claim 1 , wherein providing said first metal formation comprises providing a mandrel metal Metal-2 (M2) formation and wherein providing said second metal formation comprises providing a non-mandrel metal M2 formation.3. The method of claim 2 , wherein providing said first metal formation comprises providing a metal formation that is wider than the default M2 width for said functional cell claim 2 , and wherein providing said second metal formation comprises providing a metal formation that is wider than the default M2 width for said functional cell.4. The method of claim 3 , wherein the first and second metal formations are formed on a top edge and a bottom edge of said functional cell.5. The method of claim 1 , further comprising providing a second pair of wide metal formations comprising a third metal formation and a fourth metal placed about a second cell boundary of said functional cell for providing at least one of additional space for routing claim 1 , and high- ...

Stacked Semiconductor Devices and Methods of Forming Same

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. 113-. (canceled)14. A method comprising:forming contact pads on a die;blanket depositing a passivation layer over the contact pads;patterning the passivation layer to form first openings, the first openings exposing the contact pads;blanket depositing a buffer layer over the passivation layer and the contact pads;patterning the buffer layer to form second openings, the second openings exposing a first set of the contact pads;forming first conductive pillars in the second openings, topmost surfaces of the first conductive pillars being above a topmost surface of the buffer layer;simultaneously with forming the first conductive pillars, forming conductive lines over the buffer layer, ends of the conductive lines terminating with the first conductive pillars; andforming an external connector structure over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.15. The method of claim 14 , wherein forming the external connector structure ...

METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK

The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer. 1. A method for forming an interconnect on a substrate , comprising:depositing a barrier layer on the substrate;depositing a transition layer on the barrier layer; anddepositing an etch-stop layer on the transition layer, wherein the transition layer shares a first common element with the barrier layer, and wherein the transition layer shares a second common element with the etch-stop layer.2. The method of claim 1 , wherein the barrier layer is deposited using a silicon-based precursor.3. The method of claim 1 , wherein the etch-stop layer is formed from a metal dielectric material.4. The method of claim 1 , wherein the transition layer is configured to decrease the fringing capacitance between the barrier layer and the etch-stop layer.5. The method of claim 1 , wherein the first common element shared between the transition layer and the barrier layer forms a first covalent bond between the transition layer and the barrier layer and the second common element shared between the transition layer and the etch-stop layer forms a second covalent bond between the transition layer and the etch-stop layer.6. The method of claim 5 , wherein the first covalent bond and the second covalent bond aid in saturating dangling defects between the transition layer and the etch-stop layer and the transition layer and the barrier layer.7. The method of claim 1 , wherein the barrier layer is formed from SiOC claim 1 , the transition layer is formed from SiCN claim 1 , ...

SEMICONDUCTOR DEVICE AND METHOD

Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure and a second conductive support structure and a cavity in which an inertial mass element comprising at least one metal portion is conductively coupled to the first support structure and the second support structure by respective conductive connection portions, at least one of said conductive connection portions being designed to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by the dimensions of the conductive connection portions. A method of manufacturing such a semiconductor device is also disclosed. 1. A semiconductor device comprising: a first conductive support structure having a first metal layer and a second conductive support structure having a second metal layer;', 'a cavity between the first conductive support structure and the second conductive support structure;', 'an inertial mass element having at least one metal portion which is vertically displaced with respect to the first metal layer and the second metal layer; and', 'a first plurality of conductive connection vias that conductively couple the inertial mass element to the first metal layer and the second metal layer, wherein at least one of the first plurality of conductive connection vias is configured to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by dimensions of the first plurality of conductive connection vias., 'a stack of patterned metal layers separated by dielectric layers, the dielectric layers having a first plurality of conductive vias that connect metal layers adjacent to the dielectric layers, the stack comprising2. The semiconductor device of claim 1 , further comprising:a detector configured to detect a disruption in the conductive coupling of the inertial mass element to the first metal layer ...

POST-PASSIVATION INTERCONNECT STRUCTURE AND METHODS THEREOF

The semiconductor device includes a die that contains a substrate and a bond pad. A connective layer is disposed over the die. The connective layer includes a supporting pad and a conductive channel. A portion of the conductive channel passes at least partially through the supporting pad. At least one dielectric region is interposed between the supporting pad and the portion of the conductive channel. 1. A semiconductor device , comprising:a die comprising a substrate; and a supporting pad;', 'a conductive channel, wherein a portion of the conductive channel passes at least partially through an opening in the supporting pad, the opening extending from a first edge of the supporting pad to at least a second point within the supporting pad; and', 'at least one dielectric region interposed between the supporting pad and the portion of the conductive channel., 'a connective layer disposed over the die, wherein the connective layer includes2. The semiconductor device of claim 1 , wherein the portion of the conductive channel passes completely through the opening in the supporting pad claim 1 , the opening extending to a second edge of the supporting pad.3. The semiconductor device of claim 1 , further comprising:an intermediate layer disposed over the connective layer; anda second connective layer disposed over the intermediate layer, wherein the second connective layer contains a landing pad; anda bump structure disposed above the landing pad, wherein the bump structure includes a conductive bump.4. The semiconductor device of claim 3 , wherein the bump structure includes a bump contact region in direct physical contact with a top surface of the landing pad claim 3 , wherein a center of the bump contact region is substantially aligned with a center of the supporting pad.5. The semiconductor device of claim 4 , wherein the bump contact region has an area of a size smaller than an area of a top surface of the supporting pad.6. The semiconductor device of claim 3 , wherein ...

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad. 1. A semiconductor device , comprising:an active region defined in a semiconductor substrate;a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region;a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug;a first air gap spacer between the first contact plug and the bit line;a landing pad on the first contact plug;a blocking insulating layer on the bit line; andan air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad,an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.2. The semiconductor device as claimed in claim 1 , wherein the first air gap spacer includes a first air gap vertically overlapped by the landing pad and a second air gap not vertically overlapped by the landing pad.3. The semiconductor device as claimed in claim 1 , wherein a height from the semiconductor substrate to a lowest part of the blocking insulating layer is lower ...

INTEGRATED CIRCUIT STRUCTURE, LAYOUT DIAGRAM METHOD, AND SYSTEM

An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments. 1. An integrated circuit (IC) structure comprising:a first plurality of metal segments positioned in a first metal layer, each metal segment of the first plurality of metal segments extending in a first direction;a second plurality of metal segments positioned in a second metal layer overlying the first metal layer, each metal segment of the second plurality of metal segments extending in a second direction perpendicular to the first direction; anda third plurality of metal segments positioned in a third metal layer overlying the second metal layer, each metal segment of the third plurality of metal segments extending in the first direction,wherein a pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.2. The IC structure of claim 1 , wherein each of the pitch of the second plurality of metal segments and the pitch of the third plurality of metal segments is larger than the pitch of the first plurality of metal segments.3. The IC structure of claim 1 , further comprising a fourth plurality of metal segments positioned in a fourth metal layer overlying the third metal layer claim 1 , each metal segment of the fourth plurality of metal segments extending in the second direction claim 1 , wherein a pitch of the fourth plurality of metal segments is larger than the pitch of the second plurality of ...

SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME

A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap. 1. A semiconductor device comprising:a substrate having first and second surfaces;an interlayer dielectric layer formed over the first surface and having a first opening to expose the first surface;a first plug positioned in the first opening;a bit line extending in a first direction and covering the first plug;a second plug comprising a lower part and an upper part, wherein the lower part is at the same level as the first plug, wherein the upper part is at the same level as the bit line;a first air gap positioned between the first plug and the lower part of the second plug; anda second air gap positioned between the bit line and the upper part of the second plug,wherein the second air gap has a larger width than the first air gap.2. The semiconductor device of claim 1 ,wherein the second air gap has a line shape extending in the first direction.3. The semiconductor device of claim 1 , further comprising:a plug isolation layer extending in a direction intersecting the bit line and providing a second opening which is adjacent to the bit line and the first plug and exposes the second surface,wherein the second plug is positioned in the second opening.4. The semiconductor device of claim 1 , further comprising:a first spacer formed at both sidewalls of the ...

INTEGRATED CHIP WITH CAVITY STRUCTURE

The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment. 17-. (canceled)8. A method of forming an integrated chip , the method comprising:forming a first metal feature and a second metal feature over a substrate;forming a first dielectric liner segment between the first metal feature and the second metal feature and along sidewalls of the first metal feature and the second metal feature;forming a sacrificial segment between the sidewalls of the first metal feature and the second metal feature, and further between sidewalls of the first dielectric liner segment;forming an etch-stop layer over the first metal feature, over the second metal feature, over the sacrificial segment, and over the first dielectric liner segment; andremoving at least part of the sacrificial segment from between the sidewalls of the first metal feature and the second metal feature and from between the sidewalls of the first dielectric liner segment, thereby leaving a first cavity in place where the at least part of the sacrificial segment has been removed.9. The method of claim 8 , wherein the first cavity is defined by the sidewalls of the first dielectric liner segment claim 8 , an upper ...

SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer. 1. A method of forming a semiconductor structure , comprising:forming a plurality of mandrel patterns over a dielectric layer;forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer;removing the plurality of mandrel patterns;patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; andforming conductive lines laterally aside the dielectric layer.2. The method of claim 1 , wherein patterning the dielectric layer comprises forming a first dielectric pattern defined by the first spacer and a second dielectric pattern defined by the second spacer.3. The method of claim 2 , wherein forming the conductive lines comprises:forming first conductive lines spaced apart by the first dielectric pattern therebetween; andforming second conductive lines spaced apart by the second dielectric pattern therebetween,wherein a first spacing between the first conductive lines is larger than a second spacing between the second conductive lines.4. The method of claim 1 , further comprising forming a hard mask structure between the dielectric layer and the plurality of mandrel patterns claim 1 , wherein patterning the dielectric layer comprises:patterning the hard mask structure to transfer patterns of the first spacer and the second spacer into the hard mask structure, thereby ...

Assemblies having Conductive Interconnects which are Laterally and Vertically Offset Relative to One Another

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another. 1. An integrated assembly , comprising:a base comprising circuitry;a first conductive interconnect extending upwardly from the base;a first level over the base and comprising a first conductive structure; the first conductive structure being coupled with the circuitry through at least the first conductive interconnect; the first conductive structure having a first region directly over the first conductive interconnect, a second region laterally offset from the first region, and a third region between the first and second regions;a second conductive interconnect extending upwardly from the second region of the first conductive structure; anda second level over the first level and comprising a second conductive structure; the second conductive structure being coupled with the circuitry through at least the first conductive interconnect, the third region of the first conductive structure and the second conductive interconnect.2. The integrated assembly of wherein the first and second levels comprise first and second memory circuitries claim 1 , respectively.3. The integrated assembly of wherein the first and second memory circuitries include memory cells configured for one or more of phase change memory claim 2 , magnetic memory and resistive memory.4. The integrated assembly of wherein the first ...

Method of forming semiconductor device having a conductive via structure

A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Semiconductor structure with embedded memory device

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.

Hybrid Copper Structure for Advance Interconnect Usage

The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips. 1. An integrated chip , comprising:a first plurality of metal interconnect structures disposed within a first back-end-of-the-line (BEOL) metallization layer and comprising a first conductive material; anda second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures, wherein the second plurality of metal interconnect structures comprise a second conductive material that is different than the first conductive material.2. The integrated chip of claim 1 , wherein the first plurality of metal interconnect structures have a first width and the second plurality of metal interconnect structures have a second width that is larger than the first width.3. The integrated chip of claim 2 , wherein the first width is in a range of between approximately 3 nm and approximately 30 nm.4. The ...

Semiconductor Constructions

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

VIA CLEANING TO REDUCE RESISTANCE

A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process. 1. A method for forming a semiconductor structure , comprising:forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer; andforming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.2. The method of claim 1 , wherein the cleaning process comprises an in situ reactive ion etching.3. The method of claim 2 , wherein the cleaning process utilizes argon gas.4. The method of claim 2 , wherein the cleaning process utilizes argon gas and helium gas.5. The method of claim 2 , wherein the cleaning process utilizes a flow of one or more inert gases exceeding 1200 standard cubic centimeters per minute.6. The method of claim 2 , wherein the cleaning process utilizes a radio frequency powered magnetic field of at least 300 watts.7. The method of claim 1 , wherein forming at least one via in the multilayer structure comprises:forming the first via and at least a second via extending from the top of the second layer to a top of a second contact formed in the first layer;forming at least a first trench extending from the top of the second layer partially through the second layer, the first trench connecting the first via and the second via.8. The method of claim 7 , wherein the first via claim 7 , the second via and the first trench form a chamfer having a high chamfering angle.9. The method of claim 1 , wherein the polymer film ...

SELF-ALIGNED PATTERN FORMATION FOR A SEMICONDUCTOR DEVICE

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described. 1. A method of forming vias , the method comprising:providing a semiconductor wafer in which front end of line (FEOL) processing has been completed;depositing a hard mask on an optical planarization layer (OPL);forming a first layer with one or more mandrels on the hard mask;placing a non-mandrel material between each of the one or more mandrels;depositing an etch stop layer over the first layer of one or more mandrels;forming a second layer with one or more mandrels on the etch stop layer;etching the non-mandrel material that is not covered by the second layer; andremoving the one or more mandrels of the first layer and the one or more mandrels of the second layer down to the hard mark to form a pattern in the hard mask.2. The method of claim 1 , wherein each mandrel on the first layer of one or more mandrels is parallel to each other.3. The method of claim 2 , wherein each mandrel on the second layer of one or more mandrels is parallel to each other and orthogonal to each mandrel on the first layer of one or more mandrels.4. The method of further comprising:forming one or more vias based on the pattern in the hard mask.5. The method of claim 1 , wherein:forming the first layer of one or more mandrels on the hard mask further comprises forming spacers next to each of the one or more mandrels.6. The method of claim 5 , wherein:forming the second layer of one or more mandrels on the hard mask further comprises forming spacers next to each of the one or more mandrels.7. The method of claim 6 , wherein the spacers are formed of an oxide.8. The method of claim 1 , wherein the hard mask comprises ...

ENHANCED SELF-ALIGNMENT OF VIAS FOR A SEMICONDUCTOR DEVICE

A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein. 1. A method of forming vias , the method comprising:providing a semiconductor wafer in which front end of line (FEOL) processing has been completed;depositing a dielectric layer over a metal layer;depositing a hard mask over the dielectric layer;forming a lithographic pattern over the hard mask, wherein the lithographic pattern contains lines with one or more notched areas; andetching a via in one of the one or more the notched areas of the lithographic pattern.2. The method of further comprising claim 1 , etching lines based on the lithographic pattern.3. The method of wherein claim 2 , etching lines comprises etching into the dielectric layer without exposing the metal layer.4. The method of further comprising claim 2 , filling the etched vias and lines with a fill metal.5. The method of further comprising claim 4 , planarizing the semiconductor wafer such that the hard mask is removed and filled vias and lines are level with the dielectric layer.6. The method of wherein claim 4 , the fill metal is copper.7. The method of claim 1 , wherein claim 1 , the dielectric layer comprises an ultra-low-k dielectric material.8. The method of wherein claim 7 , the dielectric layer further comprises a dielectric cap below the ultra-low-k dielectric material.9. The method of wherein claim 1 , the hard mask comprises an oxide.10. The method of wherein claim 1 , forming the lithographic ...

MEMORY ARRAY STRUCTURE AND METHODS OF FABRICATING THEREOF

Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells. 1. A memory device comprising:an array of memory cells;a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via; anda word line coupled to a row of the array of memory cells.2. The memory device of claim 1 , wherein the at least one via extends from the first metal layer to the second metal layer.3. The memory device of claim 2 , wherein the at least one via is disposed on a first edge cell region of the array and wherein another via coupling the first and second bit-lines is disposed on a second edge cell region of the array claim 2 , the second edge cell region on an opposing side of the array from the first edge cell region.4. The memory device of claim 1 , wherein the at least one via is disposed at a cell boundary between cells of the array.5. The memory device of claim 1 , further comprising:a first complement bit-line coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit-line is disposed on the first metal layer;a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is coupled to the first complement bit-line at at least two locations, wherein the second complement bit-line is disposed on the second metal layer.6. The memory device of claim 1 , further comprising:a second ...

SEMICONDUCTOR DEVICE STRUCTURES

Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer. 1. A semiconductor device structure , comprising:a semiconductor substrate;an inner metal layer disposed on the semiconductor substrate;a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion; anda passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.2. The semiconductor device structure as claimed in claim 1 , further comprising:a polysilicon layer between the semiconductor substrate and the inner metal layer, wherein the polysilicon layer is not covered by the second portion of the top metal layer.3. The semiconductor device structure as claimed in claim 2 , wherein the first portion of the top metal layer is exposed by the hollowed pattern claim 2 , and the polysilicon layer is not covered by the passivation layer.4. The semiconductor device structure as claimed in claim 2 , wherein the second portion of the top metal layer is exposed by the hollowed pattern claim 2 , and the polysilicon layer is covered by the passivation layer.5. The ...

THROUGH-SILICON VIA WITH INSULATOR FILL

Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate. 1. A method of forming a conductive via , the method comprising:forming an opening in a substrate;forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening; andforming an insulating fill in a second portion of the area within the opening;wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.2. The method of claim 1 , wherein the conductive material and the insulating fill sufficiently fill the opening such that there are substantially no voids within the opening.3. The method of claim 1 , wherein the conductive material comprises a superconducting material.4. The method of claim 1 , wherein forming the conductive material comprises depositing a layer of the conductive material along the sidewall regions using physical vapor deposition (PVD).5. The method of claim 1 , wherein the at least one surface of the conductive material comprises a top landing pad.6. The method of claim 1 , wherein the opening extends through the substrate from the front surface of the substrate to a back surface of the substrate.7. The method of claim 6 , wherein:at least one second surface of the conductive material is substantially coplanar with the back surface of the substrate; andthe at least one second surface of the conductive ...

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure. 1. A package structure , comprising:a substrate;a package layer formed over the substrate; andan alignment structure formed over the package layer, wherein the alignment structure comprises a first alignment mark formed in a trench, and the trench has a step-shaped structure.2. The package structure as claimed in claim 1 , further comprising:a plurality of semiconductor dies formed over the substrate; anda package layer adjacent to the semiconductor dies.3. The package structure as claimed in claim 1 , further comprising:a scribe line between adjacent semiconductor dies, wherein the alignment structure is formed over the scribe line.4. The package structure as claimed in claim 1 , wherein each of the semiconductor dies comprises a plurality of sub-dies with a gap region between the sub-dies claim 1 , and the alignment structure is formed over the gap region.5. The package structure as claimed in claim 1 , wherein the trench has an ellipse-shaped or circle-shaped top-view profile.6. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the first dielectric layer comprises a first opening with an ellipse-shaped or circle-shaped top-view profile.7. The package structure as claimed in claim 1 , wherein the alignment structure comprises a second alignment mark formed over the package layer claim 1 , and the first alignment mark and the second alignment mark are in the same level.8. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the second alignment ...

Interconnect structure and manufacturing method for the same

The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

DAMASCENE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS

Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction. 1. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure , the method comprising:forming an inter-layer dielectric (ILD) layer above a substrate;forming a first plurality of photobuckets above the ILD layer, the first plurality of photobuckets defining all possible dielectric plug locations for the BEOL metallization layer;removing fewer than all of the first plurality of photobuckets and retaining one or more of the first plurality of photobuckets in select dielectric plug locations;forming a second plurality of photobuckets above the ILD layer, the second plurality of photobuckets defining all possible conductive tab locations for the BEOL metallization layer;removing fewer than all of the second plurality of photobuckets in select conductive tab locations and retaining one or more of the second plurality of photobuckets;subsequent to removing fewer than all of the first plurality of photobuckets and removing fewer than all of the second plurality of photobuckets, transferring an image including the select dielectric plug locations and the select conductive tab locations to the ILD layer; andforming a plurality of conductive lines, one or more dielectric plugs, and one or more conductive tabs in the ILD layer.2. The method of claim 1 , wherein the first and second pluralities of photobuckets are formed in a two-dimensional hardmask grating structure formed above the ILD layer.3. ...

INTEGRATED DEVICES COMPRISING UNIFORM METAL LAYER THICKNESS ACROSS ONE OR MORE METAL LAYERS

An integrated device that includes a substrate, a third plurality of interconnects formed on a third metal layer, a fourth plurality of interconnects formed on a fourth metal layer, at least one dielectric layer formed over the substrate. The third metal layer is located over the substrate. The third metal layer has a third pattern density. The third plurality of interconnects has a third thickness that is approximately the same for all interconnects of the third plurality of interconnects. The fourth metal layer is located over the third metal layer. The fourth metal layer has a fourth pattern density. The fourth pattern density is different than the third pattern density. The fourth plurality of interconnects has a fourth thickness that is approximately the same for all interconnects of the fourth plurality of interconnects. 1. An integrated device comprising:a substrate; wherein the third metal layer is located over the substrate,', 'wherein the third metal layer has a third pattern density;', 'wherein the third plurality of interconnects has a third thickness that is approximately the same for all interconnects of the third plurality of interconnects, and, 'a third plurality of interconnects formed on a third metal layer,'} wherein the fourth metal layer is located over the third metal layer,', 'wherein the fourth metal layer has a fourth pattern density,', 'wherein the fourth pattern density is different than the third pattern density,', 'wherein the fourth plurality of interconnects has a fourth thickness that is approximately the same for all interconnects of the fourth plurality of interconnects; and, 'a fourth plurality of interconnects formed on a fourth metal layer,'}at least one dielectric layer formed over the substrate.2. The integrated device of claim 1 ,wherein the integrated device is from a wafer comprising a plurality of integrated devices,wherein the third thickness of the third plurality of interconnects for all integrated devices from the ...

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer. 1. An integrated circuit device comprising:a first insulation layer on a substrate;a lower wiring structure in the first insulation layer and comprising a metal layer and a conductive barrier layer, wherein the metal layer is on the conductive barrier layer;an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness;a capping layer overlapping a first portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness;a second insulation layer overlapping the etch stop layer and the capping layer; andan upper wiring structure connected to a second portion of the upper surface of the metal layer not overlapped by the capping layer,wherein the upper wiring structure is in the second insulation layer, andwherein the upper wiring structure comprises a concave-convex structure contacting a portion of an upper surface of the etch stop layer, a sidewall of the etch stop layer, and the second portion of the upper surface of the metal layer.2. The integrated circuit device of claim 1 , wherein a lower surface of the second ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a substrate including a first surface;a dielectric layer disposed over the first surface of the substrate;a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate;a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line;a conductive via disposed over the first conductive line and extended through the dielectric layer; anda cross section of the conductive via substantially parallel to the first surface of the substrate,wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line.2. The semiconductor structure of claim 1 , wherein the conductive via is isolated from the second conductive line.3. The semiconductor structure of claim 1 , wherein a shortest length of the conductive via is substantially greater than a width of the first conductive line.4. The semiconductor structure of claim 3 , wherein the shortest length of the conductive via is substantially ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising: a device top surface;', 'a device bottom surface opposite to the device top surface; and', 'a device side surface extending between the device top surface and the device bottom surface;, 'an electronic device comprising a first region that extends from the device top surface in an upward direction; and', 'a second region coupled to the first region, wherein the second region extends from the first region in a lateral direction; and, 'an interconnect directly attached at the device top surface comprising a first portion of the second region is exposed from a first surface of the encapsulant;', 'a second portion of the second region is exposed from a second surface of the encapsulant; and', 'the encapsulant covers a third portion of the second region., 'an encapsulant that covers the device top surface, the device side surface, and a periphery of the first region, wherein2. The semiconductor device of claim 1 , wherein:the interconnect comprises a severed leadframe lead;the lateral direction is substantially parallel to the device top surface; andthe second portion extends to overlap the device side surface so as to extend outside a perimeter of the electronic device.3. The semiconductor device of ...