Integrierte Schaltung und Verfahren zu ihrer Prüfung

Das erfindungsgemäße Prüfverfahren eignet sich zum Prüfen wenigstens einer integrierten Schaltung (IC), die auf einer Hauptfläche Kontaktflächen (P) aufweist, die während einer ersten Betriebsart der Schaltung der Übertragung von Signalen dienen. Es wird nur ein Teil der Kontaktflächen (P) mit Prüfkontakten (T) eines Prüfgerätes kontaktiert, und die Schaltung in eine zweite Betriebsart versetzt, in der die in der ersten Betriebsart über wenigstens eine (1) der nicht kontaktierten Kontaktflächen übertragenen Signale über wenigstens eine der kontaktierten Kontaktflächen (2) übertragen werden.

PROCEDURE AND TEST INTERFACE FOR EXAMINING DIGITAL CIRCUITS

VERTEILTER LOGIK-ANALYSATOR FÜR EIN HARDWARE- LOGIKEMULATIONSSYSTEM

CROSS-COUPLED CHECKING CIRCUIT

Method and apparatus for on-chip monitoring of integrated circuits with a distributed system

LARGE SCALE INTEGRATED CIRCUIT WITH EXTERNAL INTEGRAL ACCESS TEST CIRCUITRY AND METHOD

A large scale integrated circuit with external integral access test circuitry having a semiconductor body with a surface. A large scale integrated circuit is formed in the semiconductor body through the surface and comprises a large number of interconnected circuit elements with a large number of input and output pads connected to the circuit elements and disposed near the outer perimeter of the semiconductor body. An integrated test circuit is formed in the semiconductor body and extends through the surface. The integrated test circuit has a plurality of probe pads carried by the semiconductor body and connected to the test circuit. The integrated test circuit is formed external of but in relatively close proximity to the large scale integrated circuit. Leads are provided on the semiconductor body which connect the integrated test circuit to the large scale integrated circuit whereby access can be obtained to the large scale integrated circuit through probing of the probe pads of the integrated ...

LARGE SCALE INTEGRATED CIRCUIT WITH EXTERNAL INTEGRAL ACCESS TEST CIRCUITRY AND METHOD

MONOLITHICALLY INTEGRATED SEMICONDUCTOR ELEMENTS

CIRCUIT INTEGRATING PUSHED WITH an EXTERNAL TEST LOOP HAS INTEGRAL ACCESS

Non-intrusive monitoring and control of integrated circuits

A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Circuit arrangement for testing integrated circuit components

A circuit arrangement is provided for testing circuit components which are formed as integrated circuits on a common base plate and operable at the base plate by way of common feed lines and input lines. In the circuit arrangement, a testing circuit and switching stages are formed on the same base plate as integrated circuits, the switching stages are controllable by the testing circuit and inserted in connecting lines for connecting the testing circuit to the circuit components, and the testing circuit is equipped with an output circuit for delivering test results. The testing circuit is arranged for testing of the components without any other connections as the power supply connections. This self-testing is achieved by means of a central unit of the testing circuit by comparing of actual and desired values, distinguishing between faulty and faultless components and deciding of the respective functionality of the components in time sequence.

Testing integrated circuit pad input and output structures

Digital integrated circuit testable input/output pad logic includes modified output driver logic and a latch for storing a test bit provided externally at the I/O pad terminal. The output driver logic selects either the normal pad output signal (O) for output during normal operation, or the stored test bit (S) or its complement (S') for output during a test operation. The output driver logic and latch are controlled by control logic signals (DP,SP,NDN,LS,NLS,NSN) derived from common tri-state (NTR) and latch (NTM) test signals provided externally at dedicated test pins (NTR,NTM). The control logic signals are provided over a bus to all similar testable I/O pads for testing all testable I/O pads within the IC under control of the two test signals.

Method for testing a test architecture within a circuit

A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.

Error detection in stored data values

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.

Communication interface for diagnostic circuits of an integrated circuit

An integrated circuit including diagnostic circuitry having serial scan chains or debug bus access circuits for establishing communication using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals. The serial protocol provides for a pacing signal for indicating to the external diagnostic device when it is ready to receive more data and/or when it has completed a particular diagnostic operation. This provides a self-pacing ability. A training signal generated by the external diagnostic device is detected by the interface circuit on initialization and used to derive sampling point timings.

Connecting multiple test access port controllers on a single test access port

Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register ( 212 ) of each of a plurality of TAP controllers ( 102, 106 ), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

Testing head having cantilever probes

The invention relates to a testing head (10) having cantilever probes, comprising at least one backing ring (12) to which a resin holder (13) is attached to hold a plurality of contact probes (14), the probes being formed with contact tips (16) suitable to mechanically and electrically contact a plurality of contact pads (17) of at least one device (11) to be tested. Advantageously according to the invention, the holder (13) has at least one outline which is suitably shaped in correspondence to the device (11) to enable different probe rows to emerge in a cantilever manner.

Verfahren zum Testen eines integrierten Schaltkreises

Es werden ein Verfahren zum Testen eines integrierten Schaltkreises (100) und ein integrierter Schaltkreis (100) vorgestellt. Der integrierte Schaltkreis (100) weist eine interne Teststruktur, auf die über einen internen Testzugangsanschluss (106) zugegriffen werden kann, und einen Steuerbus (110), der über Steueranschlüsse (108) nach außen geführt ist, auf, wobei zwischen einem Fahrbetrieb und einem Testbetrieb umgeschaltet werden kann, so dass im Testbetrieb über die Steueranschlüsse (108) und den Steuerbus (110) ein Zugriff auf den Testzugangsanschluss (106) und damit ein Testen des integrierten Schaltkreises (100) erfolgt.

INTEGRIERTE HALBLEITERSCHALTUNG MIT TESTSCHALTUNG.

Reconfiguring debug circuitry

Semiconductor device with test structure

A semiconductor device includes as part of the integrated circuit thereof a test structure which allows testing of the semiconductor device through the device pins, to allow adjustment of various parameters of the circuit if desired for obtainment of optimum performance, and with the circuit being operable under normal conditions without degradation in relation to its optimum design situation.

MONOLITHICALLY INTEGRATED SEMICONDUCTOR ELEMENTS

... 1503935 Semi-conductor devices ROBERT BOSCH GmbH 21 Feb 1975 [22 Feb 1974] 7275/75 Heading H1K A monolithically integrated semi-conductor device constituted by a number of similar component elements connected in parallel includes facilities for enabling faults in the individual components to be detected during manufacture and the faulty components to be isolated. Though the device may be a diode, thyristor, triac &c. as described, it is a transistor which in one embodiment includes measuring resistors and fuses in the leads to the emitter, base and collector of each component transistor. In alternative embodiments the measuring resistors in the emitter leads may additionally serve as equalizing resistors. Where certain faults have a higher incidence than others the resistors and/or fuses need be provided in only some of the leads. Also the dual role of measuring resistor and fuse may be served by a single element, e.g. a resistive strip of chrome-nickel or a necked portion of the interconnecting ...

CIRCUITS INTEGRATED AUTOMATIC SCANNING EXAMINATION OF COMPLEXES

ELECTRONIC CIRCUIT WITH A SECRET ONE SUBMODUL

INTEGRATED CIRCUIT WITH SIGNATURE COMPUTATION

CIRCUITS FOR THE PREVENTION OF MAXIMUM PERFORMANCE PROBLEMS DURING THE SCAN SHIFT

PROCEDURE AND DEVICE FOR THE DIAGNOSIS OF LOSSES IN AN INTEGRATED CIRCUIT USING TECHNIQUES OF THE TYPE DESIGN FOR DEBUG (DFD)

DISTRIBUTED LOGIC ANALYZER FOR USE IN A HARDWARE LOGIC EMULATION SYSTEM

A hardware emulation system is disclosed which reduces hardware cost by timemultiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

TEST LOOP AND IN SITU DIAGNOSIS AND APPLICABLE PROCESS HAS JUST LOGICAL CIRCUITS FUNCTIONING IN MODE OF CURRENT

Test card and tester for testing one or more devices under test and method for communicating with devices under test

Interface between IC operational circuitry for coupling test signal from internal test matrix

A programmable interface apparatus between a first circuit and either a second operational circuit, or a primary pin, of an IC includes a latch for receiving a test signal. The latch is controlled using probe lines and sense lines from an internal test matrix. In one configuration, such an interface is programmably configured to couple either a primary input signal or a test signal to the operational circuitry. In another configuration, such an interface is programmably configured to couple either an operational circuit signal or a test signal to a primary output pin. In still another configuration, such an interface is programmably configured to couple either an operational circuit signal or a test signal to an operational circuit element. In one embodiment, the interface is formed with a pair of transmission gates, the latch and an invertor. An advantage of such structure is the minimal IC area required. A global control signal is coupled to each transmission gate for configuring the ...

Buffer testing for reconfigurable instruction cell arrays

A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Built-in self-testing for double data rate input/output

Macro cells for a Double Data Rate (DDR) I/O interface are provided. The macro cells feature built-in self-test (BIST) functionality for testing the I/O interface at speed, without using external test or evaluation equipment. Each input or output macro cell is configured to generate test signals that are submitted to and processed by the I/O interface. The test signals are then dynamically compared to the signals produced by the interface in response to the test signals and a result is generated. The result may comprise an error signal if the test and response signals do not correspond. An I/O BIST controller may be employed to control the initiation and operation of the macro cells' self-testing.

Self test of core with unpredictable latency

A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received ...

SEMICONDUCTOR INTEGRATED CIRCUIT AND INSPECTION METHOD THEREFOR

PURPOSE: To test a high-speed interface part of LSI by using a high-speed SLI tester, having a minimum number of pins less than the number of all function terminals of the LSI to be inspected. CONSTITUTION: A selector 24 brings the input data of a high-speed interface back to an output part through a loop. An FIFO buffer 16 temporarily stores loop-back data. A sequencer 17 controls the loop-back operation. These parts are provided. Thus, the data inputted from the high-speed interface part are brought back to the high-speed interface part as the output data by way of the loop, and the testing is performed with an LSI tester. COPYRIGHT: (C)1996,JPO ...

Программно-временное и маршрутизирующее устройство бортовой аппаратуры командно-измерительной системы

Полезная модель относится к вычислительной технике и может найти применение в бортовой аппаратуре командно-измерительной системы для управления космическими аппаратами. Заявленная полезная модель позволяет применять с минимальными доработками существующую бортовую аппаратуру командно-измерительной системы в перспективных космических аппаратах, использующих интерфейсы и протоколы высокоскоростного межприборного информационного обмена и комплексирования бортовых систем космических аппаратов SpaceWire. Предложенный интерфейс может быть использован для приёма технологических команд и команд управления программно-временным и маршрутизирующим устройством. Программно-временное и маршрутизирующее устройство, содержащее программируемую логическую интегральную схему с использованием сложного функционального блока SpaceWire, маршрутизатор SpaceWire и блок выдачи временных меток, соединено с декодером командно-программной и телеметрической информации, бортовым синхронизирующим устройством, бортовым ...

ИНТЕРФЕЙС СВЯЗИ ДЛЯ ДИАГНОСТИЧЕСКИХ СХЕМ ИНТЕГРАЛЬНОЙ СХЕМЫ

... 1. Интегральная схема для обработки данных, содержащая функциональную схему, выполненную с возможностью исполнения операций по обработке данных; диагностическую схему, выполненную с возможностью исполнения диагностических операций в отношении функциональной схемы; и интерфейсную схему, выполненную с возможностью обеспечения связи между диагностической схемой и внешним диагностическим устройством; при этом интерфейсная схема использует двунаправленный последовательный сигнал для передачи управляющих сигналов от внешнего диагностического устройства на диагностическую схему для управления диагностическими операциями диагностической схемы; и диагностических данных между внешним диагностическим устройством и диагностической схемой; причем интерфейсная схема выполнена с возможностью функционирования в режиме обучения, реагируя на обучающий сигнал заранее определенной формы, посылаемый от внешнего диагностического устройства с использованием двунаправленного последовательного сигнала, для определения ...

Integrierte Schaltung und Verfahren zu ihrer Prüfung

AUTOMATISCHE GENERIERUNG VON ANWENDERDEFINIERBAREM SPEICHER-BIST-KREISLAUF

HALBLEITERBAUELEMENT

Development of integrated circuits

Integrated circuits such as "Systems on Silicon" are developed by production of integrated software and hardware specification and block models. Each block model relates to an entity having its own inputs, outputs and functionality. Test vectors are generated at this stage having stimuli applicable to all model levels. The same model code is used throughout to develop a gate-level model which is tested using the previously-generated test vectors lead times are shorter because of the integrated approach.

Enabling multiple testing devices

Reconfiguring debug circuitry

A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip comprises the debug unit collecting 601 debug data of the peripheral circuit and outputting 602 the debug data in a message stream. The debug unit receives a debug reconfiguration command 603 and in response transmits an indication of the current debug configuration 606, before reconfiguring 607 the debug configuration to a new debug configuration in accordance with the debug reconfiguration command. The debug unit then transmits an indication of the new debug configuration 609. The indication of the current debug configuration 606 and the indication of the new debug configuration 609 are transmitted adjacent to the debug data 604, 610 in the message stream. The method is used for reconfiguring a debug unit associated with e.g. a processor in a system on chip (SoC) integrated circuit.

In-situ test and diagnostic circuitry and method for CML chips

An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

SWITCHING CONFIGURATION FOR EXAMINING INTEGRATIONS CIRCUIT UNITS.

PROCEDURE FOR THE DETERMINATION OF THE PRESENT WAY BACK INTEGRITY IN AN ELECTRICAL MECHANISM, WHICH IS WITH OF A FURTHER MECHANISM GROUP OR CONNECTABLE

TEST ENTRANCE HAVEN SWITCH

ELECTRONIC ONE STREAM VERARBEITUNGSSCHALTUNG WITH TEST ENTRANCE

An electronic circuit with test unit and a method for testing interconnects between an electronic circuit with test unit and a further electronic circuit

A test arrangement for testing the interconnections of an electronic circuit (100) and a further electronic circuit is provided. A first selection of I/O nodes (120), which are arranged to receive input data in a functional mode of the electronic circuit (100), and which are coupled to a test unit in a test mode of the electronic circuit (100). The test unit has a combinatorial circuit (160) for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes (120) and a second selection of I/O nodes (130) via logic gates (141-144). These interconnections increase the interconnect test coverage of the electronic device (100), because the interconnects with the further electronic circuits that are associated with I/O nodes (131-134) become testable as well.

Very large scale integrated circuit

A monolithically very large scale integrated circuit (VLSI) having any arbitrarily given structure and an internal test circuit only requiring one, two or three additional outer terminals wherein the test circuit is integrated therein. In one embodiment the test circuit contains a counter and a combinational circuit interconnected with the counter reading outputs thereof as well as selection switches associated with test points and where the first of the additional terminals is connected to the counting input of the counter.

Clock synchronizing circuit and method of designing the same

The clock synchronizing circuit is provided with many sequential circuits which operate on the basis of same clock signal. The sequential circuits carries out sampling of input data and changing of output data at both rising and falling edge of the clock signal. The sequential circuits include input selector circuit which select either of two inputs in accordance with a test mode signal. Output of one sequential circuit is input into an input selector circuit of subsequent sequential circuit. Thus, a series of scan pass SP is formed.

Programmable output polarity devices

Disclosed is an apparatus for generating an output signal having a selected output polarity. The apparatus comprises a sensing means for generating a logic signal upon occurrence of an event. Also, a programmable means generates a programmable signal indicating a selected output polarity. The logic signal and the programmable signal are received by polarity setting means for producing an output signal equal to the logic signal with the selected output polarity. Also disclosed is a testing means for temporarily forcing the programmable signal to indicate a selected output polarity for testing.

Circuit arrangement for testing integrated circuits

TEST METHOD AND DEVICE FOR INPUT AND OUTPUT STRUCTURE OF INTEGRATED CIRCUIT PAD

PURPOSE: To test the input and output pad logic of an integrated circuit without any need of a complicated test pattern test procedures by providing a modified output driver logic. CONSTITUTION: AND gates 60 and 62 forming an OAI circuit 66 and a NOR gate 64 are substituted for an ordinary P-type driver logic, or a logic for controlling a P-type driver transistor gate. In addition, NOR gates 80 and 82 forming an OAI circuit 86 and a NAND gate 84 are substituted for an N-type driver logic. Furthermore, the novel output driver logic so formed selects an ordinary pad output signal O during an ordinary operation for transmission to a terminal, and during a test operation, an I/O terminal is kept in a tri-state. Also, test bits S (or complement bits S' thereof) latched for transmission to the terminal are selected after test bits are latched. The output driver logic is further controlled with logic signals on a bus 50. COPYRIGHT: (C)1995,JPO ...

Verfahren zur automatischen Konfiguration von programmierbaren Bausteinen, elektronische Baugruppenanordnung, Röntgendetektor und Computertomographiesystem

Verfahren zur automatischen Konfiguration von programmierbaren Bausteinen (Dev0, Dev1, ..., Dev23) zumindest einer elektronischen Baugruppe (SBP, MBP1, MBP2, ..., MBP23), bei dem die zu programmierenden Bausteine (Dev0, Dev1, ..., Dev23) über eine Konfigurations-Verschaltungseinheit (CM) mit einer Konfigurationssteuereinheit (JC) verschaltet werden, und dann mittels der Konfigurationssteuereinheit (JC) Konfigurationsdaten (CD) an die programmierbaren Bausteine (Dev0, Dev1, ..., Dev23) übermittelt werden, wobei der Konfigurations-Verschaltungseinheit (CM) ein Verbindungszustandsindikator (CI1, ..., CI23) signalisiert wird, ob eine elektronische Baugruppe (SBP, MBP1, MBP2, ..., MBP23) mit einem programmierbaren Baustein (Dev0, Dev1, ..., Dev23), mit der Konfigurations-Verschaltungseinheit (CM) physisch verbunden ist, und die Konfigurations-Verschaltungseinheit (CM) die programmierbaren Bausteine (Dev0, Dev1, ..., Dev23) in Abhängigkeit von den Verbindungszustandsindikatoren (CI1, ..., CI23 ...

Testing integrated circuits

An integrated circuit arrangement comprises a circuit (2) with first resistances (r2, r3, r4) in series with a plurality of input connections (P2, P3, P4), a tristate logic (TR2, TR3, TR4) associated with each connection and further resistances (R2, R3, R4) between each connection and each logic device, means (D) causing each logic device to be operated between a normally high impedance state and two different potential states and a comparator (C) monitoring the potential of each of the connections (P2, P3, P4) corresponding to each of the different potential states and affording a fault indication if a fault exists in the circuit (2). ...

SEMICONDUCTOR DEVICE WITH TEST STRUCTURE

TESTS OF ELECTRONIC CIRCUITS

ELECTRONIC CIRCUIT WITH TEST UNIT FOR THE EXAMINATION OF FEEDER LINES

BOUNDARY SCAN CIRCUIT WITH INTEGRATED SENSOR FOR THE MEASUREMENT OF PHYSICAL OPERATING PARAMETERS

SYSTEM AND PROCEDURE FOR TESTING SIGNAL CONNECTIONS USING AN INSERTED SELF CHECK FUNCTION

CONNECTION OF SEVERAL TEST ACCESS HAVEN PRICE INCREASE DEVICES BY A SINGLE TEST ACCESS HAVEN

BOUNDARY SCAN CIRCUIT WITH INTEGRATED SENSOR FOR SENSING PHYSICAL OPERATING PARAMETERS

INTEGRATED CIRCUITS

Circuit testing arrangement and approach therefor

A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit 332 having logic circuitry that processes data in response to an operational clock signal 308 having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock 309 having several clock-state transitions that occur during at least one clock period of the operational clock 308. An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers 340 that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Integrated parity-based testing for integrated circuits

An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.

TESTING EMBEDDED CIRCUITS WITH THE AID OF A SEPARATE SUPPLY VOLTAGE

Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected ...

Reconfigurable fabric for SoCs

An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same

A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

Dual mode ASIC BIST Controller

A method and apparatus for performing a built-in self-test ("BIST") (100) on an integrated circuit device (150) are disclosed. More particularly, in a first aspect, a dual mode BIST controller comprises both a logic built-in self-test ("LBIST") domain (160) and a memory built-in self-test ("MBIST") domain (170). The LBIST domain (160) includes a LBIST engine (110) capable of executing a LBIST and storing the results thereof and a multiple input signature (130) register ("MISR"). The MBIST domain (170) includes a MBIST engine (120) capable of executing a MBIST. In a second aspect, the invention includes a method for performing a BIST on an integrated circuit device. The method comprises externally resetting a dual mode BIST controller; performing at least one of a LBIST and a MBIST from the dual mode BIST controller; and obtaining the results of the performed BIST.

Test of circuits with Schmitt inputs

An integrated circuit in which Schmitt input circuits can be tested in a short time and a high accurate test result can be obtained. The integrated circuit comprises switches each supplying outputs of Schmitt inverters connected to input-output ports to tristate circuits connected to adjacent input-output ports without supplying the outputs to internal logical circuit, and a switch supplying an output of the Schmitt inverter to the tristate circuit during the test of the Schmitt inverter, whereby half Schmitt inverters can be tested when predetermined control signals are supplied to each switch and each tristate circuit. ...

Testing integrated circuit pad input and output structures

Halbleiterbaustein mit einer Anordnung zum Selbsttest einer Mehrzahl von Interfaceschaltungen und Testverfahren

Ein Halbleiterbaustein mit einer Mehrzahl von Interfaceschaltungen weist eine Anordnung zum Selbsttest von Interfaceschaltungen auf, welche umfaßt DOLLAR A - zwei gleich große Gruppen von Interfaceschaltungen (12a, 12b, 14a, 14b), derart, daß jeder Interfaceschaltung der ersten Gruppe (12a, 12b) genau eine Interfaceschaltung der zweiten Gruppe (14a, 14b) zugeordnet ist; DOLLAR A - eine mit der ersten Gruppe (12a, 12b) zusammenwirkende Schaltung (32a, 32b) zur Erzeugung von über die Interfaceschaltungen der ersten Gruppe (12a, 12b) ausgebbaren Testsignalen; DOLLAR A - eine mit der zweiten Gruppe (14a, 14b) zusammenwirkende Schaltung (30) zum Empfangen und Verarbeiten von über die Interfaceschaltungen der zweiten Gruppe (14a, 14b) empfangenen Testsignalen, so daß eine Verbindung (52, 54) der zugeordneten Interfaceschaltungen der ersten und zweiten Gruppe einen Selbsttest ermöglicht, wobei die erste und zweite Gruppe von Interfaceschaltungen eine getrennte Spannungsversorgung (18, 19) aufweisen ...

Anordnung zum Testen eines integrierten Schaltkreises

VERBINDUNG MEHRERER TESTZUGRIFFSPORTSTEUERUNGSVORRICHTUNGEN DURCH EIN EINZELTESTZUGRIFFSPORT

SYSTEM UND VERFAHREN ZUM TESTEN VON SIGNALVERBINDUNGEN UNTER VERWENDUNG EINER EINGEBAUTEN SELBSTTESTFUNKTION

IMPROVEMENTS IN OR RELATING TO IN-CIRCUIT TESTING

Reconfiguring debug circuitry

Development of integrated circuits

Built-in self-testing for double data rate input/output interface

ELECTRONIC CIRCUIT WITH TEST UNIT

SEMICONDUCTOR COMPONENTS

Integrated circuit and associated packaged integrated circuit

INTERFACE OF EXIT OF BINARY DATA

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME

Electronic circuit with test unit

A test arrangement for testing the interconnections of an electronic circuit (100) and a further electronic circuit is provided. A first selection of I/O nodes (120), which are arranged to receive input data in a functional mode of the electronic circuit (100), and which are coupled to a test unit in a test mode of the electronic circuit (100). The test unit has a combinatorial circuit (160) for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes (120) and a second selection of I/O nodes (130) via logic gates (141-144). These interconnections increase the interconnect test coverage of the electronic device (100), because the interconnects with the further electronic circuits that are associated with I/O nodes (131-134) become testable as well.

Integrated circuit with embedded identification code

An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the plurality of outputs (120). The logic gates from the plurality of logic gates (140) have a first input coupled to an input of the plurality of inputs (110) and a further input coupled to a fixed logic value source (150). The fixed logic value source (150) is used to define an identification code of the integrated circuit (100), which can be retrieved at the plurality of outputs (120) when an appropriate bit pattern is fed to the plurality of inputs (110).

Scheme for masking output of scan chains in test circuit

Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.

METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION

A method is provided for testing a portion of a system under test via a scan chain of the system under test. The method includes decomposing the scan chain into a plurality of segments, generating a set of instructions for testing the portion of the system under test, and executing the set of instructions for testing the portion of the system under test. The scan chain is composed of a plurality of elements, and each segment includes at least one of the elements of the scan chain. The set of instructions includes a plurality of processor instructions associated with an Instruction Set Architecture (ISA), and a plurality of test instructions. The test instructions include, for each of the plurality of segments of the scan chain, at least one scan operation to be performed on the segment. An associated apparatus also is provided.

Methodology to test pulsed logic circuits in pseudo-static mode

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

Method and apparatus for testing digital circuitry

Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back is effected from the first buffered data output to a buffered control input, from a buffered control output to the first buffered data input, or both. Advantageously, the buffering is associated to executing a conversion between a digital full swing internal signal and an analog low swing external signal with respect to core circuitry of the digital circuitry.

System and method for testing signal interconnections using built-in self test

A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system. A master ...

Integrated circuit with a test fucntion and test arrangement for testing an integrated circuit

Integrated circuit with test facility has test switch closed by applied test signal to allow test voltage to be applied to irreversible programmable switches The integrated circuit (2) is coupled to a testing device (1) for function testing, with contact pads (31,32) for connection to the supply voltage (VDD,VSS) and a test contact pad (36) coupled to a switch (38), which is closed in response to an applied test signal (TEST), for coupling the test voltage to irreversible programmable switches (42,43), e.g. fuses. An Independent claim for a test device for an integrated circuit is also included.

METHOD FOR TESTING INTEGRATED CIRCUIT

PURPOSE: To efficiently perform AC test of an integrated circuit inside the integrated circuit. CONSTITUTION: Although a register 3 sets an NAD(next address) from outside via a selector 2 during normal operation, it sets a value of an increment circuit 4 at an interval of ENB signals with a rise of ϕ (N) during a test. A memory 5 admits an output from the register 3 and outputs corresponding data. A register 7 sets output data from the memory 5 at an interval specified from an NDTSET signal during normal operation and at an interval of a reversed ENB signal with a rise of ϕ (F) at the time of test. A mismatch detecting circuit 8 compares correct value data output from the memory 5 with contents of the register 7. An SR-F/F 11 holds a mismatch signal when mismatch is detected by the mismatch detecting circuit 8 at an interval of an ENB signal with a rise of ϕ (N). COPYRIGHT: (C)1993,JPO&Japio ...

SCHALTUNGSANORDNUNG ZUM TESTEN INTEGRIERTER SCHALTUNGEN

Halbleiterbaustein mit einer Anordnung zum Selbsttest einer Mehrzahl von Interfaceschaltungen und Verwendung des Halbleiterbausteins in einem Testverfahren

Halbleiterbaustein mit einer Anordnung zum Selbsttest einer Mehrzahl von bidirektional arbeitenden Interfaceschaltungen, welche umfaßt - zwei gleich große Gruppen von Interfaceschaltungen (12a,12b,14a,14b; 112,114), derart daß jeder Interfaceschaltung der ersten Gruppe (12a,12b; 112) genau eine Interfaceschaltung der zweiten Gruppe (14a,14b; 114) zugeordnet ist, - jeweils eine elektrische Verbindung (52,54; 152,154) der einander zugeordneten Interfaceschaltungen der ersten und zweiten Gruppe außerhalb des Bausteins, um einen Selbsttest zu ermöglichen; - eine mit der ersten Gruppe (12a,12b; 112) zusammenwirkende Schaltung (32a,32b; 132) zur Erzeugung von mittels Multiplexer einkoppelbaren Testsignalen, die über die Interfaceschaltungen der erste Gruppe (12a,12b; 112) ausgebbar sind; - eine mit der zweiten Gruppe (14a,14b; 114) zusammenwirkende Schaltung (30; 130) zum Empfangen und Verarbeiten von über die Interfaceschaltungen der zweiten Gruppe (14a,14b; 114) empfangenen Testsignale; und ...

Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher

Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher

Testverfahren und Testvorrichtung zum Testen einer integrierten Schaltung

Es werden ein Testverfahren und eine Testvorrichtung zum Testen einer integrierten Schaltung bereitgestellt, wobei auf ein hardwaretechnisches Vorsehen der Boundary-Scan-Zellen in der Testvorrichtung verzichtet wird. Dagegen werden die Boundary-Scan-Zellen erfindungsgemäß durch ein Boundary-Scan-Programm nachgebildet. Sämtliche Funktionalitäten der Kette an Boundary-Scan-Zellen und des TAP-Interfaces sind durch den Einsatz des Boundary-Scan-Programms, welches durch eine die integrierte Schaltung steuerbare, programmgesteuerte Steuereinrichtung ausgeführt wird, erfüllt.

Адаптер тестирования канала оперативной памяти третьего поколения

Полезная модель относится к области испытательной техники и может быть использована для проведения испытаний на работоспособность каналов синхронной динамической памяти с произвольным доступом и удвоенной скоростью передачи данных третьего поколения в материнских платах компьютерной техники.Техническим результатом является расширение функциональных возможностей за счет обеспечения тестирования DIMM разъемов памяти третьего поколения.Адаптер тестирования канала оперативной памяти третьего поколения содержит семь штыревых соединителей, один двусторонний DIMM соединитель, девять перемычек и программируемую логическую интегральную схему, содержащую внутренний JTAG интерфейс.1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 189 608 U1 (51) МПК G11C 29/56 (2006.01) G01R 31/317 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G11C 29/56 (2019.02); G01R 31/318533 (2019.02) (21)(22) Заявка: 2019110382, 09.04.2019 (24) Дата начала отсчета срока действия патента: Дата регистрации: 29.05.2019 (73) Патентообладатель(и): Акционерное общество "МЦСТ" (RU) (45) Опубликовано: 29.05.2019 Бюл. № 16 (56) Список документов, цитированных в отчете о поиске: US 7730369 B2, 01.06.2010. EP (54) Адаптер тестирования канала оперативной памяти третьего поколения (57) Реферат: Полезная модель относится к области счет обеспечения тестирования DIMM разъемов испытательной техники и может быть памяти третьего поколения. использована для проведения испытаний на Адаптер тестирования канала оперативной работоспособность каналов синхронной памяти третьего поколения содержит семь динамической памяти с произвольным доступом штыревых соединителей, один двусторонний и удвоенной скоростью передачи данных третьего DIMM соединитель, девять перемычек и поколения в материнских платах компьютерной программируемую логическую интегральную техники. схему, содержащую внутренний JTAG интерфейс.1 Техническим результатом является ил. расширение функциональных ...

Scan test method and apparatus

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Method and apparatus for device access port selection

The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Apparatus and system for implementing variable speed scan testing

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Design-for-test technique to reduce test volume including a clock gate controller

Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.

Dual mode test access port method and apparatus

Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Test apparatus

A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer.

Method and apparatus for deferred scheduling for jtag systems

A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

Integrated circuit having a scan chain and testing method for a chip

An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.

Serial i/o using jtag tck and tms signals

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Integrated circuit with jtag port, tap linking module, and off-chip tap interface port

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

At-speed scan enable switching circuit

A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.

Removable and replaceable tap domain selection circuitry

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Semiconductor integrated circuit and power-supply voltage adaptive control system

A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

Selectable jtag or trace access with data store and output

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Two-Dimensional Scan Architecture

Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Method and Apparatus for Fault Injection

The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.

Circuit for Securing Scan Chain Data

Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Test Generator For Low Power Built-In Self-Test

Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.

Optimized jtag interface

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Semiconductor device

A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

Fault mode circuits

A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.

Selectively accessing test access ports in a multiple test access port environment

A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).

Selectable jtag or trace access with data store and output

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Semiconductor integrated circuit, scan flip-flop, and test method of semiconductor integrated circuit

A semiconductor integrated circuit according to an aspect of the invention includes scan flip-flops and a scan control unit. The scan flip-flop outputs backup data that is held as an internal state under control of the scan control unit, and the scan flip-flop holds backup data output from the scan flip-flop in the scan flip-flop under control of the scan control unit.

Clock Control of Pipelined Memory for Improved Delay Fault Testing

In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.

On-Die Logic Analyzer For Semiconductor Die

In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Scan Chain Fault Diagnosis

Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Method for testing an integrated circuit

A method for testing an integrated circuit and an integrated circuit. The integrated circuit has an internal testing structure which may be accessed via an internal test access port and a control bus which is conducted to the outside via control ports, it being possible to switch over between a running mode and a test mode so that, in the test mode, the test access port is accessed via the control ports and the control bus, thus testing the integrated circuit.

Dynamically self-reconfigurable daisy-chain of tap controllers

A self-reconfigurable daisy-chain of TAP controllers includes a main TAP controller and one or more auxiliary TAP controllers. The daisy-chain is dynamically self-reconfigurable in that the main TAP controller can configure and reconfigure the daisy-chain multiple times during the testing of a circuit. A data register within the main TAP controller is associated with a special JTAG instruction. This instruction is usable to enable and disable selected individual ones of the auxiliary TAP controllers. If an auxiliary controller is enabled, then it is made a part of the TDI-to-TDO daisy-chain scan path. If the auxiliary controller is disabled, then it is not a part of the daisy-chain scan path. A disabled controller and its registers are not, however, reset. A disabled controller can continue to supply test signals to the circuit under test. Using this mechanism, test time can be reduced by reducing the amount of shifting through slow controllers.

Critical-path circuit for performance monitoring

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

On-Die Logic Analyzer For Semiconductor Die

In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Self-reparable semiconductor and method thereof

A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals.

Boundary scan path method and system with functional and non-functional scan cell memories

An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power

This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.

Boundary scan chain for stacked memory

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

High performance compaction for test responses with many unknowns

A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m<N) and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies is provided.

SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs

A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Selectively accessing test access ports in a multiple test access port environment

A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).

Position independent testing of circuits

Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Ic output signal path with switch, bus holder, and buffer

An electronic integrated circuit includes a signal path connected between the functional logic ( 15 ) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit ( 121 B), and an output buffer ( 19 ).

Scan response reuse method and apparatus

The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Hierarchical access of test access ports in embedded core integrated circuits

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Circuit And Method For Simultaneously Measuring Multiple Changes In Delay

A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits.

Method and Apparatus for Diagnosing an Integrated Circuit

System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determine the location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure.

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Test compression in a jtag daisy-chain environment

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Method and Device For Reconstructing Scan Chains Based On Bidirectional Preference Selection in Physical Design

Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information.

System and method for electronic testing of partially processed devices

Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Die Attach Pick Error Detection

Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Apparatus and Method for Clock Glitch Detection During At-Speed Testing

A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Adapting scan-bist architectures for low power operation

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS

An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. 1. An integrated circuit comprising:{'b': '1', 'A. a TD input lead, a TCK input lead, a TMS input lead, and a TDO output lead;'}{'b': 11', '1', '1', '1, 'B. a TD output lead, a TCK output lead, a TMS output lead, and a TDO input lead;'} i. a register coupled between the TDO input lead and the TDO output lead and having an Enable1 output; and', {'b': 1', '1, 'ii. gating circuitry having inputs coupled to the TCK input lead and the TMS input lead, enable1 inputs coupled to the Enable1 output, and outputs coupled to the TCK output lead and the TMS output lead.'}], 'C. TAP linking module circuitry including2. The integrated circuit of in which the TAP linking module circuitry includes decode circuitry having inputs connected to the Enable1 output of the register and enable outputs connected to the enable inputs of the gating circuitry.3. The integrated circuit of in which the TAP linking module circuitry includes a TAP state machine having inputs connected to the TCK input lead and to the TMS input lead claim 1 , and having state outputs coupled to the register.41. The integrated circuit of in which the TAP linking module circuitry includes multiplexer circuitry having an input coupled to the TDO input lead and an output coupled to the TDO output lead. ...

System and method for sharing a communications link between multiple communications protocols

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES

Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design. 1. A method for developing a scan-based test design for an integrated circuit design , comprising the steps of:developing a plurality of candidate test designs for the circuit design, including using a computer system, generating a plurality of test vectors in dependence upon the circuit design;using a computer system, generating a test protocol figure of merit for each of the candidate test designs; andselecting, in dependence upon a comparison among the test protocol figures of merit generated for each of the candidate test designs, one of the candidate test designs for implementation in an integrated circuit device,wherein generating a plurality of test vectors employs an automatic test pattern generation algorithm,and wherein the plurality of candidate test designs include differing configuration parameter values for controlling the operation of the automatic test pattern generation algorithm.2. The method of claim 1 , wherein the plurality of candidate test designs further includes:differing arrangements of state registers of the ...

Target device providing debugging function and test system comprising the same

A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.

SEMICONDUCTOR TEST SYSTEM AND METHOD

A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. 1. An integrated circuit wafer comprising: i. first core circuitry having inputs and outputs;', 'ii. first bonds pads;', 'iii. first input buffers, each first input buffer having an input connected to one of the first bond pads and having an output connected to a separate input of the first core circuitry; and', 'iv. first test circuits, each first test circuit having a data input connected to one output of the core circuitry, an encoded expected data and mask data input coupled to another one of the first bond pads, and the data input being selectively coupled to the another one of the first bond pads as an output; and, 'A. a first die including i. second core circuitry having inputs and outputs;', 'ii. second bonds pads;', 'iii. second input buffers, each second input buffer having an input connected to one of the second bond pads and having an output connected to a separate input of the second core circuitry; and', 'iv. second test circuits, each second test circuit having a data input connected to one output of the core circuitry, an encoded expected data and mask data input coupled to another one of the second bond pads, and the data input being selectively coupled to the one of the second bond pads as an output., 'B. a second die including2. The wafer of including a pass/fail scan path and the first and second test circuits being coupled in series in the pass/fail scan path. ...

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation. 1. Controller circuitry comprising:A. state machine circuitry having a command input, a frame marker input, a scan clock input, a test enable input, a clock 2 enable output, a parallel scan enable output, and a serial scan enable output;B. first gate circuitry having a first input connected to clock 2 enable output, a second input connected to the scan clock input, and a clock 2 output; andC. second gate circuitry having a first input connected to the scan clock input, a second input connected to the test enable input, and a clock 1 output.2. The controller circuitry of including a command lead connected to the command input and a command output of a flip-flop.3. The controller circuitry of including a frame marker lead connected to the frame marker input and a frame marker output of a flip-flop.4. The controller circuitry of in which the controller circuitry is included in an integrated circuit and a scan clock lead extends from the scan clock input onto the integrated circuit.5. The controller circuitry of in which the controller circuitry is included in an integrated circuit and a test enable lead extends from the test enable input onto the integrated circuit.6. The controller of including scan circuitry and a clock 1 lead connected from the clock 1 output to the scan circuitry.7. The controller of including scan circuitry and a ...

Path-based crosstalk fault test scanning in built-in self-testing

A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Test access mechanism for diagnosis based on partitioning scan chains

Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Method for Testing a Plurality of Transistors in a Target Chip

The present invention relates to the chip testing field. A method for testing a plurality of transistors in a target chip is provided, characterized by automatically selecting a plurality of pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester. Through automatic generation of the test structures and automatic wiring, the present invention greatly shortens the design cycle of test chips for target transistor testing, and greatly reduces the error probability in the process of designing test chips for target transistor testing, and improves the testing relevancy. 1. A method for testing a plurality of transistors in a target chip , characterized by automatically selecting pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester.2. The method for testing a plurality of transistors in a target chip according to claim 1 , characterized in that the added connection layer is a metal layer.3. The method for testing a plurality of transistors in a target chip according to claim 1 , characterized in that the added connection layer comprises a metal layer and a contact layer.4. The method for testing a plurality of transistors in a target chip according to claim 1 , comprising the following steps:Step 1: entering coordinate information of the transistor in a product layout, determining positions required to be tested;Step 2: automatically selecting the transistors and keeping the key layer;Step 3: automatically identifying pins;Step 4: automatically adding pads;Step 5: determining the one-to-one correspondence between the pins and the pads, and completing wiring of the transistors from the pins to the pads; and,Step 6: taping out and testing.5. The method for testing a plurality of ...

BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY

A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. 1. A system on a chip comprising:A. a communications link including a serial test data in lead and a serial test data out lead;B. a port coupled to the communications link including the serial test data in lead and the serial test data out lead, and having a chip serial test data in lead, a chip serial test data out lead, a first select output lead, and a second select output lead;C. a first component separate from the port, the first component including a first embedded TAP controller, the first component having a test data input coupled to the chip serial test data in lead, a first component serial test data output lead, and a first override output lead;D. first multiplexer circuitry having a first input coupled to the chip serial test data in lead, a second input coupled to the first component serial test data output, an output, and a control input;E. first gating circuitry having a first input connected to the first select output lead, a second input connected to the first override output lead, and an output connected to the control input of the multiplexer circuitry;C. a second component separate from the port and first component, the second component including a second embedded TAP controller, the second component having a test data input coupled to the output of the first multiplexer circuitry, a second component serial test data output lead, and a second override output lead;D. second multiplexer circuitry having a first input coupled to output of the first multiplexer circuitry, a second input coupled to the second component ...

SEMICONDUCTOR DEVICE

The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor inducts a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU #0 determines if a module proximate to a delay monitor suffers from aged deterioration, based on the delay time measured by the delay monitor. 1. A semiconductor device comprising:a plurality of modules;a plurality of delay monitors, wherein each delay monitor includes a ring oscillator having a plurality of gate elements and measures a delay time of said gate elements, anda control unit that whether or not the delay time measured by said delay monitor exceeds a predetermined reference value,wherein, of said delay monitors, every two delay monitors disposed near to each other form one pair, wherein a ring oscillator in one delay monitor of said pair continues to oscillate except for a predetermined number of cycles before and after a delay time measurement period and a ring oscillator in the other delay monitor of said pair oscillates only during a delay time measurement period, and said control unit determines a difference between a delay time measured by said one delay monitor and a delay time measured by said other delay monitor.2. The semiconductor device according to claim 1 , wherein said control unit issues an alert claim 1 , if having determined that said module suffers from aged deterioration.3. The semiconductor device according to claim 1 , wherein said control unit performs a built-in self test of said semiconductor device claim 1 , if having determined that said module suffers from aged deterioration.4. The semiconductor device according to claim 1 , wherein said control unit decreases the power supply voltage to the module proximate to said delay monitor claim 1 , if ...

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Mixed-Signal Integrated Circuit

A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing. 111-. (canceled)12. An electronic device , comprising:a first semiconductor device;a second semiconductor device;a power supply circuit; anda passive element,wherein the first and second semiconductor devices each include a self-diagnosis control circuit, a scan target circuit, and an electrically rewritable non-volatile memory, the scan target circuit including a plurality of scan flip-flops and a selector for switching between outputs of the scan flip-flops,wherein, in each of the first and second semiconductor devices, the scan flip-flops are coupled to configure a scan chain, andwherein the self-diagnosis control circuit controls the selector in accordance with data stored in the non-volatile memory such that the first and second semiconductor devices have a same scan chain configuration and such that the first and second semiconductor devices start scanning at different times.13. The electronic device according to claim 12 , a supply voltage monitoring A/D conversion circuit; and', 'a communication circuit,, 'wherein each of the first and second semiconductor devices includeswherein the supply voltage monitoring A/D conversion circuit monitors the supply voltage during a scan test,wherein the second semiconductor device transfers supply voltage variation data to the first ...

COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA. 1. A method to compress a test pattern onto a field programmable gate array (FPGA) to test a device under test (DUT) , the method comprising:identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles;identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles;analyzing the identified values;compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins; andstoring the compressed values on the FPGA.2. The method of claim 1 , wherein a value for a drive pin is a selected one of 0 or 1; and wherein a value for a compare pin is a selected one of 0 claim 1 , 1 claim 1 , or X.3. The method of claim 1 , wherein compressing further includes identifying a plurality of values of drive pins and compare pins for an identified test cycle.4. The method of claim 1 , wherein compressing further includes identifying claim 1 , based on the analysis claim 1 , a subset of drive pins and/or compare pins having respective values for N subsequent test cycles after an identified test cycle that are equal to the respective values of the subset of drive pins and/or ...

SCALABLE INFIELD SCAN COVERAGE FOR MULTI-CHIP MODULE FOR FUCTIONAL SAFETY MISSION APPLICATION

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode. 2. The apparatus of claim 1 , wherein the indication to configure I3C interface to enable multilane comprises an indication of using four serial data lanes.3. The apparatus of claim 1 , wherein the first chip is further configured to transmit error correction data using multiple lanes after the transmission of the data to the second chip using multiple lanes.4. The apparatus of claim 3 , wherein the transmitted error correction data comprises a word for cyclic redundancy check (CRC WORD) which is transmitted over the first data lane.5. The apparatus of claim 4 , wherein the first chip is further configured to transmit HDR Exit data after the word for cyclic redundancy check (CRC WORD) over the first data lane to conclude the transmission.6. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip using multiple lanes with a duration of multiples of 10 serial clocks (SCL).7. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip in double data rate (DDR).8. The apparatus of claim 1 , wherein a plurality of data packets is transmitted to the second chip after the transmission of the Clear Command Channel (CCC) command.9. The apparatus of claim 1 , wherein the first chip is a master chip and the ...

MAXIMIZATION OF SIDE-CHANNEL SENSITIVITY FOR TROJAN DETECTION

An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold. 1. A method comprising:generating a plurality of initial test patterns that can trigger a rare condition of a Trojan circuit in an integrated circuit;generating one succeeding test pattern for each of the plurality of initial test patterns that can increase side-channel sensitivity during changing from the initial test pattern to the succeeding test pattern;applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit;measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern;applying the test pattern to a design of the integrated circuit under test;measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; anddetermining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.2. The method of claim 1 , wherein the initial test patterns comprises N-detect test patterns.3. The method of claim 2 , wherein the succeeding test patterns are generated using a genetic algorithm.4. The method of claim 1 , ...

COMMON TEST BOARD, IP EVALUATION BOARD, AND SEMICONDUCTOR DEVICE TEST METHOD

According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached. 1. A common test board comprising:a socket board to which a semiconductor device is to be connected;an IP evaluation board on which the socket board is able to be attached; anda common board on which the IP evaluation board is able to be attached.2. The common test board according to claim 1 , wherein the socket board is able to be attached on the common board without the IP evaluation board therebetween.3. The common test board according to claim 1 , whereinthe socket board includes:a socket to which the semiconductor device is connected; anda first interface electrically connected to the socket and including a first connector.4. The common test board according to claim 3 , whereinthe common board includes:a common interface on which different IP evaluation board used to evaluate different IP function block is able to be attached; anda common test circuit electrically connected to the common interface, and able to generate any of signals of a quality determination test, an IP evaluation test, and an actual apparatus test, the quality determination test being a test to determine quality of the semiconductor device, the IP evaluation test being a test to evaluate a IP function block implemented on the semiconductor device, the actual apparatus test being a test to check whether the semiconductor device can exert required performance in an actual apparatus.5. The common test board according to claim 4 , wherein the common interface is an interface on which the socket board with different specification is able to be attached.6. The common test board according to claim 4 , whereinthe IP evaluation board includes:an evaluation signal ...

REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal. 1. A register array comprising: a first latch;', 'a second latch; and', 'a test latch connected to the first latch and the second latch,, 'a plurality of groups of latches, each of the groups of latches comprisesduring functional operation the first latch and the second latch process data, in response to the same read/write clock signal, and a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch;', 'a single scan signal is input to the first latch; and', 'the first latch and the second latch are connected to the test latch to cause the single scan signal to cascade from the first latch through the test latch to the second latch, and be output by the second latch, to use a single test clock and the single scan signal to test both the first latch and the second latch within a single cycle of the original test clock signal., 'during test operation2. The register array according to claim 1 , the first latch and the second latch are physically symmetrical.3. The register array according to claim 1 , the first latch and the second latch each comprise a ...

THREE-DIMENSIONAL PROCESSING SYSTEM HAVING AT LEAST ONE LAYER WITH CIRCUITRY DEDICATED TO SCAN TESTING AND SYSTEM STATE CHECKPOINTING OF OTHER SYSTEM LAYERS

Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip. 1. A semiconductor device , comprising:a first chip and a second chip, which are physically conjoined to form a stacked structure;the first chip comprising functional circuitry, the functional circuitry including a plurality of scan cells comprising scanable flip-flop and latches;the second chip comprising scan testing circuitry, and a scan testing I/O (input/output) interface, wherein the scan cells of the first chip are connected to the scan testing I/O interface, and wherein the scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry.2. The semiconductor device of claim 1 , wherein the first chip is a processor chip.3. The semiconductor device of claim 1 , wherein the first chip is a memory chip.4. The semiconductor device of claim 1 , wherein the scan testing circuitry on the second chip comprises:demultiplexer circuits;multiplexer ...

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS

Electronic scan circuitry includes a decompressor (), a plurality of scan chains () fed by the decompressor (), a scan circuit () coupled to the plurality of scan chains () to scan them in and out, a masking circuit () fed by the scan chains (), and a scannable masking qualification circuit () coupled to the masking circuit (), the masking qualification circuit () scannable by scan-in of bits by the decompressor () along with scan-in of the scan chains (), and the scannable masking qualification circuit () operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (). Other scan circuitry, processes, circuits, devices and systems are also disclosed. 1. Electronic scan circuitry comprising:a decompressor;a plurality of scan chains fed by the decompressor;a scan circuit coupled to the plurality of scan chains to scan them in and out;a masking circuit fed by the scan chains;a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit; andbit-field decoders wherein the scannable masking qualification circuit has a shift register fed by the decompressor and including sets of shift register cells, each set operable to couple a bit-field to a corresponding one of the bit-field decoders, each one such decoder having a decode output coupled to the masking circuit to independently select at least one scan chain for qualification in a distinct respective group among the scan chains for each one such decoder corresponding to each such set of shift register cells in the shift register.2. The electronic scan circuitry of in which each set of shift register cells is operable to couple a bit-field to a corresponding one of the bit-field decoders equal to a binary ...

SEMICONDUCTOR DEVICE INCLUDING THROUGH-PACKAGE DEBUG FEATURES

A semiconductor device is disclosed including through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device. 1. A semiconductor device , comprising:a semiconductor die;a substrate including one or more test pads, the semiconductor die mounted on the substrate, the one or more test pads electrically coupled to one or more debug ports on the semiconductor die;a housing encasing the semiconductor die, the housing having a surface;one or more debug features having a first end at the surface of the housing and a second end terminating at the one or more test pads within the housing, the one or more debug features configured to receive a probe for debugging or testing the semiconductor device.2. The semiconductor device of claim 1 , wherein the housing is comprised of a thermoplastic or thermosetting resin claim 1 , the one or more debug features provided within one or more holes formed through the thermoplastic or thermosetting resin.3. The semiconductor device of claim 1 , wherein the one or more debug features are configured to receive the probe at the first end at the surface of the housing.4. The semiconductor device of claim 3 , wherein the debug features comprise one or more vias filled with a conductive material.5. The semiconductor device of claim 3 , wherein the debug features comprise one or more vias plated with a conductive material.6. The semiconductor device of claim 3 , wherein the debug features comprise one or more conductive columns soldered to the test pads.7. The semiconductor device of claim 1 , wherein the one or more debug features are configured to receive the probe at the ...

METHODS AND APPARATUS FOR AN INTEGRATED CIRCUIT

Various embodiments of the present technology may comprise methods and apparatus for an integrated circuit (IC). The methods and apparatus may comprise an integrated circuit comprising a sensor circuit and a driver circuit coupled to the sensor circuit. The driver circuit may include an amplifier configured to generate a bias voltage, a signal converter circuit coupled to the amplifier, and a control circuit coupled to the amplifier. The control circuit may comprise a switch responsive to a control signal and a transistor coupled to the switch. 1. An integrated circuit , comprising:a sensor circuit; and an amplifier configured to generate a bias voltage at a bias output terminal;', 'a signal converter circuit coupled to the amplifier, wherein the signal converter circuit comprises a digital-to-analog converter; and', a current mode; and', 'a voltage mode., 'a control circuit coupled to the amplifier and configured to selectively operate the driver circuit in one of], 'a driver circuit coupled to the sensor circuit and comprising2. The integrated circuit according to claim 1 , wherein the control circuit comprises:a plurality of switches, each responsive to a control signal; andat least one transistor coupled to at least one of the plurality of switches.3. The integrated circuit according to claim 1 , wherein the control circuit comprises: in series with a second switch; and', 'to the bias output terminal;, 'a first switch coupleda third transistor comprising a gate terminal, wherein the gate terminal is coupled to a node positioned between the first and second switches; anda third switch and a resistive element coupled between a reference voltage and the amplifier.4. The integrated circuit according to claim 1 , wherein the sensor circuit comprises a hall element configured to generate a hall signal in response to a magnetic field.5. The integrated circuit according to claim 1 , further comprising a switching circuit coupled to the sensor circuit and the driver ...

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF

A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode. 1. A semiconductor apparatus comprising:a first data output unit connected to a first data channel;a second data output unit connected to a second data channel; anda compression test data generating unit configured to generate compression data in response to a chip selection signal and first and second test data and output the compression data to one of the first and second data output units,wherein the first data output unit outputs one of the first test data and the compression data through the first data channel in response to a control signal, and the second data output unit outputs one of the second test data and the compression data through the second data channel in response to the control signal.2. The semiconductor apparatus according to claim 1 , further comprising a data compressing unit configured to compress a plurality of data and generate the first and second test data.3. The semiconductor apparatus according to claim 1 , wherein the first data output unit comprises:a first data selecting unit configured to output one of the first test data and the compression data in response to the control signal; anda first output driver unit configured to receive the output of the first data selecting unit and output the same through the first data channel.4. The semiconductor apparatus according to claim 3 , wherein the second data output unit comprises:a second data selecting unit configured to output one of the second test data and the compression data in response to the control signal; anda second output driver unit configured to receive the ...

Stuck-at fault detection on the clock tree buffers of a clock source

A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

OPTIMIZATION OF A STORAGE SYSTEM CONTAINING ECC AND SCRAMBLE ENGINES

A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table is disclosed and the steps comprises: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine; scrambling the data by the LFSR scramble engine and transmitting to a storage device; creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine; receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface. 1. A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table , the steps comprising:{'b': '1', 'step S: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine;'}{'b': '2', 'step S: scrambling the data by the LFSR scramble engine and transmitting to a storage device;'}{'b': '3', 'step S: creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine;'}{'b': '4', 'step S: receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and'}{'b': '5', 'step S: decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface.'}2. The method as claimed in claim 1 , wherein the ECC decoding engine decodes the data every X2 bytes claim 1 , saving the seed value of every beginning of X2 bytes or times of X2 bytes get ...

Optimized jtag interface

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

SCAN TESTING SYSTEM, METHOD AND APPARATUS

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. 1. An integrated circuit comprising:A. input pads and output pads;B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad;C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; andD. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, ...

Programmable scan shift testing

The disclosed technology facilitates programmable scan shift testing for a scan chain including at least a first segment of scan-flops connected in series with a second segment of scan-flops. The scan chain includes at least a first multiplexor positioned between the first segment and the second segment that is configured to selectively supply scan input from a test controller to the second segment while preventing the second segment from receiving an output of the first segment.

ROOT MONITORING ON AN FPGA USING SATELLITE ADCS

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets. 1. A device , comprising:a root monitor including circuitry configured to generate a reference voltage;a number of sensors distributed in various locations across the device, each of the sensors configured to measure operating conditions of an associated circuit at a corresponding one of the various locations;a plurality of satellite monitors distributed in the various locations across the device, each of the satellite monitors coupled to one or more associated sensors located in a vicinity of the corresponding satellite monitor; and distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and', 'selectively route digital data from each of the plurality of satellite monitors to the root monitor, wherein the digital data is indicative of the measured operating conditions., 'an interconnect system coupled to the root monitor, and to each of the plurality of satellite monitors, wherein the interconnect system is configured to2. The device of claim 1 , wherein the operating conditions include at least one of a temperature or a ...

EYE DIAGRAM MEASUREMENT DEVICE AND EYE DIAGRAM MEASUREMENT METHOD

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device. 1. An eye diagram measurement device , comprising:a first mapping circuitry configured to map one of a plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits;a counter circuitry configured to perform a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals;a second mapping circuitry configured to map the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase; anda memory circuitry configured to store the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.2. The eye diagram measurement device of claim 1 , wherein the first mapping circuitry comprises:a plurality of bit conversion circuits configured to generate a plurality of second data signals, wherein the number of bits of each one of the second signals is the same as the predetermined number ...

MULTIPLEXER-ENABLED CABLES AND TEST FIXTURES

A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer. 1. A cable for connecting one or more devices under test to a test and measurement instrument , comprising:a first port structured to electrically connect to a first signal lane;a second port structured to electrically connect to a second signal lane;a third port structured to electrically connect to a test and measurement instrument; anda multiplexer configured to switch between electrically connecting the first port to the third port, or connecting the second port to the third port.2. The cable of claim 1 , further comprising a memory structured to store calibration parameters of the test and measurement cable.3. The cable of claim 1 , wherein the first port and/or second port is a high-density connection port.4. The cable of claim 3 , wherein the third port is a high-density connection port.5. The cable of claim 1 , further comprising a processor configured to control the multiplexer.6. The cable of claim 1 , further comprising an input configured to receive a control signal to operate the multiplexer.7. The cable of claim 1 , further comprising a transceiver.8. The cable of claim 1 , wherein the first signal lane and the second signal lane are within a single device under test.9. The cable of claim 1 , wherein the first signal lane and the second signal lane are in different ...

Test circuit and semiconductor apparatus including the same

A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.

Configurable Vertical Integration

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. 1. A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;disabling a plurality of processing circuit portions;testing at least one enabled processing circuit portion at a time.2. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled as a result from one of the one or more circuit portions.3. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing with a plurality of the processing circuit portions and at least ...

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. 1. A system , comprising:a circuit comprising a register and a decompressor, the decompressor comprising a linear feedback shift register (LFSR); andautomatic testing equipment located external to the circuit,wherein the register is configured to load compressed test pattern data from an output of the automatic testing equipment and to output the compressed test pattern data to an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test pattern data and logically combine the compressed test pattern data with data stored within the LFSR.2. The system of claim 1 , wherein the register is configured to receive multiple bits of the compressed test pattern data in parallel from multiple outputs of the automatic testing equipment before the multiple bits of the compressed test pattern data are output to the input logic gate of the LFSR.3. The system of claim 1 , wherein the decompressor further includes a phase shifter having inputs coupled to outputs of the LFSR claim 1 , the phase shifter being configured ...

FLIP FLOP OF A DIGITAL ELECTRONIC CHIP

A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input. 1. A flip flop circuit comprising:a data input and a clock input;a test chain input and a test chain output;a monitoring circuit configured to generate an alert if a time between arrival of a data bit and a clock edge of a clock signal is less than a threshold; andan alert transmission circuit configured to transmit, during a monitoring phase, an alert level to the test chain output in response to the monitoring circuit issuing the alert, and to apply the alert level to the test chain output in response to the alert level being on the test chain input.2. The flip flop circuit of claim 1 , wherein the alert transmission circuit is configured to maintain the alert level at the test chain output until an arrival of a reset signal at the alert transmission circuit.3. The flip flop circuit of claim 2 , wherein the alert transmission circuit comprises:an OR gate having an input configured to receive the alert and another input coupled to the test chain input; andan asynchronous latch having an input coupled to an output of the OR gate and an output coupled to the test chain output.4. The flip flop circuit of claim 2 , further comprising a control circuit configured to apply a monitoring control signal at a first level to begin the monitoring phase claim 2 , the reset signal corresponding to a second level of the monitoring control signal.5. The flip flop circuit of claim 1 , wherein the monitoring circuit ...

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors. 1a memory element that has an output and that has a power supply terminal at which a power supply voltage is provided;a pass transistor having a gate that is coupled to the output of the memory element; anda write assist circuit that applies a temporary adjustment to the power supply voltage, wherein the pass transistor receives the adjusted power supply voltage from the output of the memory element, and wherein the pass transistor exhibits a drive strength that is unaffected by the temporary adjustment in the power supply voltage.. An integrated circuit, comprising: This application is a continuation of U.S. patent application Ser. No. 14/737,246, filed Jun. 11, 2015. This application claims the benefit of and claims priority to U.S. patent application Ser. No. 14/737,246, filed Jun. 11, 2015, which is hereby incorporated by reference herein in its entirety.This relates to integrated circuits and more particularly, to programmable integrated circuits.Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to ...

SENSOR DEFECT DIAGNOSTIC CIRCUIT

A sensor device comprises a sensor connected to a first signal and responsive to an external field to produce a sensor signal, a test device connected to a second signal and electrically connected in series with the sensor by an electrical test connection providing a test signal, and a monitor circuit electrically connected to the first, second and test signals. The monitor circuit comprises a processing circuit and a determination circuit. The processing circuit is responsive to the test signal and a predetermined processing value to form a processing output signal. The determination circuit is responsive to the processing output signal to determine a diagnostic signal. A sensor circuit responsive to the sensor signal provides a sensor device signal responsive to the external field. 1. A sensor device comprising:a sensor responsive to an external physical quantity of an environmental attribute to produce a sensor signal, the sensor electrically connected to a first signal;a test device electrically providing a test signal connected in series with the sensor by an electrical test connection, the test device electrically connected to a second signal, and wherein the first signal, the second signal and the test signal are different signals; anda monitor circuit electrically connected to the first, second and test signals, the monitor circuit comprising a processing circuit and a determination circuit, wherein the processing circuit is responsive to the test signal and a predetermined processing value to form a processing output signal and wherein the determination circuit is responsive to the processing output signal to determine a diagnostic signal.2. The sensor device as in claim 1 , wherein the test device is a resistor.3. The sensor device as in claim 1 , wherein the test device is a test sensor.4. The sensor device as in claim 3 , wherein the test sensor is a substantial duplicate of the sensor.5. The sensor device as in claim 1 , wherein the test device ...

FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains. 1. A system for testing a circuit , comprising:scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;a controller comprising first storage circuitry, second storage circuitry, and a control signal generator, the first storage circuitry comprising circuitry configured to store operational mode information, the second storage circuitry comprising circuitry configured to store information of a hold-toggle pattern, and the control signal generator configured to generate a control signal based on the operational mode information and the hold-toggle pattern, wherein the operational mode information determines whether a scan chain operates in a full-toggle mode or in a hold-toggle mode during a shift period, the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles scan chains operating in the hold-toggle mode receive bits based on corresponding bits of a test pattern during the shift period, and the hold-toggle pattern repeats multiple times during the shift period, the shift period being a period when the test pattern is being shifted into the scan chains; andhold-toggle circuitry coupled to the controller and configured to ...

Flip Flop Circuit

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal. 1. A flip flop circuit , comprising:a first master portion configured to operate at a first mode and to receive a first input and generate first master outputs;a second master portion configured to operate at a second mode and to receive a second input and generate second master outputs;at least one determining portion configured to receive at least one enable signal, and having determining inputs and determining outputs, the determining inputs connected to the first master outputs and the second master outputs, the determining portion configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal; anda slave portion configured to receive the determining outputs and generate an output signal.2. The flip flop circuit of claim 1 , wherein the first mode is a testing mode claim 1 , and the second mode is a normal mode claim 1 , the first input is a scan-in signal and the second input is a data signal claim 1 , the at least one enable signal comprise a scan enable signal and an inverted ...

IMPLEMENTING REGISTER ARRAY (RA) REPAIR USING LBIST

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array. 1. A circuit for implementing register array repair using Logic Built In Self Test (LBIST) , said circuit comprising:a plurality of Register Arrays (RAs), each RA including a redundant element enabling a single repair;a list of any repairable Register Arrays (RAs) effecting an LBIST fail result being identified; anda repair solution being detected for each of the repairable Register Arrays (RAs) in the list for isolating a failing location for the detected repair solution for each array.2. The circuit as recited in wherein each of the plurality of Register Arrays (RAs) includes a selectable iterate on each array repair data segment claim 1 , said selectable iterate including an enable latch in a scan path for each focus array to allow iterating through repair trials responsive to a trigger signal from LBIST.3. The circuit as recited in wherein said repair solution being detected for each of the repairable Register Arrays (RAs) for isolating a failing location for the detected repair solution for each array includes choosing a fail array claim 1 , repairing a failing location claim 1 , and running LBIST.4. The circuit as recited in wherein said list of any repairable Register Arrays (RAs) effecting LBIST fail result being identified includes performing a full repair on all select arrays responsive to an LBIST fail claim 1 , and checking for an LBIST fail change.5. The circuit as recited in includes choosing a focus array responsive to an LBIST fail change and performing a full repair on the focus array ...

HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE

A process and apparatus provide a JTAG TAP controller () to access a JTAG TAP domain () of a device using a reduced pin count, high speed DDR interface (). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation. 1. An integrated circuit comprising:(a) a TDI/TMS signal and a TCK signal;(b) double data rate circuitry having a TDI/TMS input coupled to the TDI/TMS signal, a TCK input coupled to the TCK signal, a DDR TDI output, and a DDR TMS output;(c) a TAP domain having a domain TDI input, a domain TMS input, and a domain TCK input; and(d) addressable TAP interface circuitry having a TDI input coupled to the DDR TDI output, a TMS input coupled to the DDR TMS output, a TCK input coupled to the TCK signal, a domain TDI output coupled to the domain TDI input, a domain TMS output coupled to the domain TMS input, and a domain TCK output coupled to the domain TCK input, the addressable TAP interface including: i. a state machine having a Test Data In input coupled to the TDI input, a Clock input coupled to the TCK input, a Match input, an Address In output, an Address Control output, an enable input, and a reset input; andii. a TAP state monitor having a Test Mode Select input coupled to the TMS input, a Clock input coupled to the TCK input, an enable output coupled to the enable input, and a reset output coupled to the reset input.2. The shadow protocol detection circuit of in which the TAP state monitor has the states of Test Logic Reset claim 1 , Run Test/Idle claim 1 , Select-DR claim 1 , Pause-DR claim 1 , Select-IR claim 1 , and ...

CONFIGURATION AND TESTING METHOD AND SYSTEM FOR FPGA CHIP USING BUMPING PROCESS

A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment. 114-. (canceled)15. A method of configuration and test of an FPGA chip , comprising the steps of:1) creating configuration files for an FPGA chip under test and storing the configuration files in a mass memory, the configuration files comprising information about a plurality of configuration resources required for function test of the FPGA chip under test, wherein each of a plurality of configuration codes comprised in the configuration files is mapped to a corresponding one of the plurality of configuration resources;2) reading, by a master FPGA, a configuration code stream comprising corresponding configuration codes from the mass memory according to a control test algorithm developed based on an automatic test equipment (ATE), configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful;3) if the configuration is successful, converting the successfully configured configuration code stream into a test signal source file recognizable and executable by the ATE by using the control test algorithm and a conversion tool, the test signal source file comprising test signal source codes reusable by multiple test ...

POWER SUPPLY MONITOR FOR DETECTING FAULTS DURING SCAN TESTING

Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold. 1. A power supply monitor , comprising:a measurement circuit to measure a voltage provided to the power supply monitor;a comparator to compare the voltage to a predetermined voltage threshold; andan interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold.2. The power supply monitor of claim 1 , wherein the predetermined voltage threshold corresponds to a reduced speed of at least one circuit block that produces a fault in response to a test pattern provided to said at least one circuit block.3. The power supply monitor of claim 1 , comprising a test interface for receiving a test pattern and providing test results in response to the test pattern claim 1 , wherein the test pattern is used to configure the power supply monitor to measure the voltage after receiving a capture clock pulse generated by a test circuit.4. The power supply monitor of claim 1 , wherein the measurement circuit comprises a ring oscillator and at least one counter to count a number of stage transitions or ring oscillator revolutions during a measurement period claim 1 , the number of stage transitions or ring ...

METHOD AND APPARATUS FOR PROVIDING CLOCK SIGNALS FOR A SCAN CHAIN

An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals. 1. An integrated circuit device , comprising:a plurality of flip flops configured into a scan chain, wherein the plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type.2. The device of claim 1 , wherein the first type comprises a multiplexer data flip flop and the second type comprises a level-sensitive scan design flip-flop.3. The device of claim 2 , further comprising:logic to provide a first scan clock signal to the multiplexer data flip flop for loading scan data and second and third scan clock signals to the level-sensitive scan design flip-flop for loading the scan data, wherein the second and third scan clock signals are non-overlapping.4. The device of claim 3 , wherein the logic is to generate the second scan clock signal from a first external scan clock signal and generate the first and third scan clock signals from a second external scan clock signal claim 3 , wherein the first and second external clock signals are received by the integrated circuit device.5. The device of claim 4 , further comprising:at least one clock distribution tree to distribute a common clock signal and the first external scan clock signal; anda multiplexer coupled to the clock distribution tree and to select one of a functional clock signal for operating ...