Error detection in stored data values

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.

Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus

In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when the subsystems are not communicating with one another on the bus. Selected pairs of the subsystems are operated at a shared clock frequency by selectively varying frequencies of clock signals to the subsystems, so that communication can occur at the shared clock frequency on the bus between the selected subsystems, but at different clock frequencies for respective different pairings of the subsystems, and so that the subsystems can operate at independent clock frequencies when not communicating with other ones of the subsystems. Communication among the subsystems is by a bus-based protocol, according to which when a subsystem is granted access to the bus the subsystem has exclusive use of the bus.

Exception prediction before an actual exception during debugging

An approach is provided for predicting an exception during a debugging of software code before the debugging encounters the exception. A number of lines X is received. During a debugging of a line number L of the code, upcoming lines consisting of line numbers L+1 through L+X are executed. Based on the execution of the upcoming lines, the exception is predicted to be encountered at line number M, which is within a range of line numbers L+1 through L+X. During the debugging of the line number L, and based on the prediction and the line number being within the range, a warning is displayed that the exception is to be encountered at line number M.

Correlated electron switch programmable fabric

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Address dependent data encryption

Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Logical interleaver

Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.

PUF and address dependent data encryption

Encryption of data within a memory (6) is provided by key generation circuitry (12) which serves to generate a key as a function of the address within the memory (6) being accessed and then encryption circuitry (14) or decryption circuitry (16) which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Correlated electron memory element-based latching circuits

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron switch, hereinafter termed CES, element. The latching circuitry further comprises a control circuit coupled to the at least one CES element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Correction of single event upset error within sequential storage circuitry of an integrated circuit

Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.

Spatial tiling of compute arrays with shared control

In one embodiment, a method for machine learning acceleration includes receiving, by a shared controller of a tensor processor cluster that includes multiple tensor processors, a multi-cycle instruction, determining, based on the instruction, a sequence of vector operations to be executed by the tensor processors and address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation. The method also includes, for each vector operation in the sequence, generating, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition on which the tensor processor is to operate, multicasting the common address offset to the tensor processors, and controlling the tensor processors to execute the vector operation in parallel and in lock step.

Storage circuit with random number generation mode

Flexible compute array utilization in a tensor processor

In one embodiment, a method for machine learning acceleration includes receiving instructions to perform convolution on an input tensor using a filter tensor, determining that the size of a first dimension of the input tensor is less than a processing capacity of each of multiple subarrays of computation units in a tensor processor, selecting a second dimension of the input tensor along which to perform the convolution, selecting, based on the second dimension, one or more dimensions of the filter tensor, generating (1) first instructions for reading, using vector read operations, activation elements in the input tensor organized such that elements with different values in the second dimension are stored contiguously in memory, and (2) second instructions for reading weights of the filter tensor along the selected one or more dimensions, and using the first and second instructions to provide the activation elements and the weights to the subarrays.

Electrical component with random electrical characteristic

An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures (2) including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

Configurable IC with interconnect circuits that also perform storage operations

Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurably routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Circuit and method for configurable impedance array

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Wordline pulse duration adaptation in a data storage apparatus

Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.

Address dependent data encryption

Correlated electron memory element-based latching circuits

Correlated electron switch programmable fabric

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Electrical component with random electrical characteristic

METHOD AND SYSTEM FOR PROCESSING TRANSACTIONS

Configurable IC with interconnect circuits that also perform storage operations

Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Memory with improved data reliability

An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value.

Memory with improved read stability

A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device ...

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 123-. (canceled)24. A method , comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.25. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for manufacturing errors in the integrated circuit.26. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for design errors in the integrated circuit.27. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises reducing power consumption in the integrated circuit at least in part by selectively disconnecting a supply voltage from the one or more portions of the integrated circuit.28. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises adjusting clock skew between specified portions of the integrated circuit.29. The method of claim 28 , wherein the integrated circuit comprises a ...

Logical Interleaver

Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit may interleave data bits from multiple different data words and store modified data words based on the multiple different data words. 1. A memory device , comprising:a first interleaving circuit that receives data words and generates a first error correction code based on the received data words; anda second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code,wherein the second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.2. The device of claim 1 , wherein each of the data bits comprises a single unit of data claim 1 , and wherein each of the multiple different data words comprises a plurality of data bits.3. The device of claim 1 , wherein the data words comprise a plurality of data words having the multiple different data words claim 1 , and wherein each of the plurality of data words having the multiple different data words comprises a plurality of data bits.4. The device of claim 1 , wherein the first interleaving circuit is coupled to read and write ports claim 1 , and wherein the first interleaving circuit receives the data words from one or more of the read and write ports.5. The device of claim 1 , wherein the first interleaving circuit comprises an error correction code (ECC) circuit that generates the first error correction code.6. The device of ...

Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device

A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells. 1. A method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device , comprising:identifying a subset of said plurality of memory cells whose value of said chosen characteristic is within a predetermined end region of said distribution;performing a burn-in process during which one or more operating parameters of the memory device are set to induce ageing of said memory cells;during the burn-in process, for each memory cell in said subset, fixing the value stored in that memory cell to a selected value which exposes that memory cell to a stress condition; andduring the burn-in process, for each memory cell not in said subset, alternating the value stored in that memory cell in order to alleviate exposure of that memory cell to said stress condition.2. A method as claimed in claim 1 , wherein:said chosen characteristic is a minimum voltage that allows a memory cell to be written to; andthe predetermined end region comprises minimum voltage values exceeding a desired minimum ...

Low overhead circuit and method for predicting timing errors

Data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a data input, a data output and a processing path arranged between the data input and the data output. The processing path comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal; and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data. The data processing circuitry further comprises: a plurality of retention circuits for storing data in a low power mode, the plurality of retention circuits being arranged in parallel with the processing path; and at least one potential error detecting circuit for determining during processing of the data if the data signal pending at an input to one of the plurality of synchronisation circuits is stable during a predetermined time prior to capture of the data and for signalling a potential error if the data input is determined to be unstable ...

Exception prediction before an actual exception during debugging

An approach is provided for predicting an exception during a debugging of software code before the debugging encounters the exception. During a debugging of a line number L of the code and based on an exception being predicted to be encountered at a line number M, a warning is displayed that the exception is to be encountered at the line number M, which is within a range of line numbers L+1 through L+X, where L>0 and X>1. Using a fix written in response to the predicted exception, the software code is modified. During a debugging of the line number M of the code, the modified software code is executed to avoid the predicted exception.

Methods, systems and computer program products for monitoring interrelated tasks executing on a computer using queues

Methods, systems and computer program products are provided for monitoring a task executing on a data processing system, the task having an associated work in process queue and an associated work pending queue. The task is configured to properly execute requests that are terminated in progress and restarted from an initial start point. A watchdog task determines if the task is executing properly and restarts the task if it is not executing properly. Restarting is provided by placing requests in the work in process queue of the terminated task in the work pending queue and clearing the work in process queue. Execution by the task of requests from the work pending queue is then reinitiated.

ONE-TIME AND MULTI-TIME PROGRAMING USING A CORRELATED ELECTRON SWITCH

An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.

Apparatus and method for generating a random number

An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random ...

Single event upset error detection within sequential storage circuitry of an integrated circuit

Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element ...

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 123-. (canceled)24. A method , comprising:configuring a programmable fabric of an integrated circuit device at least in part by selectively providing a particular lower impedance path between a first particular electrically conductive line of a first metallization layer of the programmable fabric and a second particular electrically conductive line of a second metallization layer of the programmable fabric at least in part by placing two or more particular correlated electron switch devices in a particular impedance state, wherein the particular lower impedance path includes at least a third particular electrically conductive line of a third metallization layer of the programmable fabric.25. The method of claim 24 , wherein the placing the two or more particular correlated electron switch devices in the particular impedance state comprises limiting a current flow through the two or more particular correlated electron switch devices to a specified threshold current level at least in part to establish a particular threshold current density in the two or more particular correlated electron switch devices for a subsequent operation to place the two or more particular correlated electron switch devices in a second impedance state.26. The method of claim 24 , wherein the programmable fabric comprises a cross-point array claim 24 , wherein the first metallization layer includes a first plurality of electrically conductive lines oriented approximately parallel with each other claim 24 , wherein the third metallization layer includes a third plurality of electrically conductive lines oriented approximately parallel with each other claim 24 , and wherein the first plurality of electrically conductive lines are oriented approximately orthogonally to the third plurality of electrically conductive lines.27. The method of claim 26 , wherein the second metallization ...

Multipurpose bag

METHOD AND SYSTEM FOR PROVIDING PERFORMANCE ASSESSMENT OF TERMINAL DEVICES

Dynamic selection of one of many available web browsers

A user selection of an item corresponding to a Web page can be received. The user selection can represents a request to open the Web page within an instantiated one of a set of Web browser applications installed on a computing device. A set of Web page elements unique to the Web page can be identified through an analysis conducted by the computing device. The identified set of Web page elements can be utilized to determine at the computing device one of the installed Web browser applications for the Web page. The determination of the one installed Web browser application can varies from Web page-to-Web page. At the computing device, the determined one of the Web browser applications can be instantiated. The Web page can be opened within the instantiated one of the Web browser applications.

Method, system and device for correlated electron switch (CES) device operation

Described are methods, systems and devices for operation of correlated electron switch (CES) devices. A CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. A programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.

System and method for supporting alternate number format for efficient multiplication

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2n, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

SPATIAL TILING OF COMPUTE ARRAYS WITH SHARED CONTROL

In one embodiment, a method for machine learning acceleration includes receiving, by a shared controller of a tensor processor cluster that includes multiple tensor processors, a multi-cycle instruction, determining, based on the instruction, a sequence of vector operations to be executed by the tensor processors and address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation. The method also includes, for each vector operation in the sequence, generating, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition on which the tensor processor is to operate, multicasting the common address offset to the tensor processors, and controlling the tensor processors to execute the vector operation in parallel and in lock step. 1. A system for machine learning acceleration , comprising:{'claim-text': ['a plurality of tensor processors; and', {'claim-text': ['receive a multi-cycle instruction;', 'determine, based on the multi-cycle instruction, (1) a sequence of vector operations to be executed by the tensor processors and (2) address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation; and', {'claim-text': ['generate, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition of the input tensor on which the tensor processor is to operate;', 'multicast the common address offset to the tensor processors; and', 'control the tensor processors to execute the vector operation in lock step.'], '#text': 'for each vector operation in the sequence:'}], '# ...

Multi-thread sequencing

Systems, methods and tools for identifying potential errors or inconsistencies occurring during the runtime of multi-threaded applications and reporting the errors to a user, administrator or developer for correction and adjustments to the program code or thread timings. Embodiments of the disclosure capture thread sequences during a runtime or simulation environment and store the thread sequences as a matrix or tabular representation in a file. Multi-threaded application runs having an error free thread sequence, may be used as benchmarks for identifying potential errors and mis-runs of variations to the multi-threaded application as changes occur to the application code or new threads are added to the application code. This comparison may be performed by comparing the captured thread sequences of both the passing run and the mis-run of the multi-threaded application for differences in the thread sequences that may have caused the mis-run to occur.

Memory with improved data reliability

An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory calls, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means ...

Storage circuit with random number generation mode

A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.

Error detection circuitry for use with memory

Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

EXCEPTION PREDICTION BEFORE AN ACTUAL EXCEPTION DURING DEBUGGING

An approach is provided for predicting an exception during debugging of software code before the debugging encounters the exception. A number of lines X is received. A line number L of the code is debugged. In a new thread, upcoming lines consisting of line numbers L+1 through L+X are executed. Based on the execution of the upcoming lines, a prediction is determined that the exception will be encountered at line number M, which is within a range of line numbers L+1 and L+X. Based on the prediction and the line number being within the range, a warning is displayed that the exception is likely to be encountered at line number M. Responsive to the displayed warning, an indication that a corrective action was taken to avoid the exception is received.

MULTI-THREAD SEQUENCING

Systems, methods and tools for identifying potential errors or inconsistencies occurring during the runtime of multi-threaded applications and reporting the errors to a user, administrator or developer for correction and adjustments to the program code or thread timings. Embodiments of the disclosure capture thread sequences during a runtime or simulation environment and store the thread sequences as a matrix or tabular representation in a file. Multi-threaded application runs having an error free thread sequence, may be used as benchmarks for identifying potential errors and mis-runs of variations to the multi-threaded application as changes occur to the application code or new threads are added to the application code. This comparison may be performed by comparing the captured thread sequences of both the passing run and the mis-run of the multi-threaded application for differences in the thread sequences that may have caused the mis-run to occur. 1. A method for identifying errors in a multi-threaded application comprising the steps of:running, by a processor, the multi-threaded application being tested for errors;generating, by the processor, a thread sequence of the multi-threaded application during runtime;storing, by the processor, the thread sequence being generated as a thread sequence representation file;analyzing, by the processor, the thread sequence representation file by comparing the thread sequence stored in the thread sequence representation file with a benchmark thread sequence file;identifying, by the processor, inconsistencies between the thread sequence representation file and benchmark thread sequence file as a function of the analyzing step, wherein the inconsistencies cause a mis-run thread sequence; andreporting, by the processor, the inconsistencies to a user.2. The method of claim 1 , wherein the benchmark thread sequence file is created by the steps comprising:running, by the processor, the multi-threaded application in a benchmark mode; ...

Circuit and method for configurable impedance array

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Boosting voltage levels applied to an access control line when accessing storage cells in a memory

A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage ...

EXCEPTION PREDICTION BEFORE AN ACTUAL EXCEPTION DURING DEBUGGING

An approach is provided for predicting an exception during a debugging of software code before the debugging encounters the exception. A number of lines X is received. During a debugging of a line number L of the code, upcoming lines consisting of line numbers L+1 through L+X are executed. Based on the execution of the upcoming lines, the exception is predicted to be encountered at line number M, which is within a range of line numbers L+1 through L+X. During the debugging of the line number L, and based on the prediction and the line number being within the range, a warning is displayed that the exception is to be encountered at line number M.

METHOD AND SYSTEM FOR PROCESSING TRANSACTIONS

A method and a system for processing transactions is provided. A terminal device executes a terminal action analysis on a transaction initiated at the terminal device by way of a transaction card. The terminal device compares a fraud count of the terminal device with a threshold fraud limit. If the fraud count exceeds the threshold fraud limit, the terminal device selects a first action from a set of actions for processing the transaction. When the first action is to authorize the transaction online, the terminal device transmits transaction details of the transaction to an acquirer server. The transaction details are indicative of a result of the terminal action analysis. The acquirer server generates an authorization request including a fraud indicator and updates the fraud indicator from a first value to a second value. The acquirer server communicates the authorization request, including the updated fraud indicator, to an issuer for authorization. 1. A method for processing transactions , the method comprising:receiving, by a server from a terminal device, transaction details of a transaction based on a terminal action analysis executed by the terminal device for the transaction, wherein the transaction details are indicative of a result of the terminal action analysis executed by the terminal device;generating, by the server, an authorization request, including a fraud indicator, for the transaction based on the transaction details;updating, by the server, the fraud indicator from a first value to a second value when a fraud count of the terminal device is greater than a threshold fraud limit; andcommunicating, by the server to an issuer, the authorization request, including the updated fraud indicator, for authorizing the transaction.2. The method of claim 1 , further comprising determining claim 1 , by the server claim 1 , the fraud count of the terminal device based on one or more arbitration chargebacks associated with the terminal device.3. The method of ...

Configurable IC with interconnect circuits that also perform storage operations

Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Method and system for providing performance assessment of terminal devices

A method for providing performance assessment of terminal devices is provided. A user initiates, by way of a service application that runs on a user device of the user, a first request for obtaining risk scores or connectivity scores of the terminal devices. The first request may include terminal identifiers of specific terminal devices or information pertaining to a specific geographical area. The user device communicates the first request to a server. The server determines the risk scores or the connectivity scores based on the first request. The server transmits, to the user device, a first response that includes the risk scores or the connectivity scores. The user device displays the risk scores or the connectivity scores to the user based on the first response, thereby providing the performance assessment of the terminal devices.

METHOD, SYSTEM AND DEVICE FOR CORRELATED ELECTRON SWITCH (CES) DEVICE OPERATION

Described are methods, systems and devices for operation of correlated electron switch (CES) devices. A CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. A programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.

Computer Implemented System and Method for Reducing Failure in Time Soft Errors of a Circuit Design

A computer implemented system and method is provided for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.

CORRELATED ELECTRON SWITCH DEVICE

Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.

Configurable IC with Interconnect Circuits that also Perform Storage Operations

Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurably routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Logic encryption using on-chip memory cells

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

CES-BASED LATCHING CIRCUITS

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry. 2. (canceled)3. A device comprising:a latching circuitry, the latching circuitry comprising:at least one correlated electron random access memory (CES) element; anda control circuit coupled to the at least one CES element, wherein the control circuit is configured to:receive at least one control signal; andperform at least one of storing data and outputting data based on the at least one CES element and the at least one control signal, wherein the control circuit comprises a read circuit, wherein the read circuit is configured to output the stored data based on an impedance state of the at least one CES element,wherein the read circuit comprises, an output node, a first transistor, a second transistor, and a third transistor, wherein:a drain input of the first transistor is configured to receive a first supply;a gate input of the first transistor is configured to receive the at least one control signal;a source input of the first transistor is connected to the output node;a drain input of the second transistor is connected to the output node;a gate input of the second transistor is configured to receive the at least one control signal;a drain input of the third transistor is connected to a source input of the second transistor and a first input of the at least one CES element, and wherein a second input of the at least one CES element is coupled to a second supply;a gate input of the third transistor is configured to receive the at least ...

Hierarchical functional and variable composition diagramming of a programming class

Inheritance contributions of programming class functions and class variables are diagrammed. A functional diagram illustrates individual class contributions of functions. A variable composition diagram illustrates individual class contributions of variables. A diagrammatic depiction of functions overridden and functions contributed in the inheritance hierarchy is provided. Functions which are unique, overridden and/or have contributions in different classes of the hierarchy are visually distinguished (e.g., by distinguishing marks). Classes in the hierarchy are graphically depicted with relative sizes based on percent contribution.

Video Reconstruction from Videos with Ultra-low Frame-per-second

In one embodiment, a method includes accessing a video captured by cameras which is associated with a first framerate lower than a threshold framerate, for any two adjacent frames of the accessed video: generating a warped frame from the two adjacent frames based on an optical flow associated with the two adjacent frames, determining alignments for the two adjacent frames, respectively, fusing the determined alignments for the two adjacent frames, and generating a reconstructed frame based on the fused alignment, and reconstructing the accessed video based on the any two adjacent frames and their respective reconstructed frames, wherein the reconstructed video is associated with a second framerate higher than the threshold framerate.

Methods, systems and computer program products for coordination of operations for interrelated tasks

Methods, systems and computer program products are provided which coordinate operations for a plurality of interrelated tasks executing on a computer using actual state objects and desired state objects. For each event including coordination between two of the plurality of interrelated tasks, a first (or initiator) task initiates operations by a second (or executor) task to carry out a desired sequence of operations. The initiator task sets a desired state object to the desired state and submits a request to the executor task. The executor task, in turn, operates on the request in order to update an actual state object to the desired state stored in the desired state object by the initiator task. Write control over the desired state object is therefore granted to the initiator task while write control over the actual state object is granted to the executor task. A transitional state may be provided for the actual state object during the time period while the executor task is carrying out ...

CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs. 117-. (canceled)18. A device comprising:a variable impeder device comprising a plurality of variable impedance elements connected in a series, each of the variable impedance elements being configurable to a non-volatile impedance state between or among a plurality of non-volatile impedance states, the variable plurality of variable impedance elements being connected at terminals to form a series connection of the plurality of variable impedance elements; anda programming circuit to apply voltages at a plurality of nodes in the series connection of the plurality of variable impedance elements to program at least one of the plurality of variable impedance elements to one of the plurality of non-volatile impedance states responsive to a digital input signal, the programming circuit to determine the voltages to apply at the nodes according to a mapping of the digital input signal to node voltages.19. The device of claim 18 , wherein the plurality of variable impedance elements comprise correlated electron switch (CES) elements.20. The device of claim 19 , wherein application of voltages at a plurality of nodes initiates a set operation or a reset operation in at least one of the CES elements.21. The device of claim 18 , wherein the nodes are located at terminals of the variable impedance elements.22. The device of claim 18 , wherein one or more of the nodes are located between two variable impedance elements of the plurality of variable impedance elements.23. The device of claim 18 , wherein each of the variable impedance elements comprises a first ...

Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device

A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells.

Error Detection Circuitry For Use With Memory

Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Circuit and method for configurable impedance array

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Storage circuitry and method with increased resilience to single event upsets

Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides ...

Methods, systems and computer program products for monitoring a task on a computer

Methods, systems and computer program products are provided for monitoring a task executing on a data processing system, the task having an associated work in process queue and an associated work pending queue. The task is configured to properly execute requests that are terminated in progress and restarted from an initial start point. A watchdog task determines if the task is executing properly and restarts the task if it is not executing properly. Restarting is provided by placing requests in the work in process queue of the terminated task in the work pending queue and clearing the work in process queue. Execution by the task of requests from the work pending queue is then reinitiated.

Memory with improved read stability

A static random access memory (SRAM) includes a data line for transferring data to and from the memory and at least one reset line, a plurality of storage cells, each cell including an asymmetric feedback loop; an access device for selectively providing a connection between the at data line and the cell's first access node; a reset device for selectively providing a connection between a reset line and the cell's second access node. The SRAM further includes data access control circuitry for generating control signals for independently controlling the access device and the reset device and to generate a data access control signal. The SRAM also generates a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.

Systems and methods for distributing a neural network across multiple computing devices

Disclosed herein is a method for using a neural network across multiple devices. The method can include receiving, by a first device configured with a first one or more layers of a neural network, input data for processing via the neural network implemented across the first device and a second device. The method can include outputting, by the first one or more layers of the neural network implemented on the first device, a data set that is reduced in size relative to the input data while identifying one or more features of the input data for processing by a second one or more layers of the neural network. The method can include communicating, by the first device, the data set to the second device for processing via the second one or more layers of the neural network implemented on the second device.

Sequential storage circuitry for an integrated circuit

Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted ...

METHOD AND SYSTEM FOR PROVIDING PERFORMANCE ASSESSMENT OF TERMINAL DEVICES

A method for providing performance assessment of terminal devices is provided. A user initiates, by way of a service application that runs on a user device of the user, a first request for obtaining risk scores or connectivity scores of the terminal devices. The first request may include terminal identifiers of specific terminal devices or information pertaining to a specific geographical area. The user device communicates the first request to a server. The server determines the risk scores or the connectivity scores based on the first request. The server transmits, to the user device, a first response that includes the risk scores or the connectivity scores. The user device displays the risk scores or the connectivity scores to the user based on the first response, thereby providing the performance assessment of the terminal devices. 1. A method for providing performance assessment of one or more terminal devices , the method comprising:receiving, by a server from a user device of a user, a request for one or more risk scores of the one or more terminal devices, respectively, wherein each risk score indicates a measure of risk associated with performing a transaction at a corresponding terminal device of the one or more terminal devices;determining, by the server based on the request, the one or more risk scores, wherein each risk score is determined based on a transaction history of the corresponding terminal device; andtransmitting, by the server to the user device, the one or more risk scores, wherein the one or more risk scores are presented to the user on a user interface rendered on the user device.2. The method of claim 1 , further comprising hosting claim 1 , by the server claim 1 , a service application executable on the user device claim 1 , wherein the request is received by the server by way of the service application claim 1 , and wherein the user interface is rendered by the service application.3. The method of claim 1 , wherein the transaction ...

Process variation compensation with correlated electron switch devices

Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to compensating for integrated circuit manufacturing process variation with correlated electron switch devices.

Methods, systems and computer program products for scheduled network performance testing

Methods, systems and computer program products are provided which test network performance by defining test schedules including test protocols to be implemented and when the protocols should be executed for a plurality of defined connections on a network. A connection may be defined between two endpoint nodes on the network. At times specified in the test schedule, the endpoint node pair executes the test protocol and measures the performance of the network connection between the two nodes without requiring any involvement of application software which may or may not be installed on the computer hardware supporting the endpoint node. The test protocol may define the type of network layer protocol to utilize (for example, TCP), and the test script or scripts to be communicated using the appropriate stack on the computer hardware supporting the endpoint node. The schedule may be provided with an expiration date and a console node is provided for distribution of test schedules, monitoring ...

PROCESS VARIATION COMPENSATION WITH CORRELATED ELECTRON SWITCH DEVICES

Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to compensating for integrated circuit manufacturing process variation with correlated electron switch devices. 1. A method , comprising:compensating for manufacturing process variation in an integrated circuit at least in part by programming a variable impedance circuit comprising two or more correlated electron switch devices.2. The method of claim 1 , wherein the programming the variable impedance circuit comprises individually programming at least one of the two or more correlated electron switch devices.3. The method of claim 2 , wherein the individually programming the at least one of the two or more correlated electron switch devices comprises applying one or more voltage signals to the at least one of the two or more correlated electron switch devices sufficient to transition the at least one of the two or more correlated electron switch devices from a first impedance state to a second impedance state.4. The method of claim 3 , wherein the first impedance state comprises a relatively lower impedance state and wherein the second impedance state comprises a relatively higher impedance state.5. The method of claim 4 , wherein the two or more correlated electron switch devices comprises three or more correlated electron switch devices claim 4 , and wherein the individually programming the at least one of the three or more correlated electron switch devices comprises applying two or more voltage signals to at least two of the three or more correlated electron switch devices sufficient to transition the at least two of the three or more correlated electron switch devices from the relatively lower impedance state to the relatively higher impedance state.6. The method of claim 5 , wherein the integrated circuit comprises a sense amplifier circuit.7. The method of claim 6 , wherein the compensating for the manufacturing process variation in the sense ...

SYSTEMS AND METHODS FOR DISTRIBUTING A NEURAL NETWORK ACROSS MULTIPLE COMPUTING DEVICES

Disclosed herein is a method for using a neural network across multiple devices. The method can include receiving, by a first device configured with a first one or more layers of a neural network, input data for processing via the neural network implemented across the first device and a second device. The method can include outputting, by the first one or more layers of the neural network implemented on the first device, a data set that is reduced in size relative to the input data while identifying one or more features of the input data for processing by a second one or more layers of the neural network. The method can include communicating, by the first device, the data set to the second device for processing via the second one or more layers of the neural network implemented on the second device. 1. A method comprising:receiving, by a first device configured with a first one or more layers of a neural network, input data for processing via the neural network implemented across the first device and a second device;outputting, by the first one or more layers of the neural network implemented on the first device, a data set that is reduced in size relative to the input data while identifying one or more features of the input data for processing by a second one or more layers of the neural network; andcommunicating, by the first device, the data set to the second device for processing via the second one or more layers of the neural network implemented on the second device.2. The method of claim 1 , further comprising reducing claim 1 , by the first one or more layers claim 1 , the data set by compressing the data set for transmission via a network to the second device.3. The method of claim 1 , wherein the second one or more layers detect a feature of the one or more features within the input data.4. The method of claim 3 , further comprising receiving claim 3 , by the first device claim 3 , an indication from the second device that the feature was detected by the ...

CES-based latching circuits

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Single Event Upset error detection within sequential storage circuitry of an integrated circuit

Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.

Electrical component with random electrical characteristic

An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

EXCEPTION PREDICTION BEFORE AN ACTUAL EXCEPTION DURING DEBUGGING

An approach is provided for predicting an exception during a debugging of software code before the debugging encounters the exception. During a debugging of a line number L of the code and based on an exception being predicted to be encountered at a line number M, a warning is displayed that the exception is to be encountered at the line number M, which is within a range of line numbers L+1 through L+X, where L>0 and X>1. Using a fix written in response to the predicted exception, the software code is modified. During a debugging of the line number M of the code, the modified software code is executed to avoid the predicted exception. 1. A method of predicting an exception during a debugging of software code before the debugging encounters the exception , the method implemented by computer-readable program code being executed by a processor of a computer , and the method comprising the steps of:during a debugging of a line number L of the software code and based on an exception being predicted to be encountered at a line number M, the computer displaying a warning that the exception is to be encountered at the line number M, wherein the line number M is within a range of line number (L+1) through line number (L+X), inclusively, wherein L is an integer greater than zero, and wherein X is an integer greater than one;the computer modifying, using a fix written in response to the predicted exception, the software code; andduring a debugging of the line number M of the software code, the computer executing the modified software code to avoid the predicted exception.2. The method of claim 1 , further comprising the steps of:the computer receiving a type of an exception; andthe computer determining the predicted exception is of the type received, wherein the step of displaying the warning is further based on the predicted exception being of the type received.3. The method of claim 1 , further comprising the steps of:the computer locally changing a variable in a function to ...

CES-based latching circuits

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Memory device and method of controlling a write operation within a memory device

A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse ...

Storage circuitry and method with increased resilience to single event upsets

Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs. 1. Storage circuitry comprising:a first storage block configured in at least one mode of operation to perform a first storage function;a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function; andconfiguration circuitry arranged to be responsive to a predetermined mode of operation where said second storage function is unused, to configure said second storage block to operate in parallel with said first storage block to increase resilience of said first storage block to single event upsets (SEUs) whilst performing said first storage function.2. Storage circuitry as claimed in claim 1 , wherein:said first storage block is configured as a latch to perform said first storage function;in said predetermined mode of operation, said configuration circuitry is arranged to configure said second storage block as ...

Exception prediction before an actual exception during debugging

An approach is provided for predicting an exception during debugging of software code before the debugging encounters the exception. A number of lines X is received. A line number L of the code is debugged. In a new thread, upcoming lines consisting of line numbers L+1 through L+X are executed. Based on the execution of the upcoming lines, a prediction is determined that the exception will be encountered at line number M, which is within a range of line numbers L+1 and L+X. Based on the prediction and the line number being within the range, a warning is displayed that the exception is likely to be encountered at line number M. Responsive to the displayed warning, an indication that a corrective action was taken to avoid the exception is received.

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 1. An apparatus , comprising: a programmable fabric including:a plurality of metallization layers individually comprising a plurality of electrically conductive lines; andone or more correlated electron switches to selectively provide a lower impedance connection between one or more of the plurality of electrically conductive lines of the plurality of metallization layers and one or more other of the plurality of electrically conductive lines of the plurality of metallization layers.2. The apparatus of claim 1 , wherein the programmable fabric comprises a cross-point array claim 1 , wherein the electrically conductive lines of a first metallization layer are oriented approximately parallel with each other claim 1 , wherein the electrically conductive lines of a second metallization layer are oriented approximately parallel with each other claim 1 , and wherein the electrically conductive lines of the first metallization layer are oriented approximately orthogonally to the electrically conductive lines of the second metallization layer.3. The apparatus of claim 2 , wherein the one or more correlated electron switches are individually positioned at intersections of the electrically conductive lines of the first metallization layer and the electrically conductive lines of the second metallization layer.4. The apparatus of claim 3 , wherein the programmable fabric further comprises one or more access devices positioned at a respective one or more of the intersections of the electrically conductive lines of the first metallization layer and the electrically conductive lines of the second metallization layer.5. The apparatus of claim 3 , wherein the plurality of access devices comprise schottky diodes.6. The apparatus of claim 3 , further comprising a voltage and/or current source claim 3 , wherein to transition a particular correlated electron switch of the ...

Method and apparatus having dynamically scalable clook domains for selectively interconnecting subsystems on a synchronous bus

In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when the subsystems are not communicating with one another on the bus. Selected pairs of the subsystems are operated at a shared clock frequency by selectively varying frequencies of clock signals to the subsystems, so that communication can occur at the shared clock frequency on the bus between the selected subsystems, but at different clock frequencies for respective different pairings of the subsystems, and so that the subsystems can operate at independent clock frequencies when not communicating with other ones of the subsystems. Communication among the subsystems is by a bus-based protocol, according to which when a subsystem is granted access to the bus the subsystem has exclusive use of the bus.

Sequential storage circuitry for an integrated circuit

Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted ...

CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Memory device and method of controlling a write operation within a memory device

A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques. 1. A memory device comprising:an array of memory cells, each memory cell being configured to support writing and simultaneous reading of that memory cell;write circuitry configured, during a write operation, to provide write data to a number of addressed memory cells within the array;word line select circuitry, responsive to a start of the write operation, to assert a write word line signal to enable said number of addressed memory cells to store said write data; andcomparing circuitry configured, during the write operation, to compare said write data with data currently stored in said number of addressed memory cells;the comparing circuitry being responsive to detecting that said write data matches the data currently stored in said ...

Spiking neural network

Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.

INTERACTIVE AND ANALYTICAL MOBILE SYSTEM THAT PROVIDES A DYNAMIC TOOL FOR THERAPIES TO PREVENT AND CHANGE THE PROGRESSION OF DEMENTIA-RELATED DISEASES

A computer-implemented method, system, and apparatus for providing interactive and analytical components that provide a comprehensive and dynamic tool for therapies to prevent and reverse dementia-related diseases. The invention includes one or more computers that receive and store personal information for people. The computers also generate synergic data specifying an expected adjustment of individual biological. For each person, the computers process personal information and identify a subset of biological mechanisms that are principally affected by dementia-related diseases or the substantial risk of dementia-related diseases. The computers also apply the personal generate for each person one or more messages communicating a therapy plan containing a combination of therapies and determines how to apply the therapies. The computers use several means to collect therapy compliance information and convey correctional instructions from coaches. The computers collect, store, and transmit all personal information, therapy plans, and compliance information securely. 1. A system comprising: [ receive, in response to presenting at least a portion of an individual therapy plan, conformance information;', 'send, to a monitoring server device, the conformance information;, 'a first processor and a first memory operable to, 'present at least the portion of the individual therapy plan;', 'a first display operable to], 'a participant device comprising receive participant information including two or more of personal and family background data, pre-existing conditions, current medications, genomic data, and diagnostic information, the diagnostic information relating to biological mechanisms that define dementia-related diseases as a medical condition or risk of dementia-related diseases;', 'receive therapy plan information, the therapy plan information comprising a plurality of individual therapy plans, each individual therapy plan specifying an individual biological mechanism ...

Low overhead circuit and method for predicting timing errors

A data processing circuitry includes a data input, a data output and a processing path arranged between the data input and the data output. The circuitry includes a plurality of retention circuits arranged in parallel with the processing path. At least one potential error detecting circuit including a potential error detecting path for transmitting the data signal pending at an input of one of a plurality of synchronization circuits to one of the retention circuits where the potential error detecting path includes delay circuitry for delaying the data. Also included is comparison circuitry for comparing a value of the data signal captured by one of the synchronization circuits with a value of the data signal captured by a corresponding one of the retention circuits. A comparison circuitry is configured to signal a potential error in response to detecting a difference in the captured data values.

One-time and multi-time programming using a correlated electron switch

An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.

Correction of single event upset error within sequential storage circuitry of an integrated circuit

Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and ...

APPARATUS AND METHOD FOR GENERATING A RANDOM NUMBER

An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random ...

Method and apparatus for memory wear leveling

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

SYSTEM AND METHOD FOR SUPPORTING ALTERNATE NUMBER FORMAT FOR EFFICIENT MULTIPLICATION

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values. 1. A device comprising:{'sup': 'n', 'claim-text': [{'sup': 'n', 'when the two or more second bits represent the value of 2, shift the second value by (n+1) bits via the shift circuitry to provide a first multiplication result,'}, 'based on a value of the first bit of the first value, selectively output zero or the second value to provide a second multiplication result, and', 'add the first multiplication result and the second multiplication result via the add circuitry to provide a result of the multiplication of the first value and the second value., 'circuitry comprising shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network, the first value having a predetermined format comprising a first bit, and two or more second bits to represent a value of zero or 2wherein n is an integer greater than or equal to 0, the circuitry configured to2. The device according to claim 1 , wherein the first bit of the first value is a least significant bit of the first value.3. The device according to claim 1 , wherein the circuitry is configured to provide claim 1 , when the two or more second bits represent the value of zero claim 1 ...

Computer implemented system and method for reducing failure in time soft errors of a circuit design

A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.

CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs. 1. A circuit comprising:a plurality of Correlated Electron Switches (CESs) arranged to form a configurable impeder, wherein each CES is capable of being configured to one of a plurality of impedance states; andat least one programing circuit configured to provide a plurality of programing signals each dependent on at least one input signal, wherein each programing signal configures an impedance state of a CES of the plurality of CESs.2. The circuit of claim 1 , wherein the at least one programing circuit comprises a plurality of programing circuits claim 1 , each programing circuit being configured to provide one of the plurality of programing signals.3. The circuit of claim 2 , wherein the plurality of impedance states comprises a first impedance state and a second impedance state claim 2 , and wherein each programing circuit comprises:a first driving circuit to provide a first programing signal to configure the CES into the first impedance state; anda second driving circuit to provide a second programing signal to configure the CES into the second impedance state,wherein one of the first programing signal and the second programing signal is dependent on the at least one input signal.4. The circuit of claim 2 , further comprising logic circuitry coupled to the programing circuit and arranged to enable the programming circuit to provide respective programing signals dependent on the at least one input signal.5. The circuit of claim 1 , further comprising a control circuit configured to:receive the least one input signal; andprovide at least one ...

CES-BASED LATCHING CIRCUITS

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Hierarchical functional and variable composition diagramming of a programming class

Inheritance contributions of programming class functions and class variables are diagrammed. A functional diagram illustrates individual class contributions of functions. A variable composition diagram illustrates individual class contributions of variables. A diagrammatic depiction of functions overridden and functions contributed in the inheritance hierarchy is provided. Functions which are unique, overridden and/or have contributions in different classes of the hierarchy are visually distinguished (e.g., by distinguishing marks). Classes in the hierarchy are graphically depicted with relative sizes based on percent contribution.

DYNAMIC SELECTION OF ONE OF MANY AVAILABLE WEB BROWSERS

A user selection of an item corresponding to a Web page can be received. The user selection can represents a request to open the Web page within an instantiated one of a set of Web browser applications installed on a computing device. A set of Web page elements unique to the Web page can be identified through an analysis conducted by the computing device. The identified set of Web page elements can be utilized to determine at the computing device one of the installed Web browser applications for the Web page. The determination of the one installed Web browser application can varies from Web page-to-Web page. At the computing device, the determined one of the Web browser applications can be instantiated. The Web page can be opened within the instantiated one of the Web browser applications. 1. A method comprising:at a computing device having a plurality of installed Web browser applications, receiving, via a user interface of the computing device, a user selection of an item corresponding to a Web page, wherein the user selection represents a request to open the Web page within an instantiated one of the Web browser applications;identifying a set of Web page elements unique to the Web page through an analysis conducted by the computing device;utilizing the identified set of Web page elements to determine at the computing device one of the installed Web browser applications for the Web page, where the determination of the one installed Web browser application varies from Web page-to-Web page;instantiating at the computing device the determined one of the Web browser applications;opening within the instantiated Web browser application, the Web page.2. The method of claim 1 , wherein the identifying occurs responsive to receiving the user selection claim 1 , wherein manual user interactions other than the user selection of the item occur as the computing device performs the identifying claim 1 , the utilizing claim 1 , the instantiating claim 1 , and the opening of the ...

Meloxicam co-crystals

Co-crystals of meloxicam co-formers can be prepared by co-crystallization from a polar solvent, such as aqueous dimethyl sulfoxide; or by slurry processes, such as with ethyl acetate. Such co-crystals have improved purities and are physically stable under storage for several months.

ADDRESS DEPENDENT DATA ENCRYPTION

Encryption of data within a memory is provided by key generation circuitry which serves to generate a key as a function of the address within the memory being accessed and then encryption circuitry or decryption circuitry which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance. 1. Apparatus comprising:memory to store encrypted data representing unencrypted data at a storage location specified by an address;key generation circuitry to generate a key as a function of said address;encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key.2. Apparatus as claimed in claim 1 , wherein a given data value stored at different storage locations is encrypted using keys generated as a function of different respective addresses.3. Apparatus as claimed in claim 1 , wherein key generation circuitry comprises physically unclonable function circuitry claim 1 , wherein said address is a challenge input to said physically unclonable function circuitry and said key is a response output from said physically unclonable function circuitry.4. Apparatus as claimed in claim 1 , wherein said encryption circuitry has a configuration to perform one-time-pad encryption of said unencrypted data using said key.5. Apparatus as claimed in claim 1 , wherein said key has a character width greater than or equal to a character width of said unencrypted data.6. Apparatus as claimed in claim 1 , wherein said encryption circuitry has a configuration to perform a bitwise XOR of said unencrypted data with said key to form said encrypted ...

STORAGE CIRCUIT WITH RANDOM NUMBER GENERATION MODE

A storage circuit in the form of a master slave latch includes a slave stage serving as a bit storage circuit. The slave stage includes an inverter chain which when operating in a normal mode includes an even number of inverters and when operating in an random number generation mode includes an odd number of inverters and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 1. A storage circuit having a normal mode for receiving and storing an external bit value and a random number generation mode , said data value storage circuit comprising:a bit value storage circuit having an input node for receiving an input bit value from outside said bit value storage circuit and an output node for outputting an output bit value;wherein said bit value storage circuit is configured such that:(i) when said storage circuit is operating in said normal mode, said bit value storage circuit generates at said output node as said output bit value a stable output bit value corresponding to said external bit value; and(ii) when said storage circuit is operating in said random number generation mode, said bit value storage circuit generates at said output node an oscillating output bit value and a change from said random number generation mode to said normal mode leaves said output bit value as a stable pseudo random bit value.2. A storage circuit as claimed in claim 1 , wherein said bit value storage circuit comprises an inverter chain of a plurality of serial connected inverters with said input node located at a first position along said chain and said output node located at a second position along said chain.3. A storage circuit as claimed in claim 2 , wherein said bit value storage circuit comprises a multiplexer disposed in said inverter chain and configured to switch a feedback path around said ...

ADDRESS DEPENDENT DATA ENCRYPTION

Encryption of data within a memory is provided by key generation circuitry which serves to generate a key as a function of the address within the memory being accessed and then encryption circuitry or decryption circuitry which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance. 1. Apparatus comprising:memory to store encrypted data representing unencrypted data at a storage location specified by an address;key generation circuitry to generate a key as a function of said address;encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key;wherein the key generation circuitry comprises physically unclonable function circuitry, said address is a challenge input to said physically unclonable function circuitry, and said key is a response output from said physically unclonable function circuitry.2. Apparatus as claimed in claim 1 , wherein a given data value stored at different storage locations is encrypted using keys generated as a function of different respective addresses.3. (canceled)4. Apparatus as claimed in claim 1 , wherein said encryption circuitry has a configuration to perform one-time-pad encryption of said unencrypted data using said key.5. Apparatus as claimed in claim 1 , wherein said key has a character width greater than or equal to a character width of said unencrypted data.6. Apparatus as claimed in claim 1 , wherein said encryption circuitry has a configuration to perform a bitwise XOR of said unencrypted data with said key to form said encrypted data.7. Apparatus as claimed in claim ...

Electrical component with random electrical characteristic

An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

POLYMORPHIC FORMS OF SOFOSBUVIR

The present disclosure provides novel crystalline sofosbuvir form-M3 and a process for the preparation of sofosbuvir form-M3. The crystalline sofosbuvir form-M3 disclosed herein may be useful in the formulation of pharmaceutical dosage forms. 1. Crystalline sofosbuvir form-M3.2. The crystalline sofosbuvir form-M3 of claim 1 , characterized by a PXRD pattern having peaks at 2θ angle positions of 7.61 claim 1 , 16.92 claim 1 , and 20.47±0.2°.3. The crystalline sofosbuvir form-M3 of claim 1 , characterized by a PXRD pattern having peaks at 2θ angle positions of 7.61 claim 1 , 14.19 claim 1 , 16.92 claim 1 , 17.98 claim 1 , 19.58 claim 1 , 20.47 claim 1 , and 23.27±0.2°.4. The crystalline sofosbuvir form-M3 of claim 1 , characterized by a PXRD pattern as shown in .5. A process for the preparation of crystalline sofosbuvir form-M3 claim 1 , comprising the steps of:a. dissolving sofosbuvir in a solvent to form a solution;b. adding an anti-solvent to the solution; andc. isolating crystalline sofosbuvir form-M3.6. The process according to claim 5 , wherein the solvent comprises a water-miscible solvent.7. The process according to claim 6 , wherein the solvent further comprises water.8. The process according to claim 6 , wherein the water-miscible solvent is selected from the group consisting of methanol claim 6 , ethanol claim 6 , isopropanol claim 6 , 1-butanol claim 6 , isobutanol claim 6 , 1-pentanol claim 6 , acetone claim 6 , acetonitrile claim 6 , N claim 6 ,N-dimethylformamide claim 6 , dimethylsulfoxide claim 6 , 1 claim 6 ,2-dimethoxyethane claim 6 , and mixtures thereof.9. The process according to claim 5 , wherein the anti-solvent is water.10. The process according to claim 5 , further comprising the step of stirring after adding anti-solvent and before the isolating step.11. The process according to claim 5 , wherein the solution is seeded with crystalline sofosbuvir form-M3 after adding an anti-solvent and before the isolating step.12. (canceled)13. (canceled) ...

METHOD AND APPARATUS FOR MEMORY WEAR LEVELING

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address. 1. An apparatus for wear-leveling of a storage medium , where the apparatus is supplied with electrical power during on-periods of a plurality of power cycles and comprises:a storage element that stores a key value during an off-period or a sleep-period of a power cycle of the plurality of power cycles;address translation logic configured to map a logical address to a physical address in the storage medium, where the mapping is dependent upon the key value; andkey update logic configured to update the key value stored in the storage element;where the key value is updated at one or more power cycles of the plurality of power cycles and the mapping from the logical address to the physical address is varied from one power cycle to another of the one or more power cycles.2. The apparatus of claim 1 , where the storage element comprises a non-volatile memory.3. The apparatus of claim 2 , where the storage element comprises a correlated electron switch (CES) storage element.4. The apparatus of claim 1 , where:the key value comprises an address offset value;the address translation logic comprises an adder having the logical address and the address offset value as inputs; andthe key update logic is configured to store a most recently accessed physical address in the storage element at the end of an on-period of a power cycle.5. The apparatus of claim 1 , where:the key value ...

Integrated circuit device comprising environment-hardened die and less-environment-hardened die

An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

Logic encryption using on-chip memory cells

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

Process for Synthesizing Reduced Graphene Oxide on a Substrate from Seedlac

The present invention relates to synthesizing reduced graphene oxide on the surface of a metal sheet and glass. The invention particularly relates to a process for coating a substrate with reduced graphene oxide using seedlac as a carbon source. As per the process of the current invention, a solution of seedlac is prepared in an alcohol and the substrate is dipped in to the solution for one or more time. The substrate is then dried in air for 1-10 minutes and thereafter, heated to a temperature range of 400 to 1200° C. under controlled atmosphere of Ar/N 2 /Ar—H 2 /N 2 —H 2 at a different flow rate ranging from 100 to 500 seem for a period of 10 to 120 minutes.

Wordline pulse duration adaptation in a data storage apparatus

Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.

SPIKING NEURAL NETWORK

Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element. 1. A spiking neuron for a spiking neural network , the spiking neuron comprising:a correlated electron switch (CES) element for implementing a thresholding function of the spiking neuron.2. The spiking neuron as claimed in further comprising:an accumulator circuit for summing current signals received by the spiking neuron to provide an accumulated current signal.3. The spiking neuron as claimed in wherein the CES element stores a threshold current value corresponding to a compliance current claim 2 , the spiking neuron further comprising: comparing the accumulated current signal with the threshold current value stored by the CES element, and', 'outputting a spike signal if the accumulated current signal is greater than or equal to the threshold current value., 'a comparator circuit for4. The spiking neuron as claimed in wherein the spiking neuron comprises a further CES element for storing the accumulated current signal as a compliance current.5. The spiking neuron as claimed in wherein the comparator circuit comprises: a first mirror circuit for mirroring the accumulated current signal stored in the further CES element; and a second mirror circuit for mirroring the threshold current value stored by the CES element.6. The spiking neuron as claimed in wherein the CES element is programmed into an initial high impedance state claim 2 , and the spiking neuron further comprises:circuitry for applying voltage Vset across the CES element,wherein the spiking neuron outputs a spike when the accumulated current signal exceeds a threshold current Iset and causes the CES element to switch out of the initial high impedance state.7. The spiking neuron as claimed in wherein the CES element is programmed into one of a plurality of low ...

Process for the Preparation of Sofosbuvir

A process for the preparation of intermediates 9, useful in the synthesis of sofosbuvir, as well as intermediates of formula [12] are disclosed herein. 2. The process according to claim 1 , wherein the step of converting the compound of formula 17 to the compound of formula 16 is performed in the presence of a thionyl chloride and a base.3. The process according to claim 2 , wherein the base is selected from the group consisting of alkali metal hydroxides claim 2 , alkali metal carbonates claim 2 , amine bases claim 2 , alcoholic amine bases claim 2 , and mixtures thereof.4. The process according to claim 1 , wherein the oxidizing agent is selected from the group consisting of sodium hypochlorite claim 1 , peroxides claim 1 , and mixtures thereof.5. The process according to claim 1 , wherein the compound of formula 17 may be directly converted to the compound of formula 15 by reacting the compound of formula 17 with a sulfonating agent in the presence of a base.6. The process according to claim 5 , wherein the sulfonating agent selected from the group consisting of sulfuryl chloride claim 5 , sulfuryl fluoride claim 5 , and mixtures thereof;7. The process according to wherein the base is selected from the group consisting of alkali metal hydroxides claim 5 , alkali metal carbonates claim 5 , amine bases claim 5 , alcoholic amine bases and mixtures thereof.8. The process according to claim 1 , wherein the step of fluorinating the compound of formula 15 to the compound of formula 14 is performed in the presence of a fluorinating agent.9. The process according to claim 7 , wherein the fluorinating agent is selected from the group consisting of hydrogen fluoride claim 7 , tetraethylammonium fluoride claim 7 , tetrabutylammonium fluoride claim 7 , and mixtures thereof.10. The process according to claim 1 , wherein the hydrolyzing of formula 14 is carried out in the presence of an acid.11. The process according to claim 9 , wherein the acid is selected from the group ...

ERROR DETECTION IN STORED DATA VALUES

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit. 1. A data storage apparatus comprising:a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word;stored data value parity generation circuitry configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units,wherein the stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units; andtransition detection circuitry configured to detect a change in value of the parity bit.2. The data storage apparatus as claimed in claim 1 , wherein the stored data value parity generation circuitry is configured such that switching within the store. value parity generation circuitry does not occur unless a value of a data bit stored in one of the data storage units changes.3. The data storage apparatus as claimed in claim 1 , further comprising write parity bit circuitry configured to generate a write parity bit when a new data word is written into the plurality of data storage units and to store the write parity bit claim 1 , and the transition detection circuitry is configured to detect the ...

Error detection in stored data values

An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.

System and Method for Using Object References as a Data Type

Described herein is a system and method for using object references as a data type. In response to a request for an object reference for an object by a consuming application, the object reference is generated by a source application. The object reference comprises a data structure comprising an activation uniform resource identifier for activating the referenced object, information for visually representing the object reference, and, optionally, metadata that describes the referenced object. The generated object reference is provided to an operating system component by the source application which provides the object reference to a consuming application. The consuming application can display information regard the object reference in accordance with the information for visually representing the object reference included in the object reference. The user can request reactivation of the object referenced by the object reference.

Method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping

A method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping, including storing dynamic data flow mappings, each dynamic data flow mapping including a mapping of data from an input port corresponding to a source data container to an output port corresponding to a destination data container and a dynamic hierarchical field having a dynamic hierarchical data type, determining a rule language corresponding to each dynamic hierarchical field in the dynamic data flow mappings, the rule language defining acceptable parameters for sub-fields of that dynamic hierarchical data type, and generating static data flow mappings by resolving all dynamic hierarchical fields into static hierarchical fields during compilation of the dynamic data flow mappings with the source data container and the destination data container, the static data flow mappings being generated based at least in part on the rule language corresponding to each dynamic hierarchical field and underlying data in one or more of the source data container or the destination data container.

System and method for using object references as a data type

Described herein is a system and method for using object references as a data type. In response to a request for an object reference for an object by a consuming application, the object reference is generated by a source application. The object reference comprises a data structure comprising an activation uniform resource identifier for activating the referenced object, information for visually representing the object reference, and, optionally, metadata that describes the referenced object. The generated object reference is provided to an operating system component by the source application which provides the object reference to a consuming application. The consuming application can display information regard the object reference in accordance with the information for visually representing the object reference included in the object reference. The user can request reactivation of the object referenced by the object reference.

Digital storage circuit and method with increased resilience to Single Event Upsets (SEU)

The storage circuitry comprises a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. The configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs. In one embodiment, the circuit is arranged in a master-slave configuration (figure 3A) in which the output signal of the second (slave) latch is connected by means of an addressable switch 160 to the input of the first master latch (110,120). The logic outputs produces by auxiliary elements 170,175 and 180 drive the clock and standby signals which are also connected to the supplies on the feedback inventers in the master 120 and slave 150 latches. Other embodiments (figure 5), employ a parallel redundant latch (320, figure 5) in the master latch, whilst another embodiment (figure 6) combines the switchable redundant latch across the master latch with the parallel connection of the slave latch (150/140, figure 6).

Polymorphic forms of sofosbuvir

The present disclosure provides novel crystalline sofosbuvir form-M3 and a process for the preparation of sofosbuvir form-M3. The crystalline sofosbuvir form-M3 disclosed herein may be useful in the formulation of pharmaceutical dosage forms.

Novel solvate form of sumatriptan succinate and process for preparing sumatriptan salt employing the same

The present invention provides a novel solvate of sumatriptan succinate, wherein the solvate is an ethanol solvate and is characterized by using different solid state techniques such as powder X-ray diffraction, differential scanning calorimetry and thermo gravimetric analysis. In addition, the present invention discloses a process for the preparation of said solvate, and pure and improved quality of sumatriptan succinate employing said solvate.

Process for preparing rivastigmine

An improved process for the preparation of Rivastigmine is disclosed.

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Sparse color reconstruction using deep neural networks

One embodiment of the present invention sets forth a technique for performing sparse color reconstruction. The technique includes determining multiple sets of pixel values associated with a first input image, where the multiple sets of pixel values include a first set of luminance values from the first input image and a first set of sparse color values from the first input image. The technique also includes applying, via a neural network, one or more downsampling operations and one or more upsampling operations to feature maps associated with the multiple sets of pixel values to generate an output image that includes a second set of color values for the first input image, wherein the second set of color values is larger than the first set of sparse color values.

Method, system and device for correlated electron switch (ces) device operation

The present techniques generally relate to methods, systems and devices for operation of correlated electron switch (CES) devices. In one aspect, a CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. In one embodiment, a programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.

Method and device for correlated electron switch (ces) device operation

Correlated electron memory element-based latching circuits

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron switch, hereinafter termed CES, element. The latching circuitry further comprises a control circuit coupled to the at least one CES element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Correlated electron resisitve memory element as connecting element between logic circuits

According to one embodiment of the present disclosure, a circuit is provided. The circuit includes a first logic circuit, a second logic circuit, and a Correlated Electron Switch, herein after termed CES, element. The CES element is configured to enable or disable a connection between the first logic circuit and the second logic circuit.

A process for synthesizng reduced graphene oxide on a substrate from seedlac

The present invention relates to synthesizing reduced graphene oxide on the surface of a metal sheet and glass. The invention particularly relates to a process for coating a substrate with reduced graphene oxide using seedlac as a carbon source. As per the process of the current invention, a solution of seedlac is prepared in an alcohol and the substrate is dipped in to the solution for one or more time. The substrate is then dried in air for 1-10 minutes and thereafter, heated to a temperature range of 400 to 1200°C under controlled atmosphere of Ar / N 2 / Ar-H 2 / N 2 - H 2 at a different flow rate ranging from 100 to 500 seem for a period of 10 to 120 minutes.

Process for synthesizing reduced graphene oxide on a substrate from seedlac

Electrical component with random electrical characteristic

An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures (2) including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

System and method for supporting alternate number format for efficient multiplication

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2 n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2 n , the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

System and method for supporting alternate number format for efficient multiplication

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2 n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2 n , the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

Sequential storage circuitry for an integrated circuit

Video reconstruction from videos with ultra-low frame-per-second

In one embodiment, a method includes accessing a video captured by cameras which is associated with a first framerate lower than a threshold framerate, for any two adjacent frames of the accessed video: generating a warped frame from the two adjacent frames based on an optical flow associated with the two adjacent frames, determining alignments for the two adjacent frames, respectively, fusing the determined alignments for the two adjacent frames, and generating a reconstructed frame based on the fused alignment, and reconstructing the accessed video based on the any two adjacent frames and their respective reconstructed frames, wherein the reconstructed video is associated with a second framerate higher than the threshold framerate.

Meloxicam co-crystals

Co-crystals of meloxicam co-formers can be prepared by co-crystallization from a polar solvent, such as aqueous dimethyl sulfoxide; or by slurry processes, such as with ethyl acetate. Such co-crystals have improved purities and are physically stable under storage for several months.

Meloxicam co-crystals

Co-crystals of meloxicam co-formers can be prepared by co-crystallization from a polar solvent, such as aqueous dimethyl sulfoxide; or by slurry processes, such as with ethyl acetate. Such co-crystals have improved purities and are physically stable under storage for several months.

Method, system and device for correlated electron switch (ces) device operation

The present techniques generally relate to methods, systems and devices for operation of correlated electron switch (CES) devices. In one aspect, a CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. In one embodiment, a programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.

Video reconstruction from videos with ultra-low frame-per-second

In one embodiment, a method includes accessing a video captured by cameras which is associated with a first framerate lower than a threshold framerate, for any two adjacent frames of the accessed video: generating a warped frame from the two adjacent frames based on an optical flow associated with the two adjacent frames, determining alignments for the two adjacent frames, respectively, fusing the determined alignments for the two adjacent frames, and generating a reconstructed frame based on the fused alignment, and reconstructing the accessed video based on the any two adjacent frames and their respective reconstructed frames, wherein the reconstructed video is associated with a second framerate higher than the threshold framerate.

Dynamic view of debugging state

An example operation may include one or more of tracking debugging actions performed to a software system via a runtime environment of the debugging actions, identifying one or more debugging attributes of an object of the software system based on the tracked debugging actions performed to the software system, generating a window which includes details of the one or more identified debugging attributes of the object, and displaying the window which includes the details of the one or more identified debugging attributes via a user interface of a debugging program.

Integrated circuit device comprising environment-hardened die and less-environment-hardened die

An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

具有亂數產生模式的儲存電路

以主從鎖存器形式之儲存電路2包括用作位元儲存電路的從屬平臺6。從屬平臺6包括反相器鏈，當在正常模式下運行時，該反相器鏈包括偶數個反相器10、12，且當在亂數產生模式下運行時，該反相器鏈包括奇數個反相器10、12、14，且因此該反相器鏈用作空運轉環形振盪器。當從亂數產生模式切換回正常模式時，隨後振盪停止，且從位元值儲存電路6輸出穩定偽隨機位元值。

Method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping

A method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping, including storing dynamic data flow mappings, each dynamic data flow mapping including a mapping of data from an input port corresponding to a source data container to an output port corresponding to a destination data container and a dynamic hierarchical field having a dynamic hierarchical data type, determining a rule language corresponding to each dynamic hierarchical field in the dynamic data flow mappings, the rule language defining acceptable parameters for sub-fields of that dynamic hierarchical data type, and generating static data flow mappings by resolving all dynamic hierarchical fields into static hierarchical fields during compilation of the dynamic data flow mappings with the source data container and the destination data container, the static data flow mappings being generated based at least in part on the rule language corresponding to each dynamic hierarchical field and underlying data in one or more of the source data container or the destination data container.

Method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping

A method, apparatus, and computer-readable medium for dynamic hierarchical data flow mapping, including storing dynamic data flow mappings, each dynamic data flow mapping including a mapping of data from an input port corresponding to a source data container to an output port corresponding to a destination data container and a dynamic hierarchical field having a dynamic hierarchical data type, determining a rule language corresponding to each dynamic hierarchical field in the dynamic data flow mappings, the rule language defining acceptable parameters for sub-fields of that dynamic hierarchical data type, and generating static data flow mappings by resolving all dynamic hierarchical fields into static hierarchical fields during compilation of the dynamic data flow mappings with the source data container and the destination data container, the static data flow mappings being generated based at least in part on the rule language corresponding to each dynamic hierarchical field and underlying data in one or more of the source data container or the destination data container.

Correction of single event upset error within sequential storage circuitry of an integrated circuit

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Memory with improved read stability

向上した読み取り安定性を有するメモリ

【課題】向上した読み取り安定性を有する静的ランダムアクセスメモリを提供する。 【解決手段】該ＳＲＡＭは、データ値を格納する時にデータ値を保持する第１アクセスノードとデータの相補バージョンを保持する第２アクセスノードとを備える非対称フィードバックループ、データ線と第１アクセスノードとの間に選択的に接続を提供するアクセスデバイス、およびリセット線と第２アクセスノードとの間に選択的に接続を提供するリセットデバイスを備える複数の格納セルと、所定値を格納セルに書き込む書込要求および格納セルから格納値を読み取る読取要求に応答して、第１アクセスノードと少なくとも１つのデータ線との間に接続を提供するように、かつ相補所定値を格納セルに書き込む書込要求に応答して、少なくとも１つのリセット線と第２アクセスノードとの間に接続を提供するように制御信号を生成するデータアクセス制御回路とを備える。 【選択図】図３