COMPUTER MEMORY ARRAY CONTROL

DISK DRIVE CONTROLLER WITH A POSTED WRITE CACHE MEMORY

DISK DRIVE CONTROLLER WITH A POSTED WRITE CACHE MEMORY A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

ERROR CORRECTION SYSTEM FOR USE WITH A ROTATIONAL SINGLE?ERROR CORRECTION, DOUBLE?ERROR DETECTION HAMMING CODE

DEVICE FOR the CORRECTION Of SIMPLE ERRORS AND the DETECTION Of DOUBLE ERRORS

Systematic error correcting method for e.g. computer memory chip, involves decoding corrected message bit by logical calculation performed from combination of number of control bits lower than total number of bits of control syndrome

La présente invention concerne un procédé et un dispositif de correction systématique, à partir de bits de signature fournissant un syndrome de contrôle, d'une erreur pouvant survenir dans les bits de données d'un mot de message au cours d'un traitement à risque tel qu'une mémorisation ou une transmission de données. L'invention, est caractérisée en ce que: - d'une part, au moins un bit du message corrigé est décodé par un calcul logique réalisé à partir d'une combinaison d'un nombre de bits de contrôle strictement inférieur au nombre total de bits du syndrome de contrôle, et - d'autre part, au moins un bit du message corrigé est décodé par un calcul logique réalisé à partir d'une combinaison d'au moins trois bits du syndrome de contrôle.

ERROR DETECTION AND CORRECTION CIRCUITS

분류 코드를 사용한 소프트 데이터의 결정

... 분류 코드를 사용하여 소프트 데이터를 결정하기 위한 장치들 및 방법들이 제공된다. 하나의 예시적인 장치는 분류 코드(CC) 디코더 및 이 CC코드 디코더에 결합된 외부 코드 디코더를 포함할 수 있다. CC 코드 디코더는 CC 코드워드를 수신하도록 구성된다. CC 코드워드는 외부 코드 코드워드의 피스 및 대응하는 CC 패리티 디지트들을 포함한다. CC 디코더는 대응하는 CC 패리티 디지트들을 사용하여, 적어도 부분적으로 외부 코드 코드워드의 피스와 연관된 소프트 데이터를 결정하도록 구성된다.

MEMORY DATA ERROR CORRECTION METHOD

According to the present invention, a memory data error correction method comprises: a step of receiving a burst-specific content from each of multiple bursts of a memory module; a step of storing the burst-specific content from each of the multiple bursts; and a step of using all error correction code (ECC) beats received as a part of a single error correction double error detection (SECDED) code from at least one of the multiple bursts to correct at least one error included in the first predetermined number of beats of burst-specific data. The burst-specific content includes the first predetermined number of beats of the burst-specific data as well as corresponding beats of a burst-specific ECC. According to the present invention, error correction performance can be improved even by using existing SECDED circuitry. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

가변 코드 레이트 고체-상태 드라이브

... 장치(100)뿐만 아니라 이를 위한 방법(200) 및 시스템(400)은 일반적으로 정보를 저장하는 것에 관한 것이다. 이러한 장치에서, 메모리 제어기(110)는 코드 레이트(112)를 제공하기 위한 것이다. 인코더(120)는 인코딩된 데이터(121)를 제공하기 위해 코드 레이트(112) 및 입력 데이터(111)를 수신하기 위한 것이다. 고체-상태 저장소(130)는, 저장된 데이터(133)로서, 인코딩된 데이터(121)를 수신 및 저장하기 위한 것이다. 디코더(140)는, 저장된 데이터(133)에 액세스하고, 그리고 액세스되는 저장된 데이터(133)의 디코딩된 데이터(141)를 제공하기 위해 코드 레이트(112)를 수신하기 위한 것이다. 디코딩된 데이터(141)는 소프트 판정들로서 제공된다. 메모리 제어기(110)는, 디코딩된 데이터(141)의 확률들에 대한 응답으로 코드 레이트(112)를 조정하기 위해, 디코딩된 데이터(141)를 수신하기 위한 것이다.

Data storage device and data maintenance method

DATA STORAGE DEVICE AND DATA STORAGE METHOD FOR DETECTING CURRENTLY-USED LOGICAL PAGES

Semiconductor memory device and method of controlling the same

RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT

Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.

Memory Device with Variable Code Rate

Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

PARITY GENERATION CIRCUITS FOR A PLURALITY OF ERROR CORRECTION LEVELS, MEMORY CONTROLLERS, AND MEMORY MODULES INCLUDING THE PARITY GENERATION CIRCUITS

A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.

SYSTEMS AND METHODS FOR EFFICIENT UNCORRECTABLE ERROR DETECTION IN FLASH MEMORY

A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.

Memory systems and methods of correcting errors in the memory systems

A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.

Error detection and correction in data processing systems

An error detection and correction system for use in a data processing system wherein all single bit errors in a data word can be detected and corrected by the use of a unique modified Hamming code technique. In accordance therewith, during the write portion of a memory cycle, odd and even parity checks are made on a predetermined number of different, selected combinations of bits in each data word, to form a plurality of parity check bits which are combined with the original data word bits to form an extended data word. During the read portion of the memory cycle, the same number of odd and even parity checks are made on selected combinations of bits of the extended data word which combinations include the same selected combinations of bits used during the write portion plus the parity check bit associated therewith to provide a plurality of error bits. The error bits are decoded to identify the location of any single-bit error which may have occurred in the extended data word so that the ...

Methods and apparatuses for error correction

Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

Two dimensional encoding for non-volatile memory blocks

Method for encoding information in a flash memory block which combines an independent encoding of each page with a block-level code across multiple pages. The method includes two independent error correction codes, one in horizontal direction and one in vertical direction, with horizontal direction error correction decoding; and vertical direction erasure correction decoding.

Semiconductor memory device and memory system having the same

Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

Memory reallocation during raid rebuild

Apparatus and method for managing data in a multi-device storage system, such as a RAID (redundant array of independent discs) system. Distributed data sets are stored across a plurality of storage devices. A selected storage device is replaced with a new storage device responsive to an anomalous event. A rebuild operation is performed to reconstruct data from the selected storage device to the new storage device. The rebuild process includes accessing a list of distributed data sets in a local memory. For each distributed data set in the list identified as constituting valid data, read commands are issued to the remaining storage devices and a write command is issued to the new storage device. For each distributed data set in the list identified as constituting unused data, a data clear command is issued to each of the remaining storage devices and to the new storage device.

Controller, semiconductor memory system and operating method thereof

An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.

SYSTEMS AND METHODS FOR ULTRA FAST ECC WITH PARITY

Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Soft decoding systems and methods for flash based memory systems

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Non-volatile memory controller with error correction (ECC) tuning via error statistics collection

A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

Method and system for optimized soft decoding in a data storage device

Systems and methods are disclosed for decoding solid-state memory cells. In certain embodiments, a data storage device includes a controller configured to decode a non-volatile memory array by performing a first read of a plurality of code words from the non-volatile memory array using a first reference voltage level and performing a second read of the plurality of code words using a second reference voltage level on a first side of the first reference voltage level. The controller is further configured to generate a soft-decision input value associated with a first code word of the plurality of code words based on the first and second reads and decode the first code word using the soft-decision input value.

Single-port memory with opportunistic writes

An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.

Probabilistic error correction in multi-bit-per-cell flash memory

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Method for accessing flash memory module and associated flash memory controller and electronic device

The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

Selectively de-straddling data pages in non-volatile memory

A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Pool-level solid state drive error correction

A method for performing error correction for a plurality of storage drives and a storage appliance comprising a plurality of storage devices is disclosed. In one embodiment, the method includes generating a first set of parity bits from a first set of data of at least one of the plurality of storage devices, the first set of parity bits capable of correcting a first number of error bits of the first set of data. The method further includes generating a second set of parity bits from a concatenated set of the first data and a second set of data from at least another of the plurality of storage devices, the second set of parity bits capable of correcting a second number of error bits of the first set of data, the second number being greater than the first number. The method further includes reading the first set of data and (i) correcting error bits within the first set of data with the first set of parity bits where a number of error bits is less than the first number of error bits; and ...

ERROR CORRECTION USING WOM CODES

A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY

Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.

Error correction with multiple LLR-LUTS for a single read

Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

Wirelessly communicating a data file

A dispersed storage (DS) processing module sends a plurality of undecodeable portions of a plurality of data files via a public wireless communication network to one or more targeted devices of a private wireless communication network. The DS processing module continues processing by sending data content indicators regarding the plurality of data files and in response to a selection of a data file of the plurality of data files based on a corresponding one of the data content indicators, sending, via the private wireless communication network, one or more encoded data slices of each of one or more sets of encoded data slices of the data file such that, for each of the one or more sets of encoded data slices, the one or more targeted devices obtains at least a decode threshold number of encoded data slices to decode the data file.

MEMORY SYSTEM THAT CARRIES OUT SOFT BIT DECODING

A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

METHOD AND APPARATUS FOR CORRECTING ERRORS IN MEMORY DEVICE

A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.

Memory system that carries out soft bit decoding

A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

Method of correcting errors in a memory array and method of screening weak bits in the same

A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

METHODS AND DEVICES FOR ERROR CORRECTION

Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.

POISON BIT ERROR CHECKING CODE SCHEME

LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC)

A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code, ECC, decoder may determine the chunk of data based at least in part on the component codeword.

GERAET ZUR VERRINGERUNG DES ZUR FEHLERERKENNUNG- UND KORREKTUR ERFORDERLICHEN SPEICHERS IN DATENVERARBEITUNGSMASCHINEN.

Verfahren und Überprüfungseinheit zum Überprüfen von Daten in einer Speichereinheit eines System-on-a-Chip

Die Erfindung betrifft ein Verfahren zum Überprüfen von Daten in einer Speichereinheit (120) eines System-on-a-Chip (100), wobei in dem System-on-a-Chip (100) eine Überwachungseinheit (140) implementiert ist, welche von dem System-on-a-Chip (100) aktiviert oder deaktiviert werden kann, wobei die Überwachungseinheit (140), wenn diese aktiviert wird, in der Speichereinheit (120) Fehlerkorrekturcodes zum Durchführen von Fehlerkorrekturverfahren derart hinterlegt, dass für eine vorgegebene Anzahl von Datenblöcken der Speichereinheit (120) jeweils ein Datenblock mit einem zugehörigem Fehlerkorrekturcode hinterlegt wird, wobei, wenn ein Zugriff auf Daten in der Speichereinheit (120) erfolgen soll, die Überwachungseinheit (140) die jeweiligen Daten und einen zugehörigen Fehlerkorrekturcode adressiert und die adressierten Daten vor dem jeweiligen Zugriff mit dem adressierten Fehlerkorrekturcode überprüft und bei Bedarf korrigiert.

Enhanced low overhead data protection in data storage drives

This application is for a new way of monitoring the quality of a write process to a storage medium that uses shingled magnetic recording (SMR), or a perpendicular magnetic recording (PMR). The quality is measured using position error signal (PES) metrics, and can be the number of squeezed sectors per track, distance between adjacent tracks or the accuracy of the write. The invention works by the host system 340 sending a write operation to a storage controller 321, which monitors the PES values and writes the data to a cold storage area 325 of the storage medium 322. If the quality falls below a threshold, then a data protection node determines an enhanced error correction code (ECC), which is written to the ECC area of the storage medium. When the data is read back the enhanced ECC is used to compensate for the quality of the write, and correct the data.

Recovery of multi-page failures in non-volatile memory system

Multi-chip device and method for storing data

Recording apparatus

DISK DRIVE EXPENSIVE EQUIPMENT WITH NACHSCHREIBCACHESPEICHER

Repair-optimal parity code

Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data. Cient Cient I Storage Controller 106_______ ...

Repair-optimal parity code

Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data. Cient Cient I Storage Controller 106_______ ...

SYSTEM FOR TRANSLATING TO AND FROM SINGLE ERROR CORRECTION DOUBLE ERROR DETECTION HAMMING CODE AND BYTE PARITY CODE

Computing system with data protection mechanism and method of operation thereof

ERROR CORRECTION METHOD OF MEMORY DATA

SYSTEM AND METHOD OF DISTRIBUTIVE ECC PROCESSING

ENCODING AND DECODING DATA TO ACCOMMODATE MEMORY CELLS HAVING STUCK-AT FAULTS

... 데이터 저장 시스템은, 메모리 셀들을 갖는 제어 회로 및 상기 메모리 셀들에 저장을 위해 제공된 데이터 비트들을 수신하도록 동작하는 제어 회로를 포함한다. 상기 제어 회로는 제1 매트릭스를 수신하도록 동작할 수 있다. 상기 제1 매트릭스의 각 행은 데이터 비트들의 특정한 하나에 대응한다. 상기 제어 회로는 고착 고장들을 갖는 메모리 셀들의 서브세트에 저장을 위해 제공된 데이터 비트들에 대응하는 제1 매트릭스의 행들만 갖는 제2 매트릭스를 생성하도록 동작할 수 있다. 상기 제어 회로는 제2 매트릭스의 선형 독립인 열들을 갖는 제3 매트릭스를 생성하도록 동작할 수 있다. 상기 제어 회로는 상기 제3 매트릭스를 사용하여, 부호화된 데이터 비트들 및 중복 비트들을 생성하기 위해 데이터 비트들을 부호화하도록 동작할 수 있다.

STORAGE SYSTEM BASED FLASH MEMORY AND ERROR CORRECTING METHOD THEREOF

Error correction code circuit, semiconductor memory device and memory system

메모리에서의 오류 정정

... 메모리에서의 오류 정정을 위한 장치, 시스템 및 방법이 개시된다. 일 실시예에서, 제어기는, 메모리에 저장되는 데이터에 대한 판독 요청을 호스트 디바이스로부터 수신하고, 데이터 및 연관되는 오류 정정 코드워드를 검색하고, 데이터를 호스트 디바이스에 송신하고, 데이터와 함께 검색되는 오류 정정 코드워드를 디코딩하기 위해 오류 정정 루틴을 적용하고, 오류 정정 코드워드에서의 오류에 응답하여 오류와 연관되는 데이터의 위치를 호스트 디바이스에 송신하기 위한 로직을 포함한다. 다른 실시예들도 개시되고 청구된다.

NONVOLATILE MEMORY DEVICE AND SYSTEM INCLUDING SAME FOR PROVIDING FAST BOOTING

Disclosed are a nonvolatile memory device and a system including the same for providing fast booting. According to an aspect of the present disclosure, the memory device includes a non-volatile first memory for storing boot data, a buffer for providing the boot data to a host via a volatile memory interface, and a controller for controlling transfer of the boot data from the first memory to the buffer in response to the instruction of the host. The present invention can perform fast booting without needing to read boot data from the additional interface. COPYRIGHT KIPO 2017 ...

Memory controller and method for correcting Error the same, and Memory system having the same

PURPOSE: A memory controller is provided to use a plurality of ECC data generated through same algorism for correcting errors of lead data, thereby collecting more error bit number without over design. CONSTITUTION: A memory controller comprises: a control unit(22) analyzing read data from a memory device(40) and a first ECC data according to the lead data about the lead data. In case an error bit number of the lead data is larger than the error bit number capable of being collected by using the first ECC data, the control unit generates a plurality of sub data from a write data supposed to be written in the memory device. In order to correcting each error of the plurality of sub data, ECC block(24) generates the first ECC data and the second ECC data by the use of same algorism. COPYRIGHT KIPO 2012 ...

MEMORY CONTROLLER, MEMORY SYSTEM AND OPERATING METHOD OF MEMORY CONTROLLER

소프트 데이터 결정

... 본 발명은 소프트 데이터를 결정하기 위한 장치들 및 방법들을 포함한다. 다수의 실시예는 메모리 셀의 데이터 상태와 연관된 소프트 데이터를 결정하는 단계를 포함한다. 다수의 실시예에서, 소프트 데이터는 메모리 셀 상에서 단일 단계적 감지 동작을 수행함으로써 결정될 수 있다.

NAND FLASH MEMORY CONTROLLER USING COMPRESSION RATE AND NAND FLASH MEMORY STORAGE METHOD USING SAME

The present invention relates to a NAND flash memory controller using a compression rate and a NAND flash memory storage method using the same. According to the present invention, the NAND flash memory storage method using the NAND flash memory controller comprises: a step of calculating a compression rate of input data; a step of calculating a code rate of original data by using the calculated compression rate and a plurality of predetermined threshold ranges; a step of determining the number of bits of an error correction code depending on the code rate; a step of generating an error correction code by the determined bit number; a step of generating compression data by compressing original data depending on the calculated compression rate; and a step of combining the generated error correction code with the compression data and storing the combined data in a NAND flash memory. Like the above, the present invention can improve the error correction ability and stability of data stored in ...

Checksum using sums of permutation sub-matrices

A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.

Method and apparatus for performing dynamic recovery management regarding redundant array of independent disks

A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.

DATA STORAGE SYSTEM AND RELATED METHOD

ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

SYSTEMS, METHODS AND DEVICES FOR DECODING CODEWORDS HAVING MULTIPLE PARITY SEGMENTS

An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module.

Systems and methods for enhanced data recovery in a solid state memory system

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

Priori information based post-processing in low-density parity-check code decoders

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

METHOD FOR DECODING BITS IN A SOLID STATE DRIVE, AND RELATED SOLID STATE DRIVE

A corresponding solid state drive is also proposed.

Memory circuit

When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37 , respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Systems and Methods for Managing Address-Mapping Data in Memory Devices

Methods, apparatuses, and data storage devices are provided. Address-mapping data is compressed. The address-mapping data indicates mapping from a logical address to a physical address of a non-volatile memory of a storage device. Error checking and correction (ECC) data for the compressed address-mapping data is generated. The compressed address-mapping data and the ECC data are stored in the storage device.

Method and system for determining soft information offsets

Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset.

Redundancy schemes for non-volatile memory based on physical memory layout

A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.

MEMORY PROTECTION DEVICE AND METHOD

A memory protection device is used for protecting a memory. The memory protection device includes a filtering unit and an encoding unit. The filtering unit searches an input data and outputs an encoding selection signal based on a bit component pattern of the input data. The encoding unit selects one or more encoding implementations among a plurality of encoding implementations based on the encoding selection signal from the filtering unit, to encode the input data.

PRESERVING DATA INTEGRITY IN A MEMORY SYSTEM

A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.

Memory system

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

Fault tolerant disk array system for allocating auxillary disks in place of faulty disks

When an amount of write data instructed by an upper-level system is small, a plurality of disk units are accessed individually and data split in sectors is written therein (Level 5 RAID). When an amount of write data instructed by the upper-level system is large, the plurality of disk units are accessed in parallel and data split in sectors is written therein (Level 3 RAID). When a disk unit in an array, to which a setup instruction is issued according to a processing request sent from the upper-level system, returns a fault reply, an ID management table is used to allocate an auxiliary disk instead of the failing disk unit. After the allocation, data is restored to the replacement disk using the data in normal disk units in the same rank. In a dual-port access configuration, when two transactions access disk units connected to the same port, a deadlock may occur depending on the access procedure. It is checked if the conditions for a deadlock are established, so that access will be obtained ...

VSS LDPC decoder with improved throughput for hard decoding

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.

Data storage device comprising super block parity data based on page type of word line or plane

A data storage device may include a plurality of nonvolatile memory devices including a plurality of blocks and a controller suitable for generating super block parity data for a super block, which is formed of one or more of the plurality of blocks.

Biasing schemes for storage of bits in unreliable storage locations

A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Bandwidth optimization in a non-volatile memory system

A method of bandwidth optimization in a non-volatile memory system includes: retrieving hard data bits; generating soft information from the hard data bits; applying a lossless compression to the soft information for calculating syndrome bits; and executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.

CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

An operating method of a controller, comprising: generating, when a first ECC decoding operation to codeword read from a semiconductor memory device according to a hard read voltage fails, an optimization information corresponding the result of the first ECC decoding operation; generating one or more quantization intervals determined by the optimization information; and performing a second ECC decoding operation to codeword read from the semiconductor memory device according to soft read voltages determined by the quantization intervals and the hard read voltage, wherein the optimization information includes: deterioration information of a memory block; ECC decoder parameter information; and constituent code parameter information.

Semiconductor memory device

A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed ...

FLASH MEMORY SYSTEM AND OPERATING METHOD THEREOF

An operation method of a flash memory system includes: performing hard decision decoding on a codeword, which is encoded in units of message blocks with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method; identifying a location of an error message block to which the hard decision decoding fails among a plurality of the message blocks, when the hard decision decoding fails; generating soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block; and performing soft decision decoding on the error message block based on the soft decision information.

ECC Memory Controller To Detect Dangling Pointers

A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Hierarchical data recovery processing for extended product codes

A method includes distributively encoding data stored in a storage system using an erasure-correcting code. The encoded data is distributed into multiple w storage device arrays in the storage system. Each storage device array includes n storage devices. Each storage device is divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Data erasures in the w storage device arrays are corrected by recovering erased data using the erasure-correcting code of un-erased data based on each row and column in each m×n array being protected by the erasure-correcting code for the data. Each group of t storage devices contains extra second responder parities to correct extra data erasures in addition to data erasures corrected by first responder vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.

CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

Provided herein may be a controller and a memory system including the controller. The controller may include a host interface layer, a central process unit, and a buffer memory. The host interface may include a data structure defined by a protocol, and may receive an external request from a host. The central process unit may build the data structure according to the external request or build the data structure in response to an internal request generated during an internal operation. The buffer memory may store the data structure.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a NAND flash memory, an error correction unit, and a table. The NAND flash memory is configured to hold data. The error correction unit detects and corrects errors in the data. The table holds information on an error correction method associated with each piece of data. The error correction unit selects an error correction method to be applied for each piece of data in accordance with the information in the table.

METHOD FOR CODING AND DECODING DIGITAL DATA, PARTICULARLY DATA PROCESSED IN A MICROPROCESSOR UNIT

The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series.

ERROR CORRECTION USING HIERARCHICAL DECODERS

Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

MANAGEMENT OF CORRUPTIVE READ IN MEMORY SYSTEMS

Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary.

Hybrid error correction coding to address uncorrectable errors

A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data.

Soft decoding systems and methods for flash based memory systems

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Semiconductor memory device and method of controlling the same

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Data management in solid state storage systems

Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.

Data processing method, memory controller, and memory storage device

A data processing method is provided. A data is compressed to obtain a compressed data. Compression information corresponding to the compressed data is obtained. Error checking and correcting (ECC) codes are respectively generated for the compression information and the compressed data. The compression information, the compressed data, and the ECC codes are respectively written into a rewritable non-volatile memory module. The compression information, the compressed data, and the ECC codes are respectively read from the rewritable non-volatile memory module. An ECC procedure is preformed on the compression information according to the corresponding ECC code, so as to obtain a storage state when the compression information is written. An ECC procedure is preformed on the compressed data according to the storage state of the compression information and the ECC code corresponding to the compressed data, so as to obtain a storage state when the compressed data is written.

Acquiring a Trusted Set of Encoded Data Slices

A method begins by a dispersed storage (DS) processing module receiving a decode threshold number of encoded data slices of a set of encoded data slices. The method continues with the DS processing module determining whether to evoke a trust verification function and when the trust verification function is to be evoked, selecting one or more encoded data slices of the set of encoded data slices for trust verification to produce one or more selected encoded data slices. The method continues with the DS processing module sending, to a trusted source, a request to receive the one or more selected encoded data slices and when the one or more selected encoded data slices are received from the trusted source, determining that a trusted set of encoded data slices is available based on the decode threshold number of encoded data slices and the received one or more selected encoded data slices.

Zero-one balance management in a solid-state disk controller

An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Recursively determined invertible set approach to correct multiple stuck-at faults in rewritable memory

Systems and methods are disclosed that facilitate storage and retrieval of data to/from memory with permanent faults. Permanent “stuck at” faults, associated with individual bits, interfere with Write operations. A memory bit with the SA-0 fault does not store the value “1” while a memory bit with the SA-1 fault does not store the value “0”. Hence, when later retrieved by a Read operation, stored data located on one or more bits having a permanent fault may be different from the data that was originally written. Techniques are disclosed that facilitate correct retrieval of data in the presence of “stuck at” faults by keeping track of the positions of the bits that are stuck at a value different from the ones that are written and then, at Read time, inverting the values read from those positions.

Device and method for storing encoded and/or decoded codes by re-using encoder

The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.

Storage control apparatus and error correction method

A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group. In a case where the result of this determination is affirmative, the controller corrects the fixed value, in which there is an error, to a correct fixed value, and in a case where the number of errors included in the data group is equal to or less than the number of errors correctable by the guarantee code, uses the guarantee code to correct errors in the data group.

Method of accessing a non-volatile memory

A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.

System and method for detecting errors in audio data

An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults

A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.

Masking Defective Bits in a Storage Array

A method of failure mapping is provided. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

MEDIA QUALITY AWARE ECC DECODING METHOD SELECTION TO REDUCE DATA ACCESS LATENCY

A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action. 1a semiconductor memory device having memory blocks configured to store data; and a memory characterizer configured to characterize the memory blocks, and generate an index decision table based on the characterization of the memory blocks;', 'an in-flight assessor configured to assess a read command from a host and determine an error recovery scheme in accordance with the index decision table related a memory block corresponding to the assessment of the read command; and', 'a selective decoder configured to decode the read data corresponding to the read command with the determined error recovery scheme., 'a memory controller configured to control the semiconductor memory device including. A memory system comprising: This application is a continuation of U.S. patent application Ser. No. 15/353,389 filed on Nov. 16, 2016. The disclosure of each of the foregoing applications is herein incorporated by reference in its entirety.Exemplary embodiments of the present disclosure relate to a memory system, and more particularly to a memory system having a media quality aware Error-Correcting Code (ECC) decoding selection and operating method thereof.The use of computer systems has been rapidly increased in the digital era. Due to this fact, the reliability of digital data storage, such as a memory system, is critical.Electrical or magnetic interference inside the computer system can cause a single bit of memory cells ...

Low ber hard-decision ldpc decoder

A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.

Host Device, Access System, and Access Method

A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written. 1. (canceled)2. A memory system comprising:a nonvolatile memory; anda controller electrically connected to the nonvolatile memory and configured to:manage a plurality of areas of the nonvolatile memory, the areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data,encode write data by using first coding for reducing wear of a memory cell to generate first encoded data,generate second encoded data by adding an error correction code to the first encoded data, the second encoded data including the first encoded data and the error correction code, andwrite the second encoded data to one of the first area and the second area, whereinwhen the write data is the first type of the data, the first encoded data has a first length, and the error correction code has a second length, andwhen the write data is the second type of the data, the first encoded data has a third length less than the first length and the error correction code has a fourth length greater than the second length.3. The memory system of claim 2 , wherein the encoding the write data includes converting a first code in the write data into another code longer than the first code.4. The memory system of claim 2 , wherein the controller is configured to compress the write ...

READ RECOVERY CONTROL CIRCUITRY

An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry. 1. An apparatus , comprising: receive the plurality of error corrected codewords from the error correction component;', 'determine whether codewords among the plurality of error corrected codewords contain an uncorrectable error;', 'determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error;', 'request that codewords among the plurality of error corrected codewords that contain the uncorrectable error are rewritten in response to the determination; and', 'cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry., 'an error correction component coupled to read recovery control circuitry, wherein the error correction component is configured to perform one or more initial error correction operations on a plurality of codewords contained within a managed unit received thereto, and wherein the read recovery control circuitry ...

SYSTEM AND METHOD FOR ADAPTIVE MULTIPLE READ OF NAND FLASH

A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds. 1. A method for reading data , the method comprising:performing a first read operation on a first plurality of flash memory cells, at a first reference voltage, to form a first raw data word;executing a first error correction code decoding attempt with the first raw data word; 'outputting a decoded data word generated by the first error correction code decoding attempt; and', 'when the first error correction code decoding attempt succeeds performing a second read operation on the first plurality of flash memory cells, at a second reference voltage, to form a second raw data word; and', 'executing a second error correction code decoding attempt with the first raw data word and the second raw data word., 'when the first error correction code decoding attempt does not succeed2. The method of claim 1 , wherein the performing of the first read operation comprises storing the first raw data word in a buffer claim 1 , the buffer having sufficient capacity to store the first raw data word and the second raw data word.3. The method of claim 1 , wherein the performing of the second error correction code decoding attempt comprises fetching claim 1 , from a first lookup table claim 1 , a log likelihood ratio corresponding to:a bit of the first raw data word; anda ...

Memory system with low-complexity decoding and method of operating such memory system

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

MEMORY CONTROLLER AND OPERATING METHOD THEREOF

In a memory controller for performing error correction decoding, using an iterative decoding scheme, the memory controller includes a variable node update module for allocating the initial LLR values to variable nodes, and updating values of the variable nodes, using the initial LLR values and Check to Variable (C2V) messages corresponding to the variable nodes in an ith iteration, a syndrome checker for performing a syndrome check, using the values of the variable nodes updated in the ith iteration, and a reversal determiner for determining whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of C2V messages corresponding to the target variable node, when the syndrome check corresponding to the ith iteration fails. 1. A memory controller for performing error correction decoding , using an iterative decoding scheme , the memory controller comprising:a mapper configured to convert read values received from a channel to initial log likelihood ratio (LLR) values;a variable node update module configured to allocate the initial LLR values to a plurality of variable nodes and update values of the variable nodes using the initial LLR values and check to variable (C2V) messages corresponding to the variable nodes in an ith iteration, wherein i is a natural number that is less than a predetermined number of maximum iterations;a check node update module configured to generate C2V messages to be transferred to the variable nodes using variable to check (V2C) messages corresponding to the check nodes in the ith iteration;a syndrome checker configured to perform a syndrome check using the values of the variable nodes updated in the ith iteration; anda reversal determiner configured to, upon a determination by the syndrome checker that the syndrome check corresponding to the ith iteration has failed, determine whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of the C2V ...

Method and System for Decoding Data based on Association of First Memory Location and Second Memory Location

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables. 1. A data storage system , comprising:memory having one or more first memory locations and one or more second memory locations; and receiving first data from the one or more first memory locations;', 'performing a plurality of reads for one or more memory cells at the one or more first memory locations;', 'obtaining read values based on the plurality of reads;', 'determining log likelihood ratios (LLRs) based on the first data and the read values;', 'selecting, for the one or more second memory locations, one or more LLRs from the LLRs, based on an association between the one or more second memory locations and the one or more first memory locations; and', 'decoding second data from the one or more second memory locations using the selected one or more LLRs., 'one or more controllers configured to cause2. The data storage system of claim 1 , wherein the one or more controllers are configured to cause determining that the one or more second memory locations are associated with the one or more first memory locations.3. The data storage system of claim 2 , wherein:determining that the one or more second memory locations are associated with the one or more first memory locations comprises determining that the one or more second memory locations are located in physical proximity to the one or more first memory locations; andthe physical proximity is within a threshold proximity value.4. The data storage system of claim 1 , wherein the association between the one or more second memory locations and the one or more first memory locations is a predetermined association ...

Detection and correction of data bit errors using error correction codes

A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Soft-input soft-output component code decoder for generalized low-density parity-check codes

Disclosed are devices, systems and methods for improved decoding of a binary linear code. An example method includes receiving a noisy codeword; computing a syndrome based on the noisy codeword; identifying N error patterns that correspond to the syndrome; selecting M error patterns from the N error patterns, wherein M≤N are positive integers, wherein a distance between a codeword corresponding to each of the M error patterns and the noisy codeword is less than a distance between a codeword corresponding to any other error pattern and the noisy codeword, and wherein the distance excludes a Hamming distance; modifying the noisy codeword based on each of the M error patterns one-at-a-time; and decoding the modified noisy codeword one-at-a-time until a successful decoding is achieved.

BAD COLUMN HANDLING IN FLASH MEMORY

In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. 1. A nonvolatile memory system comprising:a memory array having a plurality of columns, each of the plurality of columns comprising one or more bit lines; anda soft-input error correction code decoder configured to receive hard data and soft data for at least one bad column of the plurality of columns and further configured to decode the hard data in combination with the soft data to generate decoded data,wherein the soft data comprises compressed information including indication of locations of bad data within the at least one bad column, andwherein the locations of bad data are replaced by indications of low likelihood.2. The nonvolatile memory system of claim 1 , wherein the at least one bad column comprises at least one defective bit line.3. The nonvolatile memory system of claim 1 , wherein the compressed information comprises compressed bit line location information.4. The nonvolatile memory system of claim 1 , wherein the compressed information is obtained by dividing the plurality of columns into a plurality of sections and aggregating the plurality of sections into a folded page.5. The nonvolatile memory system of claim 4 , wherein a folded page column within the folded page is indicated as a bad column based upon a location of the folded page column corresponding to a bad column location in any of the plurality of sections.6. The nonvolatile memory system of claim 1 , wherein the memory array is a NAND flash memory array.7. The nonvolatile memory system of claim 1 , wherein the plurality of columns comprise a plurality of non-redundant columns having the at least one bad column claim 1 , and one or more redundant columns ...

METHODS AND APPARATUSES FOR ERROR CORRECTION

Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures. 1. An apparatus , comprising:a memory device having a plurality of data bits stored in a plurality of multi-level memory cells, and further having parity check bits stored with a set of data bits including a portion of the plurality of data bits, the parity check bits stored with the set of data bits in a block of multi-level cells of the plurality of multi-level memory cells; anda controller coupled to the memory device and configured to convert a flash channel associated with the plurality of multi-level memory cells from an errors channel to an erasures channel, and to perform low density parity check decoding.2. The apparatus of claim 1 , wherein the set of data bits including the portion of the plurality of data bits is less than all data bits of the plurality of data bits.3. The apparatus of claim 1 , wherein the set of data bits including the portion of the plurality of data bits is less than all data bits of the plurality of data bits claim 1 , andwherein the memory device is further configured to store another set of data bits including a remaining portion of the plurality of data bits.4. The apparatus of claim 1 , further comprising:an encoder circuit in the controller, the encoder circuit configured to store parity bits and Bose-Chaudhuri-Hocquenghem (BCH) parity bits generated based on the parity bits,wherein the BCH parity bits are used to generate the parity check bits, andwherein the memory device is further configured to store another set of data bits including a remaining portion of the plurality of data bits ...

Ldpc decoder, semiconductor memory system and operating method thereof

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

Coarse Calibration based on Signal and Noise Characteristics of Memory Cells Collected in Prior Calibration Operations

A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.

Erasure correcting coding using temporary erasure data

In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Spare substitution in memory system

Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

SSD FOR LONG TERM DATA RETENTION

A system and method for long term data retention in a flash memory. In some embodiments, the method includes transitioning the flash memory to a long term data retention state by re-storing first encoded data, the first encoded data being initially stored in the flash memory at a first code rate. The re-storing may include determining a second code rate, lower than the first code rate; reading the first encoded data from the flash memory; decoding the first encoded data at the first code rate to obtain first decoded data; encoding the first decoded data at the second code rate to form second encoded data; and storing the second encoded data in the flash memory. 1. A method , comprising:transitioning a flash memory to a long term data retention state by re-storing first encoded data, the first encoded data being initially stored in the flash memory at a first code rate, the re-storing comprising:determining a second code rate, lower than the first code rate;reading the first encoded data from the flash memory;decoding the first encoded data at the first code rate to obtain first decoded data;encoding the first decoded data at the second code rate to form second encoded data; andstoring the second encoded data in the flash memory.2. The method of claim 1 , wherein the re-storing further comprises claim 1 , after reading a portion of the first encoded data from a first physical block of the flash memory claim 1 , erasing the first physical block.3. The method of claim 2 , further comprising erasing a second physical block after erasing the first physical block claim 2 , the amount of valid data on the first physical block before the erasing of the first physical block being less than the amount of valid data on the second physical block before the erasing of the second physical block.4. The method of claim 2 , wherein the re-storing further comprises reading all valid data from the first physical block before erasing the first physical block.5. The method of claim 1 , ...

DYNAMIC MANAGEMENT OF PROGRAMMING STATES TO IMPROVE ENDURANCE

A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device. 1. A storage device , comprising:a nonvolatile memory device; anda controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding on the plurality of segments,wherein upon determination that error correction decoding of a first segment from among the plurality of segments is completed, the controller is configured to add first error correction parity to the first segment and send the first segment with the added first error correction parity to an external host device, andwherein upon determination that error correction decoding of a second segment from among the plurality of segments is not complete after a threshold time has elapsed from when sending of the first segment from among the plurality of segments was completed, the controller is configured to add an incorrect error correction parity to dummy data and send the dummy data with the added incorrect error correction parity to the external host device.2. The storage device of claim 1 , wherein upon determination that the error correction ...

PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit. 1. A permutation network designing method for a permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder corresponding to a rewritable non-volatile memory module , comprising:identifying a size of a physical page of the rewritable non-volatile memory module as a page size, wherein the physical page is configured to store a plurality of codewords;obtaining a length of each of the codewords as a codeword length according to the amount of the codewords and the page size;identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N;calculating a first value according to the default dimension value, and calculating a second value according to the first value and a saving parameter, wherein the second value is a difference value obtained by subtracting the first value with the ...

SELECTIVELY DE-STRADDLING DATA PAGES IN NON-VOLATILE MEMORY

A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments. 1. A computer-implemented method , comprising:detecting at least one read of a logical page straddled across codewords;storing an indication of a number of detected reads of the straddled logical page; andrelocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner.2. The computer-implemented method as recited in claim 1 , comprising: detecting reading of the logical page straddling across multiple codewords in a same physical page.3. The computer-implemented method as recited in claim 1 , comprising: detecting reading of the logical page straddling across multiple physical pages.4. The computer-implemented method as recited in claim 1 , comprising:storing the indication of the number of detected reads by increment a straddled page read counter in response to detecting each read of the straddled logical page; andrelocating at least the straddled logical page in response to the read counter exceeding a threshold.5. The computer-implemented method as recited in claim 4 , wherein the straddled page read counter indicates a number of reads of all straddled logical pages on a single physical page.6. The computer-implemented method as recited in claim 4 , wherein the straddled page read counter indicates a number of reads of ...

DETERMINING SOFT DATA

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell. 1. An apparatus , comprising:an array of memory cells; and sense a current on a data line to which a memory cell of the array is coupled; and', a data state of the memory cell; and', 'soft data associated with the data state of the memory cell., 'determine, based on the sensed current], 'a controller configured to operate sense circuitry to2. The apparatus of claim 1 , wherein the sense circuitry comprises boost circuitry.3. The apparatus of claim 2 , wherein the boost circuitry comprises an inverter.4. The apparatus of claim 1 , wherein the controller is configured to operate the sense circuitry to:determine, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell; anddetermine, based on the determined voltage, the data state of the memory cell and the soft data associated with the data state of the memory cell.5. The apparatus of claim 1 , wherein the controller is configured to operate the sense circuitry to sense the current on the data line by applying a single stepped sensing signal to the memory cell.6. The apparatus of claim 1 , wherein the array of memory cells is an array of NAND flash memory cells.7. A method for operating memory claim 1 , comprising:sensing a current on a data line to which a memory cell is coupled;determining, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell; and a data state of the memory cell; and', 'soft data associated with the data state of the memory cell., 'determining, based on the determined voltage8. The method of claim 7 , wherein determining the data state of the memory cell and the soft data associated with the data state of the ...

TECHNIQUES TO A SET VOLTAGE LEVEL FOR A DATA ACCESS

Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication. 1. An apparatus comprising:an interface to communicate with one or more memory devices and select a read voltage value for use in a read of a region of the one or more memory devices;', 'in response to an unsuccessful read of the region, determine an error level associated with the unsuccessful read and select a second read voltage value for use to read the region of the one or more memory devices; and', 'in response to an unsuccessful read of the region of the one or more memory devices using the second read voltage value, determine a second error level associated with the unsuccessful read using the second read voltage value and select a third voltage value based at least in part on a change between the second error level from the error level., 'a controller that includes logic, at least a portion of which comprises hardware, the logic to2. The apparatus of claim 1 , wherein the logic is to:determine the error level using a low-density parity-check (LDPC) anddetermine the second error level using a low-density parity-check (LDPC).3. The apparatus of claim 1 , wherein the error level comprises a syndrome weight and the second error level comprises a syndrome weight.4. The apparatus of claim 1 , wherein to ...

Predicted error correction apparatus, operation method thereof and memory system using the same

A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.

Memory device and method of operating the same

The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

MEMORY MODULE, MEMORY SYSTEM HAVING THE SAME, AND METHODS OF READING THEREFROM AND WRITING THERETO

A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit. 1. A method of reading from a memory module which includes a plurality of memories , the read method comprising:reading data corresponding to a plurality of burst length units from the plurality of memories;correcting an error of the read data using a storage error correction code; andoutputting the error corrected data by a unit of data corresponding to one burst length unit.2. The method of claim 1 , wherein each of the plurality of memories is a nonvolatile memory.3. The method of claim 1 , wherein the output data includes user data and read parity bits for detecting an error of the user data and the read parity bits are generated using a transfer error correction code.4. The method of claim 3 , further comprising:dividing the error corrected data by a unit of the user data; andgenerating read parity bits of the divided data using the transfer error correction code.5. The method of claim 4 , further comprising:transferring the output data to a memory management unit controlling the memory module; andcorrecting an error of the data transferred to the memory management unit using the transfer error correction code.6. The method of claim 1 , wherein the read data is formed of a set of user data corresponding to the plurality of burst length units and a set of internal parity bits and the internal parity bits are generated using the storage error correction code in the memory module.7. The method of claim 6 , further comprising:determining whether a storage error of the read data is correctable.8. The method of claim 7 , further comprising:if a storage error of the read data is uncorrectable ...

Error control in memory storage systems

A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Methods and devices to increase memory device data reliability

A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

MEMORY SYSTEM AND CONTROL METHOD

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information. 119-. (canceled)20. A method for controlling a non-volatile memory using a decoder , the method comprising:reading data stored in the non-volatile memory as a received value;converting the received value read from the non-volatile memory to first likelihood information by using a first conversion table for use by the decoder;decoding, by the decoder, the first likelihood information;outputting a first estimated value with respect to the received value when decoding of the first likelihood information has succeeded, the first estimated value being based on a decoding result of the succeeded decoding;generating a second conversion table based on a pair of the received value and a second estimated value when decoding of the first likelihood information has failed, the second estimated value being based on a decoding result of the failed decoding;converting the received value to second likelihood information by using the second conversion table for use by the decoder when the second conversion table is generated; anddecoding, ...

PARTIALLY WRITTEN SUPERBLOCK TREATMENT

The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request. 1. An apparatus , comprising:a controller; anda memory device operable as a multiplane memory resource comprising blocks organized as superblocks; maintain, internal to the memory device, a status of a number of open superblocks in the memory device, the status comprising an indicator of a write operation initiated in a respective number of the open superblocks;', 'maintain, included in the status of an open superblock, a page indicator corresponding to a last written page of the open superblock; and', 'responsive to receipt, from the controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request., 'wherein the memory device is configured to2. The apparatus of claim 1 , wherein a superblock comprises a block selected from each of a plurality of planes of the multiplane memory resource.3. The apparatus of claim 1 , wherein the controller is an external controller and is unaware of the status of the last written page corresponding to the open ...

Error correction circuit, operating method thereof and data storage device including the same

An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.

Dynamic Multi-Stage Decoding

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

Decoder, operating method thereof and memory system including the decoder

An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.

Error correction device, operating method thereof and electronic device including the same

An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values respectively corresponding to hard decision bits, based on soft decision bit sets respectively corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values, wherein the reliability values respectively correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node.

Controller, semiconductor memory system and operating method thereof

An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.

Memory system having flexible ecc scheme and method of the same

A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits of the first length; a second ECC circuit used to encode information bits of a second length into a codeword of a second ECC scheme, and to decode a codeword of the second ECC scheme read from the memory into decoded information bits of the second length; and a control circuit used to combine a plurality sets of the decoded information bits of the first length into the information bits of the second length, and to separate the decoded information bits of the second length into a plurality sets of the information bits of the first length.

Memory system, semiconductor storage device, and method for reading out data

A memory system of an embodiment includes a NAND memory and a memory controller. The NAND memory includes an encoder configured to convert first data into second data including a plurality of code words generated by dividing the first data into the code words, generate parity data in a horizontal direction of the second data for error check and correct for each code word and encode the first data, and a decoder. A control circuit of the NAND memory controls the decoder to perform hard decision decoding using the parity data in the horizontal direction on readout target data when a readout command is received and outputs the decoded readout target data to the memory controller when the hard decision decoding of the readout target data is successful.

Programmable and high-performance data scrambler for non-volatile memory controllers

Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

Memory controller, storage device and memory control method

According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.

Scaling factors for hard decision reads of codewords distributed across die

Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword.

Storage control device, storage system, and storage control method

According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.

Defective bit line management in connection with a memory access

Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

Quality of service of an adaptive soft decoder

Disclosed are devices, systems and methods for improving a quality of service of an adaptive soft decoder in a non-volatile memory device. An example method includes selecting, based on current operating conditions of the non-volatile memory device, a first decoder parameter set from an ordered plurality of decoder parameter sets, each decoder parameter set corresponding to a distinct operating condition of the non-volatile memory device and comprising parameters related to a soft decoding operation; performing, based on the first decoder parameter set, the soft decoding operation; upon a determination that the soft decoding operation has succeeded, reordering the ordered plurality of decoder parameter sets to place the first decoder parameter set at a start of the ordered plurality of decoder parameter sets, and otherwise, performing the soft decoding operation based on a second decoder parameter set selected from the ordered plurality of decoder parameter sets.

Error checking and correcting decoding method and apparatus

An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.

PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit. 1. A permutation network designing method for a permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder corresponding to a rewritable non-volatile memory module , comprising:identifying a size of a physical page of the rewritable non-volatile memory module as a page size, wherein the physical page is configured to store a plurality of codewords;obtaining a length of each of the codewords as a codeword length according to the amount of the codewords and the page size;identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N;calculating a first value according to the default dimension value, and identifying a first permutation network according to the first value, the default dimension value, and a shift type of the check matrix, wherein the first permutation network comprises a plurality of first permutation layers arranged ...

Soft Decision LDPC Decoder With Improved LLR From Neighboring Bits

A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping. 1. A memory storage system , comprising:a processor;memory connected to the processor;a data storage element connected to the processor; andnon-transitory computer executable program code embodied in the memory, configured to execute on the processor, receive a low-density parity-check encoded codeword;', 'identify one or more variable nodes associated with one or more unsatisfied check nodes in the codeword;', 'identify all backtracking nodes also belonging to a trapping set of a low-density parity-check code associated with the codeword;', 'select one of the backtracking nodes based on a probability that each of the one or more variable nodes belongs to a trapping set;', 'flip a log-likelihood ratio associated with the selected backtracking node;', 'saturate a magnitude of the log-likelihood ratio associated with the selected backtracking node; and', 'decode the codeword based on the erased log-likelihood ratios., 'wherein the computer executable program code is configured to2. The memory storage system of claim 1 , wherein the computer executable program code is further configured to:select a hard error location from one or more hard error locations associated with bits in the codeword; anderase a log-likelihood ratio associated with the selected hard error location.3. The memory storage system of claim 2 , wherein the computer executable program code is further configured to receiving a list of one or more hard error locations associated with a bit in the codeword.4. The memory storage system of claim 2 , ...

MEMORY SYSTEM AND CONTROL METHOD

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information. 1. A memory system comprising:a non-volatile memory;a memory interface that reads data recorded in the non-volatile memory as a received value;a converting unit that converts the received value read from the non-volatile memory to first likelihood information by using a first conversion table;a decoder that decodes the first likelihood information;a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded; anda generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed, whereinwhen the generating unit generates the second conversion table, the converting unit converts the received value to second likelihood information by using the second conversion table, andthe decoder decodes the second likelihood information.2. The memory system according to claim 1 , whereinevery time the ...

Tiered error correction code (ecc) operations in memory

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

Data storage device channel encoding current data using redundancy bits generated over preceding data

A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.

Memory system and method of controlling nonvolatile memory

According to an embodiment, a memory system includes: a test pattern decoding unit that detects an intermediate decoding word from a plurality of test patterns; a Euclid distance calculating unit that calculates a Euclid distance between the intermediate decoding word and a received word; and a maximum likelihood decoding word selecting unit that maintains a maximum likelihood decoding word candidate. In a case where a Euclid distance of the intermediate decoding word is shorter than a Euclid distance of the maximum likelihood decoding word candidate, the maximum likelihood decoding word selecting unit updates the maximum likelihood decoding word candidate by using the intermediate decoding word and the test pattern decoding unit does not execute decoding of a test pattern having no possibility that the Euclid distance of the intermediate decoding word becomes shorter than the Euclid distance of the maximum likelihood decoding word candidate.

MEMORY SYSTEM

A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder. 1. A memory system comprising:a nonvolatile memory in which a concatenation code is stored; anda memory controller configured to perform reading of the concatenation code from the nonvolatile memory in response to an external command, the memory controller including a first external code decoder that performs bounded distance decoding on an external code portion, and outputs a first result of decoding that is obtained by the bounded distance decoding, wherein the external code portion is a bit sequence of an external code in the concatenation code that is coded,', 'an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence that is the first result of decoding, which is output from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and', 'a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the first result ...

Cache Oblivious Algorithm for Butterfly Code

Techniques for generating parities and repairing data erasures using a cache oblivious encoding algorithm are disclosed. The system includes an encoding module which receives a request to recreate data for a subset of a plurality of content stores from a storage manager. The encoding module generates a new first parity and a new second parity using the remaining content in the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second parity for the plurality of content stores. The encoding module may recreate the data for the plurality of content stores using the first portion of the requested data and the second portion of the requested data.

MEMORY SYSTEM

A memory system includes a semiconductor memory and a memory controller. The semiconductor memory includes first memory cells, first bit lines connected to the first memory cells, second memory cells, second bit lines connected to the second memory cells, a word line connected to the first and second memory cells, and a driver configured to apply a voltage to the word line. In response to a special read command from the memory controller, the driver sequentially applies, to the word line, first read voltages to read data from the first memory cells, a second read voltage within a voltage range of the first read voltages to read data from the first memory cells, third read voltages to read data from the second memory cells, and a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells. 1. A memory device comprising:a plurality of first memory cells each storing data based on a threshold voltage;a plurality of first bit lines connected to the plurality of first memory cells;a plurality of second memory cells each storing data based on a threshold voltage;a plurality of second bit lines connected to the plurality of second memory cells;a word line connected to the plurality of first and second memory cells; anda driver configured to apply a voltage to the word line, a plurality of first read voltages to read data from the first memory cells,', 'a second read voltage within a voltage range of the first read voltages to read data from the first memory cells,', 'a plurality of third read voltages to read data from the second memory cells, and', 'a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells., 'wherein, upon receipt of a command set including a first command for instructing a first operation to be performed and a second command for instructing a read operation to be performed, the driver sequentially applies, to the word line2. The memory device ...

VARIABLE RESISTANCE RANDOM-ACCESS MEMORY AND METHOD FOR WRITE OPERATION HAVING ERROR BIT RECOVERING FUNCTION THEREOF

Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs. 1. A variable resistance random-access memory , comprising:a variable resistance random-access memory array comprising a plurality of memory cells;a memory part, configured to store failure information comprising an address of a written memory cell determined as failure and a write identify code, wherein the write identify code indicates whether the failure is in writing of SET or in writing of RESET; and writing a memory cell selected based on address information to be a predetermined resistance state;', 'determining the written memory cell as pass if the written memory cell matches the predetermined resistance state or failure if the written memory cell does not match the predetermined resistance state;', 'when a predetermined event occurs, recovering the written memory cell determined as failure based on the failure information;', 'determining the recovered memory cell as pass or failure; and', 'clearing the failure information stored in the memory part if the recovered memory cell is determined as pass., 'a controller configured to perform2. The variable resistance random-access memory according to claim 1 , wherein the predetermined resistance state is low resistance state ...

GENERATING HAMMING WEIGHTS FOR DATA

Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation. The Hamming weight has fewer bits than the bit set and is operable to correct the data bit. 1. A system , comprising:a controller operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft reads, to logically operate on the bit set, and to generate a Hamming weight for the data bit based on the logical operation, the Hamming weight having fewer bits than the bit set and being operable to correct the data bit.2. The system of claim 1 , wherein:the controller is further operable to bead sort bits of the bit set.3. The system of claim 1 , wherein:the controller is further operable to soft read the data bit from a persistent storage medium by changing a read voltage level of the data bit by the plurality of times.4. The system of claim 3 , wherein:the persistent storage medium is a NAND flash memory device, a magnetoresistive random-access memory device, or a combination thereof.5. The system of claim 1 , wherein:the controller is further operable to logically XOR bits of the bit set to generate the Hamming weight.6. The system of claim 1 , wherein:the controller is further operable to soft read another data bit the plurality of times, to generate another bit set for the other data bit from the soft reads of the other data bit, to logically operate on the bit set with the other bit set, and to correct the other data bit based on the logical operation of the bit sets.7. The system of claim 6 , wherein:the controller is further operable to generate another Hamming weight for the other data bit based on a logical operation of the other bit set, the Hamming weight of the other data bit having fewer bits than the other bit set and being operable ...

Memory system with decoders and method of operating such memory system and decoders

A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

Memory system with on-the-fly error detection and termination and operating method thereof

Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.

Storage controller and method of restoring error of the same

A storage controller includes a host interface configured to perform communication with a host device, a memory interface configured to perform communication with a nonvolatile memory device, a higher-level controller, and a lower-level controller. The higher-level controller issues operations to be performed by the nonvolatile memory device based on requests transferred through the host interface. The lower-level controller includes an operation memory configured to store an operation code and operation data. The lower-level controller controls the memory interface based on the operation code and the operation data such that the nonvolatile memory device performs issued operations received from the higher-level controller. The higher-level controller performs, when an error occurs in the lower-level controller, an error restoring operation based on state information of the lower-level controller to restore the lower-level controller to a previous state corresponding to a state before the error occurs.

Apparatus, system and method for protecting data

An apparatus and corresponding method for protecting stored data. The apparatus includes a first encoder, a memory, a second encoder and a comparator. The first encoder is configured to generate first redundancy bits using a protection method to protect input data bits, whereas the input data bits are assigned to at least one of a plurality of classes. The memory is configured to store selectively inverted input data bits and/or selectively inverted first redundancy bits, whereas the selective inversion is based on the assigned at least one of the plurality of classes. The second encoder is configured to generate second redundancy bits using the protection method by encoding the selectively inverted input data bits. The comparator is configured to generate an alarm signal if the second redundancy bits are different from the first redundancy bits.

LOW BER HARD-DECISION LDPC DECODER

A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values. 1. A method of Low Density Parity Check (“LDPC”) decoding by an LDPC decoder , the LDPC decoder operable to perform the steps comprising of:receiving a plurality of encoded data; anditeratively selecting a voting requirement, among a plurality of voting requirements, for LDPC decoding of each received encoded data of the plurality of encoded data, selecting is based on a value of a syndrome of the received encoded data;', 'employing a bit-flipping scheme of the LDPC decoder according to the selected voting requirement, and', 'correcting the encoded data based on the respective selected voting requirement and the employed bit-flipping scheme., 'wherein for each iteration of the LDPC decoder,'}2. The method of claim 1 , wherein selecting the voting requirement adjusts the number failing check-nodes of the LDPC decoder required for a flip of a bit on a variable node of the LDPC decoder.3. The method of wherein the voting requirement is further selected based on values of syndromes of previous iterations of the LDPC decoder.4. The method of wherein the voting requirement is further selected based on a history of syndromes and a degree of a variable node of the LDPC decoder.5. The method of wherein the plurality of voting requirements comprises the voting requirement and at least one weakened voting requirement or at least one strengthened voting requirement claim 1 , relative to the voting requirement claim 1 , for LDPC decoding.6. The method of claim 5 , wherein the plurality of voting requirements ...

Error Correction Hardware With Fault Detection

Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

Burst error tolerant decoder and related systems, methods, and devices

Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Memory system and operating method thereof

Provided herein is a memory system and an operation method thereof. The memory system may include a memory controller including a read retry table in which a plurality of codes are stored, and configured to output a selected code among the plurality of codes during a read retry operation. The memory system may include a memory device configured to store data, and perform the read retry operation according to the codes received from the memory controller.

ECC BYPASS USING LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL

A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit. 1. A method of providing requested data from a memory device of a computer system to a requesting unit of the computer system comprising:first transmitting the requested data as uncorrected data with correction information from a controller of the memory device to the requesting unit using a bypass path having a bypass latency;using the correction information at the requesting unit to determine that the uncorrected data contains an error having a specific complexity level;sending a retry select signal from the requesting unit to the controller wherein the retry signal is based on the specific complexity level; andsecond transmitting the requested data as corrected data from the controller to the requesting unit using a selected one of a plurality of error correction units based on the retry select signal wherein the error correction units provide different complexity levels of error correction and have different correction circuit latencies, each of the correction circuit latencies being greater than the ...

Syndrome-based codeword decoding

A device includes a memory device coupled to an error correction code (ECC) decoder. The ECC decoder is configured to generate syndromes corresponding to a representation of a codeword received from the memory device and to perform a single decoding operation on a representation of data included in the representation of the codeword. The single decoding operation is configured to change at least one bit of the representation of the data based on a majority value of a group of the syndromes that are associated with the bit.

Error protection for integrated circuits in an insensitive direction

A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells.

Transformation of Binary Data to Non-Binary Data For Storage in Non-Volatile Memory

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

DETERMINING A READ APPARENT VOLTAGE INFECTOR PAGE AND INFECTED PAGE

Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER. 1. A method for determining a read apparent voltage infector and infected page comprising:programming each page of each block within a plane;reading one or more pages within each block within the plane;setting an acting infector page within an acting infector block within the plane;setting a possible infected page within a possible infected block within the plane;reading the acting infector page a predetermined plurality of instances;subsequently reading the possible infected page;determining a raw bit error rate (RBER) of the read of the possible infected page; andsetting the acting infector page as an actual infector page and setting the possible infected page as an actual infected page based upon the determined RBER.2. The method of claim 1 , wherein programming each block comprises:electrically charging each floating gate of each page.3. The method of claim 1 , further comprising:setting the acting infector block as an actual infector block and setting the possible infected block as an actual infected block based upon the determined RBER.4. The method of claim 3 , further comprising:determining whether a ...

Methods and devices for error correction

Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.

PERFORMING A DECODING OPERATION TO SIMULATE SWITCHING A BIT OF AN IDENTIFIED SET OF BITS OF A DATA BLOCK

A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit. 1. A system comprising:a memory device; and identifying a set of bits of a segment of the memory device associated with a failed decoding operation;', 'calculating a discrepancy value for at least one bit of the set of bits;', 'determining whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation; and', 'in response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, correcting the at least one bit of the set of bits by switching a value of the at least one bit., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein the correction capability corresponds to a number of errors that are correctable by the failed decoding operation.3. The system of claim 1 , wherein calculating the discrepancy value for the at least one bit of the set of bits comprises simulating switching a value of the at least one bit of the set of bits.4. The system of claim 1 , wherein calculating the discrepancy value for the at least one bit of the set of bits is based on outputs of the failed decoding operation.5. The system of claim 1 , wherein the failed decoding operation ...

Method and decoder to adjust an error locator polynomial based on an error parity

A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first data.

ELECTRONIC DEVICES

An electronic device includes a syndrome decoder, an error insertion control circuit, and a failure detection circuit. The syndrome decoder generates an error insertion code from a write syndrome generated based on a write pulse. The error insertion control circuit inserts an error into an internal codeword according to the error insertion code based on a read pulse. The failure detection circuit compares the write syndrome with a read syndrome generated from the internal codeword to generate a failure detection signal. 1. An electronic device comprising:a syndrome decoder configured to generate an error insertion code from a write syndrome generated based on a write pulse;an error insertion control circuit configured to insert an error into an internal codeword according to the error insertion code based on a read pulse; anda failure detection circuit configured to compare the write syndrome with a read syndrome generated from the internal codeword to generate a failure detection signal.2. The electronic device of claim 1 ,wherein the write pulse is generated to perform a write operation;wherein the read pulse is generated to perform a read operation; andwherein the write pulse and the read pulse are generated by decoding a control signal.3. The electronic device of claim 1 , wherein the write syndrome is generated by counting the write pulse.4. The electronic device of claim 1 ,wherein the internal codeword is generated by buffering a codeword based on the write pulse; andwherein the internal codeword includes data and a parity.5. The electronic device of claim 1 , wherein the error insertion control circuit inverts a level of at least one bit included in the internal codeword based on the error insertion code.6. The electronic device of claim 1 , wherein the error insertion control circuit inverts a level of at least one bit included in the internal codeword based on the error insertion code when the read pulse is generated to perform a read operation.7. The ...

Memory reallocation during raid rebuild

Apparatus and method for managing data in a multi-device storage system, such as a RAID (redundant array of independent discs) system. Distributed data sets are stored across a plurality of storage devices. A selected storage device is replaced with a new storage device responsive to an anomalous event. A rebuild operation is performed to reconstruct data from the selected storage device to the new storage device. The rebuild process includes accessing a list of distributed data sets in a local memory. For each distributed data set in the list identified as constituting valid data, read commands are issued to the remaining storage devices and a write command is issued to the new storage device. For each distributed data set in the list identified as constituting unused data, a data clear command is issued to each of the remaining storage devices and to the new storage device.

Global error correction

A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory.

Error correction based on physical characteristics for memory

Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.

MEMORY SYSTEM

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship. 1. A method of controlling a memory device including a memory cell , the method comprising:reading first data from the memory device based on a first data reading;decoding the first data;reading second data from the memory device based on a second data reading when the decoding of the first data fails, the second data reading being different from the first data reading; andconverting a first value that is based on the first data and the second data, to a second value in accordance with a first relationship.2. The method according to claim 1 , wherein:the first data reading includes reading data from the memory cell using a first voltage,the second data reading includes reading third data from the memory cell using a second voltage and reading fourth data from the memory cell using a third voltage,the second voltage is lower by a first magnitude than the first voltage, andthe third voltage is higher by the first magnitude than the first voltage.3. The method according to claim 2 , wherein the second data is based on the third data and the fourth data.4. The method according to claim 3 , wherein the second data is based on a result of a logical operation executed on the third data and the fourth data.5. The method according to claim 2 , further comprising:reading fifth data from the memory device based on a third data reading when the decoding of the first data fails, ...

Codes for Enhancing the Repeated Use of Flash Memory

A basic property of flash memory is that: a 0-bit can be changed into a 1-bit, but not vice-versa, which severely limits the possibilities of reusing storage space with new data. A family of new coding methods is presented that enables double use of the memory, effectively expanding the combined amount of stored data. This can then be used as a compression booster, adding an additional layer to, and improving the compression of some rewriting methods that are not context sensitive.

Systems and Methods for Soft Decision Generation in a Solid State Memory System

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

DECODING OPTIMIZATION FOR CHANNEL MISMATCH

A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding. 1. A decoding method comprising:starting, with a controller, a first portion of a convergence process, to decode a read data set using an initial set of reliability metric values generated based on a set of reliability bins and associating bits of the read data set with the set of reliability bins;changing, with the controller, a configuration of the set of reliability bins;re-associating, with the controller, the bits of the read data set with the reliability bins according to the change in the configuration;generating, with the controller, an updated set of reliability metric values according to the changed configuration of the set of reliability bins;starting, with the controller, a second portion of the convergence process using the updated set of reliability metric values; andcompleting, with the controller, the convergence process based on the updated set of reliability metric values.2. (canceled)3. The decoding method of claim 1 , wherein changing the configuration of the set of reliability bins comprises changing claim 1 , with the controller claim 1 , a total number of the reliability bins.4. The decoding method of claim 3 , wherein changing the total number of reliability bins comprises increasing the total number of reliability bins.5. The decoding method of claim 1 , wherein changing the configuration of the set of reliability bins comprises changing claim 1 , with the controller claim 1 , the configuration of the set of reliability bins based on a change in ...

Memory, memory controller, memory system, method of memory, memory controller and memory system

In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory. An unselected word line is a word line not selected during the read operation. The method further includes performing the reliability verification read operation for the at least one unselected word line based on the determining.

Error Correction Hardware With Fault Detection

Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output. 1. A method comprising:comparing an output of a read generation error correction code (ECC) logic in read path circuitry for a memory circuit to an output of a write generation ECC logic in write path circuitry for the memory circuit; anddetecting, based on the comparing, a fault in the write generation ECC logic or in the read generation ECC logic when the output of the write generation ECC logic does not equal the output of the read generation ECC logic.2. The method of claim 8 , wherein the comparing and the detecting is performed continuously for every clock cycle.3. The method of claim 8 , wherein the memory circuit comprises a static random access memory (SRAM) claim 8 , read only memory (ROM) claim 8 , or a flash memory.4. The method of claim 1 , wherein the memory circuit is a memory for a processor of an Advanced Driver Assistance System (ADAS).5. A method of fault detection for error correction code (ECC) hardware claim 1 , comprising:comparing an output of read generation ECC logic to an output of write generation ECC logic for a memory circuit having write generation ECC logic in a write path circuitry and check ECC logic including read generation ECC logic in read path circuitry; ...

Mapping for Multi-State Programming of Memory Devices

Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.