VERFAHREN ZUR NACHSCHLAGTABELLENFREIEN SPEICHERREPERATUR

Verschiedene Ausführungsformen der vorliegenden Offenbarung richten sich an ein Verfahren zur Speicherreparatur unter Verwendung eines Nachschlagtabelle-freien (LUT-freien) dynamischen Speicherzuweisungsprozesses. Ein Array von Speicherzellen, das eine Vielzahl von Reihen und eine Vielzahl von Spalten aufweist, ist bereitgestellt. Weiter weist jede Speicherzelle des Arrays mehrere Datenzustände und einen permanenten Zustand auf. Eine oder mehrere abnormale Speicherzellen ist /sind in einer Reihe des Arrays identifiziert und in Antwort darauf, dass eine abnormale Speicherzelle identifiziert ist, wird die abnormale Speicherzelle auf den permanenten Zustand gesetzt. Die abnormalen Speicherzellen weisen defekte Speicherzellen und in manchen ausführungsformen Tail-Speicherzellen, die spärliche Arbeitsleistung aufweisen, auf. Während Lese- oder Schreiboperation an der Reihe ist/sind die eine oder mehreren abnormalen Speicherzellen durch den permanenten Zustand identifiziert und ist/sind aus einem ...

Verfahren zur Steuerung einer Operation einer nichtflüchtigen Speichervorrichtung unter Verwendung von Maschinenlernen und Speichersystem

Nach einem Verfahren zur Steuerung einer Operation einer nichtflüchtigen Speichervorrichtung unter Verwendung von Maschinenlernen werden Operationsbedingungen der nichtflüchtigen Speichervorrichtung durch Durchführen einer Ableitungsoperation unter Verwendung eines Maschinenlernmodells bestimmt. Trainingsdaten, die basierend auf Merkmalsinformationen und Fehlerinformationen erzeugt werden, werden gesammelt, wobei die Fehlerinformationen Ergebnisse einer Fehlerkorrekturcode(ECC)-Dekodierung der nichtflüchtigen Speichervorrichtung angeben. Das Maschinenlernmodell wird durch Durchführen einer Lernoperation basierend auf den Trainingsdaten aktualisiert. Optimierte Operationsbedingungen für individuelle Benutzerumgebungen werden durch Sammeln von Trainingsdaten im Speichersystem und Durchführen der Lernoperation und der Ableitungsoperation basierend auf den Trainingsdaten vorgesehen.

Verfahren und Vorrichtung zur Steigerung der Zuverlässigkeit eines nicht-flüchtigen Speichers

Die vorliegende Erfindung betrifft das Gebiet der nichtflüchtigen Speicher, NVM, wie insbesondere Flash-Speicher und stellt ein Verfahren vor, sowie Vorrichtungen zu seiner Ausführung, zum Steigern der Zuverlässigkeit eines nichtflüchtigen Speichers, NVM, unter Steuerung eines korrespondierenden NVM-Controllers, der eine vorbestimmte Fehlerkorrektur-Codierungs-ECC-Fähigkeit aufweist, die kleiner oder gleich der ECC-Anforderung des NVM ist und der Speicherseiten zum Abspeichern von Daten in dem NVM verwendet. Das Verfahren weist einen Überwachungsschritt auf, bei dem der Controller, während er einen gegenwärtigen Betriebsmodus bezüglich eines physikalischen Speicherbereichs des NVM anwendet, der zu einer bestimmten Speicherseite korrespondiert, feststellt, ob eine gegenwärtige Betriebsbedingung des genannten Speicherbereichs konsistent mit einer korrespondierenden vorbestimmten Betriebsdomäne ist, in welcher die ECC-Fähigkeit des Controllers einem tatsächlichen Bitfehlerniveau (BEL) des ...

Error-correction encoding and decoding

Encoding data supplied to a data channel using a quarter product code CQ, having identical row and column codes and being reversible, whereby a codeword corresponds to a triangular sub-array of a square matrix confined between its diagonal and anti-diagonal. K input data symbols are stored for encoding. The K input data symbols are assigned to respective symbol locations in a notional square array, having n rows and n columns of symbol locations, to define a plurality of k-symbol words in respective rows of the array. The k-symbol words are encoded by encoding rows and columns of the array in dependence on a product code C having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n. This encoding is performed so as to define a codeword, having n2 code symbols corresponding to respective locations of said array, of a quarter product code CQ defined by CQ = { X − XT − (X − XT)F } where X is an (n by n)-symbol matrix defining a ...

Data processing

Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration

METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY

A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is designated read-only. A current checksum is calculated based at least in part on data within the memory block. When the first memory block is designated read-only, and the prior checksum represents expected data within the first memory block, it is determined whether the current checksum is equal to the prior checksum. When the current checksum is not equal to the prior checksum, a verification failure for the first memory block is indicated via a notification interface. A system for verifying memory device integrity is also disclosed.

Verfahren und Einrichtung zur Kanalfehlerkorrektur

Data path protection parity value determination for data patterns in a memory device

SEMICONDUCTOR STORAGE DEVICE

Memory system with read threshold estimation and operating method thereof

Semiconductor memory apparatus and semiconductor system having the same

A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.

Solid State Storage System with High Speed and Controlling Method thereof

FLASH MEMORY SYSTEM AND ERROR CORRECTION METHOD THEREOF

Error Correcting Methods and Circuit over Interference Channel Environment, Flash Memory Device Using the Circuits and Methods

ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES

PURPOSE: An enabling an integrated memory controller is provided to improve the whole performance by applying a lower refresh rate than a predetermined refresh rate which is defined by a memory module. CONSTITUTION: A system(100) comprises an integrated circuit(102), a DRAM sub system(104), and a memory(106). The integrated circuit comprises a logic controlling the transmission of information to the DRAM sub system. The integrated circuit comprises a processor cores and a logic unit(110). The process core is comprised of one of general process cores and an integrated process cores with graphic processor cores. COPYRIGHT KIPO 2010 ...

MEMORY DATA ERROR CORRECTION METHOD

According to the present invention, a memory data error correction method comprises: a step of receiving a burst-specific content from each of multiple bursts of a memory module; a step of storing the burst-specific content from each of the multiple bursts; and a step of using all error correction code (ECC) beats received as a part of a single error correction double error detection (SECDED) code from at least one of the multiple bursts to correct at least one error included in the first predetermined number of beats of burst-specific data. The burst-specific content includes the first predetermined number of beats of the burst-specific data as well as corresponding beats of a burst-specific ECC. According to the present invention, error correction performance can be improved even by using existing SECDED circuitry. COPYRIGHT KIPO 2016 ...

CONTROL METHOD OF A NONVOLATILE MEMORY APPARATUS FOR MANAGING BLOCKS CAPABLE OF ESTABLISHING THRESHOLD VALUES OF ECC CORRECTION EXCESS BITS

PURPOSE: A control method of a nonvolatile memory apparatus for managing blocks are provided to improve the reliability of data by inducing a block to change data access to other block before ECC correction excess bit is generated. CONSTITUTION: ECC failure bits are checked when a lead command provided from a host interface is executed(S20). The change of block is determined(S30). The change of block is executed according to the determined block(S70,S80). Threshold values of an ECC failure bit is established in order to determine the excess of the threshold values for ECC failure bit numbers in the block. COPYRIGHT KIPO 2012 ...

OPTION(SETTING) DATA STORAGE CIRUIT, NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

PURPOSE: A set data storage circuit, a nonvolatile memory device including the same, and a memory system are provided to improve reliability by rewriting set data or changing a page for reading the set data. CONSTITUTION: A set data storage block(120) stores set data. An access unit accesses the set data of the set data storage block. An error sensing unit(140) senses set data errors. An error correcting unit(150) corrects errors of the set data storage block when the error sensing unit senses errors. The set data is equally stored in two or more regions of the set data storage block. COPYRIGHT KIPO 2013 [Reference numerals] (110_0) Normal data storage block 0; (110_1) Normal data storage block 1; (110_N) Normal data storage block N; (140) Error sensing unit; (150) Error correcting unit; (160) Counter; (170) Control circuit; (AA) Set data storage block; (BB) Page buffer array; ...

반도체 메모리 장치의 에러 정정 회로, 반도체 메모리 장치 및 메모리 시스템

... 메모리 셀 어레이를 포함하는 반도체 메모리 장치의 에러 정정 회로는 생성 매트릭스로 표현되는 에러 정정 코드(error correction code, 이하 'ECC') 및 ECC 엔진을 포함한다. 상기 ECC 엔진은 상기 ECC를 이용하여, 복수의 데이터 비트들을 포함하는 메인 데이터에 기초하여 패리티 데이터를 생성하고, 상기 패리티 데이터를 이용하여 상기 메인 데이터의 에러를 정정한다. 상기 데이터 비트들은 복수의 서브 코드워드 그룹들로 분할되고, 상기 ECC는 상기 서브 코드워드 그룹들에 상응하는 복수의 코드 그룹들로 분할되는 복수의 칼럼 벡터들을 포함하고, 상기 칼럼 벡터들은 상기 메인 데이터의 에러 비트들에 의한 오정정 비트가 발생하는 서브 코드워드 그룹의 위치를 제약하는 원소들을 가진다.

Data storage device and data maintenance method

Dynamically selecting between memory error detection and memory error correction

Example methods, systems, and apparatus to dynamically select between memory error detection and memory error correction are disclosed herein. An example system includes a buffer to store a flag settable to a first value to indicate that a memory page is to store error protection information to detect but not correct errors in the memory page. The flag is settable to a second value to indicate that the error protection information is to detect and correct errors for the memory page. The example system includes a memory controller to receive a request based on the flag to enable error detection without correction for the memory page when the flag is set to the first value, and to enable error detection and correction for the memory page when the flag is set to the second value.

Storage device for refreshing data pages of flash memory based on error correction code and method for the same

A storage device for refreshing data pages of a flash memory includes an error correction code (ECC) detector and a controller. The flash memory includes a plurality of data pages each having a data area for storing data and a spare area for storing ECC corresponding to the stored data. The ECC detector is used for detecting used bits of ECC stored in the spare area of each data page. The controller is used for storing data and ECC of a data page to another new data page when the used bits of the ECC are less than a predetermined value.

Data writing method for a flash memory, and controller and storage system using the same

A data writing method for writing data from a host system into a flash memory chip is provided, wherein the flash memory chip have a plurality of physical blocks. The method includes receiving a host writing command and writing data thereof, and executing the host writing command. The method also includes transmitting a data program command for writing the writing data into one of the physical blocks to the flash memory chip, and transmitting a command for determining whether data storing the physical block has any error bit. Accordingly, the method can effectively ensure the accuracy of data to be written into the flash memory chip.

Counter to locate faulty die in a distributed codeword storage system

DATA RESTORATION METHOD FOR A NON-VOLATILE MEMORY

A method and apparatus for selectively restoring data in a non- volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.

SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

FLASH MEMORY WITH CODING AND SIGNAL PROCESSING

A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.

NONVOLATILE MEMORY DEVICE

A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

BAD BLOCK MANAGEMENT FOR FLASH MEMORY

Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.

SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Bad block management for flash memory

Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.

Methods and apparatuses for error correction

Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY

Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Two dimensional encoding for non-volatile memory blocks

Method for encoding information in a flash memory block which combines an independent encoding of each page with a block-level code across multiple pages. The method includes two independent error correction codes, one in horizontal direction and one in vertical direction, with horizontal direction error correction decoding; and vertical direction erasure correction decoding.

Semiconductor memory device and memory system having the same

Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

Apparatuses and methods for erasure-assisted ECC decoding

One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.

Flash memory device and method

An improved flash memory device and method for improving the performance and reliability of a flash memory device is provided. According to one embodiment, a method for writing data to a memory device may include writing the data to a temporary storage location within the memory device before the data is copied to another location within the memory device, incrementing a count value to indicate that the data has been copied, and repeating the step of writing, if the count value is less than a threshold value. If the count value is greater than or equal to the threshold value, the method may write the data to an external memory controller, where the data is checked for errors and corrected if an error is found, before the data is copied to the other location within the memory device.

Method And Apparatus For Obtaining Memory Status Information Cross-Reference To Related Applications

In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.

Memory controller storing data in approximate memory device based on priority-based ECC, non-transitory computer-readable medium storing program code, and electronic device comprising approximate memory device and memory controller

A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.

Identifying bitstream load issues in an integrated circuit

A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

SYSTEMS AND METHODS FOR ULTRA FAST ECC WITH PARITY

Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Storage Systems with Peer Data Recovery

Example peer storage systems, storage devices, and methods provide peer data recovery across a peer communication channel. Peer storage devices establish peer communication channels that communicate data among the peer storage devices. A storage device may identify storage media segments from their storage medium for recovery of failed data units. A peer storage device may be identified that contains recovery data for the failed data units. The recovery data may be received over the peer communication channel and the storage media segments may be recovered using the recovery data.

Soft decoding systems and methods for flash based memory systems

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Semiconductor storage device

A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Non-volatile memory controller with error correction (ECC) tuning via error statistics collection

A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

Accessing data stored in a command/address register device

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

SEMICONDUCTOR MEMORY SYSTEM AND DATA WRITING METHOD

On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.

Single-port memory with opportunistic writes

An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.

Method for accessing flash memory module and associated flash memory controller and electronic device

The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

System-level validation of systems-on-a-chip (SoC)

Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains ...

STORING DEEP NEURAL NETWORK WEIGHTS IN NON-VOLATILE STORAGE SYSTEMS USING VERTICAL ERROR CORRECTION CODES

Techniques are presented for efficiently storing deep neural network (DNN) weights or similar type data sets in non-volatile memory. For data sets, such as DNN weights, where the elements are multi-bit values, bits of the same level of significance from the elements of the data set are formed into data streams. For example, the most significant bit from each of the data elements are formed into one data stream, the next most significant bit into a second data stream, and so on. The different bit streams are then encoded with differing strengths of error correction code (ECC), with streams corresponding to more significant bits encoded with stronger ECC code than streams corresponding to less significant bits, giving the more significant bits of the data set elements a higher level of protection.

Selectively de-straddling data pages in non-volatile memory

A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Recovery of data failing due to impairment whose severity depends on bit-significance value

A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.

ERROR CORRECTION USING WOM CODES

A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Programming A Memory Device

A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

High-speed multi-block-row layered decoder for low density parity check (LDPC) codes

High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

Apparatus and method for multi-mode operation of a flash memory device

Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.

Write Operations for Defect Management in Nonvolatile Memory

Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory.

MEMORY SYSTEM THAT CARRIES OUT SOFT BIT DECODING

A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

Multi-level memory safety of a sensor integrated circuit

A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.

Data storage system having multi-bit memory device and on-chip buffer program method thereof

A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation.

Memory system that carries out soft bit decoding

A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

Semiconductor memory devices, memory systems including the same and methods of operating memory systems

A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

SYSTEMS AND METHODS FOR FINE GRANULARITY MEMORY SPARING

STORAGE DEVICE AND MEMORY CONTROLLER

PROBLEM TO BE SOLVED: To provide a memory controller which can execute scramble to data without restricting copy between pages of a flash memory. SOLUTION: The memory controller includes a scramble pattern generation part, a scramble processing part, a logical and physical address conversion table, a memory interface, and a control circuit, wherein a physical page is managed by dividing it to a data part and a management part. For the data part, the control circuit controls the scramble pattern generation part to generate a scramble pattern on the basis of information related to a logical address specific to the data part, and controls the scramble processing part to scramble the data of the data part corresponding to the logical address, and for the management part, the control circuit controls the scramble pattern generation part to generate a scramble pattern on the basis of information related to a physical address, and controls the scramble processing part to scramble the management ...

Verfahren und Einrichtung zur Kanalfehlerkorrektur

Techniken zum Erkennen und Korrigieren von Fehlern in Daten

Verschiedene Ausführungsformen richten sich allgemein auf Techniken zum Verwalten von Fehlern in Daten, wie zum Beispiel mit Fehlerkorrekturcode (Error-Correcting Code (ECC). Einige Ausführungsformen richten sich insbesondere auf ein Bereitstellen von einem oder mehreren von Fehlererkennung, -lokalisierung und -korrektur für einen Satz von Speicherungspeichervorrichtungen mit einer Verwaltungsspeichervorrichtung. In einer oder mehreren Ausführungsformen kann jede der Speicher- und Verwaltungsspeichervorrichtungen einen Speicherchip einschließen, wie einen von einem Satz von Speicherchips, die in einem doppelreihigen Speichermodul (Dual In-Line Memory Module, DIMM) enthalten sind. Zum Beispiel jede Speichervorrichtung eine integrierte Schaltung für dynamischen Speicher mit wahlfreiem Zugriff (Dynamic Random-Access Memory, DRAM) sein, die in einem DIMM enthalten ist. In verschiedenen Ausführungsformen kann der Satz von Speicherverwaltungsspeichervorrichtungen verwendet werden, um eine Speicherzeile ...

Techniken zum Speichern von Bits in Speicherzellen mit Hängenbleiben-auf-0-oder-1-Fehlern

Ein Datenspeichersystem enthält eine Speicherschaltung, die Speicherzellen umfasst, und eine Steuerschaltung. Die Steuerschaltung erzeugt in Ansprechen auf eine erste Schreiboperation einen ersten Satz redundanter Bits, die die Bitpositionen der Speicherzellen, die Hängenbleiben-auf-0-oder-1-Fehler aufweisen, angeben, falls eine erste Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein erster Schwellenwert ist. Die Steuerschaltung ist betreibbar, um in Ansprechen auf eine zweite Schreiboperation die Datenbits zu codieren, um codierte Datenbits und einen zweiten Satz redundanter Bits, die eine Transformation, die an den Datenbits ausgeführt wird, um die codierten Datenbits zu erzeugen, angeben, zu erzeugen, falls eine zweite Rate der Hängenbleiben-auf-0-oder-1-Fehler in den Speicherzellen größer als ein zweiter Schwellenwert ist. Die codierten Datenbits, die in den Speicherzellen gespeichert sind, die Hängenbleiben-auf-0-oder-1-Fehler aufweisen, entsprechen den ...

Sichere Speicherung durch interneBetriebssicherstellung

Die offenbarte Erfindung stellt eine Struktur und ein Verfahren zum Ermitteln von Adressleitungs (z. B. Wortleitungs-, Bitleitungs-)Speicherausfällen bereit. Bei einer Ausführungsform weisen das Verfahren und die Struktur das Erzeugen einer Adress-Signatur durch Neucodieren eines intern erzeugten Adress-Signals aus aktivierten Elementen (z. B. Wortleitungen) in einem Speicherarray auf. Die neu erzeugte Adress-Signatur kann mit einer angeforderten Speicheradressstelle verglichen werden. Wenn die neu erzeugte Adress-Signatur und die Speicherstelle gleich sind, liegt in dem Speicherarray kein Fehler vor, wenn jedoch die neu erzeugte Adress-Signatur und die Speicherstelle nicht gleich sind, liegt ein Fehler in dem Speicherarray vor. Demgemäß stellt das Neucodieren einer Adress-Signatur einen geschlossenen Prüfkreislauf bereit, dass eine Wortleitung und/oder Bitleitung, die tatsächlich in einem Speicherarray aktiviert wurde, die korrekte angeforderte Wortleitung und/oder Bitleitung war, dass ...

Numerische Steuerung mit Wartungsfunktion für in einem nichtflüchtigen Speicher gespeicherten Daten oder dergleichen

Eine numerische Steuerung enthält: einen nichtflüchtigen Speicher; eine erste Stromquelle, welche den nichtflüchtigen Speicher mit elektrischer Energie versorgt; eine zweite Spannungsquelle, welche elektrische Energie drahtlos oder über eine verdrahtete Verbindung liefert; und einen Mikrocomputer. Der Mikrocomputer wird aus der zweiten Stromquelle mit elektrischer Leistung versorgt und liest Daten aus dem nichtflüchtigen Speicher aus und schreibt Daten in den nichtflüchtigen Speicher ein. Auch wenn die erste Stromquelle ausgeschaltet ist, wird eine Stromversorgung von außen drahtlos oder durch eine verdrahtete Verbindung möglich unter Verwendung der zweiten Stromquelle.

Memory module buffer data storage

Multi-chip device and method for storing data

Adaptive multi-bit error correction in endurance limited memories

Storing parity data separate from protected data technical field

Information storage device including a primary storage array 10 comprising a plurality of non-volatile memory NVM devices 16A-N, and one or more (separate) parity memory devices 20, and a controller 8 configured to store a block of data (17A..N fig 2). The controller 8 is configured to store the block of data by writing the block of data to the primary storage array 10, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices 20. The parity information stored forms a part of the memory Error Correction Coding information ECC. The controller may be configured to select/determine a size of the parity data for the data block and write at least a portion of the parity data to the parity memory device 20 where combined size of the selected size of parity data and block of data is larger than a size of the primary storage array. In so doing the controller determines the first and second parity data for ...

STORING PARITY DATA SEPARATE FROM PROTECTED DATA

A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.

SEMICONDUCTOR MEMORY SYSTEM AND DATA WRITING METHOD

Bit error threshold and remapping a memory device

The invention provides a bit error threshold and remapping a memory device, relates to remapping a memory device.

Memory system, data storage device, memory card, and solid state drive

Disclosed are a memory system, a data storage device, a memory card and a solid state drive. The memory system includes a nonvolatile memory having a user area and a buffer area; and wear level control logic managing a mode change operation in which memory blocks of the user area are partially changed into the buffer area, based on wear level information of the nonvolatile memory.

For processing from the state of the non-volatile memory array of the confidence data retrieval method and apparatus

메모리 디바이스에서의 에러 정정 동작들

... 메모리 디바이스들에서의 에러 정정 동작들이 개시된다. 적어도 일 실시예에서, 메모리 디바이스의 내부 제어기는 저장된 사용자 데이터에 대한 내부 에러 정정 동작들을 수행하며 외부 메모리 액세스 디바이스로부터의 지시들로부터 독립적으로 메모리 디바이스에서의 사용자 데이터를 정정하도록 구성된다.

반도체 기억장치 및 NAND 플래시 메모리의 프로그램 방법

... [과제] 데이터의 신뢰성을 유지하면서 프로그램 시간의 단축을 도모할 수 있는 반도체 기억장치를 제공한다.[해결 수단] 본 발명의 플래시 메모리는, 메모리 어레이(100)와, 페이지 버퍼/센스 회로(160)와, 외부 입출력 단자에 접속된 입출력 버퍼(110)와, 데이터의 오류 검출 및 정정을 행하는 ECC 회로(120)를 포함한다. 프로그램 동작 시, 입출력 버퍼(110)는 페이지 버퍼/센스 회로(160) 및 ECC 회로(120)에 병렬로 프로그램 데이터를 로드시키고, ECC 회로(120)는 ECC 연산에 의해 생성된 패리티 비트를 페이지 버퍼/센스 회로(160)의 스페어 영역에 기입한다. ECC 처리의 종료 후, 페이지 버퍼/센스 회로(160)에 유지된 데이터가 선택된 페이지에 프로그램된다.

낸드 메모리 디바이스를 위한 조정가능 프로그래밍 속도

... 본 발명의 실시예들은, 디바이스를 위해 실행될 에러 정정 코드를 효율적으로 이용함으로써 솔리드 스테이트 디바이스(SSD) 쓰기(write) 속도를 개선하는 방법, 시스템 및 장치를 설명한다. SSD는 다수의 낸드 메모리 디바이스로 구성될 수 있다. 그러한 디바이스는 디바이스를 위한 프로그램/이레이즈 사이클 카운트와 관련되는 로우 비트 에러율(raw bit error rate: RBER)을 갖는 경향이 있다는 것이 이해될 것이다. 본 발명의 실시예들은 구현된 ECC 알고리즘의 견고성(robustness)을 더 잘 이용하도록 SSD의 동작 상태를 변경함으로써 시스템 ECC를 효율적으로 사용한다. 예를 들어, 본 발명의 실시예들은, 쓰기 속도를 증가시키기 위해 SDD에 제공된 프로그래밍 전압을 변경할 수 있고, 그러한 증가는 디바이스의 RBER을 증가시킬 수 있으나, 제품 수명 만료시(end of life)의 스토리지 충실도에 대해 제공되는 ECC(즉, 단종시에 발생할 RBER)로 인해 그러한 동작의 정확도에 영향을 미치지 않을 것이다.

고체 상태 드라이브의 전송 버퍼 사용률을 향상시키기 위해 NAND 페이지 버퍼들을 사용하는 방법 및 시스템

... 호스트로부터 수신된 페이지 데이터(예를 들어, 상위 페이지 데이터)가 고체 상태 드라이브의 제어기의 전송 버퍼에 저장된다. 다른 페이지 데이터(예를 들어, 하위 페이지 데이터)는 에러 정정된 페이지 데이터로서 전송 버퍼에 저장하기 위해 비휘발성 메모리(예를 들어, NAND 메모리)로부터 판독된다. 에러 정정된 페이지 데이터 및 페이지 데이터는 비휘발성 메모리에 기록된다. 추가의 실시예들에서, 제어기는 호스트로부터 수신된 페이지 데이터(예를 들어, 상위 페이지 데이터)를 하나 이상의 NAND 페이지 버퍼들에 로딩한다. 제어기는 에러 정정된 페이지 데이터로서 전송 버퍼에 저장하기 위해 NAND 메모리로부터 다른 페이지 데이터(예를 들어, 하위 페이지 데이터)를 판독한다. 전송 버퍼에 저장된 에러 정정된 페이지 데이터는 하나 이상의 NAND 페이지 버퍼들에 로딩된다.

에러 정정 기능을 갖는 메모리 시스템, 메모리 모듈 및 메모리 컨트롤러의 동작 방법

... 본 개시의 기술적 사상의 일측면에 따른 메모리 시스템은, 복수의 메모리 칩들의 DQ 그룹 관리 정보를 저장하는 메모리 컨트롤러를 포함할 수 있고, 메모리 컨트롤러는 복수의 메모리 칩들 각각의 DQ 접속기들과 연결되고, DQ 접속기들로 전송되는 데이터에 대해 데이터 정정 알고리즘을 수행하는 ECC 엔진 및 DQ 접속기들을 정정 데이터 폭의 사이즈를 갖는 DQ 그룹으로 그룹화하고, DQ 그룹을 관리하기 위한 DQ 그룹 관리 정보를 저장하는 DQ 그룹 관리부를 포함할 수 있다.

소프트 데이터 결정

... 본 발명은 소프트 데이터를 결정하기 위한 장치들 및 방법들을 포함한다. 다수의 실시예는 메모리 셀의 데이터 상태와 연관된 소프트 데이터를 결정하는 단계를 포함한다. 다수의 실시예에서, 소프트 데이터는 메모리 셀 상에서 단일 단계적 감지 동작을 수행함으로써 결정될 수 있다.

METHOD OF READING PAGE DATA OF NAND FLASH MEMORY DEVICE

APPARATUS AND A METHOD FOR MANAGING A DRAM BUFFER, PARTICULARLY FOR APPLYING AN ECC TO A DRAM BUFFER

PURPOSE: An apparatus and a method for managing a DRAM buffer are provided to record data and an ECC(Error Correction code) at a DRAM buffer. CONSTITUTION: An ECC(Error Correction Code) generating unit(111) generates the ECC for the data which are supposed to be stored at a DRAM buffer, and a recording unit(112) records the data and the ECC at the DRAM buffer. A reading unit(113) reads out the data and the ECC from the DRAM buffer. A judgment unit(114) judges based on the read ECC whether or not an error for the read data is generated. If the error happens in the read data, an error correction unit(115) corrects the error. COPYRIGHT KIPO 2011 ...

반도체 메모리 장치의 동작 방법 및 메모리 시스템

... 반도체 메모리 장치의 동작 방법은 반도체 메모리 장치에 포함된 제1 페이지의 데이터를 프로그램 하기 위한 프로그램 펄스를 인가하는 단계, 상기 프로그램 펄스의 인가 횟수가 제1 임계값을 초과하는지 여부를 판단하는 단계, 및 상기 제1 임계값의 초과 여부에 대한 판단 결과에 기초하여, 상기 제1 페이지와 동일한 워드 라인으로 연결되는 제2 페이지에 대해 에러 비트 체크를 수행하는 단계를 포함한다.

SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY

In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory. COPYRIGHT KIPO & WIPO 2010 ...

Access methods for a flash memory and memory devices

A memory device comprises a flush memory and a controller, in which the flush memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. According to a read instruction from a host, the controller reads out a corresponding data with a correction code from a corresponding data block in the flush memory and executes a predetermined check by the correction code. The controller determines whether the error is correctable when result of the predetermined check represents that an error occurs, and then the controller increases the erase count of the corresponding data block by a predetermined value when the error is correctable.

Data recovery using outer codewords stored in volatile memory

Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

Semiconductor package

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Memory device

According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

Soft decoding systems and methods for flash based memory systems

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

Semiconductor memory device

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

Memory device repair apparatus, systems, and methods

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

Error indicator from ecc decoder

The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

Semiconductor memory device correcting fuse data and method of operating the same

A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

Setting data storage for semiconductor devices including memory devices and systems

A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.

Providing low-latency error correcting code capability for memory

A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

Method for monitoring a data memory

A method is described for monitoring a data memory in which an error detection method is used to detect and/or correct incorrect data words stored in memory lines of the data memory, an address of the data memory at which a data word evaluated as incorrect by the error detection method is stored being written to an auxiliary memory and being made available to a checking program.

Data integrity in memory controllers and methods

The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

Method and System For Error Correction in Flash Memory

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Switchable on-die memory error correcting engine

Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Adaptive error correction for phase change memory

Subject matter disclosed herein relates to memory operations regarding error correction or error detection.

Device and method for storing encoded and/or decoded codes by re-using encoder

The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.

Memory devices, circuits and, methods that apply different electrical conditions in access operations

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

Memory operation upon failure of one of two paired memory devices

A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy.

Outputting Information of ECC Corrected Bits

The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information.

Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults

A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.

Flash memory system and operating method thereof

An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.

DELAY-COMPENSATED ERROR INDICATION SIGNAL

A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices. 1. A memory module comprising:multiple memory devices to store data;a command/address transmission line coupled between each of the memory devices and a memory controller, wherein the command/address transmission line is driven by the memory controller; andan error alert transmission line coupled to each of the memory devices, wherein the error alert signal is driven by the memory devices, wherein the error alert transmission line is delay-compensated to provide a deterministic alert signal timing on the error alert transmission line.2. The memory module of claim 1 , wherein the memory devices comprise dynamic random access memory (DRAM) devices.3. The memory module of claim 1 , wherein the memory devices are to drive the error alert transmission line in response to detecting a parity error in a command/address signal.4. The memory module of claim 1 , wherein the error alert line is delay-compensated by having the error alert transmission line physically routed in a direction opposite a direction of physical routing of the command/address transmission line.5. The memory module of claim 4 , wherein the command/address transmission line is routed from a memory device of lowest address to a memory device of highest address claim 4 , and the error alert line is routed from the memory device of highest address to the memory device of the lowest address.6. A memory subsystem comprising:a memory controller coupled to a command/address line and an error alert line;multiple memory devices that share the command/address line ...

Low latency decoder for error correcting codes

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

Methods for Error Correction with Resistive Change Element Arrays

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

Low ber hard-decision ldpc decoder

A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.

Host Device, Access System, and Access Method

A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.

Semiconductor memory device, memory controller, and control method of memory controller

In a semiconductor memory device of an embodiment, a controller writes write data and first address management information including address information of the write data to a memory, and performs, when an error occurs in any of the write data read from the memory, an error correction process to an error correction group including the write data and the first address management information. The controller generates, when a read error is detected within a process target error correction group, second address management information including address information of write data within the process target error correction group and error position information indicative of a position of the read error, and writes invalid data and the second address management information to erased condition areas within areas to be written of the process target error correction group.

Read voltage management based on write-to-read time difference

A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can be determined. An amount of time that has elapsed since the time the performance of the write operation until the time to perform the read operation can be determined. A read voltage from a plurality of read voltages can be selected based on the amount of time that has elapsed. The read operation can be performed to retrieve the data by using the read voltage.

TEMPERATURE RELATED ERROR MANAGEMENT

Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold. 1. An apparatus , comprising:an array of memory cells;a write temperature indicator appended to at least one predetermined number of bytes of stored data in the array of memory cells; and determine an error rate during a read of data stored in the array of memory cells;', 'determine a temperature difference between the write temperature indicator and a read temperature indicator; and', 'retire a number of memory cells associated with storage of the stored data when the determined error rate is at least equal to a stored retirement error threshold and the determined error rate exceeds an error rate expected at a stored temperature difference threshold., 'a controller configured to2. The apparatus of claim 1 , wherein the apparatus is further configured to include a component to receive an ambient temperature measurement to enable storage of the read temperature indicator in a timeframe associated with a read of stored data.3. The apparatus of claim 1 , wherein the apparatus is further configured to store claim 1 , in the controller claim 1 , a write temperature stamp for the at least one predetermined number of bytes of data claim 1 , wherein the write temperature stamp indicates at least one of:an ambient temperature range in a timeframe in which the data is written for storage; ...

Memory system and method for operating semiconductor memory device

A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.

Memory device, memory system including the same, and operating method of memory system

A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.

Systems and methods for performing a write pattern in memory devices

A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

CIRCUIT AND METHOD FOR IMPRINT REDUCTION IN FRAM MEMORIES

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line. 1. A memory device comprising:a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line; and first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type;', 'a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line; and', 'a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line., 'a sense amplifier that includes2. The memory device of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type claim 1 , and wherein the first and second transistors are n-channel transistors and the third and fourth transistors are p-channel transistors.3. The memory device of claim 1 , comprising:a first switching transistor coupled between the first bit line and the first common drain terminal; anda second switching transistor ...

Storage control circuit, storage apparatus, imaging apparatus, and storage control method

It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.

Error correction device, semiconductor storage device, and error correction method

There is provided an error correction device with a simple configuration and a high correction capability. An error correction device which can perform c (c<n) error corrections on n-bit encoded data containing a parity bit includes an assumption data setting circuit for setting a plurality of assumption data, containing c error bits and (n−c) or fewer erasure bits, by assuming data of an erasure bit, and a decoding circuit which calculates a syndrome for each of the assumption data set by the assumption data setting circuit and performs decoding based on a calculation result and the parity bit.

APPARATUS, SYSTEM, AND METHOD OF BYTE ADDRESSABLE AND BLOCK ADDRESSABLE STORAGE AND RETRIVAL OF DATA TO AND FROM NON-VOLATILE STORAGE MEMORY

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks. 1. A hybrid memory apparatus , comprising:a volatile memory logically divided into a volatile byte-addressable memory and a volatile block-addressable memory;a non-volatile block-addressable memory; (a) the host system bus and the volatile byte-addressable memory,', '(b) the host system bus and the volatile block-addressable memory,', '(c) the volatile byte-addressable memory and the volatile block-addressable memory, and', '(d) the volatile block-addressable memory and the non-volatile block-addressable memory; and, 'a host parallel memory interface that receives commands from a host system bus to exchange data between each ofa traffic controller that manages data traffic as a function of a host address received by the host parallel memory interface.2. The hybrid memory apparatus of claim 1 , wherein the host parallel memory interface routes the host address to the traffic controller when the host address refers to a byte-addressable address and routes the host address to an address translation circuit when the host address refers to a block-addressable address.3. The hybrid memory apparatus of claim 2 , wherein the traffic controller routes the host address to the volatile byte-addressable memory as a physical byte-addressable address when the host address refers to a byte-addressable address.4. The hybrid memory apparatus of claim 2 , wherein the address translation circuit routes ...

Soft-input soft-output component code decoder for generalized low-density parity-check codes

Disclosed are devices, systems and methods for improved decoding of a binary linear code. An example method includes receiving a noisy codeword; computing a syndrome based on the noisy codeword; identifying N error patterns that correspond to the syndrome; selecting M error patterns from the N error patterns, wherein M≤N are positive integers, wherein a distance between a codeword corresponding to each of the M error patterns and the noisy codeword is less than a distance between a codeword corresponding to any other error pattern and the noisy codeword, and wherein the distance excludes a Hamming distance; modifying the noisy codeword based on each of the M error patterns one-at-a-time; and decoding the modified noisy codeword one-at-a-time until a successful decoding is achieved.

Cryptographic key management

Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

Optimistic read operation

A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Method and apparatus for encoding and decoding data in memory system

A memory controller of a memory system, the memory system including the memory controller and a memory device, includes a processor configured to receive write data an control the memory controller; and an encoder, the processor being configured to, receive write data, read previously programmed data from a first memory page of a memory cell array of the memory device, and control the encoder to generate encoded data by encoding the write data using stuck bit code (SBC), based on the read previously programmed data, the previously programmed data being data that has been programmed into the first memory page of the memory cell array and has not been erased; the processor being configured to write the encoded data to the first memory page without erasing the first memory page.

METHODS AND APPARATUSES FOR ERROR CORRECTION

Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures. 1. An apparatus , comprising:a memory device having a plurality of data bits stored in a plurality of multi-level memory cells, and further having parity check bits stored with a set of data bits including a portion of the plurality of data bits, the parity check bits stored with the set of data bits in a block of multi-level cells of the plurality of multi-level memory cells; anda controller coupled to the memory device and configured to convert a flash channel associated with the plurality of multi-level memory cells from an errors channel to an erasures channel, and to perform low density parity check decoding.2. The apparatus of claim 1 , wherein the set of data bits including the portion of the plurality of data bits is less than all data bits of the plurality of data bits.3. The apparatus of claim 1 , wherein the set of data bits including the portion of the plurality of data bits is less than all data bits of the plurality of data bits claim 1 , andwherein the memory device is further configured to store another set of data bits including a remaining portion of the plurality of data bits.4. The apparatus of claim 1 , further comprising:an encoder circuit in the controller, the encoder circuit configured to store parity bits and Bose-Chaudhuri-Hocquenghem (BCH) parity bits generated based on the parity bits,wherein the BCH parity bits are used to generate the parity check bits, andwherein the memory device is further configured to store another set of data bits including a remaining portion of the plurality of data bits ...

Semiconductor memory devices and methods of operating semiconductor memory devices

A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

Discrete Three-Dimensional Memory

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Discrete Three-Dimensional Vertical Memory

The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-M V arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Spare substitution in memory system

Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

Memory device, memory system, and method of operating the memory system

A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

SELECTIVELY DE-STRADDLING DATA PAGES IN NON-VOLATILE MEMORY

A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments. 1. A computer-implemented method , comprising:detecting at least one read of a logical page straddled across codewords;storing an indication of a number of detected reads of the straddled logical page; andrelocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner.2. The computer-implemented method as recited in claim 1 , comprising: detecting reading of the logical page straddling across multiple codewords in a same physical page.3. The computer-implemented method as recited in claim 1 , comprising: detecting reading of the logical page straddling across multiple physical pages.4. The computer-implemented method as recited in claim 1 , comprising:storing the indication of the number of detected reads by increment a straddled page read counter in response to detecting each read of the straddled logical page; andrelocating at least the straddled logical page in response to the read counter exceeding a threshold.5. The computer-implemented method as recited in claim 4 , wherein the straddled page read counter indicates a number of reads of all straddled logical pages on a single physical page.6. The computer-implemented method as recited in claim 4 , wherein the straddled page read counter indicates a number of reads of ...

DETERMINING SOFT DATA

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell. 1. An apparatus , comprising:an array of memory cells; and sense a current on a data line to which a memory cell of the array is coupled; and', a data state of the memory cell; and', 'soft data associated with the data state of the memory cell., 'determine, based on the sensed current], 'a controller configured to operate sense circuitry to2. The apparatus of claim 1 , wherein the sense circuitry comprises boost circuitry.3. The apparatus of claim 2 , wherein the boost circuitry comprises an inverter.4. The apparatus of claim 1 , wherein the controller is configured to operate the sense circuitry to:determine, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell; anddetermine, based on the determined voltage, the data state of the memory cell and the soft data associated with the data state of the memory cell.5. The apparatus of claim 1 , wherein the controller is configured to operate the sense circuitry to sense the current on the data line by applying a single stepped sensing signal to the memory cell.6. The apparatus of claim 1 , wherein the array of memory cells is an array of NAND flash memory cells.7. A method for operating memory claim 1 , comprising:sensing a current on a data line to which a memory cell is coupled;determining, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell; and a data state of the memory cell; and', 'soft data associated with the data state of the memory cell., 'determining, based on the determined voltage8. The method of claim 7 , wherein determining the data state of the memory cell and the soft data associated with the data state of the ...

Memory system, memory controller, and operating method thereof

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller controls the memory device to perform a plurality of read operations on memory cells included in a selected physical page among the plurality of memory cells. The memory controller calculates an inverted bit number representing different bit values, based on a plurality of read data received from the memory device. The memory controller performs a read reclaim operation on the selected physical page, based on the inverted bit number.

Predicted error correction apparatus, operation method thereof and memory system using the same

A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.

Memory device and method of operating the same

The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

Memory cell including multi-level sensing

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

Memory device with configurable error correction modes

Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

Semiconductor memory device, semiconductor memory system including the same, method of driving the semiconductor memory system

A semiconductor memory device includes a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected with the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block and a position decision block. The pattern generation block receives a row address, a column address and a deck selection signal to generate a plurality of pattern generation signals to select a plurality of memory cells in the memory deck in various patterns. The position correction block receives a temporary code for classifying the memory cells into a temporary near cell region and a temporary far cell region and for reflecting a position of the memory deck in the temporary code to output a correction code. The position decision block is configured to generate first to third reset signals to reset a near cell region, a middle cell region and a far cell region based on the pattern generation signals and the correction code.

MEMORY SYSTEMS FOR MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY SYSTEMS

A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value. 1. A memory system comprising:a memory device having a plurality of memory regions; anda memory controller configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.2. The memory system of claim 1 , wherein the memory device includes a phase change memory (PCM) device.3. The memory system of claim 1 , wherein the plurality of memory regions include a plurality of memory blocks.4. The memory system of claim 1 , wherein the plurality of memory regions include a plurality of pages.5. The memory system of claim 1 , wherein the memory controller includes:a command processing circuit configured to process a command outputted from a host and configured to generate the read command for the first memory region regardless of the host in response to a read command generation control signal; anda write counting circuit configured to output the read command generation control signal to the command processing circuit when the number of the write commands successively generated for the first memory region reaches the reference value.6. The memory system of claim 5 , wherein the command processing circuit includes a read command generator that receives the read command generation control signal and an address of the first memory region from the write counting circuit to generate the read command for the first memory region.7. The memory system of claim 5 , wherein the command processing circuit transmits both of the command and an address of ...

Memory system

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Semiconductor devices

A semiconductor device may include an error correction circuit and a fuse signal generation circuit. The error correction circuit may be configured to generate a syndrome signal from data using an error correction code. The fuse signal generation circuit may be configured to receive the syndrome signal to generate a fuse signal for repairing a cell array storing the data.

Decoder, operating method thereof and memory system including the decoder

An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.

Memory device that changes a writable region of a data buffer based on an operational state of an ecc circuit

A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.

Die-Level Monitoring in a Storage Cluster

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Memory system

A memory system includes a plurality of first memory chips connected to a first bus, a plurality of second memory chips connected to a second bus, and a controller that is connected to the first and second buses and configured to execute a write operation by performing processes that include selecting one of the plurality of first memory chips based on first information including data reading speed information and/or data writing speed information for the plurality of first memory chips, and selecting one of the plurality of second memory chips based on second information including data reading speed information and/or data writing speed information for the plurality of second memory chips.

Memory system and controlling method

A memory system includes a controller that: in a case where first data being a read target is stored across a first storage area of a first plane and a second storage area of a second plane, causes a memory chip to perform sensing to second data including a first fragment of the first data; causes the memory chip to perform sensing to third data including a second fragment of the first data stored in the second storage area; stores the second data in a first buffer; stores the third data in a second buffer; reads the first and second fragments from the first and second buffers respectively; combines the fragments to generate fourth data; and inputs the fourth data to an error correction circuit.

Error mitigation for 3d nand flash memory

NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.

INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES

A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance. 1. A method of error correction in a cross point memory device having a data block arranged in a rectangular pattern , comprising:determining that a number in an individual storage location is incorrect;subtracting the incorrect individual number from the from the data block; andinserting a new number into the data block from which the incorrect individual number has been removed.2. The method of claim 1 , further comprising:calculating a difference between the incorrect number in the individual storage location and the new number.3. The method of claim 2 , further comprising:calculating error detecting numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect; andcalculating correcting parity numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect.4. The method of claim 3 , further comprising:calculating new error detecting numbers, wherein the calculating occurs after inserting the new number; andcalculating new correcting parity numbers, wherein the calculating occurs after inserting the new number.5. The method of claim 2 , further comprising:calculating a difference between the incorrect number and the new number; andadding the difference between the incorrect number and the new number to the error detecting numbers and the correcting parity numbers.6. The method of claim 2 , wherein the data block is a nine-number data block.7. The method of claim 1 , further comprising:calculating error detecting numbers, wherein the ...

HARDWARE ASSISTED DATA LOOKUP METHODS

A method for hardware assisted data lookup in a storage unit is provided. The method includes formatting data in at least one of a plurality of data formats for storage in the storage unit. The method includes configuring a logic unit with one or more parameters associated with the plurality of data formats and identifying incoming data with the one or more parameters as an instruction for execution. 1. A method , comprising:identifying, through one or more parameters informing a logic unit about a formatting of contents of a solid state storage device, an instruction for execution from incoming data, the incoming data read from the solid state storage device responsive to a read command.2. The method of claim 1 , wherein the instruction contains information on a next action to be performed.3. The method of claim 1 , wherein the instruction encodes information indicating where data is located on a page of the incoming data.4. The method of claim 1 , wherein the incoming data is parsed as the incoming data flows through a storage unit containing the solid state storage device.5. The method of claim 1 , wherein the incoming data is error corrected data.6. The method of claim 1 , wherein the identified instruction is placed into a queue for execution and wherein the one or more parameters are generated internal to the storage system.7. The method of claim 1 , wherein the logic module executes the identified instruction.8. A storage cluster claim 1 , comprising:a plurality of storage nodes, coupled together as the storage cluster, each of the storage nodes containing a plurality of storage units each having solid state storage, each storage node having a controller configured to distribute data across the plurality of storage units; andat least one of the plurality of storage units having a data layout engine and a logic module, the data layout engine operable to configure the logic module with one or more parameters informing the logic module about a formatting of ...

Memory with guard value dependent error correction

Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed.

Memory utilizing bundle-level status values and bundle status circuits

An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.

Method of controlling nonvolatile memory

According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction.

Data Storage Device and Data Maintenance Method Thereof

The present invention provides a data storage device including a flash memory. The flash memory includes a plurality of weak pages and a plurality of strong pages, wherein each of the strong pages is paired with one of the weak pages, and each of 1. A data storage device , comprising:a flash memory, comprising:a plurality of weak pages; anda plurality of strong pages, wherein each of the strong pages is paired with one of the weak pages, and each of the strong pages comprises error-correction information of the paired weak page, wherein the error-correction information is used to correct the first weak page.2. The data storage device as claimed in claim 1 , wherein the flash memory comprises a plurality of word lines claim 1 , and each of the word lines comprises one of the strong pages and one of the weak pages claim 1 , wherein the strong page belongs to the word line that is different from the word line of the paired weak page.3. The data storage device as claimed in claim 2 , wherein the flash memory operates as a Multi-Level Cell claim 2 , the flash memory further comprises a plurality of middle pages claim 2 , and each of the word lines comprises one of the strong pages claim 2 , one of the middle pages claim 2 , and one of the weak pages.4. The data storage device as claimed in claim 1 , wherein each of the weak pages has a first user data area and a first spare area claim 1 , each of the strong pages has a second user data area and a second spare area claim 1 , the first spare area has a first parity code corresponding to the first user data area claim 1 , the second spare area has a second parity code corresponding to the second user data area claim 1 , and the length of the second parity code is shorter than the first parity code.5. The data storage device as claimed in claim 4 , wherein the second spare area further comprises the error-correction information claim 4 , and the error-correction information is a third parity code obtained by encoding the ...

Memories utilizing hybrid error correcting code techniques

Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.

ERROR CORRECTION CODE EVENT DETECTION

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node. 1. (canceled)2. A method of operating an electronic memory apparatus , comprising:performing a read operation on a set of memory cells;detecting an error in data read from the set of memory cells based at least in part on an error correction code (ECC) operation performed on the data;changing a voltage of an output pin of the electronic memory apparatus from a first level to a second level based at least in part on detecting the error, the second level indicating the error; andchanging the voltage of the output pin from the second level to the first level based at least in part on determining that a threshold amount of time has elapsed since the error was detected.3. The method of claim 1 , further comprising:incrementing a counter that represents a quantity of detected errors, wherein the counter is incremented based at least in part on the voltage of the output pin changing from the first level to the second level; andperforming a refresh operation based at least in part on the counter exceeding a threshold value.4. The method of claim 1 , further comprising:detecting a second error in data read from a second set of memory cells; andmaintaining the voltage of the output pin at the second level irrespective of the detection of the second error.5. The method of claim 1 , further comprising:selecting a second set of memory cells for a read operation; andmaintaining the voltage of the output pin at the ...

SYSTEM FOR MEMORY ACCESS BANDWIDTH MANAGEMENT USING ECC

A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information. 1. A system comprisinga memory management module;memory in communication with the memory management module;a transaction table for tracking control information including at least a plurality of WAYs and an ECC total for the plurality of WAYs within a data stream, wherein each WAY has an ECC value; andan ECC calculation module for determine a new ECC total when at least one WAY of the plurality of WAYs in the data stream is replaced with a new WAY,the ECC calculation module calculates a new ECC value using an ECC mask for the at least one WAY that was changed and replaces the ECC value for the corresponding at least one WAY that was changed with the new ECC value to determine the new ECC total, thereby reducing memory access bandwidth needed to generate the new ECC.2. The system of further comprising:a first IP, which is in communication with the memory, using a first protection scheme;a second IP, which is in communication with the memory, using a second protection scheme; andan encoder in communication with the first IP and the second IP, the encoder receives redundant information according to the first protection scheme and encodes redundant information according to the second protection scheme,wherein the first protection scheme and the second protection scheme are different.3. The system of further comprising an interconnect in communication with the first IP and the second IP claim 2 , ...

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Memory device with error check function of memory cell array and memory module including the same

A memory device that checks an error of a memory cell and a memory module including the same are disclosed. The memory module includes a first memory device and a second memory device. The first memory device includes a first area in which normal data are stored, and a second area in which error check data are stored. The second memory device stores reliability information about the normal data that is stored in the first area of the first memory device. The first memory device outputs a result of comparing the normal data read from the first area of the first memory device to the error check data read from the second area of the first memory device.

Adaptive Operation of 3D NAND Memory

In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.

APPARATUSES AND METHODS FOR ERROR CORRECTION CODING AND DATA BUS INVERSION FOR SEMICONDUCTOR MEMORIES

Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array. 1. An apparatus , comprising:an I/O circuit configured to receive first data and first ECC data associated with the first data;a memory array; anda control circuit coupled between the I/O circuit and the memory array, the control circuit configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data, the control circuit further configured to store both the corrected first data and the corrected first ECC data into the memory array.2. The apparatus of claim 1 , wherein the control circuit is further configured to receive second data and second ECC data corresponding to the second data from the memory array claim 1 , execute second ECC-decoding to produce corrected second data and corrected second ECC data claim 1 , and transmit the corrected second data and the corrected second ECC data to the I/O circuit.3. The apparatus of claim 2 , wherein each of the first ECC-decoding and the second ECC-decoding is executed based on a common H-matrix.4. The apparatus of claim 1 , wherein the I/O circuit is further configured to receive DBI data and second ECC data corresponding to the DBI data claim 1 , and the first data is DBI-encoded based on the DBI data;wherein the control circuit is ...

VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC. 1. (canceled)2. A memory module comprising:a primary data link, a first secondary data link, and a second secondary data link;a first memory component coupled to the first secondary data link; anda second memory component coupled to the second secondary data link;{'claim-text': ['a first mode in which the memory module, responsive to successive first and second read commands to the first memory component and the second memory component, respectively, successively conveys over the primary data link first read data from the first memory component via the first secondary data link and second read data from the second memory component via the second secondary data link; and', 'a second mode in which the memory module, responsive to the successive first and second read commands to the first memory component and the second memory component, respectively, interleaves over the primary data link the first read data from the first memory component via the first secondary data link and the second read data from the second memory component via the second secondary data link.'], '#text': 'the memory module operable in:'}3. The memory module of claim 2 , wherein the memory module operates the primary data link claim 2 , the first secondary data link claim 2 , and the second secondary data link at a bit rate in at least the first mode.4. The memory module of claim 3 , wherein the memory module operates the primary data link at the bit rate in the first mode and at a second bit rate faster than the bit rate in ...

DATA STATE SYNCHRONIZATION

An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells. 1. An apparatus , comprising:a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells; and performance of a cleaning operation on a selected group of the memory cells;', 'generation of error correction code (ECC) parity data; and', write an inverted state of at least one data value to the selected group of cells; and', 'write an inverted state of at least one of the ECC parity data to the selected group of cells., 'performance of a write operation on the selected group of cells to], 'a controller coupled to the memory and configured to cause2. The apparatus of claim 1 , wherein the controller is further configured to cause the cleaning operation and generate the ECC parity bit to be performed concurrently.3. The apparatus of claim 1 , wherein the controller is further configured to cause the inverted state of the at least one data value and the inverted state of the at least one ECC parity data to be written to the selected group of cells concurrently.4. The apparatus of claim 1 , wherein the memory and the controller comprise an embedded data state sync system claim 1 , and wherein the embedded data state sync system is deployed on a single chip.5. The apparatus of claim 1 , wherein the selected group of memory cells correspond to a small managed unit of ...

MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION

An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address. 1receiving, from a memory controller, a read-modify-write command on a command interface, the read-modify-write command having an associated read address indicating a location in a memory bank of the memory component;accessing read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from receiving the read-modify-write command;receiving write data associated with the read-modify-write command on a data interface;merging the received write data with the read data to form a merged data; andwriting the merged data to the location in the memory bank indicated by the read address.. A method of operation in a memory component, the method comprising: This application is a continuation of U.S. application Ser. No. 16/371,345, filed Apr. 1, 2019, now U.S. Pat. No. 10,860,253, issued Dec. 8, 2020, which is a continuation of U.S. application Ser. No. 15/990,211, filed May 25, 2018, now U.S. Pat. No. 10,248,358, issued Apr. 2, 2019, which is U.S. application Ser. No. 15/022,176, filed Mar. 15, 2016, now U.S. Pat. No. 9,983,830, issued May 29, 2018, which is a 371 application of PCT/US2014/057040 filed Sep. 23, 2014, which claims the benefit of U.S. Provisional ...

Memory system and operating method thereof

A memory system includes: a memory device including a plurality of banks; and a memory controller suitable for: controlling an operation of the memory device, calculating row hammer information for each of the banks for each program having a command set requested from a host, and scheduling the banks based on the row hammer information for each of the banks corresponding to a specific program when the specific program is requested from the host.

Memory system and method of controlling nonvolatile memory

According to an embodiment, a memory system includes: a test pattern decoding unit that detects an intermediate decoding word from a plurality of test patterns; a Euclid distance calculating unit that calculates a Euclid distance between the intermediate decoding word and a received word; and a maximum likelihood decoding word selecting unit that maintains a maximum likelihood decoding word candidate. In a case where a Euclid distance of the intermediate decoding word is shorter than a Euclid distance of the maximum likelihood decoding word candidate, the maximum likelihood decoding word selecting unit updates the maximum likelihood decoding word candidate by using the intermediate decoding word and the test pattern decoding unit does not execute decoding of a test pattern having no possibility that the Euclid distance of the intermediate decoding word becomes shorter than the Euclid distance of the maximum likelihood decoding word candidate.

NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION

Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition. 1. A method comprising:retrieving, using a memory device, first information from a first portion of a memory device;storing, using the memory device, the first information in a first additional portion of the memory device after an error detection operation is performed on the first information;retrieving, using the memory device, second information from a second portion of the memory device after the error detection operation is performed on the first information; andstoring, using the memory device, the second information in an additional second portion of the memory device after no error detection operation is performed on the second information based on a result from the error detection operation performed on the first information.2. The method of claim 1 , wherein the result from the error detection operation performed on the first information indicates whether a threshold condition is met.3. The method of claim 1 , wherein the result from the error detection operation performed on the first information indicates that the first information has no erroneous bits.4. ...

Method and system for data destruction in a phase change memory-based storage device

One embodiment facilitates data destruction in a phase change memory-based storage device. During operation, the system detects, by the storage device, a power loss. Subsequent to the power loss, the system overwrites keys and configuration information used to transform data stored in the phase change memory, wherein the keys and the configuration information are stored in the phase change memory, thereby preventing the data from being recovered.

Techniques to Recover Data Using Exclusive OR (XOR) Parity Information

Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.

Hardware assisted data lookup methods

A method for hardware assisted data lookup in a storage unit is provided. The method includes formatting data in at least one of a plurality of data formats for storage in the storage unit. The method includes configuring a logic unit with one or more parameters associated with the plurality of data formats and identifying incoming data with the one or more parameters as an instruction for execution.

Memory system to process multiple word line failures with limited storage and method of operating such memory system

Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

MEMORY CORRECTING METHOD

A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction. 1. A memory correcting method comprising steps:providing a memory with a plurality of memory bytes each having M bits, wherein M is a positive integer;respectively adding a plurality of correcting bytes to the plurality of memory bytes, wherein each of the plurality of correcting bytes has N correcting bits, and wherein N is a positive integer and less than M;{'sup': 'Q', 'respectively providing a plurality of reference memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes, wherein each of the plurality of reference memory address bytes has Q bits for labeling underperforming-bit addresses of each of the plurality of memory bytes and each of the plurality of correcting bytes, and wherein 2≥M+N; and'} if no, terminating correction of the memory; and', 'if yes, labeling the underperforming bits of the plurality of memory bytes and of correcting bytes then using a non-underperforming the correcting bit of the plurality of correcting bytes to replace the underperforming bit of the plurality of memory bytes, thereby completing correction of the ...

Memory Interface Supporting Both ECC and Per-Byte Data Masking

A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Uncorrectable error correction code (uecc) recovery time improvement

An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

CLOUD-BASED SOLID STATE DEVICE (SSD) WITH DYNAMICALLY VARIABLE ERROR CORRECTING CODE (ECC) SYSTEM

Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system. 1. A non-transitory computer-readable medium storing computer executable instructions that when executed by a computer control the computer to perform a method , the method comprising:accessing electronic forensic data about a cloud data storage system;identifying an attribute associated with a data set to be stored by the cloud data storage system;selecting an error correcting code (ECC) approach based, at least in part, on an analysis performed by the computer of the electronic forensic data, and the attribute;generating one or more ECC associated with the data set based, at least in part, on the ECC approach; andcontrolling the cloud data storage system to store a portion of the data set and a portion of the one or more ECC, where the portion of the data set or the portion of the ECC are selected based, at least in part, on the ECC approach.2. The non-transitory computer-readable medium of claim 1 , where the cloud data storage system comprises a solid state device (SSD).3. The non-transitory computer-readable medium of claim 2 , where the SSD is a NAND flash memory device.4. The non-transitory ...

NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR CORRECTION

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane. 1. An apparatus , comprising:a dynamic random access memory (DRAM);a non-volatile memory (NVM) coupled to the DRAM;a register that provides functionality to identify chip failure of the NVM associated with restoring data from the NVM to the DRAM following a loss of system power to the apparatus; anda controller configured to:receive, from a host device, a first command that is based at least in part on a loss of system power to the apparatus;transfer data from the DRAM to the NVM based at least in part on receiving the first command from the host device;receive, from the host device, a second command that is based at least in part on the system power to the apparatus being re-established;restore the data from the NVM to the DRAM upon receiving the second command from the host device;identify chip failure of the NVM in the register, the chip failure based at least in part on restoring the data from the NVM to the DRAM; andoperate the apparatus based at least in part on the chip failure identified and according to instructions from a host device.2. The apparatus of claim 1 , wherein controller is configured to:adjust a bit of the register to indicate that the chip failure comprises an error in media of the NVM.3. The apparatus of claim 1 , wherein the controller is configured to:adjust a bit of the register to indicate that the chip failure comprises an error in the controller.4. The apparatus of claim 1 , wherein the controller is configured to ...

Recovery of a coherent system in the presence of an uncorrectable error

A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.

Memory system and memory controller

According to embodiments, a second control unit creates parity from information loaded into a volatile second memory. When shifting from a normal mode to a sleep mode, the second control unit stores the created parity and the information loaded in the second memory into a buffer of a non-volatile first memory, and issues a power supply shutdown request. A power supply circuit shuts down power supply to the second memory and the second control unit in response to the issued power supply shutdown request.

Memory system with decoders and method of operating such memory system and decoders

A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

OPERATING METHOD OF MEMORY SYSTEM AND HOST RECOVERING DATA WITH WRITE ERROR

A method of operating a memory system including a memory device, including in response to a write request of a host, storing write data and a physical address received from the host in a buffer; performing a write operation on the memory device based on the write data and the physical address; based on a write error corresponding to the write data occurring, asynchronously providing the host with error occurrence information; and providing the host with the write data having the write error and information used for a recovery from the write error. 1. A method of operating a memory system comprising a memory device , the method comprising:in response to a write request of a host, storing write data and a physical address received from the host in a buffer;performing a write operation on the memory device based on the write data and the physical address;based on a write error corresponding to the write data occurring, asynchronously providing the host with error occurrence information; andproviding the host with the write data having the write error and information used for a recovery from the write error.2. The method of claim 1 , wherein the performing of the write operation comprises:based on the write data, generating at least one parity comprising at least one of an error correcting code (ECC) parity of the write data or a recovery parity of pieces of write data in a recovery unit corresponding to the write data; andwriting the write data and the generated at least one parity.3. The method of claim 2 , wherein the information used for the recovery from the write error comprises at least one of the at least one parity claim 2 , normal data included in the recovery unit claim 2 , or management information of the memory system.4. The method of claim 1 , wherein claim 1 , based on the write error occurring in a data area claim 1 , the information used for the recovery from the write error comprises metadata corresponding to the write data having the write error.5. ...

Nonvolatile memory devices and methods of operating a nonvolatile memory

Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.

COMPUTING MEMORY ARCHITECTURE

Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data. 1. A non-volatile memory architecture , comprising:a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines;a first data interface for receiving data from an external device and for outputting data to the external device, the first data interface comprises a first bandwidth; anda second data interface for outputting data to the external device, the second data interface comprises a second bandwidth different than the first bandwidth.2. The non-volatile memory architecture of claim 1 , wherein the second data interface selects a subset of bitlines from the multiple sets of bitlines claim 1 , and wherein the first data interface selects all bitlines from the multiple sets of bitlines.3. The non-volatile memory architecture of claim 1 , further comprising:programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, wherein the programmable processing elements are configured to receive stored data ...

Storage controller and method of restoring error of the same

A storage controller includes a host interface configured to perform communication with a host device, a memory interface configured to perform communication with a nonvolatile memory device, a higher-level controller, and a lower-level controller. The higher-level controller issues operations to be performed by the nonvolatile memory device based on requests transferred through the host interface. The lower-level controller includes an operation memory configured to store an operation code and operation data. The lower-level controller controls the memory interface based on the operation code and the operation data such that the nonvolatile memory device performs issued operations received from the higher-level controller. The higher-level controller performs, when an error occurs in the lower-level controller, an error restoring operation based on state information of the lower-level controller to restore the lower-level controller to a previous state corresponding to a state before the error occurs.