Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 5060. Отображено 100.
16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1
Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Подробнее
Номер записи: 1
14-06-2012 дата публикации

Embedded DRAM having Low Power Self-Correction Capability

Номер: US20120151299A1
Автор: Jungwon Suh
Принадлежит: Qualcomm Inc

Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

Подробнее
Номер записи: 2
28-06-2012 дата публикации

Early degradation detection in flash memory using test cells

Номер: US20120163074A1
Автор: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
Принадлежит: Individual

A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write V T and variable read V T . Techniques for early degradation detection (EDD) in Flash memories measure the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values.

Подробнее
Номер записи: 3
28-06-2012 дата публикации

Single check memory devices and methods

Номер: US20120163076A1
Автор: Aaron Yip, Tomoharu Tanaka, Vishal Sarin
Принадлежит: Individual

Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

Подробнее
Номер записи: 4
30-08-2012 дата публикации

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Номер: US20120218846A1
Автор: Yong Gu Kang
Принадлежит: SK hynix Inc

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

Подробнее
Номер записи: 5
30-08-2012 дата публикации

Bit-replacement technique for dram error correction

Номер: US20120221902A1
Автор: Ely Tsern, Frederick A. Ware, Thomas Vogelsang
Принадлежит: RAMBUS INC

The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

Подробнее
Номер записи: 6
13-12-2012 дата публикации

Infrastructure for performance based chip-to-chip stacking

Номер: US20120313647A1
Автор: Alan James Drake, Eren Kursun, Gary Dale Carpenter, Phillip John Restle
Принадлежит: International Business Machines Corp

A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

Подробнее
Номер записи: 7
03-01-2013 дата публикации

Estimating temporal degradation of non-volatile solid-state memory

Номер: US20130007543A1
Автор: David Scott Seekins, Mark Allen Gaertner, Ryan James Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

Representative locations of a non-volatile, solid-state memory of an apparatus store characterization data. An event during which elapsed time is not measured by the apparatus is determined. In response to the event, temporal degradation of the non-volatile, solid-state memory during the event is estimated based on electrical characteristics of the representative locations.

Подробнее
Номер записи: 8
10-01-2013 дата публикации

Semiconductor device, adjustment method thereof and data processing system

Номер: US20130010515A1
Автор: Chikara Kondo, Naohisa Nishioka
Принадлежит: Elpida Memory Inc

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

Подробнее
Номер записи: 9
28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Подробнее
Номер записи: 10
11-07-2013 дата публикации

Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit

Номер: US20130176772A1
Автор: Wah Kit Loh, Xiaowei Deng, Yang Yi
Принадлежит: Texas Instruments Inc

A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Подробнее
Номер записи: 11
22-08-2013 дата публикации

Tracking capacitive loads

Номер: US20130215693A1
Автор: Annie-Li-Keow Lum, Bing Wang, Derek C. Tao, Kuoyuan (Peter) Hsu, Young Seog Kim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.

Подробнее
Номер записи: 12
22-08-2013 дата публикации

Semiconductor memory device changing refresh interval depending on temperature

Номер: US20130215700A1
Автор: Akinobu Shirota, Kuninori Kawabata
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Подробнее
Номер записи: 13
19-09-2013 дата публикации

Semiconductor memory device for controlling write recovery time

Номер: US20130242679A1
Автор: Jae-Hyuk Im, Woon-Bok Lee
Принадлежит: 658868 N B Inc

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Подробнее
Номер записи: 14
24-10-2013 дата публикации

Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System

Номер: US20130283002A1
Автор: Abhijeet A. Chachad, Raguram Damodaran, Ramakrishnan Venkatasubramanian
Принадлежит: Texas Instruments Inc

In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Подробнее
Номер записи: 15
14-11-2013 дата публикации

Threshold voltage measurement device

Номер: US20130301343A1
Автор: Ching-Te Chuang, Geng-Cing Lin, Jyun-Kai Chu, Kuen-Di Lee, Ming-Chien Tsai, Nan-Chun Lien, Shao-cheng WANG, Shyh-Jye Jou, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: Individual

A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

Подробнее
Номер записи: 16
28-11-2013 дата публикации

Method for programming nonvolatile memory element, method for initializing nonvolatile memory element, and nonvolatile memory device

Номер: US20130314975A1
Автор: Koji Katayama, Takeshi Takagi
Принадлежит: Panasonic Corp

A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

Подробнее
Номер записи: 17
05-12-2013 дата публикации

NONVOLATILE MEMORY DEVICE AND ERROR CORRECTION METHODS THEREOF

Номер: US20130326296A1
Автор: CHOI SEONGHYEOG, KONG JUNJIN, SEOL CHANGKYU, SON Hong Rak
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding. 1. A data processing method for processing data read from a nonvolatile memory , the method comprising:receiving first bit data from the nonvolatile memory at a memory controller; andperforming erasure decoding based on the first bit data and second bit data stored in the memory controller,wherein the first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.2. The method as set forth in claim 1 , wherein the first bit data includes a bit indicating the memory cell that is erasure and a bit indicating a memory cell that is not erasure claim 1 , andwherein the bit indicating the memory cell that is erasure and the bit indicating the memory cell that is not erasure have different logical values.3. The data processing method as set forth in claim 2 , wherein the bit indicating the memory cell that is erasure has a value of “0” and the bit indicating the memory cell that is not erasure has a value of “1.”4. The data processing method as set forth in claim 2 , wherein the bit indicating the memory cell that is erasure has a value of “1” and the bit indicating the memory cell that is not erasure has a value of “0.”5. The data processing method as set forth in claim 1 , wherein performing erasure decoding comprises:generating erasure defined data based on the first bit data and the second bit data stored in the memory controller; andgenerating erasure decoded data from the erasure defined data using a decision algorithm ...

Подробнее
Номер записи: 18
26-12-2013 дата публикации

Memory components and controllers that calibrate multiphase synchronous timing references

Номер: US20130346721A1
Автор: Ian Shaeffer, Lei Luo, Scott Best, Thomas Giovannini
Принадлежит: RAMBUS INC

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Подробнее
Номер записи: 19
09-01-2014 дата публикации

Dynamically Calibrated DDR Memory Controller

Номер: US20140013149A1
Автор: Jung Lee, Mahesh Goplan
Принадлежит: Uniquify Inc

A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Подробнее
Номер записи: 20
09-01-2014 дата публикации

SCALABLE PREDICTION FAILURE ANALYSIS FOR MEMORY USED IN MODERN COMPUTERS

Номер: US20140013170A1
Автор: Dang Tu T., Elles Michael C., Hernandez Juan Q., Lowe Dwayne A., Purrington, SR. Challis L.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system. 1. A method for scalable predictive failure analysis , the method comprising:a processor gathering values for one or more characteristics of a memory of a computer system;the processor selecting one or more memory-related parameters, each of the one or more memory-related parameters representing a different characteristic of the one or more characteristics of the memory;the processor calculating a scalable single bit error threshold value using the values for each of the one or more characteristics of the memory represented by the selected one or more memory-related parameters; andthe processor setting the calculated scalable single bit error threshold value for the memory.2. The method of claim 1 , further comprising the processor re-calculating the scalable single bit error threshold value for the memory subsequent to performance of a reparative procedure.3. The method of claim 1 , further comprising causing display of a notice in response to a determination that the calculated scalable single bit error threshold value has been met or exceeded.4. The method of claim 1 , wherein the one or more memory-related parameters include a memory rank parameter.5. The method of claim 1 , wherein the one or more memory-related parameters include a memory size parameter indicative of a capacity of the ...

Подробнее
Номер записи: 21
13-02-2014 дата публикации

Method for optimizing refresh rate for dram

Номер: US20140043927A1
Автор: Ashish Jagmohan, Charles A. Kilmer, Hillery Hunter, Kyu-Hyoun Kim, Luis A. Lastras, Michele M. Franceschini, Moinuddin K. Qureshi
Принадлежит: International Business Machines Corp

A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.

Подробнее
Номер записи: 22
20-02-2014 дата публикации

Cas latency setting circuit and semiconductor memory apparatus including the same

Номер: US20140050034A1
Автор: Seong Jun Lee
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.

Подробнее
Номер записи: 23
06-03-2014 дата публикации

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20140063998A1
Автор: Song In Hwan
Принадлежит: SK HYNIX INC.

A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device. 1. A nonvolatile memory device comprising:a memory cell array comprising a main cell area and a retention flag cell area;a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result; anda control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.2. The nonvolatile memory device according to claim 1 , wherein the retention check unit is configured to compare a difference value claim 1 , obtained by subtracting the number of retention flag cells of which the read operations failed when a second retention read voltage was applied from the number of retention flag cells of which the read operations passed when a first retention read voltage was applied claim 1 , to the reference value.3. The nonvolatile memory device according to claim 2 , wherein when the difference value is larger than the reference value claim 2 , the retention check unit determines the retention state of the retention flag cells as a fail.4. The nonvolatile memory device according to claim 2 , wherein when the difference value is smaller than the reference value claim 2 , the retention check unit determines the retention state of the retention flag cells as ...

Подробнее
Номер записи: 24
13-03-2014 дата публикации

Technique for Determining Performance Characteristics Of Electronic Devices And Systems

Номер: US20140070819A1
Автор: Haw-Jyh Liaw, Mark A. Horowitz, Xingchao Yuan
Принадлежит: RAMBUS INC

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Подробнее
Номер записи: 25
13-03-2014 дата публикации

Methods for operating a memory interface circuit including calibration for cas latency compensation in a plurality of byte lanes

Номер: US20140075146A1
Автор: Jung Lee, Mahesh Goplan
Принадлежит: Uniquify Inc

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Подробнее
Номер записи: 26
13-03-2014 дата публикации

Erased Page Confirmation in Multilevel Memory

Номер: US20140075252A1
Автор: Avila Chris Nga Yee, Dusija Gautam Ashok, Huang Jianmin, Lee Dana, Luo Ting
Принадлежит: SANDISK TECHNOLOGIES INC.

In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition. 1. A method of verifying a program/erase condition of a logical page of a multilevel flash memory comprising:reading one or more flag bits that indicate the program/erase condition of the logical page;in response to determining that the one or more flag bits indicate that the logical page is erased, further verifying the erased condition of the logical page by:performing a read of the logical page;performing Error Correction Coding (ECC) analysis of data read from the logical page;subsequently identifying a number of cells that are not in a state corresponding to the logical page being erased; andcomparing the number of cells that are not in a state corresponding to the logical page being erased with a predetermined number in order to verify the program/erase condition of the logical page.2. The method of wherein the logical page is an upper page and wherein the read of the logical page is performed using two read voltages.3. The method of claim 2 , further comprising claim 2 , subsequent to performing the ECC analysis claim 2 , performing a subsequent read.4. The method of wherein the number of cells that are not in a state corresponding to the logical page being erased is identified from the subsequent read.5. The method of wherein the subsequent read is performed using one of the two read voltages.6. The method of wherein the subsequent read is performed using a voltage that is different to both of the two read voltages.7. The method of wherein the ECC analysis of data read from the logical page indicates a pass result.8. A method of verifying that a logical page in a multi-level ...

Подробнее
Номер записи: 27
20-03-2014 дата публикации

METHOD AND APPARATUS OF MEASURING ERROR CORRECTION DATA FOR MEMORY

Номер: US20140082440A1
Автор: Chang Hsie-Chia, Ho Kin-Chu, Li Hsiang-Pang
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell. 1. A memory operation method , comprising: [ (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or', '(b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation, and, '(i) a first measurement, of whether the memory cell stores either, '(ii) a second measurement, of error correction data of the memory cell, the error correction data indicating relative position within a particular threshold voltage range of the first set or second set, of a stored threshold voltage in the memory cell., 'making a plurality of measurements with one memory sense operation having a first word line sensing voltage on a memory cell, the plurality of measurements including2. The method of claim 1 , wherein the error correction data indicates whether the memory cell has a stored threshold voltage within a sub-range narrower than one of a plurality of threshold voltage ranges claim 1 , different threshold voltage ranges in the plurality of threshold voltage ranges representing different data values storable by the memory cell.3. The method of claim 1 , ...

Подробнее
Номер записи: 28
27-03-2014 дата публикации

Semiconductor memory device having adjustable refresh period, memory system comprising same, and method of operating same

Номер: US20140085999A1
Автор: Uk-Song KANG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.

Подробнее
Номер записи: 29
03-04-2014 дата публикации

Semiconductor device and operating method thereof

Номер: US20140095962A1
Автор: Hong-Sik Kim, Yong-Kee KWON, Young-Suk Moon
Принадлежит: SK hynix Inc

An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information.

Подробнее
Номер записи: 30
07-01-2021 дата публикации

MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM

Номер: US20210004282A1
Автор: Kim Jong Wook
Принадлежит: SK HYNIX INC.

The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of semiconductor memories, and a controller for controlling the memory device to perform a test program operation and a threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation. The controller sets operation performance parameters of each of the semiconductor memories based on monitoring information obtained as a result of the threshold voltage distribution monitoring operation. 1. A memory system comprising:a memory device including a plurality of semiconductor memories; anda controller for controlling the memory device to perform a test program operation and a first threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation,wherein the controller sets operation performance parameters of each of the semiconductor memories based on first monitoring information obtained as a result of the first threshold voltage distribution monitoring operation.2. The memory system of claim 1 , wherein the controller controls the memory device to perform a test erase operation and a second threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories after performing the first threshold voltage distribution monitoring operation during the operation claim 1 , and sets the operation performance parameters based on second monitoring information obtained as a result of the second threshold voltage distribution monitoring operation and the first monitoring information.3. The memory system of claim 2 , wherein each of the plurality of semiconductor memories includes a plurality of memory blocks claim 2 , andeach of the plurality of semiconductor memories programs the plurality of memory blocks to a solid program state during the test program operation.4. The ...

Подробнее
Номер записи: 31
05-01-2017 дата публикации

STRUCTURE AND METHOD FOR ADJUSTING THRESHOLD VOLTAGE OF THE ARRAY OF TRANSISTORS

Номер: US20170004873A1
Автор: Cai Jin, Cheng Kangguo, Dennard Robert H., Khakifirooz Ali, Ning Tak H.
Принадлежит:

A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. 1. A method of adjusting threshold voltage in a memory device comprising:providing a static random access memory (SRAM) device comprising at least two p-type pull up transistors, at least two n-type pull down transistors, a first pass gate transistor and a second pass gate transistor on a substrate, wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors provide a storage cell, and the first and the second pass gate transistors provide an access to the storage cell, and wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors overlie a charge storage element present in a dielectric layer of the substrate;measuring a test electrical property of at least one of the at least two p-type pull up transistors and the at least two n-type pull down transistors; andapplying at least one of a voltage to a bit line (BL) that is electrically connected to source/drain regions of the first pass gate transistor, a voltage to a bit line complement (BLC) that is electrically connected to source/drain regions of the second pass gate transistor, a voltage to a word line (WL) that is electrically connected to gate structures of the first and the second pass gate transistors, a positive supply voltage to at least one of the at least two p-type pull up transistors and a negative supply voltage to at least one of the at least two n-type pull down transistors, and a voltage to the ...

Подробнее
Номер записи: 32
03-01-2019 дата публикации

Memory system

Номер: US20190004706A1
Автор: Shinken Okamoto
Принадлежит: Toshiba Memory Corp

According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.

Подробнее
Номер записи: 33
07-01-2016 дата публикации

REDUCING DISTURBANCES IN MEMORY CELLS

Номер: US20160005495A1
Автор: LASSER MENAHEM
Принадлежит:

Methods for reducing program disturb in non-volatile memories are described. In some embodiments, a non-volatile storage system may acquire a first set of intermediate data to be written to a plurality of memory cells, determine a current set of intermediate data written in the plurality of memory cells, determine whether to invert the first set of intermediate data based on the current set of intermediate data, invert the first set of intermediate data, and write the inverted first set of intermediate data to the plurality of memory cells. The memory cells that are already at the correct state may be skipped over and not programmed, thereby improving programming speed and reducing the cumulative voltage stress applied to unselected memory cells. 1. A method for operating a non-volatile storage system , comprising:acquiring a set of user-level data to be stored in a plurality of memory cells;determining a mapping between physical states of a memory cell and data values represented by the physical states based on a number of memory cells that will change state if the set of user-level data was stored in the plurality of memory cells according to the mapping; andstoring the set of user-level data in the plurality of memory cells according to the mapping.2. The method of claim 1 , wherein:the determining a mapping includes acquiring a first set of intermediate data derived from the set of user-level data and determining the number of memory cells that will change state if the first set of intermediate data was written to the plurality of memory cells.3. The method of claim 2 , wherein:the determining the number of memory cells that will change state if the first set of intermediate data was written to the plurality of memory cells includes reading a current set of intermediate data written in the plurality of memory cells and comparing the current set of intermediate data with the first set of intermediate data.4. The method of claim 2 , wherein:the storing the set of ...

Подробнее
Номер записи: 34
03-01-2019 дата публикации

IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA

Номер: US20190004919A1
Автор: Bains Kuljit S., McCALL James A.
Принадлежит:

A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold. 122-. (canceled)23. A memory device comprising:a register selectively writeable by the memory device with an impedance calibration update flag, to indicate to a memory controller that an impedance calibration update is ready at the memory device; andI/O (input/output) hardware to receive commands from the memory controller when coupled to the memory controller, including an impedance calibration latch signal (ZQCAL LATCH) in response to detection by the memory controller of the impedance calibration update flag being set, to set a new calibration setting in the memory device.24. The memory device of claim 23 , wherein the I/O hardware is to periodically receive a polling request from the memory controller to check the impedance calibration update flag.25. The memory device of claim 23 , wherein the register comprises a Mode Register claim 23 , and the I/O hardware is to periodically receive a command to read the Mode Register to check the impedance calibration update flag.26. The memory device of claim 23 , wherein the I/O hardware is to receive the impedance calibration latch signal with receipt first of an impedance calibration start signal (ZQCAL START).27. The memory device of claim 23 , wherein the memory device is to compute a comparison between a previous impedance calibration setting an updated calibration setting claim 23 , and only set the impedance calibration update flag ...

Подробнее
Номер записи: 35
07-01-2021 дата публикации

METHOD OF OPERATING MEMORY DEVICE

Номер: US20210005275A1
Автор: HWANG Gyu Bum, KIM Hee Young
Принадлежит:

The present technology relates to an electronic device. A method of operating a memory device having improved test performance according to the present technology includes setting a plurality of program biases corresponding to a plurality of memory dies, respectively, based on an operation speed of each of the plurality of memory dies, setting a plurality of offsets corresponding to a plurality of word line groups, respectively, based on an operation speed of each of the plurality of word line groups included in a selected block of a selected memory die among the plurality of memory dies, and detecting a defect of a target block of the selected memory die using a plurality of high voltages and a set low voltage determined based on a program bias corresponding to the selected memory die and the plurality of offsets. 1. A method of operating a memory device , the method comprising:setting a plurality of program biases corresponding to a plurality of memory dies, respectively, based on an operation speed of each of the plurality of memory dies;setting a plurality of offsets corresponding to a plurality of word line groups, respectively, based on an operation speed of each of the plurality of word line groups included in a selected block of a selected memory die among the plurality of memory dies; anddetecting a defect of a target block of the selected memory die using a plurality of high voltages and a set low voltage determined based on a program bias corresponding to the selected memory die and the plurality of offsets.2. The method of claim 1 , wherein the detecting comprises:applying the set low voltage to any one word lines of odd word lines and even word lines included in the target block and applying the plurality of high voltages to the other word lines; anddetermining whether the target block is a bad block or a normal block based on a result of performing a test operation on the target block.3. The method of claim 2 , wherein the applying comprises applying ...

Подробнее
Номер записи: 36
01-01-2015 дата публикации

READ VOLTAGE SETTING METHOD, AND CONTROL CIRCUIT, AND MEMORY STORAGE APPARATUS USING THE SAME

Номер: US20150006983A1
Автор: Cheng Kuo-Yi, HSU Yu-Cheng, Lam Siu-Tung, Lin Wei, Wu Tzung-Lin
Принадлежит: PHISON ELECTRONICS CORP.

A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table. 1. A read voltage setting method for a rewritable non-volatile memory module , wherein the rewritable non-volatile memory module includes a plurality of memory cells , a plurality of word lines and a plurality of bit lines , each of the memory cells electrically connected to one of the word lines and one of the bit lines , each of the memory cells is configured to store a plurality of bit data , each of the plurality of bit data is identified as a first state or a second state based on a voltage , the read voltage setting method comprising:programming data into a plurality of memory cells connected to a first word line among the word lines;reading the data stored in the memory cells of the first word line to obtain a critical voltage distribution corresponding to the memory cells of the first word line; anddetermining a first default read voltage corresponding to the first word line based on a peak of the critical voltage distribution corresponding to the memory cells of the first word line.2. The read voltage setting method according to claim 1 , further ...

Подробнее
Номер записи: 37
20-01-2022 дата публикации

CIRCUIT FOR DETECTING STATE OF ANTI-FUSE STORAGE UNIT AND MEMORY DEVICE THEREOF

Номер: US20220020444A1
Автор: JI Rumin
Принадлежит:

A circuit for detecting a state of an anti-fuse storage unit includes a first current module, a second current module, and a comparator. The first current module has a first end connected to an anti-fuse storage unit array through a first node and a second end connected to a second node. The first current module is configured to output a detection current through the second node. The second current module has a first end connected to a first end of a reference resistor through a third node and a second end connected to a fourth node. A second end of the reference resistor is grounded. The second current module is configured to output a reference current through the fourth node. The comparator has a first input end connected to the second node and a second input end connected to the fourth node. 1. A circuit for detecting a state of an anti-fuse storage unit , comprising:a first current module, having a first end connected to an anti-fuse storage unit array through a first node and a second end connected to a second node, the anti-fuse storage unit array comprising at least one bit line, each connected to the first node and a plurality of anti-fuse storage units, and the first current module being configured to output a detection current through the second node, the detection current being correlated with a resistance of an anti-fuse storage unit to be detected in the anti-fuse storage unit array;a second current module, having a first end connected to a first end of a reference resistor through a third node and a second end connected to a fourth node, a second end of the reference resistor being grounded, and the second current module being configured to output a reference current through the fourth node, the reference current being correlated with a resistance of the reference resistor; anda comparator, having a first input end connected to the second node and a second input end connected to the fourth node for detecting a storage state of the anti-fuse storage ...

Подробнее
Номер записи: 38
08-01-2015 дата публикации

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Номер: US20150009741A1
Автор: Michael C. Stephens, Jr.
Принадлежит: III Holdings 2 LLC

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Подробнее
Номер записи: 39
27-01-2022 дата публикации

Retention Voltage Management for a Volatile Memory

Номер: US20220028479A1
Автор: Abu-Rahma Mohamed H., Barn Amrinder S., Nazar Shahzad
Принадлежит:

An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node. 120-. (canceled)21. An apparatus , comprising:a memory circuit including a plurality of sub-arrays, wherein the memory circuit is configured to implement a retention mode according to stored information indicating voltage sensitivities for the plurality of sub-arrays; and generate, based on the stored information, a first retention voltage level for a first subset of the plurality of sub-arrays; and', 'generate, based on the stored information, a second retention voltage level, higher than the first retention voltage level, for a second subset of the plurality of sub-arrays; and', 'wherein the first and second retention voltage levels are lower than a power supply voltage level of the power supply node, and wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the first retention voltage level., 'a voltage control circuit coupled to a power supply node, wherein during the retention mode for the plurality of sub-arrays, the voltage control circuit is configured to22. The apparatus of claim 21 , wherein the stored information includes test information generated from a test procedure that indicates that one or more voltage sensitive data storage cells are included in the second subset of the plurality of sub- ...

Подробнее
Номер записи: 40
27-01-2022 дата публикации

TSV Check Circuit With Replica Path

Номер: US20220028749A1
Автор: Harutaka Makabe
Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

Подробнее
Номер записи: 41
14-01-2016 дата публикации

MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD

Номер: US20160011970A1
Автор: SAKURADA Kenji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory controller controlling a nonvolatile memory which stores a code word includes a read control unit which controls reading from the nonvolatile memory and a decoding unit which obtains likelihood information of each memory cells based on a reading result from the nonvolatile memory and decodes the code word by using the likelihood information, wherein the decoding unit obtains the likelihood information of a first memory cell based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the memory cells adjacent to the first memory cell. 1. A memory controller controlling a nonvolatile memory configured to include a plurality of bit lines , a plurality of word lines , and a plurality of memory cells to store a code word , each of the plurality of memory cells connected to the bit line and the word line , comprising:a read control unit configured to control the nonvolatile memory to perform reading; anda decoding unit configured to obtain likelihood information of each of the plurality of memory cells based on a reading result output from the nonvolatile memory and decodes the code word by using the likelihood information corresponding to the code word,wherein the decoding unit obtains the likelihood information of a first memory cell which is one of the plurality of memory cells based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the plurality of memory cells adjacent to the first memory cell.2. The memory controller according to claim 1 ,wherein the likelihood information is defined as an LLR, andwherein the decoding unit retains a first LLR table and a second LLR table representing correspondence between the reading results from the memory cells and LLRs, and in the second LLR table, the LLRs are set so that influence of interference from the adjacent memory cells are canceled, andwherein the ...

Подробнее
Номер записи: 42
10-01-2019 дата публикации

TRACKING ERRORS ASSOCIATED WITH MEMORY ACCESS OPERATIONS

Номер: US20190012222A1
Автор: Faraboschi Paolo, Sherlock Derek Alan, Walker Shawn
Принадлежит:

In some examples, a controller includes a counter to track errors associated with a group of memory access operations, and processing logic to detect an error associated with the group of memory access operations, determine whether the detected error causes an error state change of the group of memory access operations, and cause advancing of the counter responsive to determining that the detected error causes the error state change of the group of memory access operations. 1. A controller comprising:a counter to track errors associated with a group of memory access operations; and detect an error associated with the group of memory access operations,', 'determine whether the detected error causes an error state change of the group of memory access operations, and', 'cause advancing of the counter responsive to determining that the detected error causes the error state change of the group of memory access operations., 'processing logic to2. The controller of claim 1 , wherein the error state change comprises a transition from a first error state to a second error state that is different from the first error state.3. The controller of claim 2 , wherein the second error state represents an error condition that is more severe than the first error state.4. The controller of claim 2 , wherein the first error state is a non-error state indicating that no error has been encountered in the group of memory access operations.5. The controller of claim 2 , wherein the second error state indicates one of a device fault claim 2 , a communication link fault claim 2 , and a poisoned flush from a cache memory.6. The controller of claim 1 , wherein the processing logic is to determine whether the detected error causes the error state change of the group of memory access operations by:determining whether the detected error corresponds to a same error state as a current error state of the group of memory access operations, andindicating that the detected error causes the error state ...

Подробнее
Номер записи: 43
10-01-2019 дата публикации

Memory system and method for operating semiconductor memory device

Номер: US20190012227A1
Автор: Min Kyu Lee, Nam Hoon Kim
Принадлежит: SK hynix Inc

A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.

Подробнее
Номер записи: 44
14-01-2016 дата публикации

Semiconductor memory device and memory system

Номер: US20160012916A1
Автор: Takuya Haga, Tokumasa Hara
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes: transistors; NAND strings; a bit line; a source line; and string sets. The transistors are stacked above a semiconductor substrate. In one of the string sets, a first transistor in a first NAND string has a first threshold, and a first transistor in a second NAND string has a second threshold lower than the first threshold.

Подробнее
Номер записи: 45
11-01-2018 дата публикации

MEMORY CONTROLLER

Номер: US20180012644A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and', 'second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and, 'a signaling interface, includingadjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.22. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.23. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times claim 21 , from the memory controller component to the DRAM claim 21 , of the first and second timing signals.24. The memory controller of wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.25. The memory controller of wherein the circuitry to ...

Подробнее
Номер записи: 46
15-01-2015 дата публикации

Direct memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability

Номер: US20150015274A1
Автор: Israel A. Wagner, Noam Jungmann
Принадлежит: International Business Machines Corp

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Подробнее
Номер записи: 47
14-01-2021 дата публикации

Non-volatile semiconductor memory device and method for driving the same

Номер: US20210012854A1
Автор: Daisuke Uchida
Принадлежит: Kioxia Corp

The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.

Подробнее
Номер записи: 48
14-01-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210012856A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range. 1. A system comprising:a memory component; and identify a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range;', 'identify a first set of the plurality of write-to-read delay times at a first end of the first range;', 'determine a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times ...

Подробнее
Номер записи: 49
14-01-2021 дата публикации

Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates

Номер: US20210012857A1
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

Подробнее
Номер записи: 50
03-02-2022 дата публикации

Device for detecting margin of circuit operating at certain speed

Номер: US20220036962A1
Автор: Chen Ying-Yen, KUO Chun-Yi
Принадлежит:

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result. 1. A device for detecting a margin of a circuit operating at a circuit operating speed , the device comprising:a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;a first adjustable delay circuit coupled to the signal generating circuit, and configured to delay the input signal by a first delay amount to generate a delayed input signal;a circuit under test (CUT) coupled to the first adjustable delay circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the delayed input signal, wherein the predetermined operation is based on a predetermined operation timing;a second adjustable delay circuit coupled to the CUT, and configured to delay the to-be-tested signal by a second delay amount in the detection process to generate a delayed to-be-tested signal;a comparison circuit coupled to the second adjustable delay circuit, and ...

Подробнее
Номер записи: 51
18-01-2018 дата публикации

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Номер: US20180019012A1
Автор: JR. Michael C., Stephens
Принадлежит:

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor device , comprising:a memory device from a plurality of memory devices aligned in a vertical stack; anda latency determiner configured to determine a signal latency;wherein the signal latency is configured to be adjusted based on a position of the memory device within the vertical stack.2. The semiconductor device of claim 1 , wherein a programmed latency is stored in a register.3. The semiconductor device of claim 2 , further comprising a latency adjustor configured to adjust the signal latency claim 2 , as appropriate claim 2 , based on the programmed latency.4. The semiconductor device of claim 3 , wherein the latency adjustment is configured to be performed using a data strobe on a common vertical connection.5. The semiconductor device of claim 1 , wherein the latency adjustment is configured to even out latency differences at a memory interface chip or substrate.6. The semiconductor device of claim 1 , wherein a stack position identifier is used to identify the position of the memory device within the vertical stack.7. A semiconductor device claim 1 , comprising:a memory device from a plurality of ...

Подробнее
Номер записи: 52
18-01-2018 дата публикации

SEMICONDUCTOR TEST DEVICE AND SEMICONDUCTOR TEST METHOD

Номер: US20180019023A1
Автор: HAN Min Sik
Принадлежит: SK HYNIX INC.

A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal. 1. A semiconductor test device comprising:a DQ signal receiver configured to receive a first DQ signal through a first DQ pin;a test mode register set signal processor configured to receive a test mode register set signal in response to the first DQ signal, and configured to output a test mode register set pulse signal; anda test mode command generator configured to generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.2. The semiconductor test device according to claim 1 , wherein the DQ signal receiver receives the first DQ signal when the first DQ test mode enable signal is activated.3. The semiconductor test device according to claim 1 , wherein the DQ signal receiver receives a second DQ signal through a second DQ pin different from the first DQ pin.4. The semiconductor test device according to claim 3 , wherein the test mode register set signal processor outputs the test mode register set pulse signal in response to one of the first DQ signal and the second DQ signal.5. The semiconductor test device according to claim 3 , wherein claim 3 , if a second DQ test mode enable signal is activated claim 3 , the DQ signal receiver receives the second DQ signal.6. A semiconductor test device comprising:a DQ signal application circuit configured to apply a first DQ signal through a first DQ pin ...

Подробнее
Номер записи: 53
26-01-2017 дата публикации

Electric fuse current sensing systems and monitoring methods

Номер: US20170023618A1
Автор: Ameer KHAN, Hrushikesh Arun BARVE, Robert Stephen Douglass, Santosh Kumar Sharma
Принадлежит: Cooper Technologies Co

Electrical current sensing and monitoring methods include connecting a compensation circuit across a conductor having a non-linear resistance such as a fuse element. The compensation circuit injects a current or voltage to the conductor that allows the resistance of the conductor to be determined. The current flowing in the conductor can be calculated based on a sensed voltage across the conductor once the resistance of the conductor has been determined.

Подробнее
Номер записи: 54
28-01-2016 дата публикации

Retention logic for non-volatile memory

Номер: US20160027522A1
Автор: Chun-Hsiung Hung, Ken-Hui Chen, Kuen-Long Chang, Nai-Ping Kuo, Yu-Chen Wang
Принадлежит: Macronix International Co Ltd

An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Подробнее
Номер записи: 55
10-02-2022 дата публикации

Operating method of generating enhanced bit line voltage and non-volatile memory device

Номер: US20220044726A1
Автор: Feng Xu, Hongtao Liu, Wenzhe WEI, Ying Huang
Принадлежит: Yangtze Memory Technologies Co Ltd

An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.

Подробнее
Номер записи: 56
10-02-2022 дата публикации

Iterative Read Calibration Enhanced according to Patterns of Shifts in Read Voltages

Номер: US20220044739A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts. 1. A device , comprising:a plurality of memory cells programmable to have threshold voltages in a plurality of voltage regions to represent data stored in the plurality of memory cells;a calibration circuit configured to apply a test voltage to the plurality of memory cells and detect whether each memory cell, among the plurality of memory cells, has a threshold voltage below the test voltage; and determine, based on first test voltages applied in a first voltage region among the plurality of voltage regions, a first shift of a threshold voltage of the plurality of memory cells in the first voltage region;', 'predict, based on the first shift, a second shift of a threshold voltage of the plurality of memory cells in a second voltage region among the plurality of voltage regions; and', 'instruct, based on the second shift, the calibration circuit to apply second test voltages in the second voltage region., 'a logic circuit configured to2. The device of claim 1 , wherein the logic circuit is further configured to:determine, based on test voltages applied to the plurality of memory cells, a plurality of shifts of threshold voltages within a portion of the plurality of voltage regions, the plurality of shifts including the first shift; andidentify a pattern in the plurality of shifts, wherein the second shift is predicted based on the pattern.3. The device of claim 2 , wherein the ...

Подробнее
Номер записи: 57
10-02-2022 дата публикации

OVERVOLTAGE PROTECTION FOR CIRCUITS OF MEMORY DEVICES

Номер: US20220044749A1
Автор: Chu Wei Lu, Pan Dong
Принадлежит:

Methods, systems, and devices for protecting components in memory from overvoltage are described. A memory system may include a voltage regulator coupled with a first voltage source and a reference circuit that is configured to output a reference signal for the voltage regulator. The reference circuit may include a transistor that is used to generate the reference signal. The memory system may also include a protection circuit that is configured to maintain a voltage between a gate of the transistor and a second node of the transistor below an upper voltage limit. The protection circuit may include a comparator that is configured to compare a difference between a voltage of the reference signal output by the reference circuit and a voltage of the first voltage source with a reference voltage. The comparator may control a pull-down circuit coupled with the output of the reference circuit based on the comparison. 1. An apparatus , comprising:a voltage regulator configured to regulate a voltage source; an amplifier coupled with a second voltage source and configured to receive an input signal associated with the reference signal generated by the reference circuit,', 'a biasing component configured to configure the transistor in a saturated state, the biasing component comprising at least one resistor, and', 'a second transistor coupled between the voltage source and the first node of the transistor; and, 'a reference circuit configured to generate a reference signal for the voltage regulator based at least in part on a first voltage of the voltage source, the reference circuit comprising a transistor having a gate, a first node that is coupled with the voltage source, and a second node, wherein the reference circuit comprisesa protection circuit configured to maintain a difference between a second voltage of the gate of the transistor and a third voltage of the second node of the transistor below an upper voltage limit.2. The apparatus of claim 1 , wherein the ...

Подробнее
Номер записи: 58
10-02-2022 дата публикации

Read Model of Memory Cells using Information Generated during Read Operations

Номер: US20220044756A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc. 1. A device , comprising:an integrated circuit die;memory cells formed on the integrated circuit die; and measure signal and noise characteristics of a memory cell group, among the memory cells, to calibrate read voltages of the memory cell group; and', 'generate, based at least in part on the signal and noise characteristics of the memory cell group, a model of changes of the group of memory cells., 'a logic circuit configured to, in response to commands to read data from the memory cells,'}2. The device of claim 1 , comprising:a calibration circuit configured to apply test voltages to the memory cell group to measure the signal and noise characteristics of the memory cell group.3. The device of claim 2 , wherein the logic circuit is configured to generate the model by updating a prior model.4. The device of claim 2 , wherein the logic circuit is configured to generate the model based on a history of the changes reflected at least in part in the signal and noise characteristics of the memory cell group measured during execution of the commands configured to read data from the memory cell groups.5. The device of claim 4 , wherein the logic circuit is ...

Подробнее
Номер записи: 59
10-02-2022 дата публикации

ADAPTING AN ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM

Номер: US20220044757A1
Автор: Lang Murong, XU Zhongguang, Zhou Zhenming
Принадлежит:

A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of the memory sub-system is determined. The value is compared to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied. In response to satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed. 1. A method comprising:determining, by a processing device, a first sequence of operations corresponding to an error recovery process of a memory sub-system;determining a value corresponding to an operating characteristic of the memory sub-system;comparing the value to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied; andin response to satisfying the condition, executing a second sequence of operations corresponding to the error recovery process.2. The method of claim 1 , wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level.3. The method of claim 2 , wherein the read retry threshold voltage level is selected from a set of read retry threshold voltage levels comprising a first read retry threshold voltage level claim 2 , a second read retry threshold voltage level claim 2 , and a third read retry threshold voltage level.4. The method of claim 2 , wherein the read retry rate is determined based on a first count of read retry operations associated with a second read retry threshold voltage level compared to a sum of counts of read retry operations associated with a plurality of read retry threshold voltage levels.5. The method of claim 1 , wherein the first condition is satisfied upon determining the value is greater than the first threshold level.6. The method of claim 1 , wherein the first sequence of operations comprises one or more read retry operations executed ...

Подробнее
Номер записи: 60
10-02-2022 дата публикации

MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY DEVICE, AND AN ERASING METHOD THEREOF

Номер: US20220044758A1
Автор: JUNG Wontaeck, NAM Buil, SON Myoungho
Принадлежит:

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value. 1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller , the fail detecting method comprising:counting, by the memory controller, the number of erases of a word line connected to a pass transistor;issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; anddetermining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.2. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises increasing a source terminal voltage of the pass transistor.3. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises decreasing a gate terminal voltage of the pass transistor.4. The fail detecting method of claim 1 , ...

Подробнее
Номер записи: 61
10-02-2022 дата публикации

IMPRINT MANAGEMENT FOR MEMORY

Номер: US20220044759A1
Автор: Bangalore Lakshman Shashank, Basuta Sukneet Singh, Harms Jonathan D., Strand Jonathan J.
Принадлежит:

Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. 1. (canceled)2. A method , comprising:writing a first set of logic states to a subset of memory cells of a memory array;reading, using a first reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;reading, using a second reference voltage, the subset of memory cells to obtain a third set of logic states that are based at least in part on the first set of logic states;determining a first quantity of errors associated with the second set of logic states and a second quantity of errors associated with the third set of logic states; andperforming a recovery operation on the memory array based at least in part on a difference between the first quantity of errors and the second quantity of errors.3. The method of claim 2 , further comprising:calculating a gradient based at least in part on the first quantity of errors and the second quantity of errors; andcomparing the calculated gradient to an expected gradient, wherein performing the recovery operation is based at least in ...

Подробнее
Номер записи: 62
23-01-2020 дата публикации

USING A STATUS INDICATOR IN A MEMORY SUB-SYSTEM TO DETECT AN EVENT

Номер: US20200027514A1
Автор: Besinga Gary F., Di Francesco Walter, Miller Michael G., Moschiano Violante, Muchherla Kishore Kumar, Padilla Renato C., Singidi Harish R.
Принадлежит:

An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component. 1. A method comprising:receiving an indication of an initialization of power to a memory component;in response to receiving the indication of the initialization, identifying a last written page of a data block of the memory component, wherein the last written page is associated with a status indicator;determining whether the status indicator can be read; andresponsive to determining that the status indicator cannot be read, determining that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.2. The method of claim 1 , further comprising claim 1 , responsive to determining that the programming of the data to the data block of the memory component did not complete based on the prior loss of power to the memory component:recovering a portion of the data programmed to one or more locations of the data block;invalidating the portion of the data at the one or more locations of the data block; andprogramming one or more other locations of the data block with the portion of the data.3. The method of claim 1 , further comprising claim 1 , responsive to determining that the status indicator can be read claim 1 , determining that programming of the memory component did complete and there is a data retention loss.4. The method of claim 3 , further comprising claim 3 , responsive to determining that programming of the memory ...

Подробнее
Номер записи: 63
23-01-2020 дата публикации

Run-Time Memory Device Failure Detection Enhancement

Номер: US20200027520A1
Автор: CHU Sanghoon, JINN Scott, PAVLENKO Yuriy
Принадлежит:

The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a “pass” but a plane pass/fail bit indicates a “fail” then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing. 1. A storage system , comprising:a plurality of memory devices; and when a time interval has elapsed, providing a first check status command, wherein the time interval is associated with an operation for a memory device of the plurality of memory devices;', 'receiving a first signal;', 'determining whether the first signal indicates a ready status;', 'providing a second check status command after the first check status command;', 'receiving a second signal;', 'determining whether the second signal is different from the first signal; and', 'when the second signal is different from the first signal, providing an indication of a failure of the memory device., 'a controller configured to cause2. The storage system of claim 1 , wherein the controller is configured to cause:when the second signal matches the first signal, determining whether an illogical status is detected;when the illogical status is detected, providing the indication of the failure of the memory device; andwhen the illogical status is not detected, providing an indication of a success of the memory device.3. The ...

Подробнее
Номер записи: 64
28-01-2021 дата публикации

MEMORY CONTROLLER

Номер: US20210027825A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: a first timing signal that requires a first time interval to propagate to the memory component;', 'write data to be sampled by the memory component synchronously with respect to the first timing signal;', 'a second timing signal that requires a second time interval to propagate to the DRAM; and', 'a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and, 'transmit circuitry to transmit to a memory componentcontrol circuitry to adjust transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.22. The memory controller component of wherein the second timing signal is a clock signal and the first timing signal is a strobe signal.23. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to render alignment claim 21 , at the memory component claim 21 , between respective rising edges of the first and second timing signals.24. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second ...

Подробнее
Номер записи: 65
04-02-2016 дата публикации

OPERATIONAL VIBRATION COMPENSATION THROUGH MEDIA CACHE MANAGEMENT

Номер: US20160034342A1
Автор: Feldman Timothy Richard, Liu Xiong, Moller Gregory Paul, Toh Michael JC, Wiggins Paul Michael, XIE WENXIANG
Принадлежит:

Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold. 1. A method comprising:partitioning a non-volatile media cache of a data storage device into at least first and second zones having different data recording characteristics;receiving input data to be stored in a non-volatile main memory of the data storage device;measuring an amount of operational vibration associated with the data storage device; andstoring the input data in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold.2. The method of claim 1 , wherein the first zone is configured to have a lower susceptibility to operational vibration and the second zone is configured to have a higher susceptibility to operational vibration.3. The method of claim 2 , wherein the data are stored in the first zone responsive to the measured amount of operational vibration falling below the predetermined operational vibration threshold claim 2 , and wherein the data are stored in the second zone responsive to the measured amount of operational vibration exceeding the predetermined operational threshold.4. The method of claim 1 , wherein the first zone is formed from a rotatable data ...

Подробнее
Номер записи: 66
04-02-2016 дата публикации

Semiconductor memory device having selective ecc function

Номер: US20160034348A1
Автор: Jong-Wook Park, Ki-Won Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device.

Подробнее
Номер записи: 67
04-02-2016 дата публикации

TIMING-DRIFT CALIBRATION

Номер: US20160035437A1
Автор: Bansal Akash, Ellis Wayne F., Frans Yohan U.
Принадлежит:

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. 1. A method of performing timing-drift measurement in a memory device , the method comprising:receiving, by the memory device, a request for a timing-drift indicator from a memory controller;in response to the request, measuring, by the memory device, the timing-drift indicator; andtransmitting the measured timing-drift indicator from the memory device to the memory controller.2. The method of claim 1 , wherein measuring the timing-drift indicator comprises measuring a frequency generated by an oscillator circuit in the memory device.3. The method of claim 2 , wherein prior to measuring the timing-drift indicator claim 2 , the method further comprises:enabling the oscillation of the oscillator circuit; andinitiating the frequency measurement on the oscillator circuit.4. The method of claim 1 , wherein the memory device stores the value of the timing-drift indicator into a register.5. The method of claim 4 , further comprising receiving a request from the memory controller to output the content of the register to the memory controller.6. The method of claim 2 , wherein the request further includes an instruction that specifies a predetermined measurement duration for measuring the frequency on the memory device.7. A memory device claim 2 , comprising:an oscillator circuit to generate a frequency, wherein a change in the frequency is indicative of a timing drift of a clock distribution circuit in the memory device; anda measurement circuit coupled to ...

Подробнее
Номер записи: 68
01-02-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20180033494A1
Автор: Kim Tae Hoon
Принадлежит:

A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line. 1. A method of operating a semiconductor memory device , the method comprising:reading first to kth page data from memory cells coupled to a word line by sequentially applying first to kth test voltages to the word line,wherein a read voltage applied to the word line during a read operation is determined by comparing a number of data bits changed between (k−2)th page data and (k−1)th page data with a number of data bits changed between the (k−1)th page data and the kth page data, andtimes during which data sensed by the first to kth test voltages are evaluated are gradually reduced.2. The method of claim 1 , where the times during which the data sensed by the first to kth test voltages are evaluated are times during which data transferred to latches of page buffers through bit lines coupled to the memory cells are determined.3. The method of claim 1 , wherein times during which the first to kth test voltages are applied are gradually reduced.4. The method of claim 3 , wherein the first to kth test voltages are gradually increased.5. The method of claim 3 , further comprising precharging bit lines coupled to the memory cells once before applying the first to kth test voltages to the word line. This application is a division of the U.S. patent application Ser. No. 15/211,779 filed on Jul. 15, 2016, titled “SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME”, which is a Continuation in Part of U.S. patent application Ser. No. 14/292,299 filed on May 30, 2014, and now U.S. Pat. No. 9,406,402 issued on Aug. 2, 2016, which claims priority to ...

Подробнее
Номер записи: 69
17-02-2022 дата публикации

RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS

Номер: US20220051742A1
Автор: Baby Kiran, Bala Phalguni, M. Ashwin S., Mishra Navin Kumar, Shelke Anirudha, Shetty Sudhir Kumar Katla, Syed Younus
Принадлежит:

In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique. 1. A method for calibrating a receiver of a communication link , the receiver comprising at least a first equalizer to generate a sampler input signal based on a receiver input signal , and a sampler sampling the sampler input signal to generate an output signal , the method comprising:receiving, at the receiver over the communication link, a receiver input signal representing a bit pattern having AC frequency components and DC frequency components;determining, for each of a plurality of reference voltages, a corresponding first equalizer coefficient for the first equalizer and a corresponding plurality of parameters of the sampler input signal that are based on the reference voltage and the corresponding first equalizer coefficient;selecting a reference voltage from among the plurality of reference voltages and the selected reference voltage's corresponding first equalizer coefficient that have the corresponding plurality of parameters of the sampler input signal that satisfy a plurality of optimization criterion; andsetting the selected reference voltage.2. The method of claim 1 , wherein the receiver input signal comprises a bit pattern having alternating current frequency components and direct ...

Подробнее
Номер записи: 70
17-02-2022 дата публикации

PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICE

Номер: US20220051747A1
Автор: KIM Boh-Chang
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed. 1. A method comprising:receiving a first program command to write first data to a memory device;programming the first data in a plurality of memory cells in the memory device using a first voltage level available in the plurality of memory cells;receiving a second program command to write second data to the memory device; andprogramming the second data in the plurality of memory cells programmed with the first data, using a second voltage level available in the plurality of memory cells,wherein each of the plurality of memory cells is programmed with two bits of data from the first data, and each of the plurality of memory cells is programmed with two bits of data from the second data, andthe second voltage level is different from the first voltage level.2. The method of claim 1 , further comprising writing a flag bit indicating completion of a first program operation into the plurality of memory cells.3. The method of claim 1 , wherein a threshold voltage associated with the first voltage level is less than a threshold voltage associated with the second voltage level.4. The method of claim 1 , wherein the memory device is a three-dimensional (3D) NAND flash memory device.5. The method of claim 1 , wherein the first voltage level has a first pulse width claim 1 , and the second voltage level has a second pulse width that is different from the first pulse width. ...

Подробнее
Номер записи: 71
04-02-2021 дата публикации

MEMORY CONTROLLER WITH INTEGRATED TEST CIRCUITRY

Номер: US20210033665A1
Автор: Ware Frederick A.
Принадлежит:

A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. 1. (canceled)2. A memory system comprising:a test-signal generator to issue a data test signal; a test-signal wire coupled to the test-signal generator to convey the data test signal;', 'a write-data transmit interface to output a write data signal, the write-data transmit interface including at least one gating transistor to gate the write data signal responsive to the data test signal; and', 'a first data contact pad to communicate the gated write data signal away from the memory controller IC; and, 'a memory controller integrated-circuit (IC) device having 'a second data contact pad bonded to the first data contact pad to receive the gated write data signal from the memory controller IC.', 'a memory IC device having3. The memory system of claim 2 , the write-data transmit interface further comprising a sequential element having a clock terminal claim 2 , coupled to a clock gate claim 2 , and a data output terminal claim 2 , the sequential element to transmit the write data signal from the data output terminal responsive to a gated clock signal.4. The memory system of claim 3 , the write-data transmit interface further comprising a data gate coupled to the data output terminal claim 3 , the data gate to gate the write data signal ...

Подробнее
Номер записи: 72
30-01-2020 дата публикации

HOST APPARATUS AND EXTENSION DEVICE

Номер: US20200035289A1
Автор: FUJIMOTO Akihisa
Принадлежит: Toshiba Memory Corporation

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Подробнее
Номер записи: 73
30-01-2020 дата публикации

Non-volatile memory with countermeasure for select gate disturb

Номер: US20200035312A1
Автор: Deepanshu Dutta, Dengtao Zhao
Принадлежит: SanDisk Technologies LLC

Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

Подробнее
Номер записи: 74
04-02-2021 дата публикации

IDENTIFICATION OF SUSCEPTIBILITY TO INDUCED CHARGE LEAKAGE

Номер: US20210035654A1
Автор: COJOCAR Lucian, Saroiu Stefan, Wolman Alastair
Принадлежит: Microsoft Technology Licensing, LLC

Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage. 1. A system comprising:at least one processor; and accessing, for a memory unit, a physical adjacency map;', 'determining, based on the physical adjacency map, a first set of adjacent memory rows for a first target row of the memory unit;', 'activating, using a susceptibility test sequence, each memory row of the first set of adjacent memory rows, wherein the susceptibility test sequence does not comprise at least one of a load instruction or a store instruction;', 'evaluating the first target row to determine if one or more bits of the first target row changed; and', 'based on determining that one or more bits of the first target row did not change, generating an indication that the memory unit is not susceptible to induced charge leakage., 'memory storing instructions that, when executed by the at least one processor, causes the system to perform a set of operations, the set of operations comprising2. The system of claim 1 , wherein the susceptibility test sequence comprises a cache line flush instruction for each memory row of the first set of adjacent memory rows.3. The ...

Подробнее
Номер записи: 75
12-02-2015 дата публикации

Addressable test circuit and test method for key parameters of transistors

Номер: US20150042372A1
Автор: Weiwei Pan, Yongjun Zheng
Принадлежит: Semitronix Corp

Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor's I dsat , I off can be measured accurately.

Подробнее
Номер записи: 76
08-02-2018 дата публикации

METHOD AND APPARATUS FOR REAL-TIME BLANK PAGE DETECTION IN DATA TRANSMISSION

Номер: US20180039432A9
Автор: FAN CHONGBIN, Wang Yong, Xie Jun
Принадлежит:

A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result. 1. A device for reading data from a first memory to a second memory , the device comprising:a memory controller for reading at least one page of data from the first memory;a buffer connected to the memory controller for buffering a portion of the at least one page of data read from the first memory;a blank page pre-detection unit, connected to the buffer, for generating a pre-detection result that indicates whether the at least one page is a blank page based on a pre-determined part of the data in the at least one page;a data processing unit, connected to the buffer and the blank page pre-detection unit, for processing all of the data in the at least one page to identify a type of the page; anda control unit, connected to the memory controller, the blank page pre-detection unit, and the data processing unit, for signaling the memory controller to read the at least one page of data from the first memory and enabling the data processing unit based on the pre-detection result.2. The device of claim 1 , wherein the pre-determined part is a metadata block of the at least one page claim 1 , wherein the metadata block includes an occupied part for storing information of the at least one page claim 1 , and a non-occupied part.3. The device of claim 2 , wherein the blank page pre-detection unit generates the pre-detection ...

Подробнее
Номер записи: 77
12-02-2015 дата публикации

Memory module

Номер: US20150043290A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Подробнее
Номер записи: 78
08-02-2018 дата публикации

Semiconductor devices and semiconductor systems

Номер: US20180040354A1
Автор: Dae Suk Kim, Hong Jung Kim, Jae Il Kim
Принадлежит: SK hynix Inc

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.

Подробнее
Номер записи: 79
08-02-2018 дата публикации

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS

Номер: US20180040355A1
Автор: KIM Dae Suk, KIM Hong Jung, Kim Jae Il
Принадлежит: SK HYNIX INC.

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. The first semiconductor device may be configured to output a strobe signal toggled and data after an initialization operation. The second semiconductor device may be configured to start the initialization operation if the commands have a first combination and stores internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination. 1. A semiconductor system comprising:a first semiconductor device configured to output commands and addresses and configured to output a strobe signal toggled and data after an initialization operation; anda second semiconductor device configured to start the initialization operation if the commands have a first combination and configured to store internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination.2. The semiconductor system of claim 1 , wherein the set period is set to be a write latency period for an alignment operation of the data.3. The semiconductor system of claim 1 , wherein the second semiconductor device stores the internal data corresponding to the data in synchronization with the strobe signal after the set period.4. The semiconductor system of claim 1 , wherein the second semiconductor device outputs the internal data as the data during the initialization operation.5. The semiconductor system of claim 1 , wherein the first semiconductor device is configured to calculate a write recovery time while the initialization operation is performed.6. The semiconductor system of claim 5 , wherein the write recovery time is set to a time period from a point of time that a last data of the data is outputted from the first semiconductor device till a point of time that a pre-charge operation is performed.7. ...

Подробнее
Номер записи: 80
08-02-2018 дата публикации

MULTIPLE TEMPERATURE TESTING OF NON-VOLATILE MEMORY DATA RETENTION TIME

Номер: US20180040384A1
Автор: Lazarov Kalin V., Petersen Michael D., ROHRER Timothy D.
Принадлежит:

The data retention time of a non-volatile memory array containing multiple non-volatile memory cells, each cell having a floating gate, may be tested. The method may include: baking the non-volatile memory array at a first temperature for a first duration and at a second temperature that is materially different than the first temperature for a second duration; testing the non-volatile memory array before and after each baking; and deciding whether to use or sell the tested non-volatile memory array based on results of the testing before and after each baking. 1. A method of testing the data retention time of a non-volatile memory array containing multiple non-volatile memory cells , each cell having a floating gate , comprising in the order recited:charging the floating gate of each memory cell;measuring the charge on the floating gate of each memory cell a first time;storing information indicative of the first-time measured charge on the floating gate of each memory cell;baking the non-volatile memory array at a first temperature for a first duration;measuring the charge on the floating gate of each memory cell a second time;storing information indicative of the second-time measured charge on the floating gate of each memory cell;baking the non-volatile memory array at a second temperature that is materially different than the first temperature for a second duration;measuring the charge on the floating gate of each memory cell a third time; andestimating the data retention time of each memory cell based on the first-time, second-time, and third-time measured charge on the floating gate of each memory cell.2. The method of further comprising claim 1 , between the baking at the first and the second temperature claim 1 , in the order recited:charging the floating gate of each memory cell a second time;measuring the charge on the floating gate of each memory cell after the second-time charging; andstoring information indicative of the measured charge on the floating ...

Подробнее
Номер записи: 81
12-02-2015 дата публикации

Data Storage Device and Method for Restricting Access Thereof

Номер: US20150046762A1
Автор: Chien Jieh-Hsin, Pao Yi-Hua
Принадлежит:

A data storage device including a flash memory, a temperature sensor and a controller. The flash memory has a plurality of blocks, and each of the blocks has a plurality of pages. The temperature sensor detects surrounding ambient temperature and to produce a temperature parameter accordingly. The controller is arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on. The controller reads the temperature sensor to obtain a first temperature parameter in the first maintenance procedure and determines a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition includes the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished. 1. A data storage device , comprising:a flash memory, having a plurality of blocks, and each of the blocks has a plurality of pages;a temperature sensor, arranged to detect surrounding ambient temperature and produce temperature parameters accordingly; anda controller, arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on, wherein the controller is further arranged to read the temperature sensor to obtain a first temperature parameter in the first maintenance procedure, and determine a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition comprises the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished.2. The data storage device as claimed in claim 1 , wherein in the first maintenance procedure claim 1 , the controller is further arranged to perform a first ...

Подробнее
Номер записи: 82
24-02-2022 дата публикации

Timing delay control circuits and electronic devices including the timing delay control circuits

Номер: US20220059143A1
Автор: Woongrae Kim
Принадлежит: SK hynix Inc

An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.

Подробнее
Номер записи: 83
24-02-2022 дата публикации

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME

Номер: US20220059148A1
Автор: HA KYUNG-SOO, KIM Si-hong, Kim Young-Hun, Oh Tae-Young
Принадлежит:

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode. 1. A memory controller configured to control a command bus training (CBT) operation of a memory device , the memory controller comprising:a clock terminal configured to transmit a clock signal;a data clock terminal configured to transmit a data clock signal;a first data terminal configured to transmit a first data signal;a plurality of command/address terminals configured to transmit a command bus training (CBT) pattern during the CBT operation, the CBT pattern comprising a plurality of command/address signals; anda plurality of second data terminals configured to transmit second data signals, the plurality of second data terminals being in one-to-one correspondence with the command/address signals during the CBT operation,wherein the memory controller is configured to:send a first logic level of the first data signal to the memory device at one of rising edge and falling edge of the data clock signal and make the memory device enter a command bus training (CBT) mode;send logic levels of the CBT pattern to the memory device at one of rising edge and falling edge of the clock signal and receive the CBT pattern output by the memory ...

Подробнее
Номер записи: 84
07-02-2019 дата публикации

METHOD AND SYSTEM FOR COMPENSATING FOR FLOATING GATE-TO-FLOATING GATE (FG-FG) INTERFERENCE IN FLASH MEMORY CELL READ OPERATIONS

Номер: US20190043565A1
Автор: Goda Akira, Miccoli Carmine
Принадлежит: Intel Corporation

Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption. 1. A memory controller , comprising: receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline;', 'perform a read operation on a second memory cell of the flash memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request; and', 'read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter if the first memory cell is in a disturbed condition; and, 'memory controller logic toerror-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level.2. The memory controller of ...

Подробнее
Номер записи: 85
06-02-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200043566A1
Автор: CHI Sung Soo, SEO Jae Hwan
Принадлежит: SK HYNIX INC.

A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2(n is an integer of n≥2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2bit-line precharge voltages to corresponding bit lines in units of 2successive bit-lines within the same cell array. 1. A semiconductor device comprising:{'sup': 'n', 'a voltage generation circuit configured to output 2(where n is an integer of n≥2) bit-line precharge voltages through different power-supply lines, based on a mode control signal; and'}{'sup': n', 'n, 'a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2bit-line precharge voltages to corresponding bit lines in units of 2successive bit-lines within a same cell array.'}2. The semiconductor device according to claim 1 , wherein the voltage generation circuit includes:a first precharge voltage generator configured to output any one of first to third voltages having different magnitudes as a bit-line precharge voltage, upon receiving a first mode control signal;a second precharge voltage generator configured to output any one of the first to third voltages as a second bit-line precharge voltage, upon receiving a second mode control signal;a third precharge voltage generator configured to output any one of the first to third voltages as a third bit-line precharge voltage, upon receiving a third mode control signal; anda fourth precharge voltage generator configured to output any one of the first to third voltages as a fourth bit-line precharge voltage, upon receiving a fourth mode control signal;3. The semiconductor device according to claim 2 , wherein each of the first to fourth ...

Подробнее
Номер записи: 86
18-02-2021 дата публикации

DATA STORAGE APPARATUS, AND INTERNAL VOLTAGE TRIMMING CIRCUIT AND TRIMMING METHOD THEREFOR

Номер: US20210050065A1
Автор: Moon Young Jin, YUK Young Sub
Принадлежит: SK HYNIX INC.

A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code is by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage. 1. A data storage apparatus comprising:storage; anda controller comprising an internal voltage trimming circuit and configured to control the storage in response to a request from a host, an integral circuit configured to sample a difference between a test voltage output by a device under test (DUT) and a reference voltage and configured to generate an integral signal by integrating a sampled signal, the integral circuit comprising an offset cancellation unit configured to cancel an offset from the sampled signal;', 'a comparison circuit configured to generate a comparison signal by comparing the integral signal with the reference voltage;', 'a code generation circuit configured to receive an initial trimming code and to generate preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal; and', 'a code average signal generation circuit configured to generate a final trimming code by averaging the preliminary trimming codes for a given time and to ...

Подробнее
Номер записи: 87
18-02-2016 дата публикации

THRESHOLD VOLTAGE EXPANSION

Номер: US20160049209A1
Автор: Belgal Hanmant P., Damle Prashant S., KRIPANIDHI Arjun, LY-GAGNON Dany-Sebastien, PANDEY Abhinav, Pangal Kiran, Rangan Sanjay, URIBE Sebastian T.
Принадлежит:

Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed. 1. An apparatus comprising:a plurality of memory cells, wherein individual memory cells of the plurality of memory cells are configured to store one or more bits of data; identify, based on a current detected in response to application of a read voltage, a state of a bit of data in a memory cell of the individual memory cells; and', 'apply, prior to the application of the read voltage, a dummy-read voltage to the memory cell., 'a bias logic coupled with the individual memory cells, the bias logic to2. The apparatus of claim 1 , wherein the individual memory cells are in a set state or a reset state claim 1 , and the bias logic is further configured to apply a voltage bias pulse to a memory cell in the reset state.3. The apparatus of claim 2 , wherein the bias logic is further configured to apply the voltage bias pulse to the memory cell immediately following performance of a memory reset operation on the memory cell.4. The apparatus of claim 2 , wherein the state of the bit of data in the memory cell is based on whether the read voltage is above or below a threshold voltage of the memory cell.5. The apparatus of claim 2 , wherein a time parameter or an amplitude parameter of the voltage bias pulse is based on a desired threshold voltage of the memory cell in the reset state.6. The apparatus of claim 2 , wherein the set state corresponds to a value of the bit of data equal to a first logical value claim 2 , and the reset state corresponds ...

Подробнее
Номер записи: 88
15-02-2018 дата публикации

MEMORY SYSTEM WITH A WEIGHTED READ RETRY TABLE

Номер: US20180046527A1
Автор: Guo Zelei, RAGHU DEEPAK, Reusswig Philip, Yip Chris Nga Yee
Принадлежит: SanDisk Technologies LLC

A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering. 1. A storage device comprising:a read retry table comprising a plurality of read retry cases, wherein each read retry case comprises a set of read thresholds; selecting one of the read retry cases from the read retry table based on a weight associated with each of the read retry cases, wherein the weight is based on one or more weighting factors;', 'shifting read thresholds according to the selected read retry case; and', 'updating the read retry table depending on whether the shifted read thresholds are correct., 'read retry circuitry configured to initiate a read retry operation comprising2. The storage device of wherein the weighting factors comprise a frequency of decode success claim 1 , a bit error rate (BER) claim 1 , or a reliability mechanism.3. The storage device of wherein the frequency of decode success comprises a frequency that a particular read retry case and its shifted read thresholds correct an error.4. The storage device of further comprising:a memory comprising memory blocks; anda controller coupled with the memory that is configured to access the read retry circuitry and initiate the read retry operation.5. The storage device of wherein the updating the read retry table comprises reordering the read retry cases according to priority.6. The storage device of wherein the priority corresponds to the weight for each of the read retry cases.7. The storage device of wherein the read thresholds comprise a voltage at which charge distributions are ...

Подробнее
Номер записи: 89
15-02-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR

Номер: US20180047457A1
Автор: ISHII Yuichiro, Saito Yoshikazu, Tanaka Shinji, Tsukude Masaki
Принадлежит:

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells. 1. A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form , the test method comprising the steps of:writing first data into a plurality of memory cells;while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a hit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data;and reading the data written into the memory cells.2. A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form , the memory cells each including a first port and a second port that are capable of reading or writing data , the test method comprising the steps of:writing first data into a memory cell selected from among a plurality of memory cells;while a plurality of first word lines disposed at the first port of the columns of the memory cells are deselected and a second word line disposed with respect to a selected memory cell that is disposed at the second port of the columns of the memory cells are selected, driving the low-potential side bit line of a first bit line pair in a selected column, which is among a plurality of first bit line pairs disposed at the first port of ...

Подробнее
Номер записи: 90
15-02-2018 дата публикации

CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION

Номер: US20180048310A1
Автор: Hardee Kim C.
Принадлежит:

Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance. 1. A calibration circuit for setting an on-chip impedance of an integrated circuit to match a target impedance comprising:a first pull-up circuit connected in series with the target impedance between a positive power supply voltage and a reference power supply voltage, the first pull-up circuit being a ratioed pull-up circuit sized to be K/(1−K) times a size of a pull-up circuit unit, K being a number between 0 and 1, other than 0.5, and the positive power supply voltage being a positive power supply voltage for input-output circuits of the integrated circuit;a first comparator configured to compare a voltage at a first common node between the first pull-up circuit and the target impedance to a reference voltage and to generate an output signal to drive the first pull-up circuit so that the voltage at the first common node equals the reference voltage, the reference voltage being K times the positive power supply voltage other than one-half the positive power supply voltage, wherein the first pull-up circuit has an impedance being set equal to (1−K)/K times the target impedance;a second pull-up circuit connected in series with a pull-down circuit between the positive power supply voltage and the ...

Подробнее
Номер записи: 91
15-02-2018 дата публикации

PAGE HEALTH PREDICTION USING PRODUCT CODES DECODER IN NAND FLASH STORAGE

Номер: US20180048434A1
Автор: Bhatia Aman, Kumar Naveen, Lin Yi-Min
Принадлежит:

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor. 1. An operating method of a memory system comprising: conducting NAND read and generating NAND data;', 'decoding in accordance with the NAND data and generating decoder information;', 'predicting a BER in accordance with at least the decoder information; and', 'evaluating the predicted BER and generating evaluation result., 'performing a decoding iteration includes'}2. The method of wherein the conducting NAND read includes conducting NAND read according to NAND read settings.3. The method of wherein the generating NAND data includes generating codewords encoded using error control coding scheme.4. The method of wherein the decoding in accordance with the NAND data includes hard decoding and soft decoding in accordance with the NAND data.5. The method of wherein the generating decoder information includes generating decoder information of a product code.6. The method of wherein the predicting the BER in accordance with at least the decoder information includes predicting the BER before completion of the decoding iteration.7. The method of wherein the generating evaluation result includes categorizing the evaluation result as at least a level of good.8. The method of further comprising: completing the decoding iteration if the evaluation result is at a level of good.9. The method of further comprising: adjusting NAND read setting according to at least the predicted BER claim 1 , and repeating the decoding ...

Подробнее
Номер записи: 92
03-03-2022 дата публикации

Method and system for adjusting memory, and semiconductor device

Номер: US20220068321A1
Автор: Jie Liu, Jun He, Shu-Liang NING, Zhan Ying
Принадлежит: Changxin Memory Technologies Inc

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Подробнее
Номер записи: 93
03-03-2022 дата публикации

Level Dependent Error Correction Code Protection in Multi-Level Non-Volatile Memory

Номер: US20220068423A1
Автор: Sharma Sahil, Singidi Harish, Yang Nian
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

Подробнее
Номер записи: 94
25-02-2016 дата публикации

Semiconductor device including temperature ranges having temperature thresholds and method of determining therefor

Номер: US20160054374A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

Подробнее
Номер записи: 95
25-02-2016 дата публикации

Testing and setting performance parameters in a semiconductor device and method therefor

Номер: US20160054379A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

Подробнее
Номер записи: 96
25-02-2016 дата публикации

DIRECT MEMORY BASED RING OSCILLATOR (DMRO) FOR ON-CHIP EVALUATION OF SRAM CELL DELAY AND STABILITY

Номер: US20160055921A1
Автор: Jungmann Noam, Wagner Israel A.
Принадлежит:

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an unmodified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures. 1. A method of measuring the delay from wordline input to bitline output of a staticrandom access memory (SRAM) cell, said method comprising:providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell;guaranteeing an initial state of each delay stage circuit, wherein an incorrect state is corrected in a subsequent memory cycle;generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input;generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input; andmeasuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell.2. The method according to claim 1 , further comprising precharging the bitline to an appropriate charge level in response to the falling edge of said wordline.3. The method according to claim 1 , further comprising monitoring stability of said SRAM cell by setting said SRAM cell to a predefined ...

Подробнее
Номер записи: 97
22-02-2018 дата публикации

Memory system and operating method for the same

Номер: US20180053565A1
Автор: Jee-Yul Kim
Принадлежит: SK hynix Inc

A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.

Подробнее
Номер записи: 98
22-02-2018 дата публикации

SEMICONDUCTOR DEVICES, SEMICONDUCTOR SYSTEMS, AND METHODS THEREOF

Номер: US20180053567A1
Автор: Kim Jae Il
Принадлежит: SK HYNIX INC.

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device outputs address signals. The first semiconductor device may receive or output data. The second semiconductor device may perform an impedance calibration operation and outputs pull-up codes and pull-down codes generated by the impedance calibration operation. The third semiconductor device may output internal data selected by the address signals as the data or store the data during a write operation or a read operation. 1. A semiconductor system comprising:a first semiconductor device configured to output chip selection signals, command signals, address signals and a clock signal and configured to receive or output data;a second semiconductor device configured to perform an impedance calibration operation and to output pull-up codes and pull-down codes generated by the impedance calibration operation, based on the chip selection signals, if a combination of the command signals is a predetermined combination; anda third semiconductor device configured to output internal data of a memory cell selected by the address signals as the data or configured to store the data in the memory cell selected by the address signals as the internal data, according to the command signals based on the chip selection signals and the command signals during a write operation or a read operation,wherein drivability of the internal data and the data is adjusted by the pull-up codes and the pull-down codes.2. The system of claim 1 ,wherein the third semiconductor device is configured to perform the impedance calibration operation and to output the pull-up codes and the pull-down codes generated by the impedance calibration operation,wherein the second semiconductor device is configured to output the internal data selected by the address signals as the data during the read operation or is ...

Подробнее
Номер записи: 99
23-02-2017 дата публикации

READ VOLTAGE OFFSET

Номер: US20170053714A1
Автор: Guy Adam C., Muchherla Kishore K., Ratnam Sampath K.
Принадлежит:

Apparatuses, methods, and data structures that can be utilized to provide a read voltage offset are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device; read a particular data segment using a read voltage offset determined based on: the write temperature data from the data structure and corresponding to the particular data segment; and read temperature data corresponding to the particular data segment. 1. An apparatus , comprising:a memory device; and access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device;', 'read a particular data segment using a read voltage offset determined based on:', 'the write temperature data from the data structure and corresponding to the particular data segment; and', 'read temperature data corresponding to the particular data segment., 'a controller coupled to the memory device and configured to2. The apparatus of claim 1 , wherein a memory device storing the data structure is volatile memory.3. The apparatus of claim 1 , wherein the memory device storing the data structure is non-volatile memory.4. The apparatus of claim 3 , wherein the non-volatile memory includes the write temperature data programmed as metadata.5. The apparatus of claim 1 , wherein the write temperature data corresponds to a range of temperatures.6. The apparatus of claim 1 , wherein the data structure is configured to include additional write temperature data respectively corresponding to additional data segments.7. The apparatus of claim 1 , wherein the write temperature data comprises from two to eight bits.8. The apparatus of claim 1 , wherein the controller is further configured to access a temperature indicator.9. A method for providing a read voltage offset claim 1 , comprising: ...

Подробнее
Номер записи: 100