СПОСОБ ОБРАЗОВАНИЯ ПЕЧАТАЮЩЕЙ ГОЛОВКИ ДЛЯ ТЕРМОГРАФИЧЕСКОЙ СТРУЙНОЙ ПЕЧАТИ, ПЕЧАТАЮЩАЯ ГОЛОВКА ДЛЯ ТЕРМОГРАФИЧЕСКОЙ СТРУЙНОЙ ПЕЧАТИ И ПОЛУПРОВОДНИКОВАЯ ПЛАСТИНА

Предусмотрен способ образования печатающей головки для термографической струйной печати, включающий по меньшей мере следующие этапы: обеспечение полупроводниковой пластины, содержащей интегральную электронную схему и секцию для образования термического приводного элемента, при этом интегральная схема содержит по меньшей мере: теплоизоляционный слой, образуемый поверх подложки; и первый металлический слой, образуемый поверх теплоизоляционного слоя; при этом первый металлический слой проходит в секцию для образования термического приводного элемента; и травление секции для образования термического приводного элемента до первого металлического слоя, так что первый металлический слой действует как слой, препятствующий травлению. Кроме того, предусмотрены печатающая головка для термографической струйной печати, образованная при помощи способа согласно настоящему изобретению, и полупроводниковая пластина для образования печатающих головок для термографической струйной печати при помощи способа ...

Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching

Prodn. of a semiconductor with IGFET structure and a polycrystalline Si gate electrode involves applying a first insulating layer of Si dioxide and then a polycrystalline Si layer to the Si substrate surface; removing the first insulating layer from the polycrystalline Si and structurising; and then applying a second insulating film and a conductive film to the remaining parts of the insulating and overlying polycrystalline Si films. Ion bombardment is used for the removal of the required parts of the first insulating film. The use of ion etching ensures a vertical edge, with no under-etching at the edges of the gate electrode. Ion etching is used, pref. using ions with a kinetic energy of over 1 keV and a dosage of 1011-1013 ions/cm2, followed by wet chemical etching.

Verfahren zur Herstellung integrierter Schaltkreise mit Isolationsgebieten, die gleichmäßige Stufenhöhen haben

Es werden Verfahren zur Herstellung integrierter Schaltkreise bereitgestellt. In einer Ausführungsform umfasst ein Verfahren zur Herstellung eines integrierten Schaltkreises ein Bereitstellen eines Halbleitersubstrats, das ein Isolationsgebiet zwischen einem ersten Bauelementgebiet und einem zweiten Bauelementgebiet umfasst. Das Isolationsgebiet umfasst einen ersten Teil neben dem ersten Bauelementgebiet und einen zweiten Teil neben dem zweiten Bauelementgebiet. Das Verfahren umfasst ein selektives Ätzen des zweiten Teils des Isolationsgebiets auf eine zweite Höhe. In dem Verfahren wird über dem ersten Bauelementgebiet und dem zweiten Bauelementgebiet eine Isolationsschicht gebildet. Das Verfahren umfasst außerdem ein selektives Ätzen der Isolationsschicht über dem ersten Bauelementgebiet und dem ersten Teil des Isolationsgebiets. Der erste Teil des Isolationsgebiets wird auf eine erste Höhe geätzt, die im Wesentlichen gleich der zweiten Höhe ist.

Struktur und Verfahren zur Hartmaskenentfernung auf einem SOI-Substrat ohne Anwendung eines CMP-Verfahrens

Ein Hartmaskenmaterial wird ohne Anwendung eines Verfahrens des chemisch-mechanischen Polierens (CMP) von einem SOI-Substrat entfernt. Ein Sperrmaterial wird nach einem Verfahren des Tiefgraben-Reaktivionenätzens (RIE) auf einem Hartmaskenmaterial abgeschieden. Das Sperrmaterial auf dem Hartmaskenmaterial wird entfernt. Es wird ein selektives Nassätzverfahren angewendet, um das Hartmaskenmaterial zu entfernen. Die Tiefe der Grabenaussparung wird wirksam gesteuert.

A METHOD OF MAKING A COMPONENT FOR A MICROELECTRONIC CIRCUIT AND A SEMICONDUCTOR DEVICE AND AN OPTICAL WAVEGUIDE MADE BY THAT METHOD

VERFAHREN ZUR ELIMINIERUNG VON ÄTZSPERREHINTERSCHNEIDUNGEN

VERFAHREN ZUM AETZEN VON SILICIUMNITRID

Selektives ätzen von Silikat

Fein-Strukturierungsverfahren und Verfahren zum Herstellen von Halbleitervorrichtungen mit denselben

Ein Fein-Strukturierungsverfahren weist ein Bilden einer Maskenschicht (45, 145) mit einer unteren und einer oberen Maskenschicht auf einer unterliegenden Schicht (20, 120), ein Bilden eines Paars von Opferstrukturen (50, 150) auf der Maskenschicht (45, 145), ein Bilden eines Verbindungsabstandshalters (64, 164) zwischen den Opferstrukturen (50, 150) und ersten Abstandshaltern (62, 162), welche voneinander mit dem Paar von Opferstrukturen (50, 150) dazwischenliegend angeordnet beabstandet sind und ein Bedecken von Seitenoberflächen der Opferstrukturen (50, 150), ein Ätzen der oberen Maskenschicht unter Verwendung der ersten Abstandshalter (62, 162) und des Verbindungsabstandshalters (64, 164) als einer Ätzmaske, um obere Maskenstrukturen zu bilden, ein Bilden von zweiten Abstandshaltern (72, 172), um Seitenoberflächen der oberen Maskenstrukturen zu bedecken, ein Ätzen der unteren Maskenschicht unter Verwendung der zweiten Abstandshalter (72, 172) als einer Ätzmaske, um untere Maskenstrukturen ...

VERFAHREN ZUM HERSTELLEN VON HALBLEITERBAUELEMENTEN

Verfahren zum Herstellen von Teilbereichen in planaren Halbleiteranordnungen,die mittels dielektrischen Materials gegeneinander sowie gegen die restlichen Bereiche des Halbleiterkoerpers isoliert sind

Composite substrate for semiconductor devices comprising a diamond layer

A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 um or less; a second layer having a thickness of no less than 0.5 pm and formed of a material having a lower thermal expansion coefficient than the first layer of single crystal material and/or is formed of a material which has a higher fracture strength than that of the first layer of single crystal material; and a third layer forming a handling wafer on which the first and second layers are disposed, wherein the substrate wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100; growing a first polycrystalline CVD diamond layer on the first layer of single crystal material using a chemical vapour deposition technique to form a composite comprising the substrate wafer bonded to ...

Improvements in or relating to Etching Processes for Semiconductor Devices

... 1,194,730. Etching. INTERNATIONAL BUSINESS MACHINES CORP. 3 Nov., 1967 [28 Dec., 1966], No. 50053/67. Heading B6J. [Also in Divisions C7 and H1] An oxide coated surface of a semi-conductor is etched with a solution comprising monobasic ammonium phosphate and ammonium fluoride. A preferred etchant comprises an aqueous solution of 2-10% by weight of monobasic ammonium phosphate and 10-35% by weight of ammonium fluoride. The etchant is stated to be suitable for the removal of oxides from the surfaces of silicon and germanium semiconductor devices. In an example, Figs. 1A- 1E, silicon dioxide film 2 on silicon substrate 1 is selectively etched through a photoresist mask with buffered hydrofluoric acid to form apertures 3. Phosphorus pentoxide is diffused through the apertures to establish source and drain diffusion regions 4 and 5 simultaneously forming phosphosilicate glass film overcoat 6, Fig. 1B, which is selectively etched through a photoresist mask 8 with buffered hydrofluoric acid to ...

SEMICONDUCTOR PLANARIZATION PROCESS

IMPROVEMENTS IN ETCHING SILICON DIOXIDE BY DIRECT PHOTOLYSIS

... 1,220,367. Etching. GENERAL ELECTRIC CO. 28 May, 1968 [29 May, 1967], No. 25429/68. Addition to 1,220,365. Heading B6J. A silicon dioxide surface is etched by contacting with a solid film of an organic polymeric material containing trityldifluoroamine or fluoranil to form an interface therebetween and exposing the interface to activating radiation in the presence of moisture. The polymeric material may be polystyrene, alcohol soluble butyrate resin or hydroxylated polymeric resin. The interface may be exposed through a metal mask.

Process for wet etching a semiconductor wafer

Wet etching a silicon dioxide layer from both sides of a rotating horizontally orientated silicon substrate is disclosed. The entire dioxide layer upon the top side of the substrate is removed and the bottom side layer is removed only a short distance (a) inside the rim. The etching medium comprises at least one carboxylic acid added to a hydrofluoric acid or a combination of hydrofluoric acid and ammonium fluoride. The carboxylic acid may be present as an anhydride or a salt, especially an ammonium salt. The solution may also be diluted up to 90% water. The process allows the edge of the silicon dioxide layer remaining upon the bottom of the wafer to be smooth (4') rather than jagged (4).

Methods and apparatus for forming a film on a substrate

A Method of Etching a Film of Silicon Nitride

... 1,170,678. Etching. INTERNATIONAL BUSINESS MACHINES CORP. 13 Dec., 1967 [13 Jan., 1967], No. 56949/67. Heading B6J. [Also in Division H1] A film of silicon nitride is selectively etched with hydrofluoric acid through a mask of molybdenum, tungsten or silicon. The silicon mask may be formed as a secondary part of a silicon nitride deposition and the molybdenum and tungsten masks may be deposited by spluttering, plasma discharge or vapour deposition. In a preferred embodiment a film of silicon nitride is applied to a silicon substrate, which film is covered with a film of molybdenum or tungsten and then with a phaloresist. The resist is exposed and developed and the molybdenum or tungsten etched with a solution of potassium ferricyanide and potssium hydroxide The exposed silicon nitride film may then be etched with concentrated hydrafluoric acid.

ETCHING GLASS

... 1,242,839. Etching. STANDARD TELEPHONES & CABLES Ltd. 12 May, 1970, No. 22845/70. Heading B6J. [Also in Division C1] Phosphorus glass is etched through an aluminium mask. The etchant may be buffered hydrofluoric acid solution. The mask may be formed by etching away portions of an aluminium layer provided on the glass. The aluminium layer may be masked with photoresist. The glass may be provided as a layer on a silicon slice intended for use as a semi-conductor device. Those portions of the aluminium layer which remain after etching of the glass are removed with phosphonic acid or sodium hydroxide.

A semiconductor device and methods of manufacture thereof

METHOD OF ETCHING MULTILAYERED ARTICLES

... 1527106 Etching TELETYPE CORP 9 Oct 1975 [10 Oct 1974] 41356/75 Heading B6J A layer of SiO 2 is etched with buffered HF, e.g. HF + NH 4 F, the underlying aluminium layer being passivated by the HF. The passivated layer is then treated with a substantially HF-free solution of NH 4 F to prevent deterioration thereof. Etching of the SiO 2 may be through apertures in a photoresist mask.

Vertical memory cell with mechanical structural reinforcement

RECESSED OXIDE N-CHANNEL FETS

... 1499848 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [28 June 1974] 21855/75 Heading H1K A semi-conductor device comprises a P-type semi-conductor substrate 11, Fig. ID, having an N-channel FET 20-23, Fig. 2, formed therein and isolated by a recessed region 18 which has an interface with the channel region, there being a region 19 containing additional P-type dopant extending from the interface into the channel region to increase its threshold. The device is formed by providing a P-type <100>substrate having a surface protection layer 12, an oxidation barrier 13, an ion-implantation blocking layer 14, and a pattern-defining photoresist (15), Fig. 1A (not shown), exposing and developing the photoresist (15) to provide a pattern on the blocking layer 14, etching the blocking layer 14, the barrier 13 and the protecting layer 12 through the pattern, etching the substrate 11 in the exposed areas with an anisotropic etchant to obtain canted sidewalls 33, ion inplanting ...

Procedure for separating a layer from corrodable silicon nitride on a firm carrier body

On-site manufacture of ultra-high-purity hydrofluoric acid f or semiconductor processing

Selective etching of silicon nitride by means of a wet chemical process

Method and apparatus for etching coated substrates

ETCHING COMPLETION INDICATION

BIPOLAR TRANSISTORS AND METHOD OF MANUFACTURING THE SAME

METHOD FOR SELECTIVE ETCHING OF TITANIUMDIOXIDE

A method of selectively etching a titanium oxide layer with a view to the formation of a mask for the localization of the anodic oxidation of an underlying metallic layer. The method is characterized in that the material comprising the said titanium oxide layer is dipped in a solution of hydrogen peroxide and ammonia. Application to the formation of contacts on semiconductor devices.

BIPOLAR TRANSISTORS AND METHOD OF MANUFACTURING THE SAME

In a transistor, around border line of the surface of a base region formed on a semiconductor the surface is formed a base electrode having polycrystalline silicon. An island shape emitter region is formed in the base region and on electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.

ETCHANT FOR SILICON DIOXIDE FILMS DISPOSED ATOP SILICON OR METALLIC SILICIDES

An etchant comprising a solution of hydrogen fluoride dissolved in an organic solvent such as glycerine. The solution is substantially free of unbound water and ammonium fluoride. The etchant is particularly suitable for removing silicon dioxide disposed atop a metallic silicide formed in a silicon semiconductor where the silicon may be exposed.

SOLUBLE SURFACTANT ADDITIVES FOR AMMONIUM FLUORIDE/HYDROFLUORIC ACID OXIDE ETCHANT SOLUTIONS

SOLUBLE SURFACTANT ADDITIVES FOR AMMONIUM FLUORIDE/HYDROFLUORIC ACID OXIDE ETCHANT SOLUTIONS Silicon trioxide etching solutions with soluble surfact additives are provided. The improved silicon dioxide etchants are produced by adding soluble perfluronated surfactant additives to standard oxide etchants in the manufacture of integrated circuits. These surfactant additives are unique because they remain dissolved in the oxide etchant (ammonium fluoride/hydrofluoric acid mixture) even after 0.2 micron filtration. In addition, the filtered solutions retain their surface active properties and are low in metallic ion impurities. The surfactant additives provide etchant solutions with lower surface tensions, which improves substrate wetting and yields better etchant performance. The surfactant does not leave residues or adversely affect etchant profiles.

PATTERN SILICON NITRIDE MASKING LAYERS

METHOD OF MAKING SEMICONDUCTOR DEVICE AND APPARATUS THEREFOR

ETCHANT FOR SILICON DIOXIDE FILMS DISPOSED ATOP SILICON OR METALLIC SILICIDES

THICK OXIDE PROCESS FOR IMPROVING METAL DEPOSITION AND STABILITY OF SEMICONDUCTOR DEVICES

PATTERN SILICON NITRIDE MASKING LAYERS

METHOD AND APPARATUS FOR NEUTRAL BEAM PROCESSING BASED ON GAS CLUSTER ION BEAM TECHNOLOGY

An apparatus, method and products thereof provide an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials.

Verfahren zum Eindiffundieren von Dotierungsstoff aus der Gasphase

VERFAHREN ZUM HERSTELLEN VON STRUKTURIERTEN SILICIUMNITRIDSCHICHTEN.

Verfahren zum Ätzen geschichteter Materialien unter Verhinderung des Überätzens

Verfahren zum Abscheiden einer Schutzschicht aus Siliciumnitrid an der Oberfläche eines erhitzten Halbleiterkristalls

Verfahren zum Herstellen von ätzbarem Siliciumnitrid in Form dünner Schichten

Wafer processing method

Manufacturing method of two-dimensional material structure and two-dimensional material device

Method for mfg. semiconductor device

Semiconductor device and method for forming pattern for semiconductor device

The ALD caulking the spacer mask self-aligning multiple patterning processing flow

High aspect ratio vertical interconnect access (VIA) interconnections in magnetic random access memory (MRAM) bit cells

Cleaner composition and preparation of thin substrate

Semiconductor device

Trench isolated capacitor

Compsns. for cleaning organic and plasma etched residues for semiconductor devices

With wettable stripping in the middle layer of the semiconductor structure of patterning

Semiconductor device and a trench field plate field effect transistor having a field dielectric comprising a thermally grown portion and a deposited portion

Method of manufacturing semiconductor device

PRODUCTION OF SILICON NITRIDE MASKING LAYERSS BY ETCHING

Semiconductor devices by etching

ETCHING SILICON DIOXIDE BY DIRECT PHOTOLYSIS

ETCHANT FOR SELECTIVELY ETCHING PATTERNS IN THIN SILICON DIOXIDE LAYERS AND METHOD OF PREPARING SUCH AN ETCHANT

PROCEDURE CORROSION TEST CHEMICAL Of OBJECTS SEVERAL LAYERS

METHOD FOR REALIZATION OF DEVICES SEMICONDUCTORS

METHOD FOR MANUFACTURING A TRANSISTOR

METHOD FOR REDUCING THE CONDUCTION OF THE SIDE WALLS IN THE TABLES OF FIELD-EFFECT TRANSISTORS HAS OXIDE EMBEDS AND DEVICE WHILE RESULTING

Process for the preparation of contestable silicon nitride chemically in the form of thin layers

TRANSISTORS BIPOLAR AND MANUFACTORING PROCESS

SOLUTION DE GRAVURE DES OUVERTURES DE CONTACTS EXTERNES POUR DISPOSITIFS SEMI-CONDUCTEURS

L'invention concerne une solution de gravure chimique destinée à attaquer le diélectrique de protection des métallisations de raccordement entre circuits internes d'un dispositif semi-conducteur, afin de mettre à nu les plots de raccordement aux connexions externes du dispositif, sans corroder lesdits plots. La composition de la solution suivant l'invention est la suivante : (pour 100 g): 1 à 5 g d'acide fluorhydrique; 10 à 40 g de fluorure d'ammonium; 40 à 80 g d'eau pure; 10 à 30 g d'une substance répondant à la formule chimique: ...

A method for carrying out a protective coating, in particular on the surface of a semiconductor crystal

FABRICATION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP

PROCEEDED OF REDUCTION OF COMPOSES IN LAYER ON A SUBSTRATE AND ITS APPLICATION TO THE MANUFACTURE OF SEMICONDUCTOR STRUCTURE HAS FIELD EFFECT

PROCESS OF ENGRAVING Of a MATERIAL IN THE PRESENCE OF SOLID PARTICLES.

METHOD OF FORMING SPACERS OF A GATE OF A TRANSISTOR

PROCESS IMPROVES OF REALIZATION OF DISTINCT Of INSULATION IN a SEMICONDUCTOR SUBSTRATE ON INSULATOR

PRODUCTION OF SILICON NITRIDE MASKING LAYERSS BY ETCHING

Production of semiconductor structure with cavities in silicon substrate, comprises atomic implantation across buried insulating layer

L'invention concerne un procédé de réalisation d'une structure semiconductrice de type SOI, comportant une couche superficielle de silicium, une couche enterrée d'isolant et un substrat, ledit procédé comportant les étapes suivantes : - une étape d'implantation atomique à travers au moins une partie de la couche d'isolant, - une étape de gravure de la couche d'isolant dans au moins une partie de cette couche traversée par l'implantation atomique.

METHOD FOR FORMING PATTERNS IN A THIN ANTIREFLECTIVE LAYER

L'invention se rapporte au domaine de la fabrication en couches minces des dispositifs électroniques et/ou de MEMS et concerne un procédé amélioré permettant de former un motif dans une couche mince anti-réfléchissante SiARC, comprenant le dopage par implantation de cette couche SiARC recouverte par un motif de résine à travers une couche de protection du motif de résine, puis gravure des zones dopées de la couche SiARC.

PROCESS Of INSULATION OF the JUST INTERCONNECTIONS OF CIRCUITS, AND INTEGRATED CIRCUIT USING THIS PROCESS

PROCESS Of AUTOALIGNEMENT OF the ELEMENTS Of a SEMICONDUCTOR DEVICE AND DEVICE CARRIED out FOLLOWING THIS PROCESS

Etching method

PROCESSES FOR THE LOCALIZED AND DEEP DIFFUSION OF GALLIUM INTO SILICON

SILICON NITRIDE LAYERS

METHOD FOR MAKING A TRANSISTOR WITH DOPING LOCATES TO PLUMB THE GRID

Method of manufacturing pattern and method of manufacturing a semiconductor capacitor using the same

금속 게이트 라인 단부에서 Ｔ 형상을 가지는 반도체 디바이스를 제조하는 디바이스 및 방법

... 반도체 디바이스에서 금속 게이트 구조를 제조하는 방법이 개시되어 있다. 방법은 더미 폴리 게이트를 제거하는 것, 반도체 디바이스에서 T 형상 공동을 형성하기 위하여 건식 에칭 프로세스 및 습식 측방향 에칭 프로세스를 이용하여 IL 산화물 및 STI를 제거하는 것, 및 금속 게이트 라인 단부에서 T 형상 구조를 형성하기 위하여 T 형상 공동에서 금속 게이트 물질을 퇴적하는 것을 포함한다. 더미 폴리 게이트의 제거를 포함하였던 프로세스로부터 제조된 반도체 디바이스가 개시되어 있다. 반도체 디바이스는 OD 핀과, OD 핀의 섹션 위에서 그리고 OD 핀의 측면 섹션에 인접하게 제조된 금속 게이트를 포함한다. 금속 게이트는 금속 게이트 라인 단부에서 T 형상 구조를 가진다. T 형상 구조는 T 형상 공동을 형성하기 위하여 건식 및 습식 측방향 에칭 프로세스를 이용하여 IL 산화물 및 STI를 제거함으로써 형성되었다.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT CHIP HAVING A CRACK STOP STRUCTURE

ETCHING SOLUTION AND METHOD OF ETCHING SEMICONDUCTOR DEVICE

PURPOSE: An etching solution and a method of etching a semiconductor device using the same are to efficiently remove a damaged silicon layer, thereby controlling an etching selecting rate of a silicon and a silicon oxide film. CONSTITUTION: An etching solution is consisting of a first solution of NH4F, HF, and pure water, and a second solution of H2O2 and pure water. The first solution is a mixing solution of the pure water containing NH4F and HF of 18%, NH4F and HF being mixed in a ratio of 7:1. H2O2 and the pure water are mixed in a ratio of 3:7. A method of etching a semiconductor device comprises the steps of: forming a first oxide film(102) on a semiconductor substrate(100); a second oxide film(104) on the first oxide film; forming a trench on the first and the second oxide films; if a damaged silicon layer is formed under the trench due to an ion of high energy, etching the damaged silicon layer using the etching solution; and forming a third oxide film on a surface of the trench, ...

METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE CAPABLE OF PROTECTING ATTACK BY WET CLEANING

METHOD AND APPARATUS FOR MANUFACTURING MEMORY DEVICE HAVING 3 DIMENSIONAL STRUCTURE

SEMICONDUCTOR DEVICE, A METHOD OF MANUFACTURING THE SAME, AND A SEMICONDUCTOR DEVICE PROTECTIVE CIRCUIT

Method for processing semiconductor substrate

SUBSTRATE TREATING APPARATUS

CLEANING SOLUTION FOR SELECTIVELY REMOVING A LAYER AND METHOD FOR SELECTIVELY REMOVING THE LAYER IN SILICIDE PROCESS USING THE CLEANING SOLUTION

FINE-PROCESSING AGENT AND FINE-PROCESSING METHOD

Semiconductor wet etchant and method of forming interconnection structure using the same

A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH 4 + ) and a chlorine ion (Cl − ).

Composition for Wet Etching of Silicon Dioxide

Provided is an etching composition for electively removing silicon dioxide at a high etch rate, more particularly, a composition for wet etching of silicon dioxide, including 1 to 40 wt % of hydrogen fluoride (HF); 5 to 40 wt % of ammonium hydrogen fluoride (NH 4 HF 2 ); and water, and further including a surfactant to improve selectivity of the silicon dioxide and a silicon nitride film. Since the composition for wet etching of silicon dioxide has the high etch selectivity of the silicon dioxide to the silicon nitride film, it is useful for selectively removing silicon dioxide.

Semiconductor device manufacturing method

In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O( 1 D 2 ) radicals produced using a processing gas that contains oxygen are dominant.

Method and apparatus for etching the silicon oxide layer of a semiconductor substrate

An aspect of the invention is to provide a method and apparatus for etching the silicon oxide layer of a semiconductor substrate, whereby the processing time for cleaning or rinsing, as well as any undesired aftereffects by residual hydrofluoric acid, may be reduced, in using the dry etching method involving the use of dense carbon dioxide that contains hydrofluoric acid, during the manufacturing process of a micro-electronic device.

Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ uv cure

Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

Method and apparatus for fabricating or altering microstructures using local chemical alterations

A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.

Method for obtaining extreme selectivity of metal nitrides and metal oxides

Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H 2 F 2 . The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Semiconductor structure with suppressed sti dishing effect at resistor region

A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.

Substrate processing method and substrate processing apparatus

A substrate processing method includes a removing step of removing unwanted matter from a substrate and a vaporizing step performed in parallel to the removing step. In the removing step, an HF vapor that contains hydrogen fluoride and a solvent vapor that contains a solvent capable of dissolving water and having a lower boiling point than water is supplied onto the substrate to etch and remove the unwanted matter. In the vaporizing step, the solvent on the substrate is vaporized.

Chemical dispersion method and device

A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided.

METHOD OF FORMING WIDE TRENCHES USING A SACRIFICIAL SILICON SLAB

A method of forming an encapsulated wide trench includes providing a silicon on oxide insulator (SOI) wafer, defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer, defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer, forming a first sacrificial oxide portion in the first trench, forming a second sacrificial oxide portion in the second trench, forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion, and etching the first sacrificial oxide portion and the second sacrificial oxide portion. 1. A method of forming an encapsulated wide trench comprising:providing a silicon on oxide insulator (SOI) wafer;defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer;defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer;forming a first sacrificial oxide portion in the first trench;forming a second sacrificial oxide portion in the second trench;forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion; andetching the first sacrificial oxide portion and the second sacrificial oxide portion.2. The method of claim 1 , wherein forming a first sacrificial oxide portion comprises:oxidizing at least a portion of the first sacrificial slab.3. The method of claim 2 , further comprising:forming an oxide layer on an upper surface of the first sacrificial oxide portion.4. The method of claim 1 , further comprising:etching the first sacrificial slab to expose opposing sides of the first sacrificial oxide portion and the second sacrificial oxide portion;forming a third sacrificial oxide portion between the exposed opposing sides of the first sacrificial oxide portion and the second sacrificial oxide portion; andetching the third sacrificial oxide ...

Semiconductor device and method of manufacturing the same

Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS

Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure. 1. A method for forming a semiconductor structure , the method comprising the steps of:forming a first structure overlying a semiconductor substrate, wherein the first structure has a first height;forming a second structure overlying the semiconductor substrate, wherein the second structure has a second height and wherein the second height is greater than the first height;depositing a first sidewall spacer-forming material overlying the first structure and the second structure;depositing a second sidewall spacer-forming material overlying the first sidewall spacer-forming material, wherein the second sidewall spacer-forming material has an etch rate when subjected to an etchant that is different from an etch rate of the first sidewall spacer-forming material when subjected to the same etchant;forming a composite spacer about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material;at least substantially removing the second sidewall spacer-forming material from the first structure; andat least substantially removing the first sidewall spacer-forming material from the first ...

Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof

A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

Method and composition for removing resist, etch residue, and copper oxide from substrates having copper, metal hardmask and low-k dielectric material

A semiconductor processing composition and method for removing photoresist, polymeric materials, etching residues and copper oxide from a substrate comprising copper, low-k dielectric material and TiN, TiNxOy or W wherein the composition includes water, at least one halide anion selected from Cl − or Br − , and, where the metal hard mask comprises only TiN or TiNxOy, optionally at least one hydroxide source.

Method of producing insulation trenches in a semiconductor on insulator substrate

A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Interconnection structures in a semiconductor device and methods of manufacturing the same

Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Apparatus and method for controlling silicon nitride etching tank

A method and apparatus for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.

Processing a sacrificial material during manufacture of a microfabricated product

A method for processing a sacrificial material of an intermediate microfabricated product includes forming a hydrogen-containing carbon layer on a surface of a base structure and releasing hydrogen from the hydrogen-containing carbon layer to obtain a hydrogen-released (i.e., densified) carbon layer with low shrink. The method further includes forming a structural layer on at least a portion of a surface of the hydrogen-released carbon layer, and oxidizing the hydrogen-released (densified) carbon layer to release the structural layer. In this manner, a cavity is formed between the base structure and the structural layer. The ashing of the hydrogen-released carbon layer leaves substantially no residues within the cavity of the intermediate or final microfabricated product. Further embodiments provide a method for manufacturing a microfabricated product, to an intermediate microfabricated product, and to a microfabrication equipment.

Compositions of Matter, and Methods of Removing Silicon Dioxide

Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX 3 and PQ 3 , where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Semiconductor device and method for fabricating the same

A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film.

FIN FIELD EFFECT TRANSISTOR WITH FIELD PLATING

An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region. 1. An integrated circuit (IC) having a fin field effect transistor (FinFET) , comprising: a source region;', 'a drain region;', 'a drift region adjacent the drain region; and', 'a field plating oxide layer on a first side, a second side, and a third side of the drift region., 'a substrate with a fin extending from a surface of the substrate, the fin including2. The IC of claim 1 , wherein:the fin comprises a body region adjacent the drift region; anda gate oxide layer on a first side, a second side, and a third side of the body region.3. The IC of claim 2 , wherein the field plating oxide layer is thicker than the gate oxide layer.4. The IC of claim 2 , wherein the gate oxide layer engages the field plating oxide layer.5. The IC of claim 2 , further comprising a conductive layer on the gate oxide layer on a first side claim 2 , a second side claim 2 , and a third side of the body region.6. The IC of claim 5 , wherein a portion of the conductive layer is on the field plating oxide layer and at least a portion of the first side claim 5 , at least a portion of the second side claim 5 , and at least a portion of the third side of the drift region.7. The IC of claim 1 , wherein the FinFET further comprises a reduced surface field layer disposed at a base of the fin.8. A method for fabricating an integrated circuit including a fin field effect transistor (FinFET) claim 1 , comprising:forming a fin on a semiconductor surface of a silicon substrate;forming a dielectric layer on the fin;etching the dielectric layer to form a field plating oxide layer on a first side, a second side, and a ...

THIN-FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A method of depositing a thin film having a desired etching characteristic while improving a loss amount and loss uniformity of a lower film includes, on the semiconductor substrate and the pattern structure: a first operation of depositing a portion of the thin film by repeating a first cycle comprising (a1) a source gas supply operation, (b1) a reactant gas supply operation, and (c1) a plasma supply operation for a certain number of times; a second operation of depositing a remaining portion of the thin film by repeating a second cycle comprising (a2) a source gas supply operation, (b2) a reactant gas supply operation, and (c2) a plasma supply operation for a certain number of times after the first operation, wherein a supply time of the source gas supply operation (a1) is longer than a supply time of the source gas supply operation (a2). 1. A method of depositing a thin film on a pattern structure of a semiconductor substrate , the method comprising , on the semiconductor substrate and the pattern structure:a first operation of depositing a portion of the thin film by repeating a first cycle comprising a source gas supply operation (a1), a reactant gas supply operation (b1), and a plasma supply operation (c1) for a certain number of times; anda second operation of depositing a remaining portion of the thin film by repeating a second cycle comprising a source gas supply operation (a2), a reactant gas supply operation (b2), and a plasma supply operation (c2) for a certain number of times after the first operation,wherein a supply time of the source gas supply operation (a1) is longer than a supply time of the source gas supply operation (a2).2. The method of claim 1 , wherein the supply time of the source gas supply operation (a1) is two to five times the supply time of the source gas supply operation (a2).3. The method of claim 1 , wherein the supply time of the source gas supply operation (a1) is 0.2 seconds to 1 second.4. The method of claim 1 , wherein the ...

PATTERN-FORMING METHOD

A pattern-forming method comprises: forming a resist underlayer film on an upper face side of a substrate; forming a silicon-containing film on an upper face side of the resist underlayer film; and removing the silicon-containing film with a basic aqueous solution. The pattern-forming method does not include, after the forming of the silicon-containing film and before the removing of the silicon-containing film, treating the silicon-containing film with a treatment liquid comprising an acid or a fluorine compound. The silicon-containing film is preferably formed a hydrolytic condensation product of a composition containing a compound represented by formula (1) in an amount of no less than 60 mol % with respect to total silicon compounds. X represents a halogen atom or —OR, and Rrepresents a monovalent organic group. 1. A pattern-forming method comprising:forming a resist underlayer film on an upper face side of a substrate;forming a silicon-containing film on an upper face side of the resist underlayer film;forming a resist pattern on an upper face side of the silicon-containing film;etching the silicon-containing film using the resist pattern as a mask; andremoving the silicon-containing film with a basic aqueous solution,wherein the pattern-forming method does not comprise, after the forming of the silicon-containing film and before the removing of the silicon-containing film, treating the silicon-containing film with a treatment liquid comprising an acid or a fluorine compound.2. The pattern-forming method according to claim 1 , wherein the silicon-containing film is formed from a hydrolytic condensation product of a composition comprising a compound represented by formula (1) in an amount of no less than 60 mol % with respect to total silicon compounds claim 1 ,{'br': None, 'sub': '4', 'SiX\u2003\u2003(1)'}{'sup': 2', '2, 'wherein, in the formula (1), X represents a halogen atom or —OR, wherein Rrepresents a monovalent organic group.'}3. The pattern-forming ...

Lcd panel and method for forming the same

The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Biosensor device and method for manufacturing thereof and method for detecting biological molecules

A biosensor device includes a substrate plate, a metal conductive layer, a plurality of working electrodes and an insulating layer. The metal conductive layer is disposed over the substrate plate and has an upper surface. The working electrodes are disposed over the upper surface of the metal conductive layer, wherein each of the working electrodes has a top surface and each of the top surfaces is higher than the upper surface of the metal conductive layer. The insulating layer covers the metal conductive layer and surrounds the working electrodes, wherein an upper surface of the insulating layer is located between the top surfaces and the upper surface of the metal conductive layer such that the working electrodes protrude beyond the upper surface of the insulating layer. A method for manufacturing the biosensor device and a method for detecting biological molecules by using the biosensor device are also provided herein.

SELECTIVE DEPOSITION OF SILICON OXIDE FILMS

Embodiments described herein generally provide a method for filling features formed on a substrate. In one embodiment, a method for selectively forming a silicon oxide layer on a substrate is provided. The method includes selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature. 1. A method for selectively forming a silicon oxide layer on a substrate , comprising:selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by exposing the patterned feature to tetraethyl orthosilicate (TEOS) and ozone.2. The method of claim 1 , further comprising:after the selectively depositing a silicon oxide layer within the patterned feature, annealing the selectively deposited silicon oxide layer.3. The method of claim 2 , further comprising:after the annealing the selectively deposited silicon oxide layer, wet etching the silicon oxide layer.4. The method of claim 1 , wherein the tetraethyl orthosilicate (TEOS) flows into a 300 mm substrate processing chamber at a rate between 400 mg/minute and 2 g/minute.5. The method of claim 4 , wherein the ozone flows into the 300 mm substrate ...

Substrate processing method and recording medium

Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.

CVD METAL SEED LAYER

The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off. 1. A method of manufacturing an integrated circuit device , comprising:forming a dielectric layer over a semiconductor substrate, wherein the dielectric layer comprises an opening being arranged within the dielectric layer;depositing a metal seed layer on surfaces of the opening using a chemical vapor deposition (CVD) process;forming a capping layer on the metal seed layer; andusing a plating bath to remove the capping layer and plate a metal layer onto the metal seed layer to fill the opening.2. The method of claim 1 , wherein the metal seed layer and the metal layer are made of cobalt (Co) and the metal seed layer is formed to abut the dielectric layer.3. The method of claim 1 , wherein metal seed layer comprises cobalt and the metal layer comprises copper.4. The method of claim 3 , further comprising:depositing a barrier layer between the metal seed layer and the dielectric layer prior to depositing the metal seed layer.5. The method of claim 1 , wherein depositing the metal seed layer and forming the capping layer comprises:depositing a metal seed precursor on surfaces of the opening using the chemical vapor deposition (CVD) process;exposing the metal seed precursor to an ambient environment at room temperature to form a passivated film as the capping layer using an uppermost portion of the ...

Transparent display apparatus

A display apparatus includes a pixel having a first area emitting light and a second area transmitting light. A pixel circuit unit is in the first area and includes a thin film transistor. An inorganic insulation layer is in the second area. A first insulation layer covers the pixel circuit unit in the first area, and has an opening exposing the inorganic insulation layer in the second area. A first electrode is on the first insulation layer in the first area. The first electrode is electrically connected to the pixel circuit unit. A second insulation layer covers edges of the first electrode and is outside the opening formed in the first insulation layer. A second electrode is in the first area. An intermediate layer, including an emissive layer, is between the first electrode and the second electrode.

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width. 1. A fin field effect transistor (FinFET) device structure , comprising:a fin structure formed over a substrate; anda gate structure traversing over the fin structure, wherein the gate structure comprises a gate electrode layer which comprises an upper portion above the fin structure and a lower portion below the fin structure, the upper portion has a top surface with a first width, and the lower portion has a bottom surface with a second width, and the first width is greater than the second width.2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein a virtual interface is formed between the upper portion and the lower portion claim 1 , and the virtual interface has a third width claim 1 , and the third width is smaller than or equal to the second width.3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the virtual interface is substantially level with a top surface of the fin structure.4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the upper portion of the gate electrode layer has vertical sidewalls.5. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the lower portion of the gate electrode layer has a trapezoidal shape.6. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the upper portion of the gate electrode ...

ETCHING METHOD, ETCHING APPARATUS AND STORAGE MEDIUM

A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times. 1. A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by a pattern layer and stopping the etching before a base layer of the silicon oxide film is etched , the method comprising:heating the target substrate in a vacuum atmosphere;intermittently supplying, as an etching gas, at least one of a first processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a second processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit in multiple cycles.2. The method of claim 1 , wherein a time period of said supplying the etching gas to the target substrate in each cycle is about 0.5 sec to 5 sec.3. The method of claim 1 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.4. The method of claim 2 , wherein a time period of stopping said supplying the etching gas to the target substrate in each cycle is about 5 sec to 20 sec.5. The method of claim 1 , wherein the compound of nitrogen claim 1 , hydrogen and fluorine is either NHF or NHFHF.6. The method of claim 2 , wherein the compound of nitrogen claim 2 , hydrogen and fluorine is either NHF or NHFHF.7. The method of claim 3 , wherein the compound of nitrogen claim 3 , hydrogen and fluorine is either NHF or NHFHF.8. The method of claim ...

Fin Spacer Protected Source and Drain Regions in FinFETs

A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin. 1. A method comprising:etching a semiconductor substrate to form a first plurality of recesses;filling the first plurality of recesses to form Shallow Trench Isolation (STI) regions, wherein a portion of the semiconductor substrate between the STI regions forms a semiconductor strip, wherein edges of the semiconductor strip contact sidewalls of the STI regions;replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is formed over the first semiconductor layer, wherein the first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer;recessing the STI regions, wherein a portion of the semiconductor strip with edges exposed by the recessed STI regions forms a semiconductor fin;forming a gate stack over a middle portion of the semiconductor fin;forming gate spacers on sidewalls of the gate stack;forming fin spacers on sidewalls of an end portion of the semiconductor fin;recessing the end portion of the ...

PROTECTION OF SEMICONDUCTOR-OXIDE-CONTAINING GATE DIELECTRIC DURING REPLACEMENT GATE FORMATION

Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors. 1. A semiconductor structure comprising:a semiconductor fin located on a substrate;a shallow trench isolation layer in contact with sidewalls of a lower portion of said semiconductor fin;a semiconductor-oxide-containing gate dielectric in contact with sidewalls of an upper portion of said semiconductor fin; anda gate electrode straddling said semiconductor fin and overlying said semiconductor-oxide-containing gate dielectric, wherein a portion of said gate electrode protrudes downward into a recess within said shallow trench isolation layer, and is laterally spaced from said lower portion of said semiconductor fin by a vertical portion of said shallow trench isolation layer.2. The semiconductor structure of claim 1 , further comprising a high dielectric constant gate dielectric having a dielectric constant greater than 8.0 and in contact with a top surface and outer sidewalls of said semiconductor-oxide-containing gate dielectric and a ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion. 1. A semiconductor memory device comprising:a first insulating layer covering a substrate;a first contact plug and a second contact plug, each penetrating the first insulating layer;a first data storage element disposed on the first contact plug and electrically connected to a portion of the substrate through the first contact plug; anda second data storage element disposed on and overlapping the second contact plug and electrically connected to a portion of the substrate through the second contact plug, a vertically extending portion; and', 'a horizontally extending portion arranged between the vertically extending portion and the first data storage element,, 'wherein the first contact plug compriseswherein the second contact plug vertically extends from a top surface of the substrate,wherein the first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view, andwherein the first data storage element is disposed on the horizontally extending portion.2. The semiconductor memory device of claim 1 , wherein the first insulating layer includes a recessed region that is disposed in an upper portion of the first insulating layer ...

MIM CAPACITORS FOR LEAKAGE CURRENT IMPROVEMENT

The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride. 1. A semiconductor device , comprising:a substrate;a bottom electrode on the substrate;a capacitor dielectric layer on the bottom electrode, the capacitor dielectric layer having a first region and a second region adjacent to the first region;a top electrode on the first region of the capacitor dielectric layer;an etching stop layer on the top electrode;a first anti-reflective coating layer on the etching stop layer, wherein the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall; anda capping layer overlying the sidewall, the etching stop layer, and the second region of the capacitor dielectric layer, wherein the capping layer is formed from oxide or nitride.2. The device of claim 1 , further comprising a second anti-reflective coating layer on the capping layer.3. The device of claim 2 , further comprising an intermetallic dielectric layer on the second anti-reflective coating layer.4. The device of claim 3 , further comprising a first contact plug electrically connected to the top electrode claim 3 , wherein the first contact plug ...

CHEMICAL LIQUID TREATMENT APPARATUS AND CHEMICAL LIQUID TREATMENT METHOD

A chemical liquid treatment apparatus includes processing chambers; a chemical liquid feeding unit configured to cyclically feed a chemical liquid into the processing chambers; and a modifying unit. The modifying unit, when using a chemical liquid in which an effect thereof varies with a chemical liquid discharge time, is configured to calculate a variation of the effect of the chemical liquid based on the chemical liquid discharge time and is configured to modify the chemical liquid discharge time for each of the processing chambers based on the calculated variation of the effect of the chemical liquid and a cumulative time of the chemical liquid discharge time. 1. A chemical liquid treatment apparatus comprising:processing chambers;a chemical liquid feeding unit configured to cyclically feed a chemical liquid into the processing chambers; anda modifying unit, when using a chemical liquid in which an effect thereof varies with a chemical liquid discharge time, being configured to calculate a variation of the effect of the chemical liquid based on the chemical liquid discharge time and being configured to modify the chemical liquid discharge time for each of the processing chambers based on the calculated variation of the effect of the chemical liquid and a cumulative time of the chemical liquid discharge time.2. The apparatus according to claim 1 , wherein the cumulative time of the chemical liquid discharge time is a sum of a time of chemical liquid discharge for each of the processing chambers obtained by measuring the time of chemical liquid discharge in each of the processing chambers.3. The apparatus according to claim 1 , wherein the chemical liquid feeding unit is configured to be capable of feeding one type of chemical liquid or a mixture of two or more types of chemical liquids.4. The apparatus according to claim 1 , wherein the chemical liquid feeding unit includes a chemical liquid tank configured to store the chemical liquid claim 1 , a pump configured ...

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer and in the first openings. The carbon-containing silicon dioxide layer is planarized to remove portions extending outside the first openings and generate a plurality of mask elements from remaining portions of the carbon-containing silicon dioxide layer. The patterned mask layer is removed. The process layer is etched using the mask elements as an etch mask.

FORMING FINS UTILIZING ALTERNATING PATTERN OF SPACERS

A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material. 1. A semiconductor structure , comprising:a substrate; andtwo or more fins formed in the substrate in a given pattern, each of the two or more fins having a pad layer formed on a top surface thereof and a spacer formed over a top of the pad layer;wherein the given pattern comprises alternating spacers of a first material and a second material with at least a portion of one of the spacers removed via a cut mask.2. The semiconductor structure of claim 1 , wherein a fin pitch between at least two of the fins is less than 30 nanometers.3. The semiconductor structure of claim 1 , wherein the first material comprises a nitride and the second material comprises an oxide.4. The semiconductor structure of claim 1 , wherein the substrate comprises one of bulk semiconductor and a semiconductor-on-insulator.5. The semiconductor structure of claim 1 , wherein the pad layer comprises silicon oxynitride.6. The semiconductor structure of claim 1 , wherein the pad layer comprises at least one of silicon carbide nitride claim 1 , silicon oxy carbide nitride and silicon boron carbide nitride.7. The semiconductor structure of claim 1 , wherein the first material ...

ETCHING APPARATUS AND ETCHING METHOD

An etching apparatus includes a substrate holder configured to hold a substrate; a rotation driver configured to rotate the substrate holder around a rotation axis; a liquid discharge unit configured to discharge an etching solution to a peripheral portion of the substrate; and a controller configured to control an operation of the etching apparatus by controlling at least the rotation driver and the liquid discharge unit. The controller controls at least one of a rotational velocity of the substrate, a discharge velocity of the etching solution from the liquid discharge unit or a discharge direction of the etching solution from the liquid discharge unit to etch the substrate under immediate deviation conditions in which the etching solution is deviated from the substrate immediately after the etching solution from the liquid discharge unit lands at a liquid landing point in the peripheral portion of the substrate. 1. An etching apparatus , comprising:a substrate holder configured to hold a substrate;a rotation driver configured to rotate the substrate holder around a rotation axis;a liquid discharge unit configured to discharge an etching solution to a peripheral portion of the substrate held by the substrate holder; anda controller configured to control an operation of the etching apparatus by controlling at least the rotation driver and the liquid discharge unit,wherein the controller controls at least one of a rotational velocity of the substrate to be rotated by the rotation driver, a discharge velocity of the etching solution from the liquid discharge unit or a discharge direction of the etching solution from the liquid discharge unit to etch the substrate under immediate deviation conditions in which the etching solution is deviated from the substrate immediately after the etching solution discharged from the liquid discharge unit lands at a liquid landing point in the peripheral portion of the substrate.2. The etching apparatus of claim 1 ,wherein a circle, ...

SEMICONDUCTOR CONTACT

A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity. 1. A method for forming a semiconductor device , the method comprising:forming a gate stack on a channel region of a semiconductor, the gate stack including sidewalls extending from a gate stack upper surface to a gate stack base that contacts the channel region, and including gate spacers formed on the sidewalls;forming a source/drain region adjacent to the channel region;depositing a first insulator layer over the source/drain region;removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region;depositing a first conductive material in the first cavity, the first conductive material including conductive sidewalls extending from a conductive base that contacts the source/drain region to a conductive upper surface, the conductive upper surface being flush with the gate stack upper surface;forming a conductive extension from the first conductive material over the first insulator layer and over the gate spacers;depositing a protective layer over the conductive extension and over the gate stack upper ...

INORGANIC WAFER HAVING THROUGH-HOLES ATTACHED TO SEMICONDUCTOR WAFER

A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. 1. A process comprising:forming a damage track in an inorganic wafer bonded to semiconductor wafer using a laser that emits a wavelength of light, wherein the semiconductor is opaque to the wavelength of light and the inorganic wafer is transparent to the wavelength of light; andenlarging the damage track in the inorganic wafer to form a hole through the inorganic wafer by etching, the hole terminating at an interface between the semiconductor wafer and the inorganic wafer.2. The process of claim 1 , wherein the semiconductor wafer is a bare semiconductor wafer.3. The process of claim 1 , wherein the semiconductor wafer is a silicon wafer.4. The process of claim 1 , wherein the etching is performed with an etchant that etches the inorganic wafer at a first rate and the semiconductor wafer at a second rate claim 1 , and the first rate is at least 10 times the second rate.5. The process of claim 1 , wherein the inorganic wafer has a resistivity of at least 10Ω-m at room temperature and a breakdown voltage of at least 1 kV for the thickness of 0.5 mm at room temperature.6. The process of claim 1 , wherein the inorganic wafer is made of ...

Interconnect structure and manufacturing method for the same

The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode. 117-. (canceled)18. A method of manufacturing a semiconductor device including the steps of:(a) providing a semiconductor substrate having a main surface, the main surface including a first region for a first MISFET and a second region for a second MISFET;(b) forming a first lamination pattern having a first gate electrode and a first cap insulation film over the first gate electrode via a first gate insulation film over the main surface of the semiconductor substrate in the first region for the first MISFET;(c) forming, after the step (b), a second lamination pattern having a first electrode and a second cap insulation film over the first electrode via a second gate insulation film over the main surface of the semiconductor substrate in the second region for the second MISFET;(d) forming, after the step (c), a first semiconductor region used for a source or a drain of the first MISFET in the first region and forming a second semiconductor region for a source or a drain of the second MISFET in the second region;(e) forming, after the step (d), ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion. 1. A semiconductor memory device , comprising:a semiconductor pillar extending in a first direction;a first electrode extending in a second direction crossing the first direction;a second electrode provided between the semiconductor pillar and the first electrode;a first insulating film provided between the semiconductor pillar and the second electrode; anda second insulating film provided between the first electrode and the second electrode, a thin sheet portion disposed on the first electrode side, and', 'a thick sheet portion disposed on the semiconductor pillar side, a length in the first direction of the thick sheet portion being longer than a length in the first direction of the thin sheet portion., 'the second electrode including'}2. The device according to claim 1 , wherein a first layer disposed between the thin sheet portion and the first electrode and on two first-direction sides of the thin sheet portion; and', 'a second layer disposed between the first layer and the first electrode and on two first-direction sides of the first electrode., 'the second insulating film includes3. The device according to claim 2 , wherein a portion of the second layer is disposed on two first-direction sides of the first ...

Integrated Assemblies Comprising Voids Between Active Regions and Conductive Shield Plates, and Methods of Forming Integrated Assemblies

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies. 1. Integrated memory comprising:a wordline;a shield plate;an access device comprising first and second diffusion regions and a channel region, the first and second diffusion regions and the channel region being arranged vertically so that the channel region is between the first and second diffusion regions; andwherein the access device is adjacent the wordline and the shield plate so that a part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween and that a part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween; the first insulating region comprising an insulative material, and the second insulating region comprising a void.2. The integrated memory of wherein the void fills an entirety of the second insulating region.3. The integrated memory of wherein the insulative material comprises silicon dioxide.4. The integrated memory of further comprising:a bitline in an electrical connection with first diffusion region; anda storage element in an electrical ...

VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer. 1. A method for manufacturing a vertical semiconductor device , comprising:forming a lower stacked layer including a lower sacrificial layer on a substrate;forming a mold structure on the lower stacked layer, the mold structure including insulation layers and sacrificial layers alternately stacked;forming preliminary channel structures passing through the mold structure and the lower stacked layer and extending to an inner portion of the substrate, each of the preliminary channel structures including a channel layer, a preliminary tunnel insulation layer, a preliminary charge storage layer and a preliminary blocking layer;etching the mold structure to form a first trench extending in one direction, and the lower sacrificial layer being exposed by a bottom portion of the first trench;removing the lower sacrificial layer exposed by the first trench to form a first gap between the substrate and the mold structure;sequentially etching portions of the preliminary blocking layer, the preliminary charge storage layer and the preliminary tunnel insulation layer through the first gap to expose channel layer; andforming a semiconductor pattern that fills the first gap and forms channel structures, ...

METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC PRODUCTS COMPRISING FINFET DEVICES

One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region. 1. A method of forming a FinFET device , comprising:forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a plurality of fins;forming a recessed layer of insulating material comprising a first insulating material in said fin-formation trenches, wherein a portion of each of said plurality of fins is exposed above an upper surface of said recessed layer of insulating material;after forming said recessed layer of insulating material, masking a first portion of a first fin of said plurality of fins and performing at least one first etching process to remove at least a portion of an unmasked second fin of said plurality of fins;after performing said at least one first etching process, forming a device isolation region for said FinFET device that comprises a second insulating material; andforming an isolation protection layer above said device isolation region, wherein said isolation protection layer comprises a different material than said second insulating material of said device isolation region.2. The method of claim 1 , wherein said first and second insulating materials comprise silicon dioxide and said isolation protection layer comprises one of silicon nitride claim 1 ...

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region. 1. A semiconductor device comprising:a capacitor region and a FET region defined by a plurality of stackedly and alternatingly arranged nanosheets and sacrificial layers disposed on a substrate,wherein the nanosheets in the capacitor region have a width and are coupled to one another by the sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width;wherein the nanosheets in the FET region are spaced apart and free of sacrificial layers, the nanosheets in the FET region having a width less than half the width of the nanosheets in the capacitor region.2. The semiconductor device of claim 1 , wherein each one of the nanosheets has a thickness equal to each one of the sacrificial layers.3. The semiconductor device of claim 1 , wherein the nanosheets comprise silicon and the sacrificial layers comprise silicon-germanium.4. The semiconductor device of claim 1 , wherein the substrate underlying the capacitor region is conductive claim 1 , and the stackedly and alternatingly arranged nanosheets and sacrificial layers of the capacitor region are conductively coupled to the substrate.5. The semiconductor device of claim 1 , wherein the substrate underlying the FET region is free of dopants that make the alternatingly arranged nanosheets and sacrificial layers of the capacitor region conductive.6. The ...

Selective Removal of an Etching Stop Layer for Improving Overlay Shift Tolerance

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL. 1. A method for semiconductor device fabrication , the method comprising:providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component;forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide, wherein the ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD;baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide; andselectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.2. The method of claim 1 , wherein baking the ESL does not transform the metal oxide located in the first portion of the ESL into metal silicon oxide claim 1 , and wherein the metal silicon oxide in the second portion of the ESL is formed during the baking by a chemical reaction between the silicon in the ILD and the metal oxide in the second portion of the ESL claim 1 , and wherein the ESL is baked in an ambient gas comprising nitrogen and hydrogen.3. The method of claim 2 , wherein the ESL is baked at a temperature between 100 to 400 degree ...

CONTACT VIA STRUCTURE INCLUDING A BARRIER METAL DISC FOR LOW RESISTANCE CONTACT AND METHODS OF MAKING THE SAME

A first metal interconnect structure embedded in a first dielectric material layer includes a first metallic nitride liner containing a first conductive metal nitride and a first metallic fill material portion. A second metal interconnect structure embedded in a second dielectric material layer overlies the first dielectric material layer. The second metal interconnect structure includes a pillar portion having a straight sidewall and a foot portion adjoined to a bottom periphery of the pillar portion and laterally protruding from the bottom periphery of the pillar portion. The foot portion can be formed by oxidizing a top surface of the first metallic fill material portion, removing the oxidized portion after formation of a cavity through the second dielectric material layer, and depositing a second metallic nitride liner in a volume from which the oxidized portion is removed. 1. A structure comprising:a first metal interconnect structure embedded within a first dielectric material layer overlying a substrate, wherein the first metal interconnect structure comprises a first metallic nitride liner comprising a first conductive metal nitride and a first metallic fill material portion embedded within the first metallic nitride liner; anda second metal interconnect structure embedded within a second dielectric material layer overlying the first dielectric material layer, wherein the second metal interconnect structure comprises a second metallic nitride liner comprising a second conductive metal nitride and a second metallic fill material portion embedded within the second metallic nitride liner,wherein the second metallic nitride liner comprises a pillar portion having a straight sidewall and a foot portion adjoined to a bottom periphery of the pillar portion and laterally protruding from the bottom periphery of the pillar portion.2. The structure of claim 1 , wherein:the straight sidewall extends diagonally with respect to a top surface of the substrate; andan ...

Methods for Fabricating FinFETs Having Different Fin Numbers and Corresponding FinFETs Thereof

Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing. 1. A method comprising:forming a dummy pattern over a substrate, wherein the dummy pattern has a first width in a first region corresponding with a first FinFET and a second width in a second region corresponding with a second FinFET, the second width being greater than the first width;forming spacers along sidewalls of the dummy pattern;removing the dummy pattern, thereby forming a spacer pattern having a first spacing between spacers in the first region and a second spacing between spacers in the second region, wherein the second spacing is greater than the first spacing;transferring the spacer pattern to the substrate, thereby forming a first fin and a second fin separated by the first spacing in the first region and separated by the second spacing in the second region; andpartially removing the second fin from the second region to form a dummy fin tip.2. The method of claim 1 , wherein a ratio of the second spacing to the first spacing is about 1.05 to about 2.3. The method of claim 1 , further comprising forming an isolation feature over the substrate claim 1 , wherein the isolation feature is ...

Forming Nitrogen-Containing Low-K Gate Spacer

A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia. 1. A method comprising:forming a dummy gate stack over a semiconductor region of a wafer; and introducing silylated methyl to the wafer;', 'purging the silylated methyl;', 'introducing ammonia to the wafer; and', 'purging the ammonia., 'depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack, wherein the depositing the gate spacer layer comprises performing an ALD cycle to form a dielectric atomic layer, wherein the ALD cycle comprises2. The method of further comprising performing an anneal on the wafer after the gate spacer layer is formed claim 1 , wherein the anneal is performed with the wafer placed in an oxygen-containing gas.3. The method of claim 2 , wherein the anneal is performed at a temperature in a range between about 400° C. and about 500° C.4. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first nitrogen atomic percentage claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.5. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first k value higher than a k value of silicon oxide claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second k value lower than the k value of silicon oxide.6. The method of claim 1 , wherein the depositing the gate spacer layer further comprises introducing ammonia to the wafer before performing the ALD cycle.7. The ...

INDUCTOR AND TRANSMISSION LINE WITH AIR GAP

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines. 1. An integrated circuit structure , comprising:one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm; andan air gap in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.2. The integrated circuit structure of claim 1 , wherein the width of the air gap and a distance between the first and second conductive lines is approximately 1 to 10 μm.3. The integrated circuit structure of claim 1 , wherein the air gap includes one or more spacers along at least one top corner of the air gap and at least one sidewall of the first and second conductive lines.4. The integrated circuit structure of claim 3 , wherein the one or more spacers leave an opening in the air gap of approximately 100-300 nm.5. The integrated circuit structure of claim 3 , wherein the air gap includes left and right spacers formed along the sidewalls of the first and second conductive lines claim 3 , respectively claim 3 , where the left and right spacers are coplanar with a top surface of the first and second conductive lines.6. The integrated circuit structure of claim 1 , wherein the air gap is formed as a continuous recess between the first and second conductive lines.7. The integrated circuit structure of claim 1 , wherein the air gap is formed as non-contiguous air gap segments that are spaced apart by the ILD to provide structural support to the sidewalls of the first and second conductive lines.8. ...

Production of semiconductor regions in an electronic chip

A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

Structure and Formation Method of Semiconductor Device Structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling. 1. A semiconductor device comprising:a fin structure;a shallow trench isolation (STI) adjacent the fin structure;a gate structure over a portion of the fin structure and the STI, wherein the gate structure comprises a gate dielectric layer, a work function layer over the gate dielectric layer, and a conductive fill material over the work function layer;spacers along opposing sidewalls of the gate structure, the spacers terminating at ends of the gate structure along a longitudinal axis of the gate structure; anda dielectric layer surrounding the gate structure and the spacers in a plan view, wherein the work function layer terminates over the STI between the fin structure and the dielectric layer along a longitudinal axis of the gate structure, wherein the gate dielectric layer completely separates the conductive fill material from the spacers and the dielectric layer.2. The semiconductor device of claim 1 , wherein the conductive fill material directly contacts the gate dielectric layer.3. The semiconductor device of claim 1 , wherein an uppermost surface of the gate dielectric layer is level with an uppermost surface of the dielectric layer.4. The semiconductor device of claim 1 , wherein a thickness of the work function layer is less than a height of the fin structure above the STI.5. The semiconductor device of claim 1 , wherein the conductive fill material is interposed between the work function layer and the dielectric layer.6. The ...

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

Method for forming an integrated circuit and an integrated circuit

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

PARTIALLY DISPOSED GATE LAYER INTO THE TRENCHES

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches. 1. A system , comprising:a substrate layer having an outer surface;a plurality of trenches extending from the outer surface into the substrate layer;a plurality of active regions, each active region positioned between a different pair of consecutive trenches of the plurality of trenches;a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions; anda floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.2. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises at least one implant layer.3. The system of claim 1 , wherein the portions of the dielectric layer in the plurality of trenches form a plurality of shallow trench isolation regions.4. The system of claim 1 , wherein the substrate layer comprises silicon claim 1 , the floating gate layer comprises polysilicon claim 1 , and the dielectric layer comprises silicon dioxide.5. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises an anti-punch through layer.6. The system of claim 1 , wherein the substrate layer includes a plurality of bitcells.7. A device claim 1 , comprising:a substrate layer;first ...

THREE-DIMENSIONAL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REPLACEMENT GATE

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material. 1. A vertical three-dimensional semiconductor memory device , comprising:a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell; andat least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.2. The memory device of claim 1 , wherein the control gate layers comprise semiconductor layers claim 1 , and wherein the electrically conductive material comprises a metallic material.3. The memory device of claim 1 , wherein the electrically conductive material comprises one or more of tungsten claim 1 , tungsten nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , ...

METAL GATE STRUCTURE CUTTING PROCESS

Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure. 18.-. (canceled)9. A method for manufacturing a semiconductor device structure , the method comprisingforming a metal gate structure over a first fin structure and a second fin structure disposed on a substrate, wherein an interlayer dielectric (ILD) layer is formed between the first and the second fin structures;performing an ILD recess etching process to selectively form a recess in the ILD layer;forming a dielectric structure in the recess;performing a metal gate structure cutting process to form a line-cut that divides the metal gate structure into sub-metal gate structures, the line-cut further being formed at least partially in the dielectric structure; andforming an isolation structure in the line-cut.10. The method of claim 9 , wherein performing the metal gate structure cutting process further comprises:removing a portion of the dielectric structure.11. The method of claim 9 , wherein forming the dielectric structure further comprises:forming a conformal liner layer along a sidewall of the ILD layer and a bottom surface of the recess.12. The method of claim 9 , wherein forming a dielectric structure in the recess further comprises:fully filling the recess with the dielectric structure.13. The method of claim 9 , wherein the dielectric structure has a first side interfaced with the ILD layer and a second side interfaced with the isolation structure.14 ...

POLYSILICON STRUCTURE INCLUDING PROTECTIVE LAYER

A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers. 1. A manufacture , comprising:a substrate comprising a first portion and a second portion;a first polysilicon structure over the first portion of the substrate;a second polysilicon structure over the second portion of the substrate;two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion; anda protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.2. The manufacture of claim 1 , wherein the two spacers are L-shaped spacers.3. The manufacture of claim 1 , further comprising:a static random access memory (SRAM) cell comprising the second polysilicon structure and the two spacers.4. The manufacture of claim 1 , further comprising:a one-time-programmable (OTP) device comprising the first polysilicon structure.5. The manufacture of claim 1 , wherein the protective layer comprises silicon oxide.6. The manufacture of claim 1 , further comprising another two spacers on opposite sidewalls of the first ...

Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor

A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed. 1. A memory array comprising vertically-alternating tiers of insulative material and memory cells , the memory cells individually comprising:a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; anda capacitor comprising ...

SEMICONDUCTOR DEVICES

A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly. 1. A semiconductor device comprising:a plurality of conductive patterns disposed on a substrate, each of the plurality of conductive patterns being spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate, each of the plurality of conductive patterns having an extension portion and a step portion, the step portion being disposed at an edge of a corresponding one of the plurality of conductive patterns; andan insulation pattern disposed between each of the plurality of conductive patterns in the vertical direction,wherein a lower surface of the step portion and an upper surface of the step portion of each of the plurality of conductive patterns are bent upwardly.2. The semiconductor device of claim 1 , wherein a first length of the insulation pattern is less than a second length of each of the plurality of conductive patterns that adjoins the insulation pattern.3. The semiconductor device of claim 1 , wherein a recess is defined by a sidewall of the insulation pattern claim 1 , an upper surface of a first one of the plurality of conductive patterns that is in contact with a lower surface of the insulation pattern and a lower surface of a second one of the plurality of conductive patterns that is in ...

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure and a dielectric layer on a substrate; and forming a sidewall spacer on a sidewall surface of the gate structure. The method also includes forming a source and drain doped region in the substrate on both sides of the gate structure. The dielectric layer covers a surface of the sidewall spacer. In addition, the method includes forming a source-drain plug in the dielectric layer. The source-drain plug is connected to the source and drain doped region. Moreover, the method includes forming an isolation opening in the dielectric layer by at least partially removing the sidewall spacer. Further, the method includes forming an isolation structure in the isolation opening, wherein the isolation structure has a dielectric constant less than the sidewall spacer.

Gate Spacer and Methods of Forming

Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment. 1. A method comprising:forming an electrode on a substrate;forming a spacer along a sidewall of the electrode;treating at least a portion of an exterior surface of the spacer, the treating terminating the at least the portion of the exterior surface with a passivating species;forming a recess in the substrate proximate the spacer;depositing a material in the recess while the at least the portion of the exterior surface is terminated with the passivating species; andafter depositing the material in the recess, removing the passivating species from the exterior surface of the spacer.2. The method of claim 1 , wherein the passivating species comprises oxygen claim 1 , fluorine claim 1 , or a combination thereof.3. The method of claim 1 , wherein the treating comprises exposing the at least the portion of the exterior surface of the spacer to a thermal treatment.4. The method of claim 1 , wherein the treating comprises exposing the at least the portion of the exterior surface of the spacer to a plasma treatment.5. The method of claim 1 , wherein the treating comprises a wet treatment applied to the at least the portion of the exterior surface of the spacer.6. The method of claim 1 , wherein depositing the material in the recess comprises epitaxially growing a semiconductor material in the recess.7. The method of claim 1 , wherein forming the spacer comprises:conformally depositing a spacer layer along the electrode; andetching the spacer ...

Gate Stack Structure and Method for Forming the Same

Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

Controlling Profiles of Replacement Gates

A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack. 1. A device comprising:a semiconductor fin;a gate stack on a top surface and sidewalls of the semiconductor fin;a gate spacer comprising portions on opposite sides of the gate stack;a protection layer between the gate spacer and the gate stack, wherein the protection layer has a first bottom surface higher than a second bottom surface of the gate spacer; anda source region and a drain region on opposite sides of the gate stack.2. The device of claim 1 , wherein the first bottom surface of the protection layer is higher than the top surface of the semiconductor fin.3. The device of claim 1 , wherein the first bottom surface of the protection layer is lower than the top surface of the semiconductor fin.4. The device of claim 1 , wherein the protection layer is formed of a first material different from a second material of the gate spacer.5. The device of claim 1 , wherein the protection layer comprises portions on opposite sides of the gate stack claim 1 , and the gate spacer comprises portions on opposite sides of a combined region that comprises the gate stack and the protection layer.6. The device of claim 1 , ...

Display substrate having a thin film transistor and method of manufacturing the same

In a method for manufacturing a display substrate, a thin film transistor is formed on a base substrate. The thin film transistor includes a gate electrode, an active pattern, a source electrode and a drain electrode. A first passivation layer is formed to cover the thin film transistor. A second passivation layer is formed on the first passivation layer. A photoresist pattern is formed to partially expose the second passivation layer. The first passivation layer and the second passivation layer are partially removed to form a contact hole exposing the drain electrode. A pixel electrode layer is formed on the second passivation layer, the drain electrode and the photoresist pattern. A portion of the pixel electrode layer and the second photoresist pattern are removed to form a pixel electrode. The portion of the pixel electrode layer is disposed on a top surface and a sidewall of the photoresist pattern.

INTERCONNECTION ELEMENT AND METHOD OF MANUFACTURING THE SAME

An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer. 1. An integrated circuit , comprising:an interconnection structure resting on a semiconductor layer, the interconnection structure comprising an interconnection element at least partly arranged in an insulating layer of said interconnection structure; a copper fill; and', 'a copper silicide layer positioned between the copper fill and the insulating layer of said interconnection structure at a lower surface and a lateral surface of the copper fill;, 'wherein the interconnection element compriseswherein the copper silicide layer comprises nitrogen atoms, and wherein a nitrogen atom concentration in the silicide layer increases as distance away from the copper fill increases.2. The circuit of claim 1 , wherein the nitrogen atom concentration in the copper silicide layer is maximum at a level of a surface of the copper silicide layer opposite to the copper fill.3. The circuit of claim 2 , where the maximum nitrogen atom concentration in the silicide layer is in a range from 40 to 60%.4. The circuit of claim 1 , wherein the copper silicide layer further covers an upper surface of the copper fill.5. The circuit of claim 1 , wherein a lower surface of the interconnection element is in contact with a conductive region.6. The ...

ETCHING COMPOSITIONS AND METHOD OF ETCHING BY USING THE SAME

The present invention relates to an etching composition, an etching method, and a method of preparing a semiconductor device using the same, and more particularly, to an etching composition comprising a compound capable of selectively removing a nitride film with a high selectivity while minimizing an etch rate of the oxide film, and a method of preparing a semiconductor device comprising an etching process using the etching composition. 2. The etching composition of claim 1 , wherein Rto Rare selected from the group consisting of hydrogen claim 1 , halogen claim 1 , hydroxy group and C-Calkyl group claim 1 , at least one of Rto Ris hydroxy group claim 1 ,{'sub': 4', '1', '5, 'Ris selected from the group consisting of hydrogen, halogen and C-Calkyl group,'}{'sub': 1', '5', '6', 'm, 'Xis —(C(R)(R))—,'}m is 0 to 1, and{'sub': 5', '6', '1', '5, 'Rand Rare each independently hydrogen or C-Calkyl group.'}3. The etching composition of claim 2 , wherein all of Rto Rare hydroxy groups.4. The etching composition of claim 3 , wherein the compound represented by Formula 1 is at least one selected from the group consisting of (2-(pyridin-4-yl)propan-2-yl)silanetriol claim 3 , (3-pyridin-4-yl)pentan-3-yl)silarietriol claim 3 , (3 claim 3 ,5-dimethylpyridin-4-yl)silanetriol and (2-(3 claim 3 ,5-dimethylpyridin-4-yl)propan-2-yl)silanetriol.5. The etching composition of claim 1 , which comprises 80 to 90% by weight of phosphoric acid and 0.1 to 3% by weight of the compound represented by Formula 1.6. The etching composition of claim 1 , further comprising an additive for improving etch rate.7. A method of etching a semiconductor device claim 1 , comprising etching a film selected from the group consisting of a silicon nitride film claim 1 , a silicon oxide film and combinations thereof claim 1 , by using the etching composition of . The present invention relates to an etching composition and a method of etching by using the same, and more particularly, to an etching composition ...

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

INCREASED CONTACT AREA FOR FINFETS

A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess. 1. A method for forming fin field effect transistors , comprising:epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section;forming a dielectric liner over the S/D regions;etching a dielectric fill formed over the S/D regions to expose a top portion of the diamond-shaped cross section;recessing the fins into the diamond-shaped cross section;exposing an outer surface of the diamond-shaped cross section of the S/D regions;forming a contact liner on the exposed outer surface of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed; andforming contacts over surfaces of the top portion and in the recess.2. The method as recited in claim 1 , wherein etching the dielectric fill includes performing a timed etch in accordance with a pattern to reach the top portion of the diamond-shaped cross section.3. The method as recited in claim 1 , wherein recessing the fins into the diamond-shaped cross section includes performing a selective etch to etch a portion of the fins within the diamond-shaped cross section.4. The method as recited in claim 3 , wherein performing the selective etch includes performing a reactive ion etch with an HBr chemistry.5. The method as recited in claim 1 , further ...

Photoresist Layer and Method

A system and method for middle layers is provided. In an embodiment the middle layer comprises a floating component in order to form a floating region along a top surface of the middle layer after the middle layer has dispersed. The floating component may be a polymer with a floating group incorporated into the polymer. The floating group may comprise a fluorine atom.

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

A method of manufacturing a polysilicon (poly-Si) layer, a method of manufacturing an organic light-emitting display apparatus using the method, and an organic light-emitting display apparatus manufactured by using the method. The method includes forming an amorphous silicon (a-Si) layer on a substrate having first and second areas, thermally treating the a-Si layer to partially crystallize the a-Si layer into a partially crystallized Si layer, removing a thermal oxide layer through a thermal treatment, selectively irradiating the first areas with laser beams to crystallize the partially crystallized Si layer. 1. A method of manufacturing a polysilicon (poly-Si) layer , the method comprising:forming an amorphous silicon (a-Si) layer on a substrate, the substrate having a first area and a second area;thermally treating the a-Si layer to convert the a-Si layer into a partially crystallized Si layer;removing a thermal oxide layer formed by the thermally treating of the a-Si layer; andselectively irradiating the first area with laser beams to crystallize the partially crystallized Si layer.2. The method of claim 1 , further comprising:forming a buffer layer on the substrate before the forming of the a-Si layer.3. The method of claim 1 , wherein the substrate has a plurality of first areas comprising the first area claim 1 , and a plurality of second areas comprising the second area claim 1 , and the plurality of first areas and the plurality of second areas alternate with each other and are spaced apart.4. The method of claim 1 , wherein a crystallinity of the partially crystallized Si layer is in a range between 65% and 80%.5. The method of claim 1 , wherein the thermally treating of the a-Si layer comprises:thermally treating the a-Si at a temperature between 650° C. and 780° C.;partially crystallizing the a-Si layer into the partially crystallized Si layer; andforming the thermal oxide layer on the partially crystallized Si layer.6. The method of claim 5 , wherein ...

Process for Silicon Nitride Removal Selective to SiGex

A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGe(x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGe. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride. 1. A method for selectively removing silicon nitride , comprising:{'sub': 'x', 'providing a substrate having a surface with silicon nitride exposed on at least one portion of said surface and SiGe, wherein x is greater than or equal to zero, exposed on at least another portion of said surface;'}{'sub': 'x', 'dispensing an oxidizing agent onto said surface of said substrate to oxidize said exposed SiGe; and'}following said dispensing said oxidizing agent, dispensing a silicon nitride etching agent as a liquid stream onto said surface of said substrate to remove at least a portion of said silicon nitride.2. The method of claim 1 , further comprising:prior to dispensing a silicon nitride etching agent, dispensing a heating agent onto said surface of said substrate to pre-heat said substrate to a target temperature.3. The method of claim 2 , wherein said target temperature exceeds 150 degrees C.4. The method of claim 2 , wherein said dispensing said oxidizing agent and dispensing said heating agent are performed simultaneously.5. The method of claim 1 , wherein said dispensing said oxidizing agent includes exposing said substrate to a mixture containing sulfuric acid and hydrogen peroxide.6. The method of claim 5 , wherein said sulfuric acid is heated to a temperature in excess of 150 degrees C.7. The method of claim 5 , wherein said sulfuric acid is heated to a temperature in excess of 200 degrees C ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS

A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set. 1. A method of making a semiconductor device , the method comprising: a substrate;', 'a dielectric layer over the substrate;', 'a first layer set over the dielectric layer, wherein the first layer set comprises a silicon-rich photoresist material;', 'a second layer set over the first layer set, wherein the second layer set comprises a plurality of layers including a carbon-rich organic material layer; and, 'forming an intermediate semiconductor device, the intermediate semiconductor device comprisingetching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the dielectric layer;etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer; andetching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer. 1. A semiconductor structure , comprising:a conductive layer having a first conductive material;a conductive strip in the same level as the conductive layer and having a second conductive material, wherein the second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material;a dielectric layer; anda conductive element crisscrossing the conductive strip and separated from the conductive strip by the dielectric layer.2. The semiconductor structure according to claim 1 , comprising a stack of conductive levels each comprising the conductive layer and the conductive strip.3. The semiconductor structure according to claim 2 , wherein the conductive layers of the different levels are exposed by openings of different depths in the stack.4. The semiconductor structure according to claim 1 , comprising a memory array region and a pad region adjacent to the memory array region claim 1 , wherein the conductive strip is in the memory array region claim 1 , the conductive layer is in the pad region.5. The semiconductor structure according to claim 1 , wherein the memory array region and the pad region are non-overlapping.6. The semiconductor structure according to claim 1 , wherein the ...

Pad Design For Reliability Enhancement in Packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated. 1. A package comprising: a corner;', 'a device die;', 'a molding material molding the device die therein; and', a corner bonding feature at the corner, wherein the corner bonding feature is elongated; and', 'an additional bonding feature, wherein the additional bonding feature is non-elongated., 'a plurality of bonding features comprising], 'a first package comprising2. The package of claim 1 , wherein the plurality of bonding features comprises a plurality of bonding pads.3. The package of further comprising a dielectric layer on a backside of the device die claim 2 , wherein the corner bonding feature comprises a first portion in the dielectric layer claim 2 , and a second portion protruding beyond the dielectric layer.4. The package of claim 1 , wherein the plurality of bonding features comprises a plurality of through-vias penetrating through the molding material.5. The package of further comprising:a second package; anda first solder region bonding the corner bonding feature to the second package; anda second solder region bonding the additional bonding feature to the second package.6. The package of claim 5 , wherein the second package comprises a metal pad in contact with the first solder region claim 5 , wherein the metal pad is elongated.7. The package of claim 5 , wherein the first solder region and the second solder region are in contact with a sidewall of the corner bonding feature and a sidewall of the additional bonding feature claim 5 , respectively.8. The package of claim 7 , wherein the second package comprises a first and a second metal pad in contact with the first solder region and ...

Tin oxide thin film spacers in semiconductor device manufacturing

Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.

METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR

A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≦0.2, and having a pH less than or equal to 1.5. 116.-. (canceled)17. A method for forming spacers of a gate of a field effect transistor , the gate comprising sides and a top and being located above a layer made of a semiconductor material , the method comprising:a step of forming a dielectric layer that covers the gate of the transistor;after the step of forming the dielectric layer, at least one step of modifying said dielectric layer by ion implantation at least in portions of the dielectric layer that are located on a top of the gate and on either side of the gate and which are perpendicular to the sides of the gate by retaining non-modified portions of the dielectric layer coveting the sides of the gate, said non-modified portions being at least non-modified over their entire thickness the ions having a hydrogen base and/or a helium base; andat least one step of removing the modified dielectric layer using a selective etching of the modified dielectric layer relative to the layer made of a semiconductor material and relative to the non-modified dielectric layer,wherein the dielectric layer is made of a material chosen from among a silicon nitride, SiC, ...

THREE-DIMENSIONAL STACKING STRUCTURE

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection. 1. A stacking structure , comprising:a first die, having a first bonding structure, wherein the first bonding structure comprises contact pads;a second die, having a second bonding structure, wherein the second die is stacked on the first die, and the second bonding structure is bonded with the first bonding structure;a spacer protective structure, disposed over the first die and surrounding the second die, wherein the spacer protective structure covers sidewalls of the second die; andan anti-bonding layer, disposed over the first die and located between the spacer protective structure and the first die.2. The structure of claim 1 , wherein the first bonding structure further comprises first bonding elements embedded in a first dielectric material claim 1 , and the second bonding structure comprises second bonding elements embedded in a second dielectric material.3. The structure of claim 2 , wherein the second bonding structure is bonded with the first bonding structure through the bonding of the first and second bonding elements and the bonding of the first and second dielectric materials.4. The structure of claim 2 , wherein the second bonding structure further comprises at least one seal ring structure embedded within the second dielectric material claim 2 , arranged along a ...

3DIC Interconnect Apparatus and Method

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

TRENCH FORMATION WITH CD LESS THAN 10NM FOR REPLACEMENT FIN GROWTH

Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs. 1. A method of forming a semiconducting fin structure , comprising:etching a first layer to form a feature bounded by a first material;depositing a second layer over the first material and the feature formed in the first layer;etching the second layer to expose a portion of the first layer within the feature through the second layer; andforming a III-V material on the exposed portion of the first layer, the III-V material filling the feature between the second layer.2. The method of claim 1 , wherein the feature has an aspect ratio of between about 5:1 and about 30:1.3. The method of claim 1 , wherein the III-V material has a critical dimension of less than about 10 nm.4. The method of claim 1 , further comprising:removing a portion of the first material, the second layer, and the III-V material to form a planar surface.5. The method of claim 1 , wherein the first layer is a conductive material.6. The method of claim 5 , wherein the first material and the second layer are insulator materials.7. The method of claim 6 , wherein the second layer is conformally deposited over the first material and the feature formed in the first material.8. A method of forming a semiconducting fin structure claim 6 , comprising:etching a conductive layer to form a feature bounded by an first insulator material;depositing a second insulator material over the first insulator material and the feature formed in the ...

METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact. 1. A method comprising:providing a structure having a FinFET disposed in an Rx region, the FinFET including a channel disposed between a pair of source/drain (S/D) regions and a gate (CB) disposed over the channel, the gate including gate metal disposed between gate spacers;forming a cap over the gate, the cap having an outer liner disposed around an inner core;forming trench silicide (TS) layers on opposing sides of the gate over the S/D regions;recessing the TS layers to a level above a level of the gate and below a level of the core;etching the liner down to a level proximate the level of the TS layers;disposing an oxide layer over the structure;patterning a CB trench into the oxide layer to expose the core at a shelf portion of the CB trench, the CB trench located within the Rx region;etching the core to further extend the CB trench to a trench bottom and to expose the gate metal, the shelf portion of the CB trench having a larger area than the trench bottom; andmetallizing the CB trench to form a CB contact electrically connected to the gate metal.2. The method of wherein the cap outer liner has a first material composition and the cap inner core has a second material composition different from the first material ...

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another. 1. A method of manufacturing an integrated circuit device , the method comprising:forming a plurality of multilayered stack structures that extend parallel to and separated from one another on a substrate;forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures, each of the plurality of conductive line patterns being between each of the multilayered stack structures;removing portions of the buried conductive layer that correspond to a plurality of fence line areas which are spaced apart from one another and extend parallel to one another in a direction crossing the extending direction of the multilayered stack structures, to thereby separate the plurality of line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered ...

Mask, manufacturing method thereof and manufacturing method of a thin film transistor

The present invention discloses a mask, a manufacturing method thereof and a manufacturing method of a thin film transistor. The mask includes: a first substrate and phase shift patterns formed above the first substrate, wherein an opening area is formed between the adjacent phase shift patterns and a halftone pattern is formed at positions corresponding to the phase shift patterns and the opening area. In the present invention, when an active layer pattern, a source and a drain are formed through one patterning process by using the mask, the design of narrow channel of the thin film transistor can be realized. As the width of the channel region of the thin film transistor becomes narrow, the volume of the thin film transistor can be effectively reduced, and the super-miniaturization of the thin film transistor can be achieved.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING BARRIER PATTERN

The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns. 1. A semiconductor device comprising:a stack structure including conductive layers and insulating layers, which are alternately stacked, each of the conductive layers including a first barrier pattern having an inclined inner surface and a metal pattern in the first barrier pattern.2. The semiconductor device of claim 1 , further comprising:channel patterns penetrating the stack structure; anda slit spaced apart from the channel patterns and penetrating the stack structure.3. The semiconductor device of claim 2 , wherein the first barrier pattern includes a first region having the inclined inner surface and a second region having a non-inclined inner surface.4. The semiconductor device of claim 3 , wherein the first region is located closer to the slit than the second region.5. The semiconductor device of claim 3 ,wherein the thickness of the first region decreases as the first region approaches the slit.6. The semiconductor device of claim 3 , wherein the second region of the first barrier pattern has a uniform thickness.7. The semiconductor device of claim 3 , wherein the metal pattern has a uniform thickness in the second region claim 3 , and the thickness of the metal pattern increases as the metal pattern approaches the slit in the first region.8. The semiconductor ...

SUPER JUNCTION MOSFET AND METHOD OF MANUFACTURING THE SAME

A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET. 1. A super junction MOSFET comprising:a substrate having a first conductive type;an epitaxial layer formed on the substrate, the epitaxial layer having the first conductive type;a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other;a set of first wells, each of the set of first wells having a second conductive type, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars;a set of second wells of the first conductive type formed in the set of first wells; anda plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other.2. The super junction MOSFET of claim 1 , wherein the set of pillars are spaced apart from one another along the first direction to have multiple columns such that the pillars are arranged to have a hexagonal array in a serpentine pattern along the first ...

Etching method and residue removal method

An etching method of etching a silica-based residue containing a base component formed in an SiO2 film, includes selectively etching the silica-based residue by supplying an HF gas, an H2O gas or an alcohol gas to a target substrate having the SiO2 film, on which the silica-based residue is formed, and removing an etching residue caused by the selectively etching the silica-based residue, after the selectively etching the silica-based residue. The removing an etching residue includes a first process of supplying an H2O gas or an alcohol gas to the target substrate and a second process of heating the target substrate after the first process.

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer. 1. A semiconductor device , comprising:an isolation insulating layer;fin structures protruding from the isolation insulating layer;gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate;a first source/drain epitaxial layer and a second source/drain epitaxial layer, both of which are disposed between two adjacent gate structures;a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer;a separation isolation layer disposed between the first and second conductive contacts; anda dielectric layer disposed between the separation isolation layer and the isolation insulating layer and between the first and second source/drain epitaxial layers,wherein the separation isolation layer is made of a different material than the dielectric layer.2. The semiconductor device of claim 1 , wherein the separation isolation layer is made of one or more layers of SiN and SiCN.3. The semiconductor device of claim 1 , wherein the dielectric layer is made of SiO.4. The semiconductor device of claim 1 , further comprising a liner insulating layer ...

GATE CUT METHOD

A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified. 1. A method of forming a semiconductor structure , comprising:forming a sacrificial gate over a plurality of semiconductor fins;forming an interlayer dielectric laterally adjacent to the sacrificial gate;forming a hard mask over the sacrificial gate and over the interlayer dielectric;etching an opening in the hard mask to expose a top surface of the sacrificial gate and form a recessed region within the interlayer dielectric;forming an oxide layer within the recessed region; andetching the sacrificial gate to form a gate cut opening that extends through the sacrificial gate, wherein the gate cut opening is located between an adjacent pair of the fins in the plurality of semiconductor fins.2. The method of claim 1 , further comprising filling the gate cut opening with a dielectric material.3. The method of claim 2 , wherein the dielectric material comprises silicon nitride.4. The method of claim 2 , wherein the dielectric material is formed over the oxide layer.5. The method of claim 1 , wherein the oxide layer is formed over a sidewall surface of the hard mask within the opening.6. The method of claim 1 , further comprising anisotropically etching the oxide layer to expose a top surface of the ...

Array Substrate and Manufacturing Method Thereof, and Display Device

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a base substrate; a planarization layer, located on the base substrate; a first electrode layer, located on a side of the planarization layer away from the base substrate; and an insulating layer, located on a side of the planarization layer and the first electrode layer away from the base substrate, the insulating layer includes a plurality of first pores. 1. An array substrate , comprising:a base substrate;a planarization layer, located on the base substrate;a first electrode layer, located on a side of the planarization layer away from the base substrate; andan insulating layer, located on a side of the planarization layer and the first electrode layer away from the base substrate,wherein the insulating layer comprises a plurality of first pore structures.2. The array substrate according to claim 1 , wherein each of the first pore structures has a shape of ellipse.3. The array substrate according to claim 2 , wherein long axis directions of adjacent ones of the first pore structures are perpendicular to each other.4. The array substrate according to claim 1 , wherein each of the first pore structures has a shape of rectangle.5. The array substrate according to claim 4 , wherein long edge directions of adjacent ones of the first pore structures are perpendicular to each other.6. The array substrate according to claim 1 , further comprising:a second electrode layer, located on a side of the insulating layer away from the first electrode layer, and comprising a plurality of openings,wherein an orthographic projection of the second electrode layer on the base substrate is at least partially overlapped with an orthographic projection of the first electrode layer on the base substrate, in an overlapped region of the orthographic projections of the first electrode layer on the base substrate and the second electrode layer on the base substrate, an ...

Germanium Nanowire Fabrication

Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeO. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeO. 1. A method of forming a semiconductor device comprising at least one Ge nanowire , the method comprising:providing a semiconductor structure comprising at least one fin, the at least one fin comprising a stack of at least one Ge layer alternated with SiGe layers;{'sub': 'x', 'at least partially oxidizing the SiGe layers into SiGeO;'}capping the fin with a dielectric material;annealing; and{'sub': 'x', 'selectively removing the dielectric material and the SiGeO.'}2. The method according to claim 1 , further comprising repeating the steps of oxidizing claim 1 , capping claim 1 , annealing claim 1 , and removing.3. The method according to claim 1 , wherein removing the dielectric material and the SiGeOcomprises wet etching.4. The method according to claim 3 , wherein HF is used as an etchant in the wet etching.5. The method according to claim 1 , wherein a temperature during oxidizing is below 450° C.6. The method according to claim 1 , wherein a temperature during annealing is above 500° C.7. The method according to claim 1 , wherein the at least one fin of the provided semiconductor structure is formed on a Ge substrate.8. The method according to claim 1 , wherein the at least one fin of the provided semiconductor structure is formed on a SiGe substrate.9. The method according to claim 1 , wherein the at least one fin of the provided ...

Method for forming spacers of a transistor

A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.

SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD

A substrate treating apparatus and a substrate treating method are provided. The substrate treating apparatus includes a support member to support a substrate, a treatment liquid nozzle to supply a treatment liquid to the substrate positioned on the support member, and a controller to control the treatment liquid nozzle such that the treatment liquid supplied to the substrate is differently discharged in a low-flow-supply section and a high-flow-supply section in which an average discharge amount per hour is more than an average discharge amount per hour in the low-flow-supply section. 1. A substrate treating apparatus comprising:a support member to support a substrate;a treatment liquid nozzle to supply a treatment liquid to the substrate supported to the support member;a heating member to heat the substrate supported to the support member; anda controller to control the heating member to change a heating temperature for the substrate at least one time while treating the substrate.2. The substrate treating apparatus of claim 1 , wherein the controller controls the heating member to repeatedly perform higher-temperature heating and lower-temperature heating for the substrate supported to the support member.3. The substrate treating apparatus of claim 2 , wherein the controller controls the heating member such that a temperature in the lower-temperature heating is ½ lower than a temperature in the higher-temperature heating.4. The substrate treating apparatus of claim 2 , wherein the controller controls the heating member to perform the higher-temperature heating after the lower-temperature heating.5. The substrate treating apparatus of claim 2 , wherein the controller controls the heating member such that claim 2 , when at least two sections in which the higher-temperature heating is performed appear claim 2 , the at least two sections in which the higher-temperature heating is performed have equal durations.6. The substrate treating apparatus of claim 2 , wherein ...

Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed. 1. A method used in forming a memory array comprising strings of memory cells and operative through array-vias (TAVs) , the method comprising:forming a stack comprising vertically-alternating insulative tiers and conductive tiers, the stack comprising a TAV region and an operative memory cell string region;forming operative channel-material strings in the stack in the operative memory cell string region and dummy channel-material strings in the stack in the TAV region;replacing at least a majority of channel material of the dummy channel material strings in the TAV region with insulator material; andforming operative TAVs in the TAV region.2. The method of wherein the replacing removes all of the channel material of the channel material strings.3. The method of wherein the operative channel-material strings are within laterally-spaced memory blocks that comprise part of a memory plane; and 'forming multiple of said TAV regions that are laterally spaced relative one another, at least one of said TAV regions being within the memory plane, at least another one of said TAV regions being outside of the memory plane.', 'further comprising4. The method of wherein the replacing comprises:masking the operative channel-material strings in the operative memory cell string ...

SELECTIVELY ETCHING MATERIALS

A method of selectively removing aluminium oxide or nitride material from a microelectronic substrate, the method comprising contacting the material with an aqueous etching composition comprising: an etchant comprising a source of fluoride; and a metal corrosion inhibitor; wherein the composition has a pH in the range of from 3 to 8. Aqueous etching compositions and uses are also described. 2. The method of claim 1 , wherein the etchant is selected from HF claim 1 , ammonium fluoride and tetraalkylammonium fluorides.3. The method of claim 1 , wherein the amount of etchant in the composition is in the range of from 0.001 to 0.5 wt./wt. % based on the total weight of the composition.4. The method of claim 1 , wherein the composition comprises a heterocyclic nitrogen compound metal corrosion inhibitor.5. The method of claim 4 , wherein the composition comprises a substituted benzotriazole corrosion inhibitor claim 4 , optionally 5-methyl-benzotriazole.6. The method of claim 5 , wherein the amount of optionally substituted benzotriazole corrosion inhibitor in the composition is in the range of from 0.1 wt./wt. % to 1 wt./wt. % based on the total weight of the composition.7. The method of claim 1 , wherein the composition comprises a cationic surfactant corrosion inhibitor.9. The method of claim 8 , wherein Rcomprises a substituted or unsubstituted aryl quaternizing group claim 8 , and/or wherein Rand Rare independently selected from substituted or unsubstituted alkyl groups having in the range of from 1 to 5 carbon atoms.10. The method of claim 8 , wherein the quat metal corrosion inhibitor comprises benzyldimethyldodecylammonium chloride.11. The method of claim 8 , wherein the amount of quat metal corrosion inhibitor in the composition is in the range of from 0.001 wt./wt. % to 0.01wt./wt. % based on the total weight of the composition.12. The method of claim 1 , wherein the composition has a pH in the range of from 3 to 5.13. The method of claim 1 , wherein the ...

INTEGRATED CIRCUIT STRUCTURE TO REDUCE SOFT-FAIL INCIDENCE AND METHOD OF FORMING SAME

This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap. 1. An integrated circuit (IC) structure comprising:a semiconductor structure;a first source/drain region formed in the semiconductor structure;a second source/drain region formed in the semiconductor structure;a metal gate positioned on the semiconductor structure adjacent to and between the first source/drain region and the second source/drain region, the metal gate including a first metal;a metal cap positioned on the metal gate, wherein the metal cap has a different metal composition than the first metal, and wherein the metal cap has a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm;a first dielectric cap layer positioned on at least a portion of the semiconductor structure;a first inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein a height of an upper surface of the first ILD above the semiconductor structure is greater than a height of an upper surface of the metal gate above the semiconductor structure;a second ...

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure and a second gate structure formed over a fin structure;raised source and drain regions formed adjacent to the first gate structure; andraised source and drain regions formed adjacent to the second gate structure,wherein side surfaces of the raised source and drain regions of the first gate structure contact a first liner material covering a portion of the first gate structure, which first liner material extends to an upper surface of the fin structure,wherein the side surfaces of the raised source and drain regions of the first gate structure are separated from a first spacer material formed on the first gate structure by the first liner material covering the portion of the first gate structure, andwherein side surfaces of the raised source and drain regions of the second gate structure contact a side surface of a second liner material covering a portion of the second gate structure and a side surface of a second spacer material formed on the second gate structure which is not covered by the second liner material.2. The structure of claim 1 , wherein the first gate structure is a gate structure of an N-type FET (NFET) and the second gate structure is a gate structure of a P-type FET (PFET).3. The structure of claim 2 , wherein:the first liner material and first spacer material formed on the first gate structure form a first sidewall spacer on a side surface of the first ...