Precursors for deposition of silicon nitride,silicon oxynitride and metal silicon oxynitrides

APPARATUS AND PROCEDURE FOR THE MINIMIZATION OF PARASITI CVD DURING THE ATOM LAYER COATING

RADICAL-SUPPORTED SEQUENTIAL ONE GASPHASENABCHEIDUNG

METHOD FOR ENERGY-ASSISTED ATOMIC LAYER DEPOSITON AND REMOVAL

Semiconductor device and method for manufacturing semiconductor device

A method for manufacturing a semiconductor device in which a film of an oxide of Hf1-xAlx (0 Подробнее

STRUCTURE HAS HEAD TANK.

Formation of insulating nanostructured materials by controlled growth on a semiconductor material for the fabrication of capacitance devices such as Dynamic Random Access Memory

Technique de formation de matériaux isolants nanostructurés Une technique de formation de matériau diélectrique nanostructuré au-dessus d'un matériau semi-conducteur ou d'un matériau conducteur caractérisée en ce qu'elle consiste en un cycle de réactions moléculaires et de saturation des surfaces comprenant des étapes successives et indissociables pour faire croître un matériau isolant à nanostructures dont chaque nanostructure peut être épaisse de 4, 10 ou 15 Angstroms et formant des composés stables comme par exemple des composés de LaaHfbOcNd entrant dans la fabrication de mémoires DRAM, de transistor et de composants passifs et capacitifs et permettant d'atteindre des épaisseurs électriques équivalentes en dioxyde de silicium inférieures à 8 Angstroms.

STRUCTURE HAS HEAD TANK.

La présente invention concerne un procédé de fabrication d'une structure de type semi-conducteur sur isolant comprenant une couche semi-conductrice (11) d'un substrat donneur (10), une couche isolante (60) et un substrat receveur (20), le procédé comprenant le collage du substrat donneur (10) sur le substrat receveur (20), l'un au moins des substrats étant recouvert d'une couche isolante. Le procédé comprend la formation à l'interface de collage d'une couche (30) dite de piégeage comprenant des pièges électriquement actifs aptes à retenir des porteurs de charges. L'invention concerne également une structure de type semi-conducteur sur isolant comprenant une couche de piégeage.

ALD of metal silicate films

Semiconductor device including capacitor and method for fabricating the same

Capacitor of a semiconductor device and manufacturing method whereof

산화 알루미늄막/고유전체막/산화 알루미늄막으로 구성된 유전막을 포함하는 반도체 소자의 커패시터 및 그 제조방법에 대하여 개시한다. 본 발명에 의한 반도체 소자의 커패시터는 반도체 기판에 형성된 커패시터 하부 전극과 커패시터 하부 전극 상에 산화 알루미늄으로 형성된 제1 유전막, 제1 유전막 상에 산화 알루미늄보다 유전 상수가 큰 물질로 형성된 제2 유전막 및 제2 유전막 상에 산화 알루미늄으로 형성된 제3 유전막으로 구성된 유전막과 이 유전막 상에 형성된 커패시터 상부 전극을 포함한다. 본 발명에 의한 커패시터는 전력의 소모가 적고 고집적화에 유리하도록 단위 면적당 높은 커패시턴스를 갖는 등 여러 가지 전기적 특성이 우수하다. A capacitor of a semiconductor device comprising a dielectric film composed of an aluminum oxide film / a dielectric film / aluminum oxide film and a method of manufacturing the same are described. The capacitor of the semiconductor device according to the present invention includes a capacitor lower electrode formed on a semiconductor substrate and a first dielectric film formed of aluminum oxide on the capacitor lower electrode, a second dielectric film formed of a material having a larger dielectric constant than aluminum oxide on the first dielectric film, and a first dielectric film. A dielectric film composed of a third dielectric film formed of aluminum oxide on the second dielectric film and a capacitor upper electrode formed on the dielectric film. The capacitor according to the present invention is excellent in various electrical characteristics, such as low power consumption and high capacitance per unit area, which is advantageous for high integration.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CAPACITOR WITH ENHANCED STRUCTURE FOR PREVENTING FALL-DOWN OF LOWER ELECTRODE AND IMPROVING CAPACITANCE

PURPOSE: A method of manufacturing a semiconductor device with a capacitor is provided to prevent the fall-down of a lower electrode and to improve capacitance by inserting partially the lower electrode into a landing pad. CONSTITUTION: A first insulating layer(110) with contact plugs(115) is formed on a semiconductor substrate(100). A second insulating layer(120) with landing pads(125a) connected to the contact plugs is formed thereon. An etch stop layer(130a) and a third insulating layer are sequentially formed on the resultant structure. Third holes for exposing the landing pads to the outside are formed in the third insulating layer and the etch stop layer by using etching. The exposed landing pad is selectively etched. A lower electrode(140a) is formed on the landing pad through the third hole. © KIPO 2005 ...

CAPACITOR WITH DIELECTRIC LAYER MIXED WITH HfO2 AND Al2O3 AND MANUFACTURING METHOD THEREOF FOR RESTRAINING LEAKAGE CURRENT AND PREVENTING DEGRADATION OF ELECTRICAL PROPERTIES

PURPOSE: A capacitor with a dielectric layer and a manufacturing method thereof are provided to restrain leakage current at a high voltage level and to prevent the degradation of electrical properties due to a heat treatment by forming the dielectric layer using HfO2 and Al2O3. CONSTITUTION: A capacitor includes a lower electrode(21), a dielectric layer(22) on the lower electrode, and an upper electrode(23) on the dielectric layer. The dielectric layer includes a predetermined dielectric film mixed with HfO2 and Al2O3. The predetermined dielectric film is formed on the lower electrode and under the upper electrode within the dielectric layer by using an ALD(Atomic Layer Deposition). © KIPO 2006 ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE THEREOF

A method for manufacturing a semiconductor device, which comprises forming a zirconium silicate layer (103) on a silicon substrate (100) and simultaneously a zirconium oxide layer (102) on the zirconium silicate layer (103) and then removing the zirconium oxide layer (102) to thereby form a gate insulating film (104) consisting essentially of the zirconium silicate layer (103). © KIPO & WIPO 2007 ...

METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE USING ATOMIC LAYER DEPOSITIONS FOR ACQUIRING NANO-CRYSTAL WITH UNIFORM SIZE AND PROPER DENSITY

PURPOSE: A method of manufacturing a nonvolatile memory device is provided to acquire a nano-crystal structure with uniform size and proper density by performing repeatedly ALDs(Atomic Layer Depositions). CONSTITUTION: A tunnel insulating layer is formed on a semiconductor substrate(13). The substrate is loaded into an ALD apparatus(15). An aiming nano-crystal structure is formed on the tunnel insulating layer by using a plurality of ALDs(30). The substrate is unloaded from the ALD apparatus(32). A control gate insulating layer is formed on the resultant structure(35). A control gate electrode is formed on the control gate insulating layer(37). © KIPO 2006 ...

Charge reservoir structure

The present invention relates to a production process of a semiconductor on insulator type structure comprising a semiconductor layer (11) of a donor substrate (10), an insulator layer (60) and a receiver substrate (20), the process comprising the bonding of the donor substrate (10) on the receiver substrate (20), at least one of the substrates being coated with an insulator layer, characterised in that it comprises the formation at the bonding interface of a so-called trapping interface (30) comprising electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure comprising a trapping interface. COPYRIGHT KIPO & WIPO 2010 ...

INSULATING FILM AND SEMICONDUCTOR APPARATUS, CAPABLE OF IMPROVING LEAK PROPERTY AND INTERFACIAL STABILITY BY FORMING AN INSULATING LAYER WITH A LAMINATE-TYPED STRUCTURE

PURPOSE: An insulating film and a semiconductor apparatus are provided to offer the insulating film having high reliability for a long time by a small amount of leak electric currents. CONSTITUTION: A semiconductor apparatus includes a semiconductor substrate, an insulating layer, a gate electrode, and source and drain regions. The insulating layer is formed on the semiconductor substrate and has an insulating film. The gate electrode is provided to the insulating layer. The source and drain regions are maintained on a surface of the semiconductor substrate. An area of a lower part of the gate electrode is formed between the source and drain regions. The semiconductor apparatus includes a first electrode, an insulating layer, and a second electrode. The insulating layer is formed on the first electrode and has the insulating film. The second electrode is formed on the insulating layer. © KIPO 2007 ...

Method of improving to deposit dielectric

A method of improving to deposit dielectric, is for making a MOS. A special process pretreats a surface contained silicon oxide. Then a high dielectric material layer is formed on the treated surface contained silicon oxide by a deposition process. The special process is to form a nitrogen contained bonding or hydroxyl contained boding on the surface contained silicon oxide.

Ferroelectric memory transistor and method for forming the same

An object of the present invention is to provide a non-volatile ferroelectric memory device, which eliminates leakage-related transistor memory retention degradation. A ferroelectric memory transistor according to the present invention comprises: a substrate having a source region, a gate region, and a drain region; a gate stack located on the gate region, including: a high-k insulator element, including a first high-k cup and a second high-k cup; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator element; a passivation oxide layer located over the substrate and gate stack; and metalizations to form respective contacts to the source region, the drain regions and the gate stack.

PROCESS GAS DELIVERY FOR SEMICONDUCTOR PROCESS CHAMBER

Methods and apparatus for a gas delivery assembly are provided herein. In some embodiments, the gas delivery assembly includes a gas inlet funnel having a first volume; and a gas conduit having an inlet to receive a gas and an outlet to facilitate the flow of the gas out of the gas conduit and into the first volume, wherein the gas conduit has a second volume less than the first volume, and an increasing cross-section from a first cross-section proximate the inlet to a second cross-section proximate the outlet, wherein the second cross-section is non-circular. In some embodiments, each conduit has a longitudinal axis that intersects a central axis of the gas inlet funnel.

METHODS OF FORMING INTERFACIAL LAYERS FOR HIGH-K GATES BY OZONE OXIDATION

A new method of forming an interfacial oxide layer for gate structures is provided. The method comprises ozone oxidation of a silicon substrate at low temperatures to form an interfacial oxide layer. A method of making gate stacks is also provided which includes forming an interfacial oxide layer on the top surface of a silicon substrate by ozone oxidation at a low temperature, and depositing dielectric layers on the top of the interfacial oxide layer.

SYSTEM AND METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC FILMS

The present invention provides systems and methods for mixing precursors such that a mixture of precursors are present together in a chamber during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The precursors are comprised of at least one different chemical component, and such different components will form a mono-layer to produce a multi-component film. In a further aspect of the present invention, a dielectric film having a composition gradient is provided.

Radical-assisted sequential CVD

A new method for CVD deposition on a substrate is taught wherein radical species are used in alternate steps to depositions from a molecular precursor to treat the material deposited from the molecular precursor and to prepare the substrate surface with a reactive chemical in preparation for the next molecular precursor step. By repetitive cycles a composite integrated film is produced. In a preferred embodiment the depositions from the molecular precursor are metals, and the radicals in the alternate steps are used to remove ligands left from the metal precursor reactions, and to oxidize or nitridize the metal surface in subsequent layers. A variety of alternative chemistries are taught for different films, and hardware combinations to practice the invention are taught as well.

System and method for forming a gate dielectric

A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydroflouric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH₃ in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH₃, forming the stack after the pre-treating, and providing a flow of N₂ in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming. The pre-treating includes providing an inert gas flow in a process zone surrounding the HF-last surface, reacting hydrogen with an oxidizer in the process zone for a very short ...

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.

Reverse ALD

A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.

Methods of forming a thin layer including hafnium silicon oxide using atomic layer deposition and methods of forming a gate structure and a capacitor including the same

Methods of forming a thin film include applying a first reactant to a substrate, chemisorbing a first portion of the first reactant and physisorbing a second portion of the first reactant on the substrate, applying a first oxidizer to the substrate, chemically reacting the first oxidizer with the first portion of the first reactant to form a first solid material on the substrate, applying a second reactant to the first solid material, chemisorbing a first portion of the second reactant and physisorbing a second portion of the second reactant on the first solid material, applying a second oxidizer to the first solid material; and chemically reacting the second oxidizer with the first portion of the second reactant to form a second solid material on the first solid material.

Method of manufacturing a dielectric layer and corresponding semiconductor device

A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.

High charge storage density integrated circuit capacitor

An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

Nanolaminates of hafnium oxide and zirconium oxide

A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric layer containing a HfO2/ZrO2 nanolaminate may be realized in a wide variety of electronic devices and systems.

Hafnium tantalum oxide dielectrics

A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same

Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO₂ layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf_1-xLa_xO layer on the bottom electrode; and a top electrode on the Hf_1-xLa_xO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf_1-xLa_xO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf_1-xLa_xO layer and removing impurities existed within the Hf_1-xLa_xO layer; nitriding a surface of the crystallized Hf_1-xLa_xO layer; and forming the top ...

Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device

A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.

Scalable gate and storage dielectric

Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

METHOD OF FORMING HIGH-K DIELECTRIC FILMS BASED ON NOVEL ZIRCONIUM, AND HAFNIUM PRECURSORS AND THEIR USE FOR SEMICONDUCTOR MANUFACTURING

Method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (I): (M11-aM2a)ObNc, (I) wherein 0 ≤ a < 1, 0 < b ≤ 3, 0 ≤ c ≤ 1, M1 represents a metal selected from (Hf), (Zr) and (Ti); and M2 represents a metal atom atoms, which comprises the following steps: - A step a) of providing a substrate into a reaction chamber; - A step (b) of vaporizing a M1 metal containing precursor selected from: Zr(MeCp)(NMe2)3, Zr(EtCp)(NMe2)3, ZrCp(NMe2)3, Zr(MeCp)(NEtMe)3, Zr(EtCp)(NEtMe)3, ZrCp(NEtMe)3, Zr(MeCp)(NEt2)3, Zr(EtCp)(NEt2)3, ZrCp(NEt2)3, Zr(iPr2Cp)(NMe2)3, Zr(tBu2Cp)(NMe2)3, Hf(MeCp)(NMe2)3, Hf(EtCp)(NMe2)3, HfCp(NMe2)3, Hf(MeCp)(NEtMe)3, Hf(EtCp)(NEtMe)3, HfCp(NEtMe)3, Hf(MeCp)(NEt2)3, Hf(EtCp)(NEt2)3, HfCp(NEt2)3, Hf(iPr2Cp)(NMe2)3, Hf(tBu2Cp)(NMe2)3, to form a first gas phase metal source; - A step c) of introducing the first gas phase metal source in the reaction chamber, in order to provoke their contact with said substrate, to generate ...

Producing isolator thin film on substrate involves atom deposition of silicon atom layer on substrate, oxygen atom layer on silicon atom layer and atom deposition of metal-atom layer on substrate, oxygen atom layer on metal-atom layer

The method involves a first step of producing a silicon atom layer on the substrate (100) and an oxygen atom layer on the silicon atom layer and a second step of producing a metal-atom layer on the substrate and an oxygen atom layer on the metal-atom layer, whereby all the layers are produced by an atom deposition process. The concentration of metal atoms in the thin film is controlled by controlling the number of implementations of the first and second steps. An independent claim is also included for a method of manufacturing a semiconductor component including a step for producing an isolator thin film.

SYSTEM AND METHOD FOR THE PRODUCTION OF ZIRCONUND/ODER HAFNIUMHÄLTIGER LAYERS

PROCEDURE FOR THE PRODUCTION OF ALUMINUM-BEARING OF FILMS OF MEANS AMINO ALUMINUM PRECURSOREN

Hafnium alloy target and process for producing the same

JUST ELECTRONIC CIRCUIT INCLUDING/UNDERSTANDING a THIN PORTION OF LAYER CONTAINING HAFNIUM OXIDE.

Integrated electronic circuit, has hafnium oxide based electrically isolating thin layer portion containing atoms of magnesium under form of oxide mixing of hafnium and magnesium and separated of transistor channel by intermediate layer

Un circuit électronique intégré comprend une portion de couche mince à base d'oxyde d'hafnium (1). Selon l'invention, cette portion contient en outre des atomes de magnésium, sous forme d'un oxyde mixte d'hafnium et de magnésium. Une telle portion présente une permittivité diélectrique élevée et un courant de fuite très faible. Elle est particulièrement adaptée pour former une partie d'une couche d'isolation de grille d'un transistor MOS ou une partie d'un diélectrique de condensateur MIM.

Method of forming a dielectric layer in semiconductor memory device

본 발명은 반도체 기판 상에 제1 산화막을 형성하는 단계; 상기 제1 산화막 상에 고유전체막을 형성하는 단계; 후속의 열처리 공정시 상기 고유전체막이 비정질 박막 특성을 유지하기 위한 플라즈마 산화 처리 공정을 실시하는 단계; 및 상기 고유전체막 상에 제2 산화막을 형성하는 단계를 포함하는 반도체 메모리 소자의 유전체막 형성 방법으로 이루어진다. The present invention comprises the steps of forming a first oxide film on a semiconductor substrate; Forming a high dielectric film on the first oxide film; Performing a plasma oxidation process to maintain the amorphous thin film characteristics of the high-k dielectric film in a subsequent heat treatment process; And forming a second oxide film on the high dielectric film. 유전체막, 산화막, 질화막, 고유전체, 플라즈마, 누설전류, 결정화 Dielectric, Oxide, Nitride, High Dielectric, Plasma, Leakage Current, Crystallization

METHOD OF FORMING GATE INSULATING FILM, STORAGE MEDIUM AND COMPUTER PROGRAM

METHOD FOR FORMING HIGH DIELECTRIC FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Disclosed is a method for forming a high dielectric film, which comprises a step for forming a high dielectric film on a substrate by ALD or CVD using an organic metal raw material at a temperature not more than 350°C, and a step for eliminating hydrogen in the high dielectric film by irradiating the film with ultraviolet light in an oxygen-containing atmosphere at a low pressure.Also disclosed is a method for manufacturing a semiconductor device, which comprises a step for forming a high dielectric film as a gate insulating film on a semiconductor substrate by ALD or CVD using an organic metal raw material at a temperature not more than 350°C, a step for eliminating hydrogen in the high dielectric film by irradiating the film with ultraviolet light in an oxygen-containing atmosphere at a low pressure, and a step for forming a gate electrode on the high dielectric film. © KIPO & WIPO 2009 ...

MULTIPLE DIELECTRIC FILM FOR A SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF, CAPABLE OF OBTAINING A MULTIPLE DIELECTRIC FILM HAVING HIGH DIELECTRIC CONSTANT FORMING A THIN FILM USING A COMPOSITE LAYER COMPOSED OF ZIRCONIUM-HAFNIUM OXIDE AND A METAL OXIDE LAYER COMPOSED OF AN AMORPHOUS METAL OXIDE

PURPOSE: A multiple dielectric film for a semiconductor device and a method for manufacturing the same are provided to prevent oxidization of a lower electrode during a formation of a capacitor of the semiconductor device, thereby reducing the leakage current of the semiconductor device by using the multiple dielectric film as a dielectric film of the semiconductor device. CONSTITUTION: A multiple dielectric film(130) for a semiconductor device includes at least two staked dielectric layers. Each of the dielectric layers is made of a composite layer(110) composed of a zirconium-hafnium oxide or a metal oxide layer(120) composed of an amorphous metal oxide. Adjacent dielectric layers are made by different materials. The dielectric layers are three stacked layers. The three stacked layers have a first dielectric layer composed of the composite layer, a second dielectric layer composed of the metal oxide layer, and a third dielectric layer composed of the composite layer. The metal oxide layer ...

NONVOLATILE SEMICONDUCTOR MEMORY FOR ELECTRICALLY REWRITING OF DATA AND A MANUFACTURING METHOD THEREOF

PURPOSE: A nonvolatile semiconductor memory and a manufacturing method thereof are provided to improve a data retention characteristic by thickly forming a barrier insulation film to a top insulating layer. CONSTITUTION: A nonvolatile semiconductor memory has a plurality of memory strings in which a plurality of memory cells for electrically rewriting of data which is serially connected. The memory strings comprises a pillar shape semiconductor, a first charge storing layer, a first block insulating film(22) and a first conductive film. The pillar semiconductor is extended to a vertical direction about substrate. The first charge storing layer is contacted to the pillar semiconductor. The first charge storing layer accumulates electric charge. The first block insulating film contacts to the first charge storing layer. The first conductive film contacts to the first block insulating film. © KIPO 2009 ...

METHOD OF FORMING DIELECTRIC FILMS

A method for depositing a high-k dielelectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate. © KIPO & WIPO 2007 ...

METHOD OF CLUSTERING SEQUENTIAL PROCESSING FOR A GATE STACK STRUCTURE

A method of forming a gate dielectric comprising silicon and oxygen is provided. The gate dielectric may also include nitrogen or another high k material. In one aspect, forming the gate dielectric includes annealing a substrate in an oxidizing atmosphere to form a silicon oxide layer, depositing a silicon nitride layer or a high k layer on the silicon oxide layer by a vapor deposition, oxidizing an upper surface of the silicon nitride layer or high k layer, and then annealing the substrate. The gate dielectric may be formed within an integrated processing system. COPYRIGHT KIPO & WIPO 2010 ...

NITRIDING METHOD FOR INSULATION FILM, SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE, SUBSTRATE TREATING DEVICE AND SUBSTRATE TREATING METHOD

Nitrogen radicals are formed by high- frequency plasma, and the nitrogen radicals are supplied onto the surface of an insulation film containing oxygen to thereby nitride the surface of the insulation film. The oxygen-containing insulation film is up to 0.4 nm in thickness, and a high- dielectric film is formed on the surface- nitrided insulation film. The nitrogen radicals are supplied by a gas flow formed so as to move along the surface of the insulation film. © KIPO & WIPO 2007 ...

Silicon oxide cap over high dielectric constant films

A method for forming an integrated circuit structure on a semiconductor substrate comprises depositing a high k gate dielectric material over the substrate using an atomic layer deposition process. A silicon oxide capping layer is deposited over the gate dielectric material in a rapid thermal chemical vapor deposition process. A gate electrode is formed over the silicon oxide capping layer.

NITRIDING METHOD FOR INSULATION FILM, SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE, SUBSTRATE TREATING DEVICE AND SUBSTRATE TREATING METHOD

A method of nitriding an insulation film includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulation film.

Integrated circuit devices including a dual gate stack structure and methods of forming the same

Method for energy-assisted atomic layer deposition and removal

A method for energy-assisted atomic layer deposition and removal of a dielectric film are provided. In one embodiment a substrate is placed into a reaction chamber and a gaseous precursor is introduced into the reaction chamber. Energy is provide by a pulse of electromagnetic radiation which forms radical species of the gaseous precursor. The radical species react with the surface of the substrate to form a radical terminated surface on the substrate. The reaction chamber is purged and a second gaseous precursor is introduced. A second electromagnetic radiation pulse is initiated and forms second radical species. The second radical species of the second gas react with the surface to form a film on the substrate. Alternately, the gaseous species can be chosen to produce radicals that result in the removal of material from the surface of the substrate.

SEMICONDUCTOR DEVICE AND MAKING THEREOF

By forming a conductive smoothing layer (16, 19) over the bottom electrode (11) and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, a first layer (16) including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer (14) formed of a refractory nitride. In addition, a second layer (19) including a refractory metal (18) or a refractory metal-rich nitride may be formed on the capacitor dielectric. The conductive smoothing layer (16, 19) could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND ELECTRONIC APPARATUS

An semiconductor device (1) of the invention includes a semiconductor substrate provided with a channel region (21), a source region (22) and a drain region (23), a gate insulating film (3) laminated on the channel region (21), and a gate electrode (5). The gate insulating film (3) is formed of an insulative inorganic material as a main material, and further contains hydrogen. The absorbance of infrared radiation of which wave number is in the range of 3200 to 3500 cm-1is 0.02 or less when the gate insulating film (3) to which an electric field has never been applied is measured with Fourier Transform Infrared Spectroscopy at room temperature.

Graded dielectric structures

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

High κ gate stack on III-V compound semiconductors

A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

Method of manufacturing a semiconductor device

A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming a first amorphous insulating film comprising a first element on a substrate; adding a second element different from the first element to the first amorphous insulating film so as to form a second amorphous insulating film on the substrate; and annealing the second amorphous insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second amorphous insulating film. The concentration of the second element added to the first amorphous insulating film is controlled according to the annealing temperature.

NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT EXCELLENT IN CHARGE RETENTION PROPERTIES AND PROCESS FOR PRODUCING THE SAME

A nonvolatile semiconductor memory element enabling to improve insulation performance of an insulator around a floating gate and to decrease the ratio of oxidized metal ultrafine particles in the floating gate, are provided. In a process for producing nonvolatile semiconductor memory element comprising a floating gate made of a hardly oxidizable material having a Gibbs' formation free energy for forming its oxide higher than that of Si in a range of from 0° C. to 1,200° C., and an insulator made of an oxide of an easily oxidizable material surrounding the floating gate and having such an energy equivalent or lower than that of Si, the floating gate made of hardly oxidizable material is formed by using a physical forming method, the oxide of the easily oxidizable material is formed by using a physical forming method or a chemical forming method, and after a gate insulation film is formed, a heat treatment is carried out in a mixed atmosphere of an oxidizing gas and a reducing gas in a temperature ...

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof

Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.

ALD of metal silicate films

Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a metal source chemical, a silicon source chemical and an oxidizing agent. In preferred embodiments, an alkyl amide metal compound and a silicon halide compound are used. Methods according to preferred embodiments can be used to form hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surfaces comprising high aspect ratio features (e.g., vias and/or trenches).

Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure

In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.

Semiconductor device and manufacturing method therefor

A first insulating film is formed on a base substrate, then a second insulating film is formed on the first insulating film, the second insulating film having a relative permittivity higher than that of the first insulating film. A gate electrode is formed on the second insulating film. The second insulating film forming includes first to sixth steps, and a cycle consisting of the first to sixth steps is repeated.

Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride

Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Metal interconnection of a semiconductor device and method of fabricating the same

Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.

Process gas delivery for semiconductor process chambers

Methods for gas delivery to a process chamber are provided herein. In some embodiments, a method may include flowing a process gas through one or more gas conduits, each gas conduit having an inlet and an outlet for facilitating the flow of gas through the gas conduits and into a gas inlet funnel having a second volume, wherein each gas conduit has a first volume less than the second volume, and wherein each gas conduit has a cross-section that increases from a first cross-section proximate the inlet to a second cross-section proximate the outlet but excluding any intersection points between the gas inlet funnel and the gas conduit, and wherein the second cross-section is non-circular; and delivering the process gas to the substrate via the gas inlet funnel.

Method of forming a film containing dysprosium oxide and hafnium oxide using atomic layer deposition

The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized ...

Semiconductor device and method for manufacture thereof

A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.

METHOD OF FORMING DIELECTRIC FILMS

A method of forming dielectric films including a metal silicate on a silicon substrate comprises a first step of oxidizing a surface layer portion of the silicon substrate and forming a silicon dioxide film; a second step of irradiating ion on the surface of the silicon dioxide film and making the surface layer portion of the silicon dioxide film into a reaction-accelerating layer with Si-O cohesion cut; a third step of laminating a metal film on the reaction-accelerating layer in a non-oxidizing atmosphere; and a fourth step of oxidizing the metal film and forming a metal silicate film that diffuses a metal from the metal film to the silicon dioxide film.

Composite dielectric forming methods and composite dielectrics

A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide can be thermally stable, crystalline hafnium oxide and the lanthanum oxide can be thermally stable, crystalline lanthanum oxide. A transistor may comprise the composite dielectric as a gate dielectric. A capacitor may comprise the composite dielectric as a capacitor dielectric.

METHODS FOR FORMING ALUMINUM CONTAINING FILMS UTILIZING AMINO ALUMINUM PRECURSORS

DEVICE AND METHOD FOR PROCESSING SUBSTRATE

A method of fabricating a memory device includes preparing a silicon substrate; depositing a layer of high-k insulator on the silicon substrate; depositing a buffering layer on the high-k insulating layer; depositing a layer of ferroelectric material on the buffering layer by metal organic chemical vapor deposition; forming a top electrode on the layer of ferroelectric material; and completing the device obtained by above steps.

Halbleiteranordnungen und Verfahren zur Herstellung derselben

Halbleiteranordnungen und Verfahren zur Herstellung derselben werden offenbart. Ein bevorzugtes Ausführungsbeispiel umfasst ein Verfahren zum Ausbildung einer Materialschicht. Das Verfahren beinhaltet ein Ausbilden zumindest einer ersten Schicht eines ersten Materials und ein Ausbilden zumindest einer zweiten Schicht eines zweiten Materials über der zumindest einen ersten Schicht vom ersten Material. Das erste Material umfasst ein Oxid oder ein Silikat von Hf, Zr oder La. Das zweite Material umfasst ein Siliziumoxinitrid von Hf, Zr oder La.

Dielektrische Mehrfachschicht, mikroelektronisches Bauelement, Kondensator und Herstellungsverfahren

Die Erfindung bezieht sich auf eine dielektrische Mehrfachschicht, ein mikroelektronisches Bauelement, einen Kondensator und zugehörige Herstellungsverfahren. DOLLAR A Erfindungsgemäß beinhaltet die dielektrische Mehrfachschicht eine Kompositschicht aus einem Oxid von zwei oder mehr verschiedenen Elementen in einer nicht-laminaren Struktur und eine Einzelschicht aus einem Oxid eines einzelnen Elements auf wenigstens einer Oberfläche der Kompositschicht. DOLLAR A Verwendung z. B. in der Technik hochintegrierter Halbleiterbauelemente.

Non aqueous thin film formation

DIELECTRIC BOUNDARY SURFACE FOR A GROUP III VHALBLEITERBAUELEMENT

PROCEDURE FOR MANUFACTURING DIELECTRIC FILMS WITH HIGH K-VALUE ON BASIS NEW ZIRCON AND HAFNIUM FORERUNNER AND YOUR USE FOR THE SEMICONDUCTOR MANUFACTURE

NITRIDATION OF HIGH-K DIELECTRICS

SYSTEMS AND METHODS FOR FORMING ZIRCONIUM AND/OR HAFNIUM-CONTAINING LAYERS

Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricating the same

METHOD FOR DEPOSITING ALD THIN FILM USING Al2O3, HfO2, AND ZrO2 TO ENHANCE PRODUCTIVITY

PURPOSE: A method for depositing an ALD thin film is provided to enhance productivity by removing a layer including Al2O3, HfO2, and ZrO2 without opening a reaction chamber. CONSTITUTION: A substrate is loaded on a wafer block(S1). An ALD layer is deposited on an upper surface of the substrate(S2). The substrate including the ALD thin film is unloaded from the wafer block(S3). A dummy substrate is loaded on the wafer block(S4-1). A pre-conditioning process is performed by using an inert gas or a mixed gas of the inert gas and a cleaning gas(S4-2). A stacked layer is removed from a surface of a shower head by activating the cleaning gas(S4-3). The dummy substrate is unloaded from the wafer block(S4-4). A new dummy substrate is loaded on the wafer block and the above processes are performed repeatedly(S4-5). A reaction chamber is purged by using the inert gas(S5). © KIPO 2005 ...

A METHOD FOR FORMING A THIN COMPLETE HIGH-PERMITTIVITY DIELECTRIC LAYER

A method for forming a thin complete high-k layer (106, 207) for semiconductor applications. The method includes providing a substrate (25, 102, 202, 406) in a process chamber (10, 402), depositing a thick complete high-k layer (206) on the substrate (25, 102, 202, 406), and thinning the deposited high-k layer (206) to form a thin complete high-k layer (106, 207) on the substrate (25, 102, 202, 406). Alternately, the substrate (25, 102, 202, 406) can contain an interface layer (104, 204) between the substrate (25, 102, 202, 406) and the high-k layer (106, 207). The thinning can be performed by exposing the thick high-k layer (206) to a reactive plasma etch process or, alternately, a plasma process capable of modifying a portion of the thick high-k layer (206) and subsequently removing the modified portion (206a) of the thick high-k layer (206) using wet processing. © KIPO & WIPO 2007 ...

Fabricating method for semiconductor device comprising capacitor

LIQUID MATERIAL CARBURETOR, AND FILMING DEVICE USING THE CARBURETOR

HAFNIUM ALLOY TARGET AND PROCESS FOR PRODUCING THE SAME

A hafnium alloy target characterized in that either or both of Zr and Ti are contained in a total amount of 100 wt.ppm to 10 wt.% in I and Hf. The average crystal grain diameter thereof is in the range of 1 to 100 μm, and the content of each of impurities Fe, Cr and Ni therein is 1 wt.ppm or less. Further, with respect to the hafnium alloy target, the crystal habit face orientation factor of four planes consisting of {002} plane and, lying within 35° from this plane, {103}, {014} and {015} planes is 55% or greater, and the dispersion of total of four-plane intensity ratios depending on locations is 20% or less. The hafnium alloy target excels in film forming property and film forming rate, can reduce particle occurrence and is suitable for formation of a high dielectric gate insulating film such as HfO film or HfON film. Further, there is provided a process for producing the hafnium alloy target. © KIPO & WIPO 2007 ...

METHOD FOR FORMING A METAL OXIDE LAYER USING AN ATOMIC LAYER DEPOSITION, CAPABLE OF EASILY CONTROLLING PLASMA POWER BY UNIFORMLY GENERATING REFLECTED POWER

A method for forming a metal oxide layer using an atomic layer deposition is provided to easily control plasma power by reducing reflected power and uniformly generating the reflected power. First metal source gas excluding the amino group and the alkoxyl group is supplied in a chemical reactor where a substrate is formed(S120). Second metal source gas containing the amino group or the alkoxyl group is supplied in the chemical reactor(S130). Plasma of reactive gas including oxygen is formed in the chemical reactor to reduce or make uniform the reflected gas generated from the chemical reactor(S140). The metal element of the second metal source gas is excluded in a metal oxide layer. The first metal source gas is TMA(Tri Methyl Aluminum), DMAH(DiMethyl Aluminum Hydride), DMAH-EPP(DiMethyl Aluminum Hydride-Ethyl PiPeridine), and DMAP(DiMethyl Aluminum Peridine). The second metal source gas is TEMAH(Tetrakis EthylMethyAmino Hafnium), TDEAH(Tetrakis DiEthylAmino Hafnium), TDMAH(Tetrakis DiMethylAmino Hafnium), TEMAZ(Tetrakis EthylMethylAmino Zirconium), TDEAZ(Tetrakis DiRthylAmino Zirconium), TDMAZ(Tetrakis DiMethylAmino Zirconium), TDMAT(Tetrakis DiMethylAmino Titanium), TDEAT(Tetrakis DiEthylAmino Titanium), TEMAT(Tetrakis EthylMethylAmino Titanium), PEMAT(Pentakis EthylAmino Tantalum), PDMAT(Petakis DiMethylAmino Tantalum), PDEAT(Pentakis DiEthylAmino Tantalum), and TBTDET(Tert-Butylimido-Tris-Dithylamino tantalum).

MANUFACTURING METHOD FOR SEMICONDUCTOR APPARATUS

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS

적어도 1매의 기판을 처리실 내에 반입하는 공정과, 제1 원료인 금속 화합물 또는 규소 화합물, 제2 원료인 산소 원자를 포함하는 산화 원료, 및 제3 원료인 원자상(原子狀) 수소를 상기 처리실 내에 소정 회수를 반복적으로 공급하여 상기 기판 표면에 금속 산화막 또는 규소 산화막을 형성하는 공정과, 상기 기판을 상기 처리실 내로부터 반출하는 공정을 포함하되, 상기 제2 원료와 상기 제3 원료를 상기 처리실 내에 공급함으로써 상기 기판 표면의 반응 사이트를 OH기로 치환하는 것인 반도체 디바이스의 제조 방법이 개시되어 있다. A process of bringing in at least one substrate into the processing chamber, an oxidation raw material containing a metal compound or silicon compound as a first raw material, an oxygen raw material including an oxygen atom as a second raw material, and atomic hydrogen as a third raw material; And repeatedly supplying a predetermined number of times to form a metal oxide film or silicon oxide film on the surface of the substrate, and carrying out the substrate from the processing chamber, wherein the second raw material and the third raw material are introduced into the processing chamber. The manufacturing method of the semiconductor device which replaces the reaction site of the said board | substrate surface with OH group by supplying is disclosed.

Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same

A high-k dielectric films is provided, which is doped with divalent or trivalent metals to vary the electron affinity, and consequently the electron and hole barrier height. The high-k dielectric film is a metal oxide of either zirconium (Zr) or hafnium (Hf), doped with a divalent metal, such as calcium (Ca) or strontium (Sr), or a trivalent metal, such as aluminum (Al), scandium (Sc), lanthanum (La), or yttrium (Y). By selecting either a divalent or trivalent doping metal, the electron affinity of the dielectric material can be controlled, while also providing a higher dielectric constant material then silicon dioxide. Preferably, the dielectric material will also be amorphous to reduce leakage caused by grain boundaries. Also provided are sputtering, CVD, Atomic Layer CVD, and evaporation deposition methods for the above-mentioned, doped high dielectric films.

Substrate processing method and substrate processing apparatus

A substrate processing method includes: a step of arranging a substrate in a container; an introducing step wherein an H2 gas is introduced into a catalytic reaction section having a catalyst contained therein with a first flow volume, an O2 gas is introduced into the catalytic reaction section with a second flow volume independently from the H2 gas, and an H2O gas generated from the H2 gas and the O2 gas brought into contact with the catalyst is ejected from the catalytic reaction section toward a substrate; and an O2 flow volume reducing step wherein the flow volume of the O2 gas to be introduced into the catalytic reaction section is reduced to a third flow volume which is smaller than the second flow volume. The introducing step and the O2 flow volume reducing step are repeated in this order at a predetermined repetition frequency, and the substrate is processed.

METHODS FOR FORMING ALUMINUM CONTAINING FILMS UTILIZING AMINO ALUMINUM PRECURSORS

Method of forming a semiconductor device having a high-k dielectric

A metal oxide (8) is formed over a high quality oxide (16) which has been deposited over a substrate (12). An anneal drives a reaction to form a metal silicon oxynitrides layer (22) which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices as well as improved leakage currents.

System and method for forming multi-component films

The present invention provides systems and methods for mixing vaporized precursors such that a mixture of vaporized precursors are present together in a chamber during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The vaporized precursors are comprised of at least one different chemical component, and such different components will form a mono-layer to produce a multi-component film. In a further aspect of the present invention, a dielectric film having a composition gradient is provided.

METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE

Disclosed is a method for manufacturing a semiconductor device wherein a first raw material gas containing Si, a second raw material gas containing a metal element M, and an oxidation gas are used. This method for manufacturing a semiconductor device comprises a step for supplying the second raw material gas or a mixed gas of the first raw material gas and the second raw material gas to a substrate to be processed after sequentially performing a first step for supplying the oxidation gas to the substrate to be processed and a second step for supplying the first raw material gas to the substrate to be processed.

METHOD FOR MANUFACTURING SEMICONDUCTOR EPITAXIAL CRYSTAL SUBSTRATE

This invention provides a gallium nitride-type semiconductor epitaxial crystal substrate with a dielectric film, having a low gate leak current and very low and negligible gate lag, drain lag and current collapse characteristics. There is also provided a method for manufacturing a semiconductor epitaxial crystal substrate comprising a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form as a passivation film or a gate insulating film applied onto the surface of a nitride semiconductor crystal layer grown by an organometal vapor phase epitaxial growth method. After the nitride semiconductor crystal layer is grown within an epitaxial growth furnace, the dielectric layer is also continuously grown on the nitride semiconductor crystal layer in the same epitaxial growth furnace.

METHODS FOR FORMING ALUMINUM CONTAINING FILMS UTILIZING AMINO ALUMINUM PRECURSORS

A method of forming an aluminum containing film on a substrate includes providing a precursor having the chemical structure: AI(NR1R2)(NR3R4)(NR5R6); where each of R1, R2, R3, R4, R5 and R6 is independently selected from the group consisting of hydrogen and an alkyl group including at least two carbon atoms. The precursor is utilized to form a film on the substrate including at least one of aluminum oxide, aluminum nitride and aluminum oxy-nitride. Each of the R1 - R6 groups can be the same or different and can by straight or branched chain alkyls. An exemplary precursor that has is useful in forming aluminum containing films is tris diethylamino aluminum.

Conductive layers for hafnium silicon oxynitride

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

Methods of Forming A Semiconductor Device

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Enhanced thin film deposition

Methods of producing metal-containing thin films with low impurity contents on a substrate by atomic layer deposition (ALD) are provided. The methods preferably comprise contacting a substrate with alternating and sequential pulses of a metal source chemical, a second source chemical and a deposition enhancing agent. The deposition enhancing agent is preferably selected from the group consisting of hydrocarbons, hydrogen, hydrogen plasma, hydrogen radicals, silanes, germanium compounds, nitrogen compounds, and boron compounds. In some embodiments, the deposition-enhancing agent reacts with halide contaminants in the growing thin film, improving film properties.

Graded dielectric structures

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

ENHANCED THIN FILM DEPOSITION

Methods of producing metal-containing thin films with low impurity contents on a substrate by atomic layer deposition (ALD) are provided. The methods preferably comprise contacting a substrate with alternating and sequential pulses of a metal source chemical, a second source chemical and a deposition enhancing agent. The deposition enhancing agent is preferably selected from the group consisting of hydrocarbons, hydrogen, hydrogen plasma, hydrogen radicals, silanes, germanium compounds, nitrogen compounds, and boron compounds. In some embodiments, the deposition-enhancing agent reacts with halide contaminants in the growing thin film, improving film properties. 1. (canceled)2. A process for forming an electrode comprising:depositing a high-k layer on a substrate by atomic layer deposition (ALD); andsubsequently depositing a carbon-containing metal film on the substrate by ALD to form an electrode structure comprising a carbon-containing metal film over a high-k layer,wherein the carbon-containing metal film is deposited by a plurality of ALD cycles comprising contacting the substrate with alternating and sequential pulses of a first reactant that comprises the metal of the carbon-containing metal thin film and a second reactant comprising aluminum and carbon.3. The process of claim 2 , additionally comprising depositing a conductive material over the carbon-containing metal thin film.4. The process of claim 3 , wherein the conductive material comprises metal or poly-Si.5. The process of claim 4 , wherein the conductive material is deposited by ALD.6. The process of claim 2 , wherein the deposition of the carbon-containing metal film is selective.7. The process of claim 2 , wherein the first reactant comprises a metal selected from the group consisting of Ti and Nb.8. The process of claim 2 , wherein the first reactant comprises at least one halide ligand.9. The process of claim 8 , wherein the first reactant is selected from the group consisting of TiCland NbCl.10. ...

Methods of forming dielectric films, new precursors and their use in semiconductor manufacturing

Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe 2 ) 3 , Zr(EtCp)(NMe 2 ) 3 , ZrCp(NMe 2 ) 3 , Zr(MeCp)(NEtMe) 3 , Zr(EtCp)(NEtMe) 3 , ZrCp(NEtMe) 3 , Zr(MeCp)(NEt 2 ) 3 , Zr(EtCp)(NEt 2 ) 3 , ZrCp(NEt 2 ) 3 , Zr(iPr 2 Cp)(NMe 2 ) 3 , Zr(tBu 2 Cp)(NMe 2 ) 3 , Hf(MeCp)(NMe 2 ) 3 , Hf(EtCp)(NMe 2 ) 3 , HfCp(NMe 2 ) 3 , Hf(MeCp)(NEtMe) 3 , Hf(EtCp)(NEtMe) 3 , HfCp(NEtMe) 3 , Hf(MeCp)(NEt 2 ) 3 , Hf(EtCp)(NEt 2 ) 3 , HfCp(NEt 2 ) 3 , Hf(iPr 2 Cp)(NMe 2 ) 3 , Hf(tBu 2 Cp)(NMe 2 ) 3 , and mixtures thereof; and depositing the dielectric film on the substrate.

Method of forming dielectric films, new precursors and their use in semiconductor manufacturing

Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe2)3, Zr(EtCp)(NMe2)3, ZrCp(NMe2)3, Zr(MeCp)(NEtMe)3, Zr(EtCp)(NEtMe)3, ZrCp(NEtMe)3, Zr(MeCp)(NEt2)3, Zr(EtCp)(NEt2)3, ZrCp(NEt2)3, Zr(iPr2Cp)(NMe2)3, Zr(tBu2Cp)(NMe2)3, Hf(MeCp)(NMe2)3, Hf(EtCp)(NMe2)3, HfCp(NMe2)3, Hf(MeCp)(NEtMe)3, Hf(EtCp)(NEtMe)3, HfCp(NEtMe)3, Hf(MeCp)(NEt2)3, Hf(EtCp)(NEt2)3, HfCp(NEt2)3, Hf(iPr2Cp)(NMe2)3, Hf(tBu2Cp)(NMe2)3, and mixtures thereof; and depositing the dielectric film on the substrate.

Method of forming high-k dielectric films based on novel titanium, zirconium, and hafnium precursors and their use for semiconductor manufacturing

A method of forming on at least one support at least one metal containing dielectric films having the formula (M11-aMa)ObNc, wherein: 0≤a<1, 0<b≤3, preferably 1.5≤b≤2.5, 0≤c≤1, preferably 0≤c≤0.5 M1 and M2 being metals Hf, Zr or Ti using precursors with pentadienyl ligands and/or cyclopentadienyl ligands.

Hafnium titanium oxide films

Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices.

Etching agent composition for thin films having high permittivity and process for etching

An etching agent composition for thin films having a high permittivity which is an aqueous solution comprising at least one acid selected from organic acids and inorganic acids and a fluorine compound and a process which comprises etching a thin film having a high permittivity using the composition are provided. The composition and the process are used in the process for producing semiconductor devices using thin films having a high permittivity and, in particular, very thin gate insulation films and very thin gate electrodes which are indispensable for enhancing integration and speed of MOSFET.

Method of forming high-k dielectric films based on novel titanium, zirconium, and hafnium precursors and their use for semiconductor manufacturing

A method of forming on at least one support at least one metal containing dielectric films having the formula (M 1 1-a M 2 a ) O b N c , wherein: 0≦a<1, 01 and M 2 being metals Hf, Zr or Ti using precursors with pentadienyl ligands and/or cyclopentadienyl ligands.

Method of forming dielectric films, new precursors and their use in semiconductor manufacturing

Method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (I): (M 1 1-a M 2 a )O b N c ,  (I) wherein 0≦a<1, 0<b≦3, 0≦c≦1, M 1 represents a metal selected from (Hf), (Zr) and (Ti); and M 2 represents a metal atom atoms, which comprises the following steps: A step a) of providing a substrate into a reaction chamber; A step (b) of vaporizing a M 1 metal containing precursor of the formula (II): (R 1 y Op) x (R 2 t Cp) z M 1 R′ 4-x-z ,  (II) wherein 0≦x≦3, preferably x=0 or 1, 0≦z≦3, preferably z=1 or 2, 1≦(x+z)≦4, 0≦y≦7, preferably y=2 0≦t≦5, preferably t=1, (R 1 y Op) represents a pentadienyl ligand, which is either unsubstituted or substituted; (R 2 t Cp) represents a cyclopentadienyl (Cp) ligand, which is either unsubstituted or substituted, to form a first gas phase metal source; A step c) of introducing the first gas phase metal source in the reaction chamber, in order to provoke their contact with said substrate, to generate the deposition of a metal containing dielectric film comprising a compound of the formula (I) as hereinbefore defined, on said substrate. Compound the formula (II 1 ): (R 2 t Cp)M 1 [N(R 39 )(R 40 )] 3   (II 1 ) corresponding to the formula (II) as hereinabove defined in Claim 1 , wherein x=0, z=1 and R′ represents the group N(R 39 )(R 40 ).

Method of forming dielectric films, new precursors and their use in semiconductor manufacturing

Method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (I): (M 1 1-a M 2 a )O b N c ,  (I) wherein 0≦a<1, 0<b≦3, 0≦c≦1, M 1 represents a metal selected from (Hf), (Zr) and (Ti); and M 2 represents a metal atom atoms, which comprises the following steps: A step a) of providing a substrate into a reaction chamber; A step (b) of vaporizing a M 1 metal containing precursor of the formula (II): (R 1 y Op) x (R 2 t Cp) z M 1 R′ 4-x-z   (II) wherein 0≦x≦3, preferably x=0 or 1, 0≦z≦3, preferably z=1 or 2, 1≦(x+z)≦4, 0≦y≦7, preferably y=2 0≦t≦5, preferably t=1, (R 1 y Op) represents a pentadienyl ligand, which is either unsubstituted or substituted; (R 2 t Cp) represents a cyclopentadienyl (Cp) ligand, which is either unsubstituted or substituted, to form a first gas phase metal source; A step c) of introducing the first gas phase metal source in the reaction chamber, in order to provoke their contact with said substrate, to generate the deposition of a metal containing dielectric film comprising a compound of the formula (I) as hereinbefore defined, on said substrate. Compound the formula (II 1 ): (R 2 t Cp)M 1 [N(R 39 )(R 40 )] 3   (II 1 ) corresponding to the formula (II) as hereinabove defined in Claim 1 , wherein x=0, z=1 and R′ represents the group N(R 39 )(R 40 ).

Method of forming dielectric films, new precursors and their use in semiconductor manufacturing

Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe 2 ) 3 , Zr(EtCp)(NMe 2 ) 3 , ZrCp(NMe 2 ) 3 , Zr(MeCp)(NEtMe) 3 , Zr(EtCp)(NEtMe) 3 , ZrCp(NEtMe) 3 , Zr(MeCp)(NEt 2 ) 3 , Zr(EtCp)(NEt 2 ) 3 , ZrCp(NEt 2 ) 3 , Zr(iPr 2 Cp)(NMe 2 ) 3 , Zr(tBu 2 Cp)(NMe 2 ) 3 , Hf(MeCp)(NMe 2 ) 3 , Hf(EtCp)(NMe 2 ) 3 , HfCp(NMe 2 ) 3 , Hf(MeCp)(NEtMe) 3 , Hf(EtCp)(NEtMe) 3 , HfCp(NEtMe) 3 , Hf(MeCp)(NEt 2 ) 3 , Hf(EtCp)(NEt 2 ) 3 , HfCp(NEt 2 ) 3 , Hf(iPr 2 Cp)(NMe 2 ) 3 , Hf(tBu 2 Cp)(NMe 2 ) 3 , and mixtures thereof; and depositing the dielectric film on the substrate.

Method of depositing a metal-containing dielectric film

Methods of depositing a metal containing dielectric film on a substrate are disclosed. The metal containing dielectric film has the formula (M 1 1-a M 2 a ) O b N c , wherein 0≦a<1, 0<b≦3, 0≦c≦1, M 1 represents a metal selected from (Hf) or (Zr); and M 2 represents a metal atom. The method generally uses an M 1 metal containing precursor selected from: Zr(MeCp)(NMe 2 ) 3 , Zr(EtCp)(NMe 2 ) 3 , ZrCp(NMe 2 ) 3 , Zr(MeCp)(NEtMe) 3 , Zr(EtCp)(NEtMe) 3 , ZrCp(NEtMe) 3 , Zr(MeCp)(NEt 2 ) 3 , Zr(EtCp)(NEt 2 ) 3 , ZrCp(NEt 2 ) 3 , Zr(iPr 2 Cp)(NMe 2 ) 3 , Zr(tBu 2 Cp)(NMe 2 ) 3 , Hf(MeCp)(NMe 2 ) 3 , Hf(EtCp)(NMe 2 ) 3 , HfCp(NMe 2 ) 3 , Hf(MeCp)(NEtMe) 3 , Hf(EtCp)(NEtMe) 3 , HfCp(NEtMe) 3 , Hf(MeCp)(NEt 2 ) 3 , Hf(EtCp)(NEt 2 ) 3 , HfCp(NEt 2 ) 3 , Hf(iPr 2 Cp)(NMe 2 ) 3 , or Hf(tBu 2 Cp)(NMe 2 ) 3 .

Method of forming dielectric films, new precursors and their use in semiconductor manufacturing

The application relates to a method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (M 1 1-a M 2 a )O b N c , wherein 0≦a<1, 0<b≦3, 0≦c≦1, M 1 represents a metal selected from (Hf), (Zr) and (Ti); and M 2 represents a metal atom atoms. The method generally uses an M 1 metal containing precursor selected from: Zr(MeCp)(NMe 2 ) 3 , Zr(EtCp)(NMe 2 ) 3 , ZrCp(NMe 2 ) 3 , Zr(MeCp)(NEtMe) 3 , Zr(EtCp)(NEtMe) 3 , ZrCp(NEtMe) 3 , Zr(MeCp)(NEt 2 ) 3 , Zr(EtCp)(NEt 2 ) 3 , ZrCp(NEt 2 ) 3 , Zr(iPr 2 Cp)(NMe 2 ) 3 , Zr(tBu 2 Cp)(NMe 2 ) 3 , Hf(MeCp)(NMe 2 ) 3 , Hf(EtCp)(NMe 2 ) 3 , HfCp(NMe 2 ) 3 , Hf(MeCp)(NEtMe) 3 , Hf(EtCp)(NEtMe) 3 , HfCp(NEtMe) 3 , Hf(MeCp)(NEt 2 ) 3 , Hf(EtCp)(NEt 2 ) 3 , HfCp(NEt 2 ) 3 , Hf(iPr 2 Cp)(NMe 2 ) 3 , Hf(tBu 2 Cp)(NMe 2 ) 3 .

Method of forming high-k dielectric films based on novel titanium, zirconium, and hafnium precursors and their use for semiconductor manufacturing

A method of forming on at least one support at least one metal containing dielectric films having the formula (M 1 1-a M 2 a ) O b N c , wherein: 0≦a<1, 01 and M 2 being metals Hf, Zr or Ti using precursors with pentadienyl ligands and/or cyclopentadienyl ligands.

Method of forming a metal oxide layer, method of manufacturing a gate structure, and method of manufacturing a capacitor using the same

열적 안정성이 우수한 유기 금속 화합물을 전구체로 이용하여 금속 산화막을 형성하는 방법, 게이트 구조물의 제조 방법 및 커패시터의 제조 방법에서, 일반식 M(NR 1 R 2 ) 3 R 3 (식 중에서, M은 금속을 나타내고, R 1 내지 R 2 는 동일하거나 서로 상이하며, R 1 및 R 2 는 수소 또는 탄소수 1 내지 5의 알킬기이며, R 3 은 탄소수 1 내지 5의 알킬기 또는 탄소수 4 이상의 방향족성 고리화합물 또는 헤테로 고리화합물이며, 상기 고리화합물은 치환기를 포함하지 않거나 메틸기, 에틸기 또는 t-부틸기를 상기 고리화합물의 탄소 개수만큼 갖는다)으로 표기되는 유기 금속 화합물을 기판 상에 제공하고, 기판의 상부에 산화제를 도입하여 금속 산화물을 형성한다. 이에 따라 고유전율을 가지면서 열적으로 안정하고, 우수한 스텝 커버리지 특성을 갖는 금속 산화막을 형성할 수 있다. In a method of forming a metal oxide film using an organometallic compound having excellent thermal stability as a precursor, a method of manufacturing a gate structure, and a method of manufacturing a capacitor, the general formula M (NR 1 R 2 ) 3 R 3 (wherein M is a metal R 1 to R 2 are the same or different from each other, R 1 and R 2 are hydrogen or an alkyl group having 1 to 5 carbon atoms, and R 3 is an alkyl group having 1 to 5 carbon atoms or an aromatic cyclic compound or hetero having 4 or more carbon atoms. A cyclic compound, the cyclic compound having no substituent or having an methyl group, an ethyl group or a t-butyl group as the number of carbons of the cyclic compound) is provided on the substrate, and an oxidant is introduced on the substrate. To form a metal oxide. This makes it possible to form a metal oxide film having a high dielectric constant and thermally stable and having excellent step coverage characteristics.

Electronic systems having doped aluminum oxide dielectrics

Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and method for forming silicon oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Deposition methods for forming silicon oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Systems and methods for forming metal oxide layers

A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

method of manufacturing a thin layer using atomic layer deposition, and method of manufacturing a gate structure and a capacitor using the same

원자층 적층 방법에 있어서, 제1 반응 물질로서 TEMAH를 기판의 상부로 도입한 후, 상기 제1 반응 물질의 제1 부분은 상기 기판 상에 화학 흡착시키고, 제2 부분은 물리 흡착시킨다. 이어서, 상기 제1 반응 물질의 제1 부분과 상기 산화제를 화학적으로 반응시킨다. 그 결과, 상기 기판 상에는 하프늄-산화물을 함유하는 제1 고상 물질이 형성된다. 계속해서, 제2 반응 물질로서 APTES를 상기 제1 고상 물질의 상부로 도입한 후, 상기 제2 반응 물질의 제1 부분은 상기 제1 고상 물질 상에 화학 흡착시키고, 제2 부분은 물리 흡착시킨다. 이어서, 상기 제2 반응 물질의 제1 부분과 상기 산화제를 화학적으로 반응시킨다. 그 결과, 상기 제1 고상 물질 상에는 실리콘-산화물을 함유하는 제2 고상 물질이 형성된다. 이에 따라, 상기 기판 상에는 하프늄-실리콘-산화물을 함유하는 고체 박막 즉, 하프늄 실리콘 산화막이 형성된다. In the atomic layer deposition method, after introducing TEMAH as a first reaction material onto a substrate, a first portion of the first reactant is chemisorbed onto the substrate and a second portion is physically adsorbed. Subsequently, the first portion of the first reactant and the oxidant are chemically reacted. As a result, a first solid material containing hafnium-oxide is formed on the substrate. Subsequently, after introducing APTES as a second reaction material on top of the first solid material, the first part of the second reaction material is chemisorbed on the first solid material and the second part is physically adsorbed. . Subsequently, the first portion of the second reactant and the oxidant are chemically reacted. As a result, a second solid material containing silicon-oxide is formed on the first solid material. As a result, a solid thin film containing hafnium-silicon oxide is formed on the substrate, that is, a hafnium silicon oxide film.

Capacitor of semiconductor device applying a damascene process and method for fabricating the same

다미신 공정을 적용한 반도체 소자의 커패시터 및 그 형성방법에 관해 개시한다. 이를 위해 본 발명은 하부전극의 높이를 높이고 하부전극 이 형성된 층간절연막 내부에 하부전극 및 층간절연막의 일부를 식각하여 이중 다마신 구조 형성을 위한 트랜치를 형성한 후, 트랜치 내부에 유전막 및 상부전극을 형성한다. 따라서 상부전극 형성시 미스얼라인에 의한 금속배선의 합선(short)을 예방하고 균일한 커패시턴스를 확보할 수 있다. Disclosed are a capacitor of a semiconductor device to which the damycin process is applied and a method of forming the same. To this end, the present invention increases the height of the lower electrode, and forms a trench for forming a double damascene structure by etching a portion of the lower electrode and the interlayer insulating layer in the interlayer insulating layer on which the lower electrode is formed, and then forming a dielectric film and the upper electrode in the trench. Form. Therefore, when forming the upper electrode, it is possible to prevent a short circuit of the metal wiring due to misalignment and to secure a uniform capacitance.

Method for film formation of gate insulator, apparatus for film formation of gate insulator, and cluster tool

본 발명의 성막 방법은 반도체 기판면상에 제 1 비유전율을 갖는 재료를 본질적인 성분으로 하는 제 1 절연막을 형성하는 제 1 공정과 제 1 절연막상에 상기 제 1 비유전율보다 큰 제 2 비유전율을 갖는 재료를 본질적인 성분으로 하는 제 2 절연막을 상기 제 1 절연막의 막 두께보다 두껍게 형성하는 제 2 공정을 포함한다. 제 2 절연막인 고유전율 재료의 막형성 프로세스를 제 1 절연막인 배리어층 형성 후에 연속해서 실시하므로, 기판에 대해 안정한 고유전율 재료의 게이트를 형성할 수 있다. The film forming method of the present invention has a first step of forming a first insulating film having essentially a material having a first dielectric constant on a surface of a semiconductor substrate and a second dielectric constant greater than the first dielectric constant on a first insulating film. And a second step of forming a second insulating film having a material as an essential component thicker than the film thickness of the first insulating film. Since the film formation process of the high dielectric constant material which is a 2nd insulating film is performed continuously after formation of the barrier layer which is a 1st insulating film, the gate of the high dielectric constant material stable with respect to a board | substrate can be formed.

Method of manufacturing semiconductor device, semiconductor device, and substrate processing apparatus

고유전율 및 고온 상태로 안정된 캐패시터 절연막의 형성을 실현한다. 기판 상에 제1 원소를 포함하며 비정질(非晶質)인 제1 절연막을 형성하는 제1 공정; 상기 제1 원소와는 다른 제2 원소를 상기 제1 절연막에 첨가하여 비정질인 제2 절연막을 형성하는 제2 공정; 및 상기 제2 절연막을 소정의 어닐링 온도로 어닐링하여 제3 절연막에 상전이(相轉移)시키는 제3 공정을 포함하고, 상기 어닐링 온도에 따라서 상기 제2 원소의 첨가 농도를 제어한다. Formation of a capacitor insulating film stable at high dielectric constant and high temperature is realized. A first step of forming an amorphous first insulating film containing a first element on the substrate; A second step of forming an amorphous second insulating film by adding a second element different from the first element to the first insulating film; And a third step of annealing the second insulating film to a predetermined annealing temperature to phase change the third insulating film, and controlling the addition concentration of the second element in accordance with the annealing temperature.

반도체 디바이스의 제조 방법

본 발명은 웨이퍼를 처리실 내에 반입하는 공정과, TEMAH와 O 3 를 가열하면서 처리실 내에 교대로 공급하여 웨이퍼에 HfO 2 막을 형성하는 공정과, 웨이퍼를 처리실 내로부터 반출하는 공정을 포함한다. HfO 2 막을 형성하는 공정에서는 TEMAH의 가열 온도와 O 3 의 가열 온도를 다르게 하는 반도체 디바이스의 제조 방법이 제공된다. 금속 산화막, 오존, 산화물

유전막을 갖는 반도체 소자 및 그 형성방법

반도체 소자의 형성방법이 제공된다. 상기 반도체 소자의 형성방법은 반도체 기판을 반응 챔버에 로딩하는 것, 그리고 상기 반응 챔버에 하프늄 및 지르코늄을 포함하는 금속 유기 전구체를 공급하여 상기 반도체 기판 상에 정방정계의 결정구조를 갖는 하프늄-지르코늄 산화막(Hf X Zr 1 - X O; 0＜X＜1)을 형성하는 것을 포함한다. 하프늄-지르코늄 산화막, 정방정계 결정구조

Multiple vapor sources for vapor deposition

A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical.

Method of fabricating non-volatile memory device

본 발명의 불휘발성 메모리소자의 제조방법은, 반도체기판 위에 터널절연막패턴 및 플로팅게이트전극막패턴을 형성하는 단계와, 터널절연막패턴 및 플로팅게이트전극막패턴에 정렬되도록 반도체기판의 노출부분을 식각하여 소자분리용 트랜치를 형성하는 단계와, 소자분리용 트랜치를 매립절연막으로 채워 트랜치 소자분리막을 형성하는 단계와, 트랜치 소자분리막 및 플로팅게이트전극막패턴 위에 하프늄-리치 하프늄실리콘옥사이드막을 형성하는 단계와, 하프늄-리치 하프늄실리콘옥사이드막에 대한 1차 질화공정으로 하프늄-리치 하프늄실리콘옥시나이트라이드막을 형성하는 단계와, 하프늄-리치 하프늄실리콘옥시나이트라이드막 위에 실리콘-리치 하프늄실리콘옥사이드막을 형성하는 단계와, 실리콘-리치 하프늄실리콘옥사이드막에 대한 2차 질화공정으로 실리콘-리치 하프늄실리콘옥시나이트라이드막을 형성하는 단계와, 그리고 실리콘-리치 하프늄실리콘옥시나이트라이드막 위에 컨트롤게이트전극막을 형성하는 단계를 포함한다. A method of manufacturing a nonvolatile memory device according to the present invention includes forming a tunnel insulating film pattern and a floating gate electrode film pattern on a semiconductor substrate, and etching the exposed portion of the semiconductor substrate so as to be aligned with the tunnel insulating film pattern and the floating gate electrode film pattern. Forming a device isolation trench, filling the device isolation trench with a buried insulating film to form a trench device isolation film, forming a hafnium-rich hafnium silicon oxide film over the trench device isolation film and the floating gate electrode film pattern; Forming a hafnium-rich hafnium silicon oxynitride film as a first nitridation process for the hafnium-rich hafnium silicon oxide film, forming a silicon-rich hafnium silicon oxide film on the hafnium-rich hafnium silicon oxynitride film; 2 for Silicon-Rich Hafnium Silicon Oxide Films And a rich hafnium silicon oxynitride hydride film forming a control gate electrode film on-stage, and to form a film and the silicon nitride rich hafnium silicon oxynitride-silicon nitride process. 불휘발성 메모리(NVM)소자, 게이트간절연(inter-gate dielectric)막, 하이-케이 유전체막, 유효 산화막 두께, 플래너 셀 구조 Non-Volatile Memory (NVM) Devices, Inter-gate Dielectric Films, High-K Dielectric Films, Effective Oxide Thickness, Planar Cell Structures

Insulating film evaluation method

Method of manufacturing a dielectric film and method of manufacturing Metal Insulator Metal capacitor having the dielectric film and batch type atomic layer deposition apparatus for manufacturing the dielectric film

쓰루풋을 개선함과 동시에 고온 공정시 유전막의 누설 전류를 방지할 수 있는 300mm 웨이퍼상에 유전막 제조방법, 그 유전막을 포함하는 MIM 캐패시터의 제조방법 및 그 유전막을 제조하기 위한 배치 타입 ALD 장치를 개시한다. 개시된 유전막 제조방법은 먼저, 제 1 배치 타입 장비에서, 웨이퍼상에 원자층 증착법으로 제 1 유전막을 형성한다. 그 후에, 제 2 배치 타입 장비에서 상기 제 1 유전막 상부에 상기 제 1 유전막 보다 높은 결정화 온도를 갖는 제 2 유전막을 원자층 증착법으로 형성한다음, 제 3 배치 타입 장비에서, 상기 제 2 유전막상에 제 3 유전막을 원자층 증착법으로 형성한다. A method of manufacturing a dielectric film on a 300mm wafer capable of improving throughput and preventing leakage current of a dielectric film during a high temperature process, a method of manufacturing a MIM capacitor including the dielectric film, and a batch type ALD device for manufacturing the dielectric film are disclosed. . The disclosed dielectric film manufacturing method first forms, in a first batch type equipment, a first dielectric film by atomic layer deposition on a wafer. Thereafter, in the second batch type equipment, a second dielectric film having a higher crystallization temperature than the first dielectric film is formed by atomic layer deposition on the first dielectric film, and then on the second dielectric film in the third batch type equipment. The third dielectric film is formed by atomic layer deposition. 하프늄 산화막, 알루미늄 산화막, ALD, 배치(batch), 노즐, MIM Hafnium oxide, aluminum oxide, ALD, batch, nozzles, MIM

Atomic layer deposition of hafnium-based high-k dielectric

하프늄-기재 유전체막을 증착하는 방법이 제공된다. 상기 방법은 하프늄 전구체를 포함하는 하나 이상의 반응물과 오존을 사용하는 원자층 증착을 포함한다. 또한 반도체 소자가 제공된다. 상기 소자는 기판, 기판의 상부에 형성된 하프늄-기재 유전체층, 및 상기 기판과 상기 하프늄-기재 유전체층 사이에 형성된 계면층을 포함하며, 상기 계면층은 실리콘 이산화물을 포함하며 결정성 구조를 갖는다.

Method of manufacturing in semiconductor device

A method for fabricating a semiconductor device is provided to improve a capacitance equivalent thickness and leakage current characteristic by lowering a degree of crystallization of a high-dielectric insulation layer at an annealing process. A high-dielectric insulation layer(140) comprising a hafnium oxide layer is formed on a semiconductor substrate(100) by using at least one precursor selected from a group consisting of Hf[C5H4(CH3)]2(CH3)2, Hf[C5H4(CH3)]2(OCH3)3, and Hf[C5H4(CH3)][N(CH3)(CH2(CH3))]3 at a temperature of 400 to 500 degrees centigrade. The high-dielectric insulation layer is formed by an atomic layer deposition method. The high-dielectric insulation layer has a thickness of 40 to 500 angstrom.

Flat type capacitor for integrated circuit and method for manufacturing the same

캐패시터의 유전막의 열화를 방지하여, 캐패시터의 전기적 특성을 개선할 수 있는 평판형 캐패시터 및 그 제조방법을 개시한다. 개시된 본 발명의 평판형 캐패시터는, 반도체 기판의 소정 부분에 형성되는 하부 배선, 상기 하부 배선과 전기적으로 연결되며 하부 배선 상에 형성되는 하부 전극, 상기 하부 전극 상부에 양 모서리를 갖는 콘케이브 형태로 형성된 유전막, 상기 유전막 표면에 콘케이브 형태로 형성되는 상부 전극, 상기 하부 배선과 전기적으로 연결되는 제 1 상부 배선, 및 상기 상부 전극과 연결되는 제 2 상부 배선을 포함하며, 상기 콘케이브 형태의 상부 전극이 하부 전극 보다 크게 형성된다. Disclosed are a flat plate capacitor and a method of manufacturing the same, which can prevent deterioration of a dielectric film of a capacitor and can improve electrical characteristics of the capacitor. The disclosed flat plate capacitor has a lower wiring formed on a predetermined portion of a semiconductor substrate, a lower electrode electrically connected to the lower wiring and formed on the lower wiring, and in a concave form having both corners on the lower electrode. A dielectric film formed on the surface of the dielectric film, an upper electrode formed in a concave shape on the surface of the dielectric film, a first upper wire electrically connected to the lower wire, and a second upper wire connected to the upper electrode. The electrode is formed larger than the lower electrode.

Analog capacitor having at least 3 layers of high-k dielectric layers and method of fabricating the same

적어도 3층의 고유전막들을 갖는 아날로그 커패시터 및 그것을 제조하는 방법이 개시된다. 상기 아날로그 커패시터는 하부전극, 상부전극 및 상기 하부전극과 상기 상부전극 사이에 개재된 적어도 3층의 고유전막들을 포함한다. 상기 적어도 3층의 고유전막들은 상기 하부전극과 접촉하는 하부유전막, 상기 상부전극과 접촉하는 상부유전막 및 상기 하부유전막과 상기 상부유전막 사이에 개재된 중간유전막을 포함한다. 또한, 상기 하부유전막 및 상기 상부유전막 각각은 상기 중간유전막에 비해 상대적으로 전압효율의 이차항의 계수의 절대값이 작은 고유전막이고, 상기 중간유전막은 상기 하부유전막 및 상기 상부유전막 각각에 비해 누설전류가 작은 고유전막이다. 이에 따라, 상기 적어도 3층의 고유전막들을 사용하여 아날로그 커패시터의 전압효율 특성 및 누설전류 특성을 최적화할 수 있다. An analog capacitor having at least three high dielectric films and a method of manufacturing the same are disclosed. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a lower dielectric layer in contact with the lower electrode, an upper dielectric layer in contact with the upper electrode, and an intermediate dielectric layer interposed between the lower dielectric layer and the upper dielectric layer. In addition, each of the lower dielectric film and the upper dielectric film is a high dielectric film having a smaller absolute value of the coefficient of the secondary term of voltage efficiency relative to the intermediate dielectric film, and the intermediate dielectric film has a leakage current compared to the lower dielectric film and the upper dielectric film, respectively. It is a small high dielectric film. Accordingly, the voltage efficiency characteristics and leakage current characteristics of the analog capacitor may be optimized by using the at least three high-k dielectric layers. 아날로그 커패시터, 고유전막(high-k dielectric layer), 전압효율(voltage coefficient of capacitance; VCC), 누설전류 Analog capacitors, high-k dielectric layers, voltage coefficient of capacitance (VCC), leakage current

SONOS type memory device

소노스 타입 메모리 소자에 관해 개시되어 있다. 개시된 본 발명은 반도체 기판과, 상기 반도체 기판 상에 소정의 도전성 불순물이 주입된 것으로, 소정 간격으로 이격 되어 있고, 그 사이에 채널이 형성되어 있는 제1 및 제2 불순물 영역과, 상기 제1 및 제2 불순물 영역 사이의 반도체 기판 상에 형성된 데이터 저장형 적층물을 구비한다. 상기 데이터 저장형 적층물은, 터널링 산화막, 데이터가 저장되는 메모리 노드층, 블로킹 산화막 및 전극층으로 순차적으로 형성된다. 상기 메모리 노드층의 유전상수가 상기 터널링 산화막 및 상기 블로킹 산화막의 유전상수 보다 크며, 상기 터널링 산화막 및 상기 블로킹 산화막은 고유전체 절연막이다. A sonos type memory device is disclosed. The present invention discloses a semiconductor substrate, first and second impurity regions in which predetermined conductive impurities are implanted on the semiconductor substrate, spaced at predetermined intervals, and channels are formed therebetween; And a data storage stack formed on the semiconductor substrate between the second impurity regions. The data storage stack is sequentially formed of a tunneling oxide film, a memory node layer in which data is stored, a blocking oxide film, and an electrode layer. The dielectric constant of the memory node layer is larger than the dielectric constants of the tunneling oxide film and the blocking oxide film, and the tunneling oxide film and the blocking oxide film are high dielectric insulating films.

Manufacturing method of insulator thin film

기판 및 전극 계면의 고정 전하를 저감하고, 또한 계면 준위의 증대없이 붕소의 관통을 억제함으로써, Vth 시프트 및 이동도 열화가 없는 양호한 MOSFET를 형성할 수 있는 절연체 박막을 제공하는 것을 가능하게 한다. 원자층 증착법을 이용하여 기판(100) 상에 박막을 형성하는 절연체 박막(102)의 제조 방법으로서, 상기 기판(100)의 처리 표면에 실리콘 원자층을 형성하고, 상기 실리콘 원자층 상에 산소 원자층을 형성하는 제1 공정과, 상기 기판(100)의 처리 표면에 금속 원자층을 형성하고, 상기 금속 원자층 상에 산소 원자층을 형성하는 제2 공정을 갖는 것을 특징으로 하며, 상기 제1 공정 및 상기 제2 공정의 실시 횟수를 제어함으로써 상기 절연체 박막(102) 내의 상기 금속 원자의 농도를 제어하는 절연체 박막의 제조 방법이다. 원자층 증착법, 실리콘 원자층, 산소 원자층, 농도, 어닐링, 불활성 가스

Semiconductor device and manufacturing method of semiconductor device

シリコン基板の界面に良質のゲート絶縁膜の形成を可能とし、界面電気特性を改善した半導体装置を提供する。シリコン基板（１０１）表面にシリコンを含む下地層（酸化膜、または、酸窒化膜）（１０２）を形成し、該形成した下地層（１０２）表面上に金属供給源または金属拡散源として金属化合物からなる金属化合物層（１０３）を堆積し、下地層（１０２）と、金属化合物層（１０３）と、に熱処理を施すことで、金属化合物層（１０３）に含まれる金属化合物の金属元素を下地層（１０２）に拡散させ、シリコン基板（１０１）上に高誘電率のゲート絶縁膜（１０６）を形成し、金属化合物層（１０３）の金属化合物中の金属原子量が、１．５Ｅ＋１５ｃｍ-2から２．６Ｅ＋１５ｃｍ-2の範囲となる半導体装置を形成する。 Provided is a semiconductor device capable of forming a high-quality gate insulating film at an interface of a silicon substrate and having improved interface electrical characteristics. A base layer (oxide film or oxynitride film) (102) containing silicon is formed on the surface of the silicon substrate (101), and a metal compound is used as a metal supply source or metal diffusion source on the surface of the formed base layer (102). A metal compound layer (103) made of the above is deposited, and a heat treatment is performed on the base layer (102) and the metal compound layer (103), thereby lowering the metal element of the metal compound contained in the metal compound layer (103). A gate insulating film (106) having a high dielectric constant is formed on the silicon substrate (101) by diffusing into the base layer (102), and the metal atom amount in the metal compound of the metal compound layer (103) is 1.5E + 15 cm −2 A semiconductor device having a range of 2.6E + 15 cm −2 is formed.

Alkoxide compound, raw material for thin film formation and process for producing thin film

본 발명의 알콕시드 화합물은 하기 일반식(I)으로 나타내는 것이며, CVD법 등의 화합물을 기화시켜서 박막을 형성하는 방법에 사용되는 박막 형성용 원료에 적합한 것이다. 또한 본 발명의 박막 형성용 원료는 상기 알콕시드 화합물을 함유하여 이루어지는 것이며, 본 발명의 박막의 제조방법은 상기 박막 형성용 원료를 기화시켜서 얻은 알콕시드 화합물을 함유하는 증기를 기체상에 도입하고, 이것을 분해 및/또는 화학반응시켜서 기체상에 박막을 형성하는 것이다. The alkoxide compound of this invention is represented by following General formula (I), and is suitable for the raw material for thin film formation used for the method of vaporizing compounds, such as CVD method, and forming a thin film. Moreover, the raw material for thin film formation of this invention contains the said alkoxide compound, The manufacturing method of the thin film of this invention introduce | transduces the vapor containing the alkoxide compound obtained by vaporizing the said thin film formation raw material in gas phase, It is decomposed and / or chemically reacted to form a thin film on the gas. (식 중, R 1 및 R 2 는 한쪽은 탄소수 1~4의 알킬기를 나타내고, 다른쪽은 수소원자 또는 탄소수 1~4의 알킬기를 나타내고, R 3 및 R 4 는 탄소수 1~4의 알킬기를 나타내고, A는 탄소수 1~8의 알칸디일기를 나타내고, M은 규소원자 또는 하프늄원자를 나타내고, n은 4를 나타낸다.) (In formula, R < 1> and R < 2> represents a C1-C4 alkyl group, the other represents a hydrogen atom or a C1-C4 alkyl group, and R < 3> and R < 4> represents a C1-C4 alkyl group. And A represents an alkanediyl group having 1 to 8 carbon atoms, M represents a silicon atom or a hafnium atom, and n represents 4. 알콕시드 화합물, 웨이퍼, 박막, 하프늄, CVD Alkoxide Compounds, Wafers, Thin Films, Hafnium, CVD

MOSFET transistor and manufacturing method thereof

A method of evaluating characteristics of and forming of an insulating film for a semiconductor device

절역막(1)의 특성을 평가하는 방법이 개시된다. 절연막 (1)은 절연성 무기물질을 주재료로 하여 형성되고, 절연성 무기 물질은 실리콘 및 산소를 포함한다. 절연막(1)은 수소 원자를 더욱 포함한다. 방법은 다음 단계를 포함한다: 전계를 인가하지 않은 상태의 상기 절연막을 승온 이탈 가스 분석법으로 분석하는 단계; 가열 온도가 500 내지 1000 ℃ 범위의 온도에서 측정되는 H 2 프레그먼트의 강도와 OH 프레그먼트의 강도를 비교하는 단계, 및 상기 비교 결과에 기초하여 상기 절연막의 특성을 평가하는 단계. 절연막, 반도체, 특성평가

Capacitor with alloyed hafnium oxide and aluminium oxide and method for fabricating the same

본 발명은 HfO 2 /Al 2 O 3 적층 유전막을 갖는 캐패시터가 갖고 있는 고전압에서의 높은 누설전류 및 상부전극 형성후에 진행되는 후속 열공정에 의한 전기적 특성의 저하를 억제하는데 적합한 캐패시터 및 그 제조 방법을 제공하기 위한 것으로, 본 발명의 캐패시터는 하부전극, 상기 하부전극 상의 산화하프늄과 산화알루미늄이 혼합된 유전막(HfO 2 와 Al 2 O 3 은 하부전극 표면과 동시에 접촉하면서 상부전극에도 동시에 접촉하도록 단원자 박막임), 및 상기 유전막 상의 상부전극을 포함한다. The present invention provides a capacitor suitable for suppressing the deterioration of electrical characteristics by a high leakage current at a high voltage of a capacitor having a HfO 2 / Al 2 O 3 laminated dielectric film and a subsequent thermal process performed after the formation of the upper electrode, and a manufacturing method thereof. To provide, the capacitor of the present invention is a lower electrode, the dielectric film mixed with hafnium oxide and aluminum oxide on the lower electrode (HfO 2 and Al 2 O 3 is in contact with the upper electrode while simultaneously contacting the lower electrode surface at the same time Thin film), and an upper electrode on the dielectric layer. 캐패시터, 하프늄산화막, 알루미늄산화막, 단원자증착법, 누설전류, 유전특성 Capacitor, Hafnium Oxide, Aluminum Oxide, Monoatomic Deposition, Leakage Current, Dielectric Properties

Manufacturing method of semiconductor device

Method of forming dielectric films, new precursors and their use in the semi-conductor manufacturing

본 발명은 - 단계 a) 기판을 반응 챔버에 제공하는 단계; - 단계 b) 하기 화학식 II의 1종 이상의 M 1 금속 함유 전구체를 증발시켜 제1 기체 상 금속 공급원을 형성하는 단계; 및 - 단계 c) 상기 제1 기체 상 금속 공급원 및 임의의 상기 제2 기체 상 금속 공급원을 상기 기판과 접촉시키기 위해 반응 챔버에 도입하여 하기 정의된 바와 같은 화학식 I의 화합물을 포함하는 금속 함유 유전체 필름을 상기 기판 상에 침착시키는 단계를 포함하는, 하기 화학식 I의 화합물을 포함하는 금속 함유 유전체 필름의 기판 상 침착 방법에 관한 것이다. <화학식 I> (M 1 1 - a M 2 a )O b N c <화학식 II> (R 1 y Op) x (R 2 t Cp) z M 1 R' 4 -x-z (상기 식에서, 0 ≤ a < 1; 0 < b ≤ 3; O ≤ c ≤ 1; M 1 은 (Hf), (Zr) 및 (Ti)으로부터 선택된 금속을 나타내고; M 2 는 금속 원자를 나타내고; 0 ≤ x ≤ 3, 바람직하게는 x = 0 또는 1; 0 ≤ z ≤ 3, 바람직하게는 z = 1 또는 2; 1 ≤ (x + z) ≤ 4; 0 ≤ y ≤ 7, 바람직하게는 y = 2, 0 ≤ t ≤ 5, 바람직하게는 t = 1; (R 1 y Op)는 비치환되거나, 치환된 펜타디에닐 리간드를 나타내고; (R 2 t Cp)는 비치환되거나, 치환된 시클로펜타디에닐 (Cp) 리간드를 나타낸다. 또한, 본 발명은 x = 0, z = 1 및 R'은 N(R 39 )(R 40 ) 기를 나타내는 제1항에 기재된 바와 같은 화학식 II에 상응하는 하기 화학식 II 1 의 화합물에 관한 것이다. <화학식 II 1 > (R 2 t Cp)M 1 [N(R 39 )(R 40 )] 3 The present invention - a) providing a substrate to a reaction chamber; B) evaporating at least one M 1 metal-containing precursor of formula II to form a first gaseous metal source; And - c) introducing the first gas phase metal source and any of the second gas phase metal source into the reaction chamber for contacting the substrate to form a metal containing dielectric film comprising a compound of formula I as defined below, And depositing on the substrate a metal-containing dielectric film comprising a compound of formula < RTI ID = 0.0 > (I) < / RTI > (I) (M 1 1 - a M 2 a ) O b N c &Lt; (R 1 y Op) x (R 2 t Cp) z M 1 R 4 -xz (Wherein, 0 < a &lt;1; 0 &lt; b? 3; O? C? 1; M 1 represents a metal selected from (Hf), (Zr) and (Ti); M 2 represents a metal atom; 0? X? 3, preferably x = 0 or 1; 0? Z? 3, preferably z = 1 or 2; 1? (X + z)? 4; 0? Y? 7, preferably y = 2, 0? T? 5, preferably t = 1; (R 1 y Op) represents an unsubstituted or substituted pentadienyl ligand; (R 2 t Cp) represents an unsubstituted or substituted cyclopentadienyl (Cp) ligand. The present ...

Gate insulating film, semiconductor element, electronic device and electronic equipment

A method for preparing metal-insulator-metal capacitor

본 발명은 금속-절연체-금속(Metal-insulator-metal: MIM) 커패시터의 제조 방법을 개시한다. 본 발명에 따른 MIM 커패시터의 제조 방법은 반도체 기판상에 콘택 플러그를 구비하는 층간 절연막을 형성하는 단계, 상기 층간 절연막 상에 식각 정지막을 형성하는 단계, 상기 식각 정지막 상에 상기 콘택 플러그를 노출시키는 개구부를 포함하는 몰드막을 형성하는 단계, 상기 개구부의 측면 및 저면에 하부 전극용 제 1 도전막을 형성하는 단계, 상기 제 1 도전막 상에 감광막을 형성하는 단계, 상기 제 1 도전막으로부터 노드 분리된 하부 전극을 형성하는 단계, 상기 몰드막 및 상기 감광막을 제거하는 단계, 상기 하부 전극 상에 복합 유전막을 형성하는 단계, 및 상기 복합 유전막 상에 제 2 도전막을 형성하여 상부 전극을 완성하는 단계를 포함한다. 상기 복합 유전막은 산화하프늄(HfO 2 ) 유전막 및 산화알루미늄(Al 2 O 3 ) 유전막으로 형성되며, 산화하프늄 유전막은 20Å 초과 50Å 미만의 두께를 갖는다. 산화알루미늄 유전막은 소정의 커패시터의 용량을 얻기 위해 설정된 등가 산화 유전막(Toex)의 실두께에서 상기 산화하프늄 유전막의 두께를 뺀 두께로 형성된다. The present invention discloses a method of manufacturing a metal-insulator-metal (MIM) capacitor. A method of manufacturing a MIM capacitor according to the present invention includes forming an interlayer insulating film having a contact plug on a semiconductor substrate, forming an etch stop film on the interlayer insulating film, and exposing the contact plug on the etch stop film. Forming a mold film including an opening, forming a first conductive film for lower electrodes on side and bottom surfaces of the opening, forming a photosensitive film on the first conductive film, and separating a node from the first conductive film Forming a lower electrode, removing the mold layer and the photosensitive film, forming a composite dielectric film on the lower electrode, and forming a second conductive film on the composite dielectric film to complete the upper electrode. do. The composite dielectric film is formed of a hafnium oxide (HfO 2 ) dielectric film and an aluminum oxide (Al 2 O 3 ) dielectric film, and the hafnium oxide dielectric film has a thickness of more than 20 GPa and less than 50 GPa. The aluminum oxide dielectric layer is formed to have a thickness obtained by subtracting the thickness of the hafnium oxide dielectric layer from the actual thickness of the equivalent oxide dielectric layer Toex set to obtain a predetermined capacitor capacity. ...

Insulating film and semiconductor device

절연막은 Hf 및 Zr로부터 선택되는 금속의 산화물을 포함하고, 그 산화물에는 Ba, Sr 및 Mg 중 적어도 하나를 도핑한다. 그리고 절연막은 다음의 공식 (1)을 만족시킨다. The insulating film includes an oxide of a metal selected from Hf and Zr, and the oxide is doped with at least one of Ba, Sr, and Mg. The insulating film satisfies the following formula (1). 0.06at%≤[Ba]+[Sr]+[Mg]≤1.4at% 0.06at% ≤ [Ba] + [Sr] + [Mg] ≤1.4at% 여기서, [Ba]는 Ba의 원자%를 나타내고, [Sr]은 Sr의 원자%를 나타내며, [Mg]는 Mg의 원자%를 나타낸다. Here, [Ba] represents atomic% of Ba, [Sr] represents atomic% of Sr, and [Mg] represents atomic% of Mg. 절연막, 산화물, Ba, Sr, Mg Insulating film, oxide, Ba, Sr, Mg

Method of manufacturing a thin layer using atomic layer deposition, and method of manufacturing a gate structure and a capacitor using the same

원자층 적층 방법과 이를 이용한 게이트 구조물 및 커패시터의 제조 방법에 있어서, 제1 반응 물질로서 하프늄 전구체를 기판의 상부로 도입한 후, 상기 제1 반응 물질의 제1 부분은 상기 기판 상에 화학 흡착시키고, 제2 부분은 물리 흡착시킨다. 그리고, 상기 기판의 상부로 산화제를 도입한 후, 상기 제1 반응 물질의 제1 부분과 상기 산화제를 화학적으로 반응시켜 상기 기판 상에 하프늄-산화물을 함유하는 제1 고상 물질을 형성한다. 이어서, 제2 반응 물질로서 티타늄 전구체를 상기 제1 고상 물질의 상부로 도입하여 상기 제2 반응 물질의 제1 부분은 상기 제1 고상 물질 상에 화학 흡착시키고, 제2 부분은 물리 흡착시킨다. 계속해서, 상기 제1 고상 물질의 상부로 산화제를 도입하여 상기 제2 반응 물질의 제1 부분과 상기 산화제를 화학적으로 반응시킴으로서 상기 제1 고상 물질 상에 티타늄-산화물을 함유하는 제2 고상 물질을 형성한다. In the atomic layer deposition method and the method of manufacturing the gate structure and capacitor using the same, after introducing a hafnium precursor as a first reaction material to the upper portion of the substrate, the first portion of the first reaction material is chemisorbed on the substrate , The second part is physically adsorbed. After introducing an oxidant into the upper portion of the substrate, the first portion of the first reactant and the oxidant are chemically reacted to form a first solid material containing hafnium-oxide on the substrate. A titanium precursor as a second reactant is then introduced over the first solid phase material so that the first portion of the second reactant chemically adsorbs onto the first solid phase material and the second portion is physically adsorbed. Subsequently, an oxidant is introduced on top of the first solid material to chemically react the first portion of the second reactant with the oxidant to form a second solid material containing titanium oxide on the first solid material. Form.

Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same

提供一种具有至少3层高－k介电层的模拟电容器和制造它的方法。该模拟电容器包含下电极、上电极、置于下电极与上电极之间的至少3层高－k介电层。该至少3层高－k介电层包含接触下电极的底介电层、接触上电极的顶介电层和置于底介电层与顶介电层之间的中介电层。而且，各底介电层和顶介电层是，与中介电层相比，VCC的二次系数的绝对值相对低的高－k介电层，中介电层是，与底介电层和顶介电层相比，漏电流相对低的高－k介电层。因此，由于使用至少3层高－k介电层，可以使模拟电容器的VCC特性和漏电流特性最佳。

Nonvolatile semiconductor memory element having excellent charge retention properties and process for producing the same

부유 게이트 주위의 절연체의 절연성의 향상과, 부유 게이트 중의 산화된 금속 초미립자의 비율의 저감을 가능하게 하는 불휘발성 반도체 기억 소자 및 제조 방법을 제공한다. Provided are a nonvolatile semiconductor memory device and a manufacturing method which enable the insulation of the insulator around the floating gate to be improved and the ratio of the oxidized ultrafine metal particles in the floating gate to be reduced. 깁스의 산화물 생성 자유 에너지가, 0℃ 내지 1200℃ 의 범위 내에서, Si 의 그것보다 높은 원소인 난산화성 물질로 이루어지는 부유 게이트와, 그 부유 게이트의 주위를 둘러싸는, 동 에너지가 Si 와 동일 또는 Si 보다 낮은 이산화성 물질의 산화물로 이루어지는 절연체를 갖는 불휘발성 반도체 기억 소자의 제조 방법에 있어서, 난산화성 물질의 부유 게이트가 물리적 형성법을 이용하여 형성되고, 이산화성 물질의 산화물이 물리적 형성법 또는 화학적 형성법을 이용하여 형성되고, 게이트 절연막을 형성한 후에, 산화용 기체와 환원용 기체의 혼합 기체 중에서, 0℃ ∼ 1200℃ 까지의 온도 범위 내에 있어서 난산화성 물질만을 환원하고, 이산화성 물질의 산화물만을 산화하도록, 혼합 기체의 혼합비 및 온도를 제어하여 열처리를 실시한다. In the range of 0 degreeC-1200 degreeC, the oxide generation free energy of a cast is the floating gate which consists of a non-oxidizing material which is an element higher than that of Si, and the copper energy surrounding the floating gate is equal to Si, or In the method of manufacturing a nonvolatile semiconductor memory device having an insulator made of an oxide of a dioxide material lower than Si, a floating gate of a non-oxidizing material is formed using a physical forming method, and an oxide of the dioxide material is a physical forming method or a chemical forming method. After forming the gate insulating film, in the mixed gas of the oxidizing gas and the reducing gas, only the non-oxidizing substance is reduced within the temperature range of 0 ° C to 1200 ° C, and only the oxide of the dioxide is oxidized. The heat treatment is performed by controlling the mixing ratio and the temperature of the mixed gas. 깁스의 생성 자유 에너지, 난산화성 원소, 이산화성 원소, 불활성 분위기 Generating free energy of cast, Refractory element, Dioxide element, Inert atmosphere

Method of manufacturing a thin film layer and methods of manufacturing a gate structure and a capacitor using the same

박막 제조 방법 및 이를 이용한 게이트 구조물, 커패시터의 제조 방법에서, 1개의 알콕시기(alkoxy group)와 3개의 아미노기(amino group)를 포함하는 하프늄 전구체 및 상기 하프늄 전구체를 산화시키기 위한 산화제를 상기 기판 상부로 제공한다. 이어서, 상기 기판의 상부로 제공된 하프늄 전구체와 산화제를 이용하여 상기 기판 상에 하프늄 산화물을 포함하는 고체물질을 형성한다. 그 결과, 상기 기판 상에는 하프늄 산화물을 포함하는 고체 물질로 이루어지는 박막이 형성된다. 그리고, 상기 박막을 게이트 구조물의 게이트 절연막, 커패시터의 유전막 등에 용이하게 적용한다.

Stabilization of high-k dielectric materials

In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Plasma treatment of hafnium-containing materials

In one embodiment, a method for forming a dielectric material is provided which includes exposing a substrate sequentially to a metal-containing precursor and an oxidizing gas to form metal oxide (e.g., HfO x ) during an ALD process and subsequently exposing the substrate to an inert plasma process and a thermal annealing process. Generally, the metal oxide contains hafnium, tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof. In one example, the inert plasma process contains argon and is free of nitrogen, while the thermal annealing process contains oxygen. In another example, an ALD process to form a metal oxide includes exposing the substrate sequentially to a metal precursor and an oxidizing gas containing water vapor formed by a catalytic water vapor generator. In an alternative embodiment, a method for forming a dielectric material is provide which includes exposing a substrate to a deposition process to form a metal oxide layer and subsequently exposing the substrate to a nitridation plasma process and a thermal annealing process to form metal oxynitride (e.g., HfO x N y ).

Stabilization of high-k dielectric materials

In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Method of manufacturing a non-volatile memory device

A method of fabricating a non-volatile memory device is provided to prevent diffusion of silicon and metal between a bottom silicon oxide layer and a metal oxide layer by using a silicon hydrolyzed layer. A tunnel insulating layer is formed on a substrate(100), and a conductive pattern(122) is formed on the tunnel insulating layer. A bottom silicon oxide layer(126) is formed on the conductive pattern, and then a nitriding process is performed on the bottom silicon oxide to form a silicon hydrolyzed layer(128) on a surface of the bottom silicon oxide layer. A metal oxide layer(130) is formed on the silicon hydrolyzed layer, and a top silicon oxide layer(132) is formed on the metal oxide layer. A conductive layer is formed on the top silicon oxide layer.

Method for forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure

높은 유전율을 갖는 유전체 구조물 및 이를 포함하는 반도체 소자의 제조 방법이 개시된다. 반도체 기판 상에 실리콘이 도핑된 금속 산화물을 사용하여 제1 유전층을 형성한 후, 제1 유전층이 형성된 반도체 기판을 챔버 내에 설치된 서셉터 상에 위치시킨다. 챔버에 전기적으로 연결된 전원으로부터 서셉터와 접지 사이의 전압차를 조절하면서 제1 유전층을 플라즈마 처리하여 제1 유전층 상에 제2 유전층을 형성한다. 제1 유전층 상에 충분한 질소 함량을 갖는 실리콘이 도핑된 금속 산질화물로 구성된 제2 유전층을 형성한다. 따라서, 제1 및 제2 유전층을 포함하는 유전체 구조물을 유전 특성을 향상시키고, 누설 전류를 크게 감소시킬 수 있다. 유전체 구조물을 휘발성 반도체 메모리 소자의 게이트 절연막 및/또는 캐패시터의 유전층이나 불휘발성 반도체 메모리 소자의 유전층으로 적용하여, 반도체 소자의 용량 및 전기적 특성을 개선할 수 있다. Disclosed are a dielectric structure having a high dielectric constant and a method of manufacturing a semiconductor device including the same. After forming the first dielectric layer using the metal oxide doped with silicon on the semiconductor substrate, the semiconductor substrate on which the first dielectric layer is formed is placed on a susceptor installed in the chamber. The first dielectric layer is plasma treated to form a second dielectric layer on the first dielectric layer while controlling the voltage difference between the susceptor and ground from a power source electrically connected to the chamber. A second dielectric layer is formed on the first dielectric layer, which is composed of silicon doped metal oxynitride having sufficient nitrogen content. Thus, dielectric structures including the first and second dielectric layers can improve dielectric properties and significantly reduce leakage current. The dielectric structure may be applied to the gate insulating layer and / or the capacitor dielectric layer of the volatile semiconductor memory device or the dielectric layer of the nonvolatile semiconductor memory device, thereby improving the capacitance and electrical characteristics of the semiconductor device.

Method of forming dielectric films, new precursors and their use in the semi-conductor manufacturing

本发明涉及形成介电膜的方法、新型前体及其在半导体制造中的用途。在一个方面，本发明涉及在基底上沉积含至少一种金属的介电膜的方法，该介电膜包含式(I)的化合物：(Zr 1-a M 2 a )O b N c (I)，其中0≤a＜1，0＜b≤3，0≤c≤1；和M 2 代表金属原子，该方法包括下列步骤：步骤a)，将基底供应到反应室中；步骤b)，将至少一种选自Zr(MeCp)(NMe 2 ) 3 、Zr(EtCp)(NMe 2 ) 3 、ZrCp(NMe 2 ) 3 、Zr(MeCp)(NEtMe) 3 、Zr(EtCp)(NEtMe) 3 、ZrCp(NEtMe) 3 、Zr(MeCp)(NEt 2 ) 3 、Zr(EtCp)(NEt 2 ) 3 、ZrCp(NEt 2 ) 3 、Zr(iPr 2 Cp)(NMe 2 ) 3 、Zr(tBu 2 Cp)(NMe 2 ) 3 的含锆金属的前体气化；步骤c)，将所述第一气相金属源引入反应室中以使它们与所述基底接触，从而在所述基底上沉积包含如上定义的式(I)化合物的含金属的介电膜。

High dielectric constant grid dielectric material forming method and a semiconductor device

本发明提供一种高介电常数栅极介电材料的形成方法与半导体元件，该方法包括下列步骤：提供一半导体基材；清洗该基材；对该基材进行一热处理，其中该热处理在一无氧化环境中进行，导致形成一薄界面层；以及沉积一高介电常数材料于薄界面层之上。本发明的方法能产生均匀且薄的、具有适当的末端的界面层，使其能够相容于后续高介电常数(high-k)材料的沉积，并能改善界面层的粗糙度与品质。同时，本发明的结构能增进在半导体元件中的电荷载流子迁移率。

Method of manufacturing semiconductor device

一种制造半导体器件的方法，所述方法包括形成高介电绝缘层。通过利用前体物形成具有高密度的非晶高介电绝缘层，所述前体物可以在400℃以上的温度下通过原子层沉积法来沉积。所产生的绝缘在后续退火工艺中表现出降低的结晶化。改善了电容等效厚度(CET)特性和漏电流特性。

Pulsed chemical vapor deposition of metal-silicon-containing films

펄스형 화학 기상 증착 공정으로 기판 상에 금속-실리콘 함유 막을 형성하는 형성 방법이 제공된다. 이 형성 방법은, 상기 기판을 프로세스 챔버 내에 제공하는 단계와, 금속 함유 가스와 실리콘 함유 가스의 열분해에 의해 상기 기판 상에 상기 금속-실리콘 함유 막을 화학 기상 증착하기에 적합한 온도로 상기 기판을 유지하는 단계와, 상기 기판을 상기 금속 함유 가스의 연속적 흐름에 노출시키는 단계와, 상기 연속적 흐름 중에, 상기 기판을 실리콘 함유 가스의 순차적 펄스에 노출시키는 단계를 포함한다. A method of forming a metal-silicon containing film on a substrate by a pulsed chemical vapor deposition process is provided. This forming method includes the steps of providing the substrate in a process chamber and maintaining the substrate at a temperature suitable for chemical vapor deposition of the metal-silicon containing film on the substrate by thermal decomposition of the metal containing gas and the silicon containing gas Exposing the substrate to a continuous flow of the metal-containing gas; and, during the continuous flow, exposing the substrate to a sequential pulse of silicon-containing gas.

SONOS type memory device

A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.

Method for film formation of gate insulator, apparatus for film formation of gate insulator, and cluster tool

Method of manufacturing semiconductor device, method of processing substrate, and substrate processing apparatus

고온 영역에 있어서, 막 중의 불순물 농도가 지극히 낮고, 막 두께 균일성이 양호한 절연막을 형성한다. 본 발명에 따르면, (a) 기판을 수용한 처리 용기 내에 소정 원소를 포함하는 원료 가스를 공급하고 배기하여 상기 기판 상에 소정 원소 함유층을 형성하는 공정; (b) 가열된 대기압 미만의 압력 분위기 하에 있는 상기 처리 용기 내에 산소 함유 가스와 수소 함유 가스를 공급하고 배기하여 상기 소정 원소 함유층을 산화층으로 변화시키는 공정; (c) 상기 처리 용기 내에 불활성 가스를 공급하고 배기하여 상기 처리 용기 내를 퍼지하는 공정; (d) 상기 공정 (a) 및 상기 공정 (b)를 교호적으로 반복하면서, 상기 공정 (c)가 상기 공정 (a) 및 상기 공정 (b) 사이에 수행되어, 상기 기판 상에 소정 막 두께의 산화막을 형성하는 공정을 포함하고, 상기 공정 (a)에서는, 상기 원료 가스를 상기 기판의 측방(側方)에 설치된 노즐을 개재하여 상기 기판을 향하여 공급하고, 그 때, 그 노즐을 개재하여 상기 원료 가스와 함께 불활성 가스 또는 수소 함유 가스를 상기 기판을 향하여 공급하는 것으로, 상기 기판의 표면과 평행 방향으로 흐르는 상기 원료 가스의 유속을, 상기 공정 (c)에 있어서 상기 기판의 표면과 평행 방향으로 흐르는 불활성 가스의 유속보다도 크게 한다.

Dielectric multilayer of microelectronic device and fabricating method the same

미세 전자 소자 성능 개선에 적합한 다층 유전체막 및 그 제조 방법이 제공된다. 미세 전자 소자의 다층 유전체막은 두 개 이상의 서로 다른 성분의 산화물로 층상 구조가 없도록 형성되어 있는 복합막 및 복합막의 적어도 한 면에 형성되어 있는 단일 성분의 산화물로 형성되어 있는 단일막을 포함한다. Provided are a multilayer dielectric film suitable for improving microelectronic device performance and a method of manufacturing the same. The multilayer dielectric film of the microelectronic device includes a composite film formed of two or more different components of an oxide such that there is no layered structure, and a single film formed of a single component oxide formed on at least one side of the composite film. 다층 유전체막, 단일막, 복합막 Multi-layer dielectric film, single film, composite film

Method of forming insulating film, method of manufacturing semiconductor device and semiconductor device

이하의 공정을 포함한다. 산화제에 노출됨으로써 그 표면에 산화막을 형성하는 재료로 이루어지는 도전막이 형성된다. 금속 원료를 포함하는 소스 가스와 제1 산화력을 갖는 제1 산화제를 교대로 공급함으로써, 도전막 상에 제1 절연막이 형성된다. 금속 원료를 포함하는 소스 가스와 제1 산화력보다 강한 제2 산화력을 갖는 제2 산화제를 교대로 공급함으로써, 제1 절연막 상에 제2 절연막이 형성된다. The following process is included. Exposure to an oxidizing agent forms a conductive film made of a material for forming an oxide film on the surface thereof. The first insulating film is formed on the conductive film by alternately supplying a source gas containing a metal raw material and a first oxidant having a first oxidizing power. The second insulating film is formed on the first insulating film by alternately supplying a source gas containing a metal raw material and a second oxidizing agent having a second oxidizing power that is stronger than the first oxidizing power. 절연막, 산화막, 산화제, 반도체 장치, 플로팅 게이트 전극, 컨트롤 게이트 전극, 유전체막, 리크 전류 Insulating film, oxide film, oxidant, semiconductor device, floating gate electrode, control gate electrode, dielectric film, leakage current

Insulating film and electronic device

Semiconductor device having high dielectric film neutralizing fixed charge

Film formation apparatus and method of using the same

A method of using a film formation apparatus for a semiconductor process includes processing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is arranged to supply the cleaning gas into the reaction chamber, and set an interior of the reaction chamber at a first temperature and a first pressure. The by-product film mainly contains a high-dielectric-constant material. The cleaning gas contains chlorine without containing fluorine. The first temperature and the first pressure are set to activate chlorine in the cleaning gas.

Radical-assisted sequential CVD

A new method for CVD deposition on a substrate is taught wherein radical species are used in alternate steps to depositions from a molecular precursor to treat the material deposited from the molecular precursor and to prepare the substrate surface with a reactive chemical in preparation for the next molecular precursor step. By repetitive cycles a composite integrated film is produced. In a preferred embodiment the depositions from the molecular precursor are metals, and the radicals in the alternate steps are used to remove ligands left from the metal precursor reactions, and to oxidize or nitridize the metal surface in subsequent layers. A variety of alternative chemistries are taught for different films, and hardware combinations to practice the invention are taught as well.

Semiconductor device provided with MIS field effect transistor

Capacitor forming method for semiconductor device

Semiconductor device and the manufacturing method thereof

Method of manufacturing semiconductor device

Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

Scalable gate and storage dielectric

Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Hafnium tantalum oxide dielectrics

A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Method for depositing a dielectric coating

A method of evaluating charcteristics of and forming of an insulating film for a semiconductor device

A method of evaluating characteristics of an insulating film 1 is disclosed. The insulating film 1 is formed of an insulative inorganic material as a main material, the insulative inorganic material containing silicon and oxygen. The insulating film 1 further contains hydrogen atoms. The method includes the steps of : analyzing the insulating film 1 to which an electric field has never been applied by Thermal Desorption Spectroscopy; comparing intensity of an H2 fragment with intensity of an OH fragment, the intensity of the H2 fragment and the intensity of the OH fragment being measured at a state where the insulating film 1 is heated at a temperature in the range of 500 to 1000 °C; and evaluating the characteristics of the insulating film 1 on the basis of the comparison result.

Use of dissolved hafnium alkoxides or zirconium alkoxides as precursors for hafnium oxide and hafnium oxynitride layers or zirconium oxide and zirconium oxynitride layers

Die vorliegende Erfindung betrifft die Verwendung einer Lösung eines oder mehrerer Hafniumalkoxide als Precursoren für Hafniumoxid- und Hafniumoxynitrid-Schichten. Die vorliegende Erfindung betrifft insbesondere die Verwendung einer 30 bis 90 Gew.-%igen Lösung eines oder mehrerer Hafniumalkoxide zur Erzeugung von Hafniumoxid- und Hafniumoxynitrid-Schichten für CVD- oder ALD-Verfahren. Darüber hinaus betrifft die Erfindung ein Verfahren zur Erzeugung einer Hafniumoxid- und Hafniumoxynitrid-Schicht auf einem zu beschichtenden Gegenstand sowie eine Hafniumalkoxidlösung, die 30 bis 90 Gew.-% eines oder mehrerer Hafniumalkoxide enthält. In einer weiteren Ausgestaltungsform der Erfindung wird in den genannten Verbindungen Hafnium durch Zirkonium ersetzt. The present invention relates to the use of a solution of one or more hafnium alkoxides as precursors for hafnium oxide and hafnium oxynitride layers. In particular, the present invention relates to the use of a 30 to 90% by weight solution of one or more hafnium alkoxides for producing hafnium oxide and hafnium oxynitride layers for CVD or ALD processes. Moreover, the invention relates to a process for producing a hafnium oxide and Hafniumoxynitrid layer on an article to be coated and a Hafniumalkoxidlösung containing 30 to 90 wt .-% of one or more Hafniumalkoxide. In a further embodiment of the invention hafnium is replaced by zirconium in said compounds.

Transistor device

A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.

Thin Film Capacitor, Method for Forming Same, and Computer Readable Recording Medium

In a thin film capacitor, reducing a leak current by suppressing concentration of an electric filed. Forming a zirconium oxide layer ( 26 A) on a lower electrode ( 22 ) made of a conductive material. Forming a buffer layer ( 28 ) made of an amorphous material on the first zirconium oxide layer ( 26 A). Forming a second zirconium oxide layer ( 26 B) on the buffer layer ( 28 ), and forming an upper electrode ( 24 ) made of a conductive material on the second zirconium oxide layer ( 26 B)

Method for manufacturing semiconductor epitaxial crystal substrate

The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Method of fabricating non-volatile memory device

본 발명의 불휘발성 메모리소자의 제조방법은, 반도체기판 위에 터널절연막패턴 및 플로팅게이트전극막패턴을 형성하는 단계와, 터널절연막패턴 및 플로팅게이트전극막패턴에 정렬되도록 반도체기판의 노출부분을 식각하여 소자분리용 트랜치를 형성하는 단계와, 소자분리용 트랜치를 매립절연막으로 채워 트랜치 소자분리막을 형성하는 단계와, 트랜치 소자분리막 및 플로팅게이트전극막패턴 위에 하프늄-리치 하프늄실리콘옥사이드막을 형성하는 단계와, 하프늄-리치 하프늄실리콘옥사이드막에 대한 1차 질화공정으로 하프늄-리치 하프늄실리콘옥시나이트라이드막을 형성하는 단계와, 하프늄-리치 하프늄실리콘옥시나이트라이드막 위에 실리콘-리치 하프늄실리콘옥사이드막을 형성하는 단계와, 실리콘-리치 하프늄실리콘옥사이드막에 대한 2차 질화공정으로 실리콘-리치 하프늄실리콘옥시나이트라이드막을 형성하는 단계와, 그리고 실리콘-리치 하프늄실리콘옥시나이트라이드막 위에 컨트롤게이트전극막을 형성하는 단계를 포함한다. 불휘발성 메모리(NVM)소자, 게이트간절연(inter-gate dielectric)막, 하이-케이 유전체막, 유효 산화막 두께, 플래너 셀 구조

Method for controlling defects in gate dielectrics

A method for improving high-κ gate dielectric film ( 104 ) properties. The high-κ film ( 104 ) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient ( 106 ) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient ( 108 ) with a low partial pressure of reducer to remove defects and impurities.

Insulating film and electronic element

【課題】誘電率が高く、かつ、リーク電流の小さな絶縁膜及びこれを用いた電子素子を提供することを目的とする。 【解決手段】高誘電率をもつがバリアーの低い物質を、誘電率は低いが高いバリアーを持ったもので挟んだ絶縁膜の量子井戸構造あるいは多重量子井戸構造を用いる。または、▲１▼格子定数を基板に対してプラスマイナス１．５％以内にする、▲２▼障壁高さが高いこと、▲３▼誘電率が大きいこと、という３点の条件を満たす絶縁体を用いる。 【選択図】 図１

METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT

A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103. <IMAGE>