ЭЛЕКТРОННЫЙ КОМПОНЕНТ И ЭЛЕКТРОННОЕ УСТРОЙСТВО

Изобретение относится к устройствам для переноса тепла, созданного в электронном устройстве. Техническим результатом является повышение эффективности отвода тепла от электронного устройства. Устройство содержит корпус, который вмещает электронное устройство, при этом корпус включает в себя тело основания, тело крышки и тело рамки, причем тело рамки имеет первый участок и второй участок. Второй участок имеет более большую длину, чем длина первого участка, а толщина первого участка меньше, чем длина первого участка в упомянутом направлении, причем тело основания и тело рамки имеют более высокую удельную теплопроводность, чем удельная теплопроводность тела крышки. 3 н. и 17 з.п. ф-лы, 25 ил.

СПОСОБ СОЕДИНЕНИЯ, ГЕРМЕТИЧНАЯ КОНСТРУКЦИЯ, ИЗГОТОВЛЕННАЯ ДАННЫМ СПОСОБОМ, И СИСТЕМА ГЕРМЕТИЧНЫХ КОНСТРУКЦИЙ

... 1. Способ соединения с применением взаимной диффузии металлов для формирования, на уровне пластин, герметичных корпусов для устройств на базе микроэлектромеханических систем (МЭМС), включающий следующие этапы:формирование на поверхности как первой пластины, так и второй пластины стопы из первого металла, подверженного окислению на воздухе;формирование на верхней поверхности каждой стопы из первого металла слоя второго металла, температура плавления у которого ниже, чем у первого металла, причем толщину слоя второго металла выбирают достаточной для предотвращения окисления верхней поверхности первого металла;приведение слоя второго металла на первой пластине в контакт со слоем второго металла на второй пластине, чтобы образовать зону соединения, иприложение к первой и второй пластинам давления соединения при температуре зоны соединения, которая ниже температуры плавления второго металла, чтобы инициировать соединение, причем давление соединения выбирают достаточным для деформирования слоев ...

ЛАМИНИРОВАНИЕ КАРТ

... 1. Способ изготовления RFID структуры, причем способ содержит:предоставление подложки антенны;предоставление первого слоя стека;формирование на первой поверхности подложки антенны антенного узла, включающего в себя антенную дорожку и по меньшей мере две контактные площадки;соединение интегральной схемы с по меньшей мере двумя контактными площадками;покрытие первой поверхности первого слоя стека, первой поверхности подложки антенны или обоих однонаправленным термически расширяемым покрывающим материалом; ипозиционирование первой поверхности подложки антенны для прилегания к первой поверхности первого слоя стека.2. Способ по п. 1, дополнительно содержащий:предоставление второго слоя стека;покрытие первой поверхности второго слоя стека или второй поверхности подложки антенны, противоположной первой поверхности подложки антенны, термически расширяемым покрывающим материалом; ипозиционирование первой поверхности второго слоя стека для прилегания к второй поверхности подложки антенны.3. Способ ...

Verfahren zur Laserverpackung von elektronischen Schaltungen, insbesondere für Hybrid-Schaltungen zur Minimisierung von Spannungen

Halbleitervorrichtung, Verfahren zu deren Herstellung, und Leistungswandler

Eine Halbleitervorrichtung 100 umfasst eine Metallgrundplatte 1P, eine Gehäusekomponente 2, und eine Metallkomponente 3P. Die Metallkomponente 3P ist an der Gehäusekomponente 2 befestigt. Eine Teilregion der Metallkomponente 3P ist von der Gehäusekomponente 2 freigelegt. Die Teilregion ist mit der Grundplatte 1P in einem Verbindungsabschnitt 13P verbunden. Im Verbindungsabschnitt 13P stehen eine Fläche der Teilregion und eine Fläche der Grundplatte 1P in direktem Kontakt miteinander und sind integriert.

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Halbleitermodulanordnung und Verfahren zur Montage eines Halbleitermoduls an einem Kühlkörper

Halbeitermodulanordnung umfassend:ein Halbleitermodul (10) das eine Unterseite (10b) mit einer Wärmeableitfläche (11) aufweist, sowie eine der Unterseite (10b) entgegengesetzte Oberseite (10t), die in einer vertikalen Richtung (v) von der Unterseite (10b) beabstandet ist;ein Wärmeübertragungsmaterial (50), das strukturiert oder unstrukturiert auf die Wärmeableitfläche (11) aufgebracht ist; undeinen Schutzdeckel (20), der derart unverlierbar an dem Halbleitermodul (10) montiert ist, dass im montierten Zustanddie Oberseite (10t) frei liegt und der Schutzdeckel (20) die Wärmeableitfläche (11) überdeckt; undder Schutzdeckel (20) mit dem Halbleitermodul (10) verrastet oder verklebt und dadurch unverlierbar an dem Halbleitermodul (10) montiert ist und von dem Wärmeübertragungsmaterial (50) beabstandet ist und dieses nicht berührt.

Haft-Klebemittel-Zusammensetzung für Halbleiter.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

VERFAHREN ZUM HERSTELLEN EINES GEKAPSELTEN IC-PLAETTCHENS.

Halbleitereinheit und Verfahren zu deren Herstellung

Substrat, verwendbar bei der Herstellung einer Dickschichtschaltung.

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

Control unit for motor vehicles braking systems comprises a frame having a recess filled with a sealing gel which is viscous enough the flow around electrical strip conductors in the recess

Control unit (1) comprises a frame (8) having a recess (9) filled with a sealing gel (16) which is viscous enough the flow around electrical strip conductors (10) in the recess. An independent claim is also included for a process for the production of a control unit. Preferred Features: The sealing gel is a silicone gel which remains elastic after hardening. The recess of the frame is formed as a peripheral groove (9). The unit has a base plate (11) made from a conducting material, e.g. a metal.

VORRICHTUNG ZUM POSITIONIEREN UND/ODER ANPRESSEN EINES FLÄCHIGEN BAUTEILS RELATIV ZU EINEM SUBSTRAT ZEUGS RELATIV ZU EINEM SUBSTRAT

VERFAHREN ZUM HERSTELLEN EINES HYBRID-SCHALTKREISES

VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG

Anschlussleiterloses Package (100) mit:- einem zumindest teilweise elektrisch leitenden Träger (102), der einen Aufbaubereich (104) und einen Anschlussleiterbereich (106) aufweist;- einem elektronischen Chip (108), der an dem Aufbaubereich (104) angebracht ist,- einer Verkapselung (110), die zumindest teilweise den elektronischen Chip (108) verkapselt und teilweise den Träger (102) verkapselt, so dass zumindest ein Teil einer Innenseitenwand (112, 130, 132) des Anschlussleiterbereichs (106) freiliegt, die nicht einen Teil einer Außenseitenwand (115) des Packages (100) bildet, wobeider Anschlussleiterbereich (106) eine Mehrzahl von beabstandeten Anschlussleiterkörpern (118) aufweist, von denen zumindest einer eine zumindest teilweise freiliegende Innenseitenwand (112, 130, 132) hat, die nicht einen Teil der Außenseitenwand (115) des Packages (100) bildet, undeine Bodenfläche (116') der Verkapselung (110) zumindest eine Ausnehmung (198) hat, die zumindest teilweise zumindest eine der Innenseitenwände ...

Gehäuse für mikroelektronische Bauelemente und Verfahren zu seiner Herstellung

Gehäuse für mikroelektronische Bauelemente, das überwiegend aus einem Hochtemperatur-Thermoplast besteht, welcher eine Dauergebrauchstemperatur von mindestens 120° C aufweist, - mit einem Untergehäuse (4), bei welchem innere, elektrische, zungenförmige Anschlüsse (6) für Bauelemente (7) als Teil eines Leitenahmens mit einem Kunststoff rahmenförmig umgespritzt sind und einem Deckel (9), welcher die Bauelemente (7) mit ihren elektrischen Verbindungen (10) und den inneren Anschlüssen (6) umschliesst und mit dem Kunststoffrahmen des Untergehäuses (4) verbunden ist, - wobei der Leiterrahmen an der Stelle, an der die zungenförmigen, inneren Anschlüsse (6) durch die Wand des Untergehäuses (4) hindurchtreten, mit einer rechteckförmigen schmalen Bahn (2) aus einem elektrischen isolierenden Material an seiner Unterseite bedeckt ist, und - wobei die rechteckförmige, schmale Bahn (2) auf einer Wärmesenke (3) in Form einer Scheibe oder eines Rechteckes aus gut wärmeleitendem Material, welche vom Kunststoff ...

Bondvorrichtung und -Verfahren

Eine Bondvorrichtung weist einen Wafertisch, eine erste Chiphalterung, eine erste Transportvorrichtung, eine zweite Chiphalterung und eine zweite Transportvorrichtung auf. Der Wafertisch dient zum Halten des Wafers. Die erste Chiphalterung dient zum Halten mindestens eines ersten Chips. Die erste Transportvorrichtung dient zum Befördern des ersten Chips von der ersten Chiphalterung auf den Wafer. Die zweite Chiphalterung dient zum Halten mindestens eines zweiten Chips. Die zweite Transportvorrichtung dient zum Befördern des zweiten Chips von der zweiten Chiphalterung auf den Wafer.

Leistungshalbleiterbaugruppe und Verfahren zum Herstellen eines Leistungsmoduls und der Leistungshalbleiterbaugruppe

Die vorliegende Erfindung offenbart eine Leistungsbaugruppe, aufweisend ein Leistungsmodul, das einen kupferbasierten Leiterrahmen, mindestens einen Halbleiter, der auf einer ersten Seite des kupferbasierten Leiterrahmens bereitgestellt ist, eine Metallgrundplatte, die auf einer zweiten Seite des kupferbasierten Leiterrahmens bereitgestellt ist, und eine organische Isolierungsschicht, die zwischen dem kupferbasierten Leiterrahmen und der Metallgrundplatte bereitgestellt ist, aufweist. Mindestens ein Mittenloch ist in der Mitte des Leistungsmoduls gebildet. Ein Herstellungsverfahren für das Leistungsmodul und die Leistungshalbleiterbaugruppe sind ebenfalls offenbart.

Halbleiterbauelement und Verfahren zu seiner Herstellung

Ein Halbleiterbauelement enthält einen Halbleiter-Chip, der eine erste Hauptoberfläche und eine zweite Hauptoberfläche umfasst, wobei die zweite Hauptoberfläche die Rückseite des Halbleiter-Chips ist. Weiterhin umfasst das Halbleiterbauelement eine elektrisch leitfähige Schicht, insbesondere eine elektrisch leitfähige Schicht, die auf einem ersten Gebiet der zweiten Hauptoberfläche des Halbleiter-Chips angeordnet ist. Weiterhin umfasst das Halbleiterbauelement eine Polymerstruktur, die auf einem zweiten Gebiet der zweiten Hauptoberfläche des Halbleiter-Chips angeordnet ist, wobei das zweite Gebiet ein Randgebiet der zweiten Hauptoberfläche des Halbleiter-Chips ist und das erste Gebiet dem zweiten Gebiet benachbart ist.

Aufbringung von Schutzmaterial auf Wafer-Ebene bei einem Eingangsprozess für Frühphasen-Teilchen- und -Feuchtigkeitsschutz

Ein Halbleiterbauelement und ein Verfahren zur Herstellung desselben werden derart bereitgestellt, dass ein Element mit mikroelektromechanischen Systemen (MEMS-Element) in einer frühen Herstellungsphase geschützt wird. Ein Verfahren zum Schützen eines MEMS-Elements beinhaltet folgende Schritte: Bereitstellen zumindest eines MEMS-Elements mit einem empfindlichen Bereich auf einem Substrat; und Aufbringen, vor einem Package-Zusammenbau-Prozess, eines Schutzmaterials über dem empfindlichen Bereich des zumindest einen MEMS-Elements, so dass der empfindliche Bereich zumindest eines MEMS-Elements vor einer äußeren Umgebung abgedichtet ist, wobei das Schutzmaterial eine Sensorfunktionalität des zumindest einen MEMS-Elements erlaubt.

Verfahren zum Verkapseln von elektrischen oder elektronischen Bauelementen oder Baugruppen und Verkapselung von elektrischen oder elektronischen Bauelementen oder Baugruppen

STEUERGERÄTEEINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

VERFAHREN ZUM ABDICHTEN VON UMHUELLUNGEN FUER ELEKTRISCHE TEILE

HOUSINGS FOR SEMICONDUCTOR DEVICES

Hermetically sealed wafer level packaging for optical MEMS devices

Optical MEMS chips 315 are assembled on a CMOS semiconductor wafer substrate 310 comprising integrated circuits 312 and interconnects 314. A transparent cover 337 having standoff portions 324 is mounted on the semiconductor wafer and seals the individual chips. The assembly can then be subdivided into individual device packages (see figure 3D).

A method of casting

LEADED CHIP CARRIER

Hermetically sealed wafer level packaging for optical MEMS devices

Optical MEMS chips 315 are assembled on a CMOS semiconductor wafer substrate 310 comprising integrated circuits 312 and interconnects 314. A transparent cover 337 having standoff portions 324 is mounted on the semiconductor wafer and seals the individual chips. The assembly can then be subdivided into individual device packages. An optical stop or spatial filter 825 may be arranged on the transparent cover (figure 8).

Casting mould comprising a photopolymer

A method of casting a product comprises creating a finished photopolymer mould, introducing liquid into the mould, hardening the liquid and removing the photopolymer mould. Removal may be conventional or comprise destroying the mould by burning or dissolving the. The mould may comprise a photopolymer plate attached to a formwork and treated with release agent or a heat resistant material prior to casting. The mould may be used to cast a refractory mould used to cast a secondary product comprising glass metal or ceramics. The mould may be used to cast concrete, glass, gels, metal, polymer, plaster and foodstuffs such as high-resolution embossed icing on a cake. A design having line work or halftones by way of recesses in the photopolymer can produce a cast product with tonal variations. During production one or both sides of a photopolymer plate may be exposed to light through a mask comprising a filter which permits variable intensity of light to reach the photopolymer. The mould may be ...

Method for interconnecting stacked semiconductor devices

Magnetic field sensor and method for making same

A semiconductor chip 100 for measuring a magnetic field, the semiconductor chip comprises a magnetic sensing element 110 and an electronic circuit 120, wherein: the magnetic sensing element 110 is mounted on the electronic circuit 120; the magnetic sensing element 110 is electrically connected with the electronic circuit 120; the electronic circuit 120 is produced in a first technology and/or first material and the magnetic sensing element 110 is produced in a second technology and/or second material different from the first technology / material. Also disclosed is a method of making the above semiconductor chip 100, the method comprising manufacturing at least one target device comprising the electronic circuit 120 on a first wafer; manufacturing at least one source device comprising the magnetic sensing element 110 on a second wafer, where the second material has a higher carrier mobility than the first material at room temperature; transferring the at least one target device to the at ...

LEADED CHIP CARRIER

SEALING SYSTEM FOR HERMETIC MICROCHIP PACKAGES

Passive semiconductor device assembly technology

Improvements in or relating to the manufacture of semi-conductor devices

... 775,191. Welding by pressure. GENERAL ELECTRIC CO., Ltd. Aug. 19, 1955 [Aug. 23, 1954], No. 24500/54. Class 83 (4). [Also in Group XXXVI] In the manufacture of a semi-conductor device in a sealed envelope, at least one seal is made by cold pressure welding, after the operative part of the device is mounted in the envelope. Fig. 1 shows a PN junction rectifier comprising a germanium wafer 3 on an oxygen-free high conductivity copper base I and having an alloy electrode comprising a bead of indium 5 and lead wire 7. The assembly is completed by placing a copper cover-plate 8 on to base 1 and cold welding the flanges 11 and 12. The lead wire 7 which may be of nickel, passes through, and is cold welded to, nickel tube 10 which is insulated from cover 8 by a glass region 9. In Fig. 2, which shows the apparatus for the cold welding, steel punches 15 and 16 sliding in tube 13, compress the flanges 11 and 12 together. A groove 12 in the base 1 accommodates the flow of metal. Wire 7 is welded to ...

VERFAHREN UND VORRICHTUNG ZUM HERSTELLEN EINER, INSBESONDERE VERTIKALEN, ANORDNUNG AUS MINDESTENS ZWEI ELEKTRONISCHEN KOMPONENTEN

ADHESIVE FILM FOR CHIPBONDIERUNG

STRUCTURAL UNIT AND PROCEDURE FOR THE PRODUCTION OF A STRUCTURAL UNIT

THIN FILM GETTER PROTECTION

ULTRASONIC CLEANING MODULE AND PROCEDURE

PROCEDURE FOR THE PRODUCTION OF A CURRENT SETTER ARRANGEMENT WITH COOLING EQUIPMENT AND STATIC INVERTER ARRANGEMENT

PROCEDURE AND DEVICE FOR THE EXAMINATION OF A CHIP BEFORE BONDING

ARTS OF MANUFACTURING FOR ELECTRICAL MECHANISM

HERMETICALLY SEALINGS POLE ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION.

Procedure for the production of a glass-metal seal

SEMICONDUCTOR BODY WITH PLUMB BOB MATERIAL LAYER AND PROCEDURE FOR THE AUFLÖTEN OF THE SEMICONDUCTOR BODY ON A METALLIC MOTHER BOARD

METHOD OF MAKING A HERMETICALLY SEALED PACKAGE HAVING AN ELECTRONIC COMPONENT

HERMETICALLY SEALED MICRO-DEVICE PACKAGE WITH WINDOW

METHOD FOR FORMING HOUSINGS FOR ELECTRONIC COMPONENTS AND ELECTRONIC COMPONENTS THAT ARE HERMETICALLY ENCAPSULATED THEREBY

Arrangement for encasing a functional device, and a process for the production of same

ARRANGEMENT FOR ENCASING A FUNCTIONAL DEVICE, AND A PROCESS FOR THE PRODUCTION OF SAME

Semiconductor device fabrication method and semiconductor device fabrication device

Chip scale package

Method of and apparatus for sealing a hermetic lid to a semicond uctor die

NICKEL/INDIUM PLATED COVER FOR HERMETICALLY SEALED CONTAINER FOR ELECTRONIC DEVICE

This invention relates to a new and improved hermetically sealed container for semiconductor and other electronic devices, to a novel sealing cover for use in fabricating the above-referenced hermetically sealed container, and to novel processes for manufacturing said container and cover. The specification discloses an improved method of fabricating a hermetically sealed container consisting of a body having a cavity therein for receiving a semiconductor device and a cobalt-nickel-iron alloy sealing cover therefor comprising superimposing upon the sealing cover and in registry with the periphery thereof a preformed ring of heat-fusible material of a thickness which is a minor fraction of that of said cover; engaging said ring with at least one pair of spaced electrodes; passing a pulse of current through the electrodes, the ring, and the cover, thereby producing an effective attachment between said ring and said cover adjacent each of said electrodes; disposing a semiconductor device in ...

MULTI-COMPONENT MICROCIRCUIT PACKAGES

MULTI-COMPONENT MICROCIRCUIT PACKAGES A multi-component microcircuit package is formed from a plurality of separate components which are secured together to form a lower package portion having a base and a continuous composite side wall frame having irregularities on its upper surface as a result of the component junctions. Secured to the top of this side wall frame is a one-piece continuous top frame member having a uniform upper surface. This top frame member covers the irregularities present in side wall frame and provides a surface more suitable for hermetic sealing of a package lid to the package.

SOLDER PREFORM

SOLDER PREFORM A solder preform for hermetically sealing a cover to a container for a semiconductor package comprises a relatively thick Mat ring of an alloy comsisting of substantially 63% tin and 37% lead and having a characteristic that it solidifies from the fluid state as a homogeneous mixture. The solder preform has a relatively thin coating clad on each surface thereof of an oxidation-resistant alloy consisting of substantially 96.5% tin and 3.5% silver. The thickness of the ring is of the order of 0.0018 inch and the thickness of the alloy coaling is of the order of 0.0001 inch.

FABRICATION OF CIRCUIT PACKAGES

HALL-1 FABRICATION OF CIRCUIT PACKAGES A method of fabricating circuit packages which employ macro-components mounted on supporting substrates. In order to maintain sufficient clearance between the component and substrate and achieve high reliability bonds, massive solder preforms are applied to contact pads on either the component or substrate. After contact pads of both carrier and substrate are brought into contact with the spheres, the bond is formed.

SOLDER PREFORM FOR USE IN HERMETICALLY SEALING A CONTAINER

SOLDER PREFORM FOR USE IN HERMETICALLY SEALING A CONTAINER A solder preform for hermetically sealing a cover to a container for a semiconductor package comprises a relatively thick flat ring of an alloy consisting of substantially 95% lead, 2.5% tin, and 2.5% silver, which alloy has the characteristic that it solidifies from the fluid state as a homogeneous mixture without substantial separation of the minority element crystals. The solder preform further comprises a relatively thin coating clad on each surface of the flat ring of an oxidation-resistant alloy, preferably an alloy consisting of substantially 96.5% tin and 3.5% silver.

PLASTIC RESIN AND FIBRE ENCAPSULATION OF ELECTRONIC CIRCUIT DEVICE AND METHOD AND APPARATUS FOR MAKING SAME

PACKAGE FOR INTEGRATED CIRCUIT DIE

A circuit package for housing semiconductor or other integrated circuit devices ("die") includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

METHOD OF MAKING PACKAGED IC CHIP

NICKEL/INDIUM PLATED COVER FOR HERMETICALLY SEALED CONTAINER FOR ELECTRONIC DEVICE

ASSEMBLY OF A CARRIER AND A PLURALITY OF ELECTRICAL CIRCUITS FIXED THERETO, AND METHOD OF MAKING THE SAME

A method of obtaining an elongate carrier (12) to which a plurality of circuits (14) are fixed at their outer portions. The central portions (141) of the circuits are removed while the outer portions remain fixed to the carrier. A circuit (14) is fastened to a carrier (12) where electrical conductors extend from conducting pads of the circuit through holes (121) in the carrier to conducting pads of the carrier on an opposite side of the carrier.

SYSTEM AND METHOD FOR PROVIDING IC CHIP MODULES FOR PAYMENT OBJECTS

A system and method are disclosed for providing integrated circuit (IC) chip modules for inclusion in payment objects. IC chip modules may be received from a supplier of IC chip modules, wherein the IC chip modules are supportably interconnected to a flexible substrate and transport key data is encoded in the IC chip modules. Each IC chip module may be encoded with personalization data and issuer key data. Encoding of IC chip modules may be completed utilizing either a contact IC chip interface device or a non-contact IC chip interface device. Encoding the IC chip modules may be completed with the IC chip modules supportably interconnected to the flexible substrate as supplied by the supplier of the IC chip modules, free from fixed interconnection of the IC chip modules and carrier to another support structure.

ENCAPSULATION FOR AN ELECTRONIC COMPONENT AND A PROCESS FOR ITS MANUFACTURE

Sensitive component structures (2) can be encapsulated by enclosing them with a frame structure (6) consisting of a light-sensitive reaction resin and covering the latter with another, structured layer of reaction resin after applying an auxiliary film (7). Top structures (10) which fit over the frame structures (6) can be produced e.g., by structured imprinting or photostructuring. The residual parts of the exposed auxiliary film are removed by dissolving or etching.

METHOD OF FABRICATING AN HERMETICALLY SEALED CONTAINER AND A SEALING COVER THEREFOR

REACTIVE FOIL ASSEMBLY

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS TEMPERATURE INSTABILITY (BTI) IN SILICON CARBIDE DEVICES

A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.

GLASS MATERIAL FOR USE AT HIGH FREQUENCIES

The aim of the invention is to improve the high-frequency characteristics of high-frequency substrates or high-frequency conductor assemblies. To achieve this, the invention provides a glass material for producing insulation layers for high-frequency conductor assemblies. Said material is applied as a layer, in particular with a layer thickness ranging between 0.05 .mu.m and 5 mm, with a tangent of loss angle tan.delta. in at least one frequency range above 1 GHz of less than or equal to 70*10-4.

SEALING SYSTEM FOR HERMETIC MICROCHIP PACKAGES

SEALING SYSTEM FOR HERMETIC MICROCHIP PACKAGES A sealable hermetic microchip package includes a vent therein that permits gas to escape during the sealing operation, but then itself is sealed at the completion of the sealing operation to render the package hermetic. The venting of gas from the interior of the package avoids the buildup of internal pressure during the sealing operation that can introduce bubbles and other faults into the sealing material. The vent may be a channel in the sealing surface of the lid of the package that is initially open, and then fills with the seal material as it flows to effect the seal. The vent may also be a hole in the lid that is sealed by the flow of a bead of the seal material. An equivalent approach to venting provides that the lid be mounted on standoffs that flow during sealing to permit the lid to settle onto the base of the package.

Verfahren zur Herstellung einer mit einer hermetisch verschlossenen Ummantelung versehenen Halbleiter-Vorrichtung und gemäss dem Verfahren hergestellte Halbleiter-Vorrichtung

Verfahren zur Herstellung einer Halbleitervorrichtung und gemäss diesem Verfahren hergestellte Halbleitervorrichtung

Verfahren zur Herstellung einer eine Legierungselektrode aufweisenden Halbleitervorrichtung und nach dem Verfahren hergestellte Halbleitervorrichtung

Verfahren und Vorrichtung zum maschinellen Zusammensetzen von Einzelteilen für Kristalldioden und nach dem Verfahren hergestellte Kathodenteile

Verfahren zum Zuschmelzen von in ein gläsernes Material eingeschlossenen Halbleiter-Schaltelementen und Vorrichtung zur Durchführung dieses Verfahrens

Verfahren zum örtlichen Aneinanderheften von Metallteilen

Verfahren zum örtlichen Aneinanderheften von Metallteilen

Procédé pour mettre sous boîtier un composant électronique

Procedimento per formare elementi di base muniti di conduttori per montaggio di dispositivi elettrici ed elemento ottenuto con tale procedimento

Verfahren zur Herstellung zusammengesetzter Körper, insbesondere von Teilen einer Umhüllung für Transistoren für hohe Leistungen

Verfahren zum vakuumdichten Verbinden eines Verschlussteils aus Metall mit dem Rand eines Gehäuses mittels Widerstandsschweissung und nach diesem Verfahren hergestelltes, mit dem Verschlussteil versehenes Gehäuse für Halbleitervorrichtun gen

Verfahren zum serienweisen Herstellen von mit den erforderlichen elektrischen Anschlüssen versehenen Gehäusen für Halbleitervorrichtungen

Procédé de fabrication d'un dispositif électrique enfermé dans un boîtier et dispositif sous boîtier obtenu par ce procédé

Mounting for microchip - comprises cylindrical casing with screw fitting cover, and connection pins passing through base

The mounting for a microchip includes a support which forms a cylindrical casing around the microchip, with fixing points (2) for attachment to a rigid object. Connection pins (16) pass through the base of the support, connecting the microchip to an associated circuit. The support includes aligning parts (8), and projecting pegs which engage internal grooves (10) in a cover which is to be fitted to the support. USE - Mechanical protection of microchip used in computers, household appliances and scientific equipment.

Mechanism for the assembly of semiconductor chips.

Eine Einrichtung für die Montage von Halbleiterchips (12) umfasst ein Pick-and-Place-System (4) mit einem Bondkopf (5), einen Pickkopf (7) und einen Auflagetisch (8). Der Pickkopf (7) und der Auflagetisch (8) sind an einem Schlitten (6) gelagert. Die Einrichtung ist in einem Direktmodus und einem Parallelmodus betreibbar, wobei im Direktmodus der Schlitten (6) in der ersten Position ist, die eine Parkposition ist, und eine Steuereinheit (9) das Pick-and-Place-System (4) derart betreibt, dass der Bondkopf (5) einen Halbleiterchip (12) nach dem andern vom Wafertisch (1) entnimmt und auf dem Substrat (2) platziert. Im Parallelmodus ist der Schlitten (6) in der zweiten Position, und die Steuereinheit (9) betreibt den Pickkopf (7), den Auflagetisch (8) und das Pick-and-Place-System (4) derart, dass der Pickkopf (7) einen Halbleiterchip (12) nach dem anderen vom Wafertisch (1) entnimmt und auf dem Auflagetisch (8) platziert, und der Bondkopf (5) einen Halbleiterchip (12) nach dem anderen vom ...

Apparatus for mounting semiconductor chips.

Eine Einrichtung für die Montage von Halbleiterchips (12) umfasst ein Pick-and-Place-System (4) mit einem Bondkopf (5), einen Pickkopf (7) und einen Auflagetisch (8). Der Pickkopf (7) und der Auflagetisch (8) sind an einem Schlitten (6) gelagert. Die Einrichtung ist in einem Direktmodus und einem Parallelmodus betreibbar, wobei im Direktmodus der Schlitten (6) in der ersten Position ist, die eine Parkposition ist, und eine Steuereinheit (9) das Pick-and-Place-System (4) derart betreibt, dass der Bondkopf (5) einen Halbleiterchip (12) nach dem andern vom Wafertisch (1) entnimmt und auf dem Substrat (2) platziert. Im Parallelmodus ist der Schlitten (6) in der zweiten Position, und die Steuereinheit (9) betreibt den Pickkopf (7), den Auflagetisch (8) und das Pick-and-Place-System (4) derart, dass der Pickkopf (7) einen Halbleiterchip (12) nach dem anderen vom Wafertisch (1) entnimmt und auf dem Auflagetisch (8) platziert und der Bondkopf (5) einen Halbleiterchip (12) nach dem anderen vom Auflagetisch ...

Method for removing a semiconductor chip from a film.

Ein Verfahren zum Ablösen eines Halbleiterchips von einer Folie verwendet einen Chip-Auswerfer, der erste Platten, die eine gerade Stützkante haben, und zweite Platten (8), die eine L-förmige Stützkante (19) haben, aufweist. Das Verfahren umfasst folgende Schritte: A) Beaufschlagen einer Unterseite der Abdeckplatte mit Vakuum, um die Folie an die Abdeckplatte zu ziehen, B) Anheben der Platten, so dass die Stützkanten der Platten eine Höhe H 1 , über der Oberfläche der Abdeckplatte einnehmen, C) Absenken eines ersten Paares von Platten (8) mit L-förmiger Stützkante (19), D) fakultativ, Absenken eines zweiten Paares von Platten (8) mit L-förmiger Stützkante (19), E) Anheben zumindest der bisher noch nicht abgesenkten Platten, so dass die Stützkanten der bisher noch nicht abgesenkten Platten eine Höhe H 2 > H 1 einnehmen, F) gestaffeltes Absenken von bisher noch nicht abgesenkten Platten in einer vorbestimmten Reihenfolge, wobei jedoch mindestens eine oder mehrere Platten nicht abgesenkt werden ...

Procedure for the replacement of a semiconductor chip of a foil.

Ein Verfahren zum Ablösen eines Halbleiterchips von einer Folie verwendet einen Chip-Auswerfer, der erste Platten, die eine gerade Stützkante haben, und zweite Platten, die eine L-förmige Stützkante haben, aufweist. Das Verfahren umfasst folgende Schritte: A) Anheben der Platten, so dass die Stützkanten (19) der Platten eine Höhe H 1 über der Oberfläche (12) der Abdeckplatte einnehmen, B) Absenken eines ersten Paares von Platten mit L-förmiger Stützkante, C) fakultativ, Absenken eines zweiten Paares von Platten mit L-förmiger Stützkante, D) Anheben zumindest der bisher noch nicht abgesenkten Platten, so dass die Stützkanten (19) der bisher noch nicht abgesenkten Platten eine Höhe H 2 > H 1 einnehmen, E) gestaffeltes Absenken von bisher noch nicht abgesenkten Platten in einer vorbestimmten Reihenfolge, wobei jedoch mindestens eine oder mehrere Platten nicht abgesenkt werden, F) fakultativ, Absenken zumindest der bisher noch nicht abgesenkten Platten, so dass die Stützkanten (19) der bisher ...

Procedure and device for the inspection of a semiconductor chip before the assembly.

Eine Chipmanipulationsvorrichtung und ein Verfahren zum Manipulieren von Chips werden präsentiert. Die Chipmanipulationsvorrichtung, umfasst eine Vorratsstation für Chips, eine Montagestation für Chips und eine oder mehrere Chipmanipulationseinheiten welche dazu ausgelegt sind, einen Chip von der Vorratsstation aufzunehmen, zu der Montagestation zu transportieren und an einer Montageposition zu platzieren, wobei jede Chipmanipulationseinheit dazu ausgelegt ist, den Chip vorübergehend in einer definierten Lage in Bezug auf die Chipmanipulationseinheit zu halten. Die Chipmanipulationsvorrichtung umfasst Mittel zum Anregen von Schwingungen, insbesondere akustischen Schwingungen und/oder Ultraschallschwingungen im Chip, während dieser von einer der Chipmanipulationseinheiten gehalten wird, sowie Mittel zum Messen der im Chip angeregten Schwingungen.

Method and apparatus for mounting semiconductor chips.

Eine Halbleiter-Montageeinrichtung, mit einer Dispensstation (1) zum Auftragen von Klebstoffportionen auf die Substratplätze eines Substrats, mit einer Bondstation (3) zum Platzieren von Halbleiterchips auf den mit Klebstoff versehenen Substratplätzen und mit einer Transportvorrichtung für den Transport der Substrate entlang eines Transportwegs enthält eine zwischen der Dispensstation (1) und der Bondstation (3) angeordnete Pufferstation (2), die es ermöglicht, entweder ein Substrat, das von der Dispensstation (1) zur Bondstation (3) zu transportieren ist, temporär aus dem Transportweg herauszunehmen, so dass ein anderes Substrat von der Transportvorrichtung von der Bondstation (3) zur Dispensstation (1) transportiert werden kann, oder ein Substrat, das von der Bondstation (3) zur Dispensstation (1) zu transportieren ist, temporär aus dem Transportweg herauszunehmen, so dass ein anderes Substrat von der Transportvorrichtung von der Dispensstation (1) zur Bondstation (3) transportiert werden ...

Procedure and device for the assembly of semiconductor chips.

Eine Halbleiter-Montageeinrichtung, mit einer Dispensstation (1) zum Auftragen von Klebstoffportionen auf die Substratplätze eines Substrats, mit einer Bondstation (3) zum Platzieren von Halbleiterchips auf den mit Klebstoff versehenen Substratplätzen und mit einer Transportvorrichtung für den Transport der Substrate entlang eines Transportwegs enthält eine zwischen der Dispensstation (1) und der Bondstation (3) angeordnete Pufferstation (2), die es ermöglicht, entweder ein Substrat, das von der Dispensstation (1) zur Bondstation (3) zu transportieren ist, temporär aus dem Transportweg herauszunehmen, so dass ein anderes Substrat von der Transportvorrichtung von der Bondstation (3) zur Dispensstation (1) transportiert werden kann, oder ein Substrat, das von der Bondstation (3) zur Dispensstation (1) zu transportieren ist, temporär aus dem Transportweg herauszunehmen, so dass ein anderes Substrat von der Transportvorrichtung von der Dispensstation (1) zur Bondstation (3) transportiert werden ...

thermo-compression procedure and apparatus for mounting semiconductor chips on a substrate.

Gegenstand der Erfindung ist ein Thermokompressionsverfahren für die Montage von Halbleiterchips (5) auf einem Substrat (4) und umfasst: Aufnehmen des Halbleiterchips (5) mit einem an einem TC-Bondkopf (2) verschiebbar gelagerten Chipgreifer (8), positionieren des Chipgreifers (8) oberhalb des zugeordneten Substratplatzes (4), absenken des TC-Bondkopfs (2) bis auf eine Position, bei der der Chipgreifer (8) relativ zum TC-Bondkopf (2) um eine vorbestimmte Distanz ausgelenkt ist, aufheizen des Halbleiterchips (5) auf eine Temperatur oberhalb der Schmelztemperatur des Lötmittels, so dass die Auslenkung des Chipgreifers (8) wieder null wird, warten bis die Temperatur des Halbleiterchips (5) auf einen Wert unterhalb der Schmelztemperatur des Lötmittels abgesunken ist, und anheben des TC-Bondkopfs (2).

Method for mounting semiconductor chip on a substrate provided with bumps substrate locations.

Die Erfindung betrifft ein Verfahren für die Montage von mit Bumps (1) versehenen Halbleiterchips (2) als Flipchips (3) auf Substratplätzen eines Substrats (11). Das Verfahren umfasst das Platzieren eines Flipchips (3) in einer ortsfest angeordneten Kavität (18), wo die Bumps (1) mit Flussmittel benetzt werden und mittels einer Kamera (14) die Lage des Flipchips (3) ermittelt wird. Das Verfahren umfasst weiter das Verwenden eines Transportkopfs (8) und eines Bondkopfs (10), die eine schnelle und hochgenaue Montage ermöglichen.

Semiconductor package

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Method and system for template assisted wafer bonding

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Sealed electronic housing and method for the sealed assembly of such a housing

Method for the sealed assembly of an electronic housing containing one or more electronic components, the method including: assembling the housing by bringing a support, to which the electronic components are fixed, in contact with a cover by means of a mixture including a paste and nanoparticles in suspension in said paste, the size of the nanoparticles ranging from 10 to 30 nm; and closing the housing in a sealed manner by heating the housing to a temperature T of between 150° C. and 180° C. making it possible to sinter the metal nanoparticles, while subjecting the housing to a pressure greater than 2.5×10 5 Pa.

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

Semiconductor device and semiconductor chip

The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Method of Manufacturing a Device with a Cavity

The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof. 1. A micro-device , comprising a substrate with a cavity , wherein the cavity is covered with a porous layer that is permeable to vapor HF etchant , wherein the micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device , wherein the component is arranged within the cavity.2. The micro-device of claim 1 , further comprising a patterned packaging cap layer with a release hole extending to the cavity claim 1 , wherein the porous layer is provided on the packaging cap layer and in the release hole.3. The micro-device of claim 1 , wherein the micro-device does not include a packaging cap layer between the porous layer and the cavity.4. The micro-device of claim 1 , further comprising a sealing layer deposited over the porous layer.5. The micro-device of claim 1 , wherein the porous layer comprises carbon-doped oxide.6. The micro-device of claim 5 , wherein the porous layer is densified.7. The micro-device of claim 1 , wherein the cavity comprises an air gap in a sacrificial oxide region.8. The micro-device of claim 6 , wherein the sacrificial oxide region comprises silicon oxide.9. The micro-device of claim 1 , wherein the porous layer has a thickness less than 700 nm.10. A method of manufacturing a semiconductor ...

ELECTRO-ACOUSTIC CONVERSION DEVICE MOUNT SUBSTRATE, MICROPHONE UNIT, AND MANUFACTURING METHOD THEREFOR

The disclosed substrate () has an electro-acoustic conversion element (), which converts sound signals into electric signals, mounted thereon. Furthermore, the substrate is provided with: a mounting surface () in which an opening () covered by the electro-acoustic conversion element () is formed; an intra-substrate space () connected to the opening (); and a coating layer (CL) that covers at least part of the wall surface () of the intra-substrate space (). 112-. (canceled)13. An electro-acoustic conversion device mount substrate that is mounted with an electro-acoustic conversion device which converts a sound signal into an electric signal , comprising:a mount surface on which the electro-acoustic conversion device is mounted and which is provided with an opening that is covered by the electro-acoustic conversion device;an intra-substrate space that connects to the opening; anda coating layer that covers at least a portion of a wall surface of the substrate which composes the intra-substrate space.14. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the coating layer is a plated layer.15. The electro-acoustic conversion device mount substrate according to claim 13 , wherein a glass epoxy material is used as a substrate material.16. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the intra-substrate space does not connect to an opening other than the opening that is covered by the electro-acoustic conversion device.17. The electro-acoustic conversion device mount substrate according to claim 13 , wherein the intra-substrate space connects to an opening other than the opening that is covered by the electro-acoustic conversion device.18. The electro-acoustic conversion device mount substrate according to claim 17 , wherein the other opening is disposed through a rear surface opposite to the mount surface.19. The electro-acoustic conversion device mount substrate according to claim 17 , ...

Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding

A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a plurality of interconnect sites over the substrate;forming a plurality of conductive traces over the substrate adjacent to the interconnect sites;forming a plurality of insulating layers respectively over each of the conductive traces; anddisposing a semiconductor die over the substrate with a plurality of interconnect structures electrically connecting the semiconductor die to the interconnect sites and contacting the insulating layers over the conductive traces.2. The method of claim 1 , further including forming a surface treatment over the interconnect sites.3. The method of claim 1 , wherein the interconnect structures are selected from a group consisting of a bump including fusible material claim 1 , bump including non-fusible portion and fusible portion claim 1 , bump including surface asperities claim 1 , bump having a length along the interconnect sites greater than a width across the interconnect sites claim 1 , and bump including a tip.4. The method of claim 1 , wherein the interconnect sites include a ...

Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers

A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first polymer layer;forming a first conductive layer over a first surface of the first polymer layer;disposing a first semiconductor die over a second surface of the first polymer layer opposite the first surface of the first polymer layer;forming a second polymer layer over the first polymer layer and first semiconductor die;forming a first conductive via through the first polymer layer and second polymer layer and electrically connected to the first conductive layer; andforming a third polymer layer over the second polymer layer.2. The method of claim 1 , further including forming a second conductive layer over the second polymer layer and electrically connected to the first conductive via prior to forming the third polymer layer.3. The method of claim 1 , further including forming an interconnect structure over and through the third polymer layer.4. The method of claim 3 , wherein forming the interconnect structure includes:forming a second conductive via ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode. 1. A method of manufacturing a semiconductor device , comprising: a step (a) of mounting a first electronic part to one face of a flexible circuit board; a step (b) of mounting a supporter , which includes a groove that houses the firstelectronic part, to the one face of the flexible circuit board so as to enclose the first electronic part;a step (c) of bending the flexible circuit board along a perimeter of the supporter to be wrapped around at least one side face of the supporter and at least a portion of a face of the supporter that is opposite to a face where the groove is formed, and adhering the flexible circuit board to at least the portion of the face of the supporter;a step (d) of mounting a second electronic part to a face of the flexible circuit board that is opposite to the one face where the first electronic part is mounted; anda step (e) of ...

Method for producing a two-chip assembly and corresponding two-chip assembly

A method for producing a two-chip assembly includes: providing a wafer having a first thickness, which wafer has a front side and a back side, a first plurality of first chips being provided on the front side of the wafer; attaching a second plurality of second chips on the front side of the wafer, so that every first chip is joined in each instance to a second chip and forms a corresponding two-chip pair; forming a cohesive mold package on the front side of the wafer, so that the second chips are packaged; thinning the wafer from the back side to a second thickness which is less than the first thickness; forming vias from the back side to the second chips; and separating the two-chip pairs into corresponding two-chip assemblies. 1. A method for producing a two-chip assembly , comprising:providing a wafer having a first thickness, a front side, and a back side, a first plurality of first chips being provided as part of the wafer;mounting a second plurality of second chips on the front side of the wafer so that every first chip is joined in each instance to a corresponding second chip and forms a corresponding two-chip pair;forming a cohesive one-sided mold package on the front side of the wafer so that the second chips are packaged;thinning the wafer from the back side to a second thickness which is less than the first thickness;forming multiple vias and electrical connections from the back side to the second chips; andseparating the two-chip pairs into corresponding two-chip assemblies.2. The method as recited in claim 1 , wherein:the first chips have first electrical connection areas on the front side of the wafer; andthe first electrical connection areas are connected to corresponding second connection areas of the second chips upon mounting of the second plurality of second chips.3. The method as recited in claim 2 , wherein the first connection areas are used as stop surfaces when forming the vias.4. The method as recited in claim 3 , wherein the thinning of ...

Method of fabricating a memory card using sip/smt hybrid technology

A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDTM card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.

FLANGE PACKAGE FOR A SEMICONDUCTOR DEVICE

In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed. 1. An apparatus comprising:a substrate;an interposer trench formed within the substrate; anda mold lock formed within the substrate and about the interposer trench, wherein the mold lock includes an alignment structure formed thereon.2. The apparatus of claim 1 , further comprising a channel that extends between the interposer trench and the mold lock.3. The apparatus of claim 2 , wherein the channel extends to a depth shallower than a depth of the interposer trench and a depth of the mold lock.4. The apparatus of claim 1 , further comprising a channel that extends from the interposer trench toward the mold lock but remains spaced apart from the mold lock.5. The apparatus of claim 1 , further comprising a U-shaped trench extending from the interposer trench.6. The apparatus of claim 1 , further comprising a trench extension extending from the interposer trench claim 1 , wherein the trench extension and the interposer trench surround a plurality of contacts formed on the substrate.7. The apparatus of claim 1 , wherein the mold lock surrounds a periphery of the interposer trench.8. The apparatus of claim 1 , wherein the mold lock comprises a trench within the substrate.9. The apparatus of claim 8 , wherein the trench ...

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement

A semiconductor arrangement includes an artificial chip having a semiconductor chip and an electrically insulating molding compound. The semiconductor chip has circuit structures and is embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip. A thin-film substrate is applied to the enlarged base area and extends beyond the base area of the semiconductor chip into the enlarged base area. The substrate has at least two layers composed of nonconductive material between which a structured metallization is disposed. A first coil is formed by one or a plurality of structured metallization layers in the substrate. A second coil is magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil. 1. A semiconductor arrangement for galvanically isolated signal transmission , comprising:an artificial chip including a semiconductor chip and an electrically insulating molding compound, the semiconductor chip having circuit structures and being embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip;a thin-film substrate applied to the enlarged base area of the artificial chip and extending beyond the base area of the semiconductor chip into the enlarged base area, the substrate having at least two layers composed of nonconductive material between which a structured metallization is disposed;a first coil formed by one or a plurality of structured metallization layers in the substrate; anda second coil magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil.2. The semiconductor arrangement as claimed in claim 1 , wherein the ...

Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof

The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield. 1. A three-dimensional vertically interconnected structure , characterized in that , it comprises at least two layers of chip which are stacked in sequence or stacked together face to face , and a layer of adhesive material is used for adhesion between adjacent layers of said chip , each layer of said chip containing a substrate layer and a dielectric layer sequentially from bottom to top; a front surface of the chip has a first concave with an annular cross section , and the first concave is filled with metal therein to form a first electrical conductive ring which is connected to microelectronic devices inside the chip via a redistribution layer; a first through layers of wafers or chips hole having the same radius ...

TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION

Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. 1. A method for providing an inductive coupling between dies , comprising:fabricating a first inductor on a first die using a passive process;fabricating a second inductor on a second die using a semiconductor process; andassembling each die so the first and second inductor are configured as a transformer.2. The method of claim 1 , further comprising:placing a ferromagnetic material between the first and second inductor.3. The method of claim 2 , wherein the ferromagnetic material comprises a ferrite film.4. The method of claim 1 , further comprising:fabricating the first inductor with a greater number of windings than the second inductor.5. The method of claim 1 , further comprising:fabricating active components on the first die; andfabricating additional passive components on the second die.6. The method of claim 1 , wherein the first and second die are assembled using a three-dimensional flip chip process.7. The method of claim 1 , further comprising:physically coupling a low noise RF amplifier to the second inductor, which receives an inductively coupled RF signal that does not contact a mechanical connection from the first inductor, ...

WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS

A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. 1. A method of manufacturing semiconductor package from a wafer having at least one integrated circuit (IC) formed on an active surface , said method comprising:a) attaching a stiffener to an inactive surface of said wafer;b) forming substantially rectangular under bump metallization (UBM) pads, each one of said UBM pads in communication with said IC, said UBM pads comprising at least a first UBM pad, and a second UBM pad larger than said first UBM pad;c) forming solder bumps extending from each of said UBM pads; andd) separating said wafer into semiconductor packages.2. The method of claim 1 , further comprising forming a compliant layer on said active surface of said wafer prior to said forming said UBM pads.3. The method of claim 2 , wherein said compliant layer comprises a dielectric material.4. The method of claim 1 , further comprising thinning said wafer by grinding claim 1 , prior to said attaching said stiffener.5. The method of claim 1 , wherein said first UBM pad is formed near a periphery of said semiconductor chip package.6. The method of claim 5 , wherein said second UBM pad is formed near a center of said semiconductor chip package.7. The method of claim 1 , wherein said stiffener is made of one of organic and metallic materials.8. The method of claim 2 , further comprising forming conductive rerouting to interconnect each of a plurality of die pads corresponding to each IC claim 2 , to a corresponding one of ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate having a sensor region and an integrated circuit region, with a cavity formed immediately under a surface layer portion of the sensor region;a capacitive acceleration sensor formed on the sensor region; anda CMIS transistor formed on the integrated circuit region, whereinthe capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode formed by working the surface layer portion opposed to the cavity to mesh with each other at an interval, andthe CMIS transistor includes an N-type well region formed on a surface layer portion of the semiconductor substrate in the integrated circuit region and having a P-type source region and a P-type drain region, a P-type well region formed on the surface layer portion of the semiconductor substrate in the integrated circuit region and having an N-type source region and an N-type drain region, and a gate electrode opposed to the respective ones of the N-type well region and the P-type well region through a gate insulating film formed on a surface of the semiconductor substrate.2. The ...

Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

FILM FOR BACK SURFACE OF FLIP-CHIP SEMICONDUCTOR

The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented. 1. A film for back surface of flip-chip semiconductor , which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend ,wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa.2. The film for back surface of flip-chip semiconductor according to claim 1 , wherein the film for back surface of flip-chip semiconductor is formed of at least a thermosetting resin component.3. The film for back surface of flip-chip semiconductor according to claim 2 , which comprises at least a layer formed of at least a thermosetting resin component and a thermoplastic resin component having a glass transition temperature of 25° C. or higher and not higher than 200° C.4. The film for back surface of flip-chip semiconductor according to claim 3 , wherein a blending proportion of the thermoplastic resin component having a glass transition temperature of 25° C. or higher and not higher than 200° C. falls within ...

STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). 1stacking at least two semiconductor chips, one of the semiconductor chips being a master memory device and another of the semiconductor chips being a slave memory device, the master memory device being substantially larger dimensioned than the slave memory device;wiring the stacked semiconductor chips together by Through-Silicon Vias; andconnecting the stacked semiconductor chips to a package printed circuit board by flip chip and bumping.. A method comprising: This application is a continuation of U.S. application Ser. No. 13/005,774, filed Jan. 13, 2011, which is a continuation of U.S. application Ser. No. 12/429,310, filed Apr. 24, 2009, which claims the benefit of priority of U.S. Provisional Patent Application Ser. No. 61/154,910 filed Feb. 24, 2009. The entire teachings of the above applications are incorporated herein by reference in their entirety.Today, many electronic devices include memory systems to store information. Some memory systems store, for example, digitized audio or video information for playback by a respective media player. Other memory systems store, for example, software and related information to carry out different types of processing functions. Also, some types of memory systems such as, for example, Dynamic Random Access Memory (DRAM) systems and Static Random Access Memory (SRAM) systems are volatile memory systems in that stored data is not preserved when the power is off, whereas other types of memory systems such as, for example, NAND flash memory systems and NOR flash memory systems are nonvolatile memory systems in that stored data is preserved when the power is off.As time progresses, consumers have an expectation that memory systems will have increasingly larger capacities provided by chips of increasing smaller size. Historically ...

THERMAL DISSIPATION IN CHIP

A system for dissipating heat from a semiconductor board includes a first substrate including an opening formed therein, a second substrate attached to a surface of the first substrate, and a microchip positioned in the opening and bumped to the second substrate. The system further includes a heat sink directly adhered to the microchip. A method of manufacturing a heat dissipating semiconductor board includes forming an opening in a first substrate and positioning a microchip in the opening. The method further includes directly adhering the microchip to a heat sink, bonding the microchip to a second substrate and boding a surface of the first substrate to the second substrate. 1. An apparatus , comprising: a first substrate;', 'a second substrate connected to the first substrate;', 'a microchip connected to the second substrate;', 'at least one chip bumped to the second substrate;', 'a third substrate connected to the at least one chip; and', 'a first heat sink connected to the microchip such that the first heat sink dissipates heat away from the microchip., 'a system for dissipating heat, comprising2. The apparatus of claim 1 , further comprising an opening formed as part of the first substrate claim 1 , wherein the microchip is connected to the second substrate such that at least a portion of the microchip is located in the opening of the first substrate.3. The apparatus of claim 1 , further comprising a second heat sink connected to the third substrate claim 1 , wherein the second heat sink dissipates heat from the third substrate.4. The apparatus of claim 3 , wherein at least one of the first heat sink or the second heat seat is integrally formed as part of a transmission case.5. The apparatus of claim 3 , wherein both of the first heat sink and the second heat sink are integrally formed as part of a transmission case.6. The apparatus of claim 1 , the first substrate being one selected from the group consisting of FR-4 board claim 1 , low density ceramic board ...

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE

Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. 1. A package comprising:a substrate configured to support a flip chip die, the flip chip die including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.2. The package of further comprising a plurality of bump connections interposed between the substrate and the first surface of the flip chip die.3. The package of wherein the plurality of bump connections include copper.4. The package of wherein the second surface of the flip chip die is opposite the first surface of the flip chip die.5. The package of further comprising a second die interposed between the flip chip die and the substrate.6. The package of further comprising a mold configured to protect the flip chip die and enclose a plurality of exposed surfaces of the flip chip die.7. The package of wherein the thermal collection layer includes copper.8. A multi-chip package comprising:a substrate configured to support a plurality of flip chip dies, each flip chip die from the plurality of flip chip dies including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of each flip chip die from the plurality of flip chip dies, the thermal collection layer configured to dissipate heat generated by the plurality of flip chip dies.9. The package of further comprising a plurality of bump connections interposed ...

METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY

Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided. 1. A method for fabricating a carbon nanotube-based integrated circuit , comprising the steps of:providing a first wafer comprising carbon nanotubes which is formed by depositing the carbon nanotubes on a first substrate, depositing a first oxide layer onto the substrate covering the carbon nanotubes, and forming one or more first electrodes that extend at least part way through the first oxide layer and are in contact with one or more of the carbon nanotubes;providing a second wafer comprising one or more device elements which is formed by fabricating the device elements on a second substrate, depositing a second oxide layer over the device elements, and forming one or more second electrodes that extend at least part way through the second oxide layer connected to one or more of the device elements; andconnecting one or more of the carbon nanotubes with one or more of the device elements by bonding the first wafer and the second wafer together.2. (canceled)3. The method of claim 1 , further comprising the step of:forming one or more metal layers in the second oxide layer in contact with the device elements.4. The method of claim 1 , wherein both the first electrodes and the second electrodes comprise copper and wherein the step of connecting the carbon nanotubes with the device elements further comprises the steps of forming an oxide-to-oxide bond between the first oxide layer and the second oxide layer; andforming a copper-to-copper ...

PACKAGING STRUCTURAL MEMBER

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. 1. A singulated semiconductor package comprising: a die attach region defined in the structural member, the die attach region accommodates a die for packaging and includes an opening passing through the major surfaces,', 'a peripheral region surrounding the die attach region, and', 'at least one through-via disposed in the peripheral region of the structural member, the through-via extending through the first and second major surfaces of the structural member;, 'a structural member having first and second major surfaces, the structural member includes'}a die having first and second die surfaces being disposed in the opening of the structural member, wherein gaps exist between the die and sidewalls of the opening; anda mold compound having first and second surfaces disposed in the gaps, wherein the first and second surfaces of the mold compound are coplanar with the first and second major surfaces of the structural member, and wherein the structural member and the mold compound are separate components and the structural member comprises the same material as the mold compound which fills the gaps.2. The singulated semiconductor package of wherein the first and second major surfaces of the structural member claim ...

Package for mounting electronic components, electronic apparatus, and method for manufacturing the package

A package includes: a leadframe made of conductive material and on which the plurality of electronic components are to be mounted, the leadframe including a first surface and a second surface opposite to the first surface and including a plurality of elongate portions arranged in parallel to each other with a gap interposed between the adjacent elongate portions; a heat sink including a first surface and a second surface opposite to the first surface, wherein the leadframe is disposed above the heat sink such that the second surface of the leadframe faces the first surface of the heat sink; and a resin portion, wherein the leadframe and the heat sink are embedded in the resin portion such that the first surface of the leadframe and the second surface of the heat sink are exposed from the resin portion, respectively.

REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY

Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements. 1. A semiconductor device comprising:a plurality of conductive pads coupled to active circuitry of the semiconductor device; andat least one extended pad coupled to a ground plane of the semiconductor device, the at least one extended pad having a structure including a first portion similar to the plurality of conductive pads of the semiconductor device and a second portion that increases a height of the at least one extended pad.2. The semiconductor device of claim 1 , in which the height of the at least one extended pad is greater than a height of the plurality of the conductive pads on the semiconductor device.3. The semiconductor device of claim 1 , in which the at least one extended pad includes a passivation layer formed at least in part adjacent to the first portion and the semiconductor device.4. The semiconductor device o claim 1 , in which the first portion is substantially hemispherical in shape.5. The semiconductor device of claim 1 , in which the second portion does not substantially affect a pitch between micro-bumps for bonding the semiconductor device to another semiconductor device during a reflow process.6. The semiconductor device of claim 1 , in which the second portion comprises a pillar.7. The semiconductor device of claim integrated into at least one of a mobile phone claim 1 , a set top box claim 1 , a ...

DYNAMIC RANDOM ACCESS MEMORY DEVICE WITH IMPROVED CONTROL CIRCUITRY FOR THE WORD LINES

A dynamic random access memory device may include DRAM memory cells including several lines of memory cells, and line selection circuitry associated with each line. The line selection circuitry may include a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state, and to deliver two intermediate control logic signals each having an intermediate voltage level above the initial level and corresponding to the first logic state. The line selection circuitry may also include a control circuit to be supplied by PMOS transistors with a supply voltage having a second voltage level greater than the intermediate voltage level, and configured to, in the presence of the two intermediate control logic signals have their first logic state deliver to the gates of the memory cell transistors, a selection logic signal having the second voltage level. 18-. (canceled)9. A random access memory device comprising: a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state and to deliver first and second intermediate control logic signals each having an intermediate voltage level above the initial voltage level and corresponding to the first logic state, and', 'a control circuit comprising a first pair of PMOS transistors to be coupled with a supply voltage having a second voltage level greater than the intermediate level, said control circuit configured to, in the presence of the first and second intermediate control logic signals having their first logic state, deliver a selection logic signal having the second voltage level., 'a plurality of dynamic random access memory (DRAM) cells, and line selection circuitry associated therewith and comprising'}10. The random access memory device according to claim 9 , wherein said control circuit comprises a plurality of NMOS transistors coupled ...

CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD

A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die. 1. A method of packaging one or more semiconductor dies , the method comprising:providing a first die having a circuit surface and a connecting surface;providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface;coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling;providing a substrate having a top surface and a bottom surface;coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate;coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism; andattaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die, the lid being positioned in a gap between the circuit surface of the first die and the top surface of the substrate.2. The method of claim 1 , wherein the airtight chamber ...

SEMICONDUCTOR DEVICE INCLUDING CLADDED BASE PLATE

A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1. 1. A semiconductor device comprising:a semiconductor chip joined with a substrate; the second metal layer comprises a sub-layer that has no pins and no pin-fins;', 'the first metal layer comprises a first thickness;', 'the sub-layer comprises a second thickness; and', 'the ratio between the first thickness and the second thickness is at least 4:1., 'a base plate joined with the substrate, the base plate comprising a first metal layer clad to a second metal layer, the second metal layer deformed to provide a pin-fin or fin cooling structure, wherein'}2. The semiconductor device of claim 1 , wherein the ratio between the first thickness and the second thickness is at least 10:1.3. The semiconductor device of claim 1 , wherein the second thickness is between 0.2 mm and 0.5 mm.4. The semiconductor device of claim 1 , wherein the first metal layer comprises copper and the second metal layer comprises aluminum.5. The semiconductor device of claim 1 , wherein the first metal layer has a thickness between 2.5 mm and 10 mm.6. The semiconductor device of claim 1 , further comprising:a third metal layer clad to the first metal layer opposite the second metal layer.7. The semiconductor device of claim 6 , wherein the third metal layer has a thickness between 1 μm and 0.1 mm.8. The semiconductor device of claim 6 , wherein the third metal layer comprises one of silver and palladium.9. The semiconductor device of claim 6 , wherein the substrate is one of diffusion soldered ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips. 1. A semiconductor device , comprising:a first semiconductor chip having a first surface including a first connection region and a first non-connection region excluding the first connection region;a second semiconductor chip having a second surface including a second connection region facing the first connection region and a second non-connection region excluding the second connection region, and stacked on the first semiconductor chip;first bump connection parts provided the first connection region of the first surface and the second connection region of the second surface to electrically connect between the first semiconductor chip and the second semiconductor chip;first stopper projections locally provided at least one region of the first non-connection region of the first surface and the second non-connection region of the second surface, and being in contact with the other region of the first non-connection region and the second non-connection region in an unbonded state;first bonding projections locally provided between the first non-connection region of the first surface and the second non-connection region of the second surface, and bonded to the first and second surfaces; anda first resin filled into a gap between the first surface of the first semiconductor chip and the second surface of the second semiconductor chip.2. The semiconductor device according to claim 1 , further comprising:a third ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device, comprising preparing a wiring substrate and mounting a first rectangular semiconductor chip having plural of first electrodes arranged along short sides thereof on the wiring substrate. A second rectangular semiconductor chip having plural of second electrodes arranged along short sides thereof is stacked on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip. The method further comprises filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip. The first and the second electrodes are connected to connection pads of the wiring substrate by first and second wires, respectively. 1. A method of manufacturing a semiconductor device , the method comprising:preparing a wiring substrate having a plurality of connection pads;mounting a first rectangular semiconductor chip having a plurality of first electrodes arranged along short sides thereof on the wiring substrate;stacking a second rectangular semiconductor chip having a plurality of second electrodes arranged along short sides thereof on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip;filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip;electrically connecting the first electrodes and the connection pads to each other by first wires; andelectrically connecting the second electrodes and the connection pads to ...

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME

The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost, 1. A method for making a semiconductor structure , comprising:(a) providing a first wafer and a second wafer, wherein the first wafer has a first active surface and at least one first conductive pad, the first conductive pad is exposed to the first active surface, and has at least one through hole, the second wafer has a second active surface and at least one second conductive pad, the second conductive pad is exposed to the second active surface;(b) disposing the first wafer on the second wafer;(c) removing part of the first wafer, so as to form a groove, wherein the groove communicates with the through hole of the first conductive pad, and exposes the first conductive pad and the second conductive pad;(d) forming a through via in the groove, wherein the through via electrically connects the first conductive pad and the second conductive pad; and(e) forming at least one electrical connecting element on the first wafer, wherein the electrical connecting element is electrically connected to the through via.2. The method as claimed in claim 1 , wherein in the step (b) claim 1 , the first wafer and the second wafer are connected by a bonding material.3. The method as claimed in claim 1 , wherein in the step (c) claim 1 , the cross-sectional area of the groove is smaller than or equal to those of the first conductive pad and the second conductive pad claim 1 , and the cross-sectional area of the ...

Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel. 1. A method of making a semiconductor device , comprising:providing a substrate including a die attach area;forming a first channel in the substrate;forming a first dam material over the substrate;disposing a semiconductor die over the die attach area of the substrate; anddepositing an underfill material between the semiconductor die and substrate, wherein the first channel and first dam material control outward flow of excess underfill material.2. The method of claim 1 , further including forming the first dam material between the first channel and a contact pad area of the substrate.3. The method of claim 2 , further including forming a second channel between the first dam material and the contact pad area of the substrate.4. The method of claim 1 , further including forming the first dam material between the first channel and die attach area.5. The method of claim 4 , further including forming a second dam material between the first channel and a contact pad area of the substrate.6. The method of claim 1 , wherein the semiconductor die is a flipchip type semiconductor die or package-on-package semiconductor device.7. A ...

LIGHT-EMITTING ELEMENT MOUNTING PACKAGE, LIGHT-EMITTING ELEMENT PACKAGE, AND METHOD OF MANUFACTURING THESE

A light-emitting element mounting package includes a light-emitting element mounting portion that includes a plurality of wiring portions arranged interposing a predetermined gap between the wiring portions facing each other, and an insulating layer on which the light-emitting element mounting portion is mounted, wherein an upper surface of the light-emitting element mounting portion is exposed on the insulating layer, wherein cutout portions are formed on lower sides of side edges of the wiring portions and contact the insulating layer. 1. A light-emitting element mounting package comprising:a light-emitting element mounting portion that includes a plurality of wiring portions arranged interposing a predetermined gap between the wiring portions facing each other, andan insulating layer on which the light-emitting element mounting portion is mounted,wherein an upper surface of the light-emitting element mounting portion is exposed on the insulating layer,wherein cutout portions are formed on lower sides of side edges of the wiring portions and contact the insulating layer.2. The light-emitting element mounting package according to claim 1 ,wherein the cutout portions are formed on the lower sides of some of the side edges which face each other and on the lower sides of other of the side edges which do not face each other.3. The light-emitting element mounting package according to claim 1 ,wherein a thickness of a part of each wiring portion where the corresponding cutout portion is formed is less than a thickness of another part of each wiring portion where the corresponding cutout portion is not formed.4. The light-emitting element mounting package according to claim 1 ,wherein a cross-sectional shape of one of the cutout portions and a cross-sectional shape of another of the cutout portions which faces the one of the cutout portions are line-symmetric with respect to an imaginary line passing in a thickness direction of the corresponding wiring portions through a ...

METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE

A method of manufacturing a substrate for mounting an electronic device, includes forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof. An electrode substrate having at least one core on an upper surface thereof is formed such that the at least one core corresponds to the at least one through-hole. The electrode substrate is coupled to the substrate body by inserting the at least one core into the at least one through-hole. A portion of the coupled electrode substrate is removed except for the at least one core. 1. A method of manufacturing a substrate for mounting an electronic device , the method comprising steps of:forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof;forming an electrode substrate having at least one core on an upper surface thereof, such that the at least one core corresponds to the at least one through-hole;coupling the electrode substrate to the substrate body by inserting the at least one core into the at least one through-hole; andremoving a portion of the coupled electrode substrate except for the at least one core.2. The method of claim 1 , wherein the electrode substrate is formed by etching a silicon (Si) substrate.3. The method of claim 2 , wherein the substrate body is a silicon (Si) substrate.4. The method of claim 1 , wherein the step of forming the electrode substrate is performed by injecting a synthetic resin into a mold having a shape corresponding to a shape of the electrode substrate.5. The method of claim 4 , wherein the step of forming the electrode substrate further includes forming a metal layer on a surface of the electrode substrate.6. The method of claim 1 , wherein the step of forming the electrode substrate includes processing an upper surface of a metal plate to form the at least one core.7. The method of claim 1 , wherein the step of coupling the electrode substrate to the substrate body is performed by inserting the at ...

METHOD FOR BONDING TWO SILICON SUBSTRATES, AND A CORRESPONDEING SYSTEM OF TWO SILICON SUBSTRATES

A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1 and 5% on a first bonding surface of the first silicon substrate; depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate; subsequently joining the first and second silicon substrates, so that the first and the second bonding surfaces lie opposite each other; and implementing a thermal treatment step to form an eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as the main component, between the first silicon substrate and the second silicon substrate, spikes which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface. 1. A method for bonding two silicon substrates , the method comprising:providing a first silicon substrate and a second silicon substrate;depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1% and 5% on a first bonding surface of the first silicon substrate;depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate;subsequently bonding the first silicon substrate and the second silicon substrate, so that the first bonding surface and the second bonding surface lie opposite each other; andimplementing a thermal treatment step to form a eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as main component, between the first silicon substrate and the second silicon substrate, spikes, which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface.2. The method of claim 1 , ...

Semiconductor-On-Insulator Devices and Associated Methods

Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer. 1. A method for making a semiconductor-on-insulator device , comprising:forming a device layer on a front side of a semiconductor layer;bonding a first substrate to the front side of the device layer;processing the semiconductor layer on a back side opposite the device layer to form a processed surface;bonding a second substrate to the processed surface; andremoving the first substrate from the front side to expose the device layer.2. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry at the front side of the semiconductor layer.3. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry claim 1 , imaging devices claim 1 , RF circuitry claim 1 , photovoltaic circuitry claim 1 , or a combination thereof.4. The method of claim 1 , wherein the semiconductor layer includes a silicon material.5. The method of claim 4 , wherein the silicon material is a single crystal silicon wafer.6. The method of claim 1 , wherein processing the semiconductor layer on the back side further includes thinning the semiconductor layer from the back side to expose the device layer.7. The method of claim 1 , wherein ...

UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING

A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. 1. A method of making a microelectronic package comprising: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel.2. The method of claim 1 , further comprising evacuating air from a space between the IHS panel and the substrate panel of the combination through a porous plug extending through a thickness of the IHS panel.3. The method of claim 2 , further comprising injecting an underfill material into the space between the IHS panel and the substrate panel of the combination through an opening extending through a thickness of the IHS panel.4. The method of claim 1 , further comprising singulating the combination to yield a plurality of microelectronic packages claim 1 , each of the packages including: an IHS component of the IHS panel claim 1 , one of the plurality IC dies bonded and thermally coupled to said IHS component claim 1 , ...

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. 1. A manufacturing method , comprising:providing a carrier;disposing a semiconductor device over the carrier such that an active surface of the semiconductor device faces the carrier, wherein the semiconductor device includes a pad adjacent to the active surface;forming a package body over the carrier and the semiconductor device, wherein the package body includes a first package surface and a second package surface opposite to the first package surface, and the first package surface faces the carrier;forming a through-hole in the package body, wherein the through-hole extends between the first package surface and the second package surface;separating the carrier from the package body;forming a dielectric layer adjacent to the first package surface, wherein the dielectric layer exposes the pad and the through-hole;forming a conductive via in the through-hole, wherein the conductive via includes a first end, adjacent to the first package surface, and a second end, adjacent to the second package surface;forming a patterned conductive layer adjacent to the dielectric layer, wherein the patterned conductive layer is electrically connected to at least one of the pad and the first end of the conductive via; andforming a stud bump adjacent to the second end of the conductive via.2. The manufacturing method of claim 1 , wherein forming the stud bump is carried out using a wiring tool.3. The manufacturing method of claim 1 , wherein the stud bump is one of a gold stud bump claim 1 , an aluminum stud bump claim 1 , and a copper stud bump.4. The manufacturing method of claim 1 , wherein forming ...

EXPOSED DIE PAD PACKAGE WITH POWER RING

A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion. 1. A method of fabricating a packaged semiconductor , the method comprising: an inner portion and', 'a ring portion encircling the inner portion,', 'wherein the ring portion includes (i) a first ring portion that encircles first and second sides of the inner portion, and (ii) a first bar portion located on a third side of the inner portion;, 'forming a conductive frame as an integral piece of conductive material, the conductive frame including'}mounting a semiconductor die to a first surface of the inner portion of the conductive frame, wherein the semiconductor die is configured to receive power via the first ring portion;applying a casing to the conductive frame, wherein the casing covers the semiconductor die; andafter the casing is applied to the conductive frame, removing (i) sections of the conductive frame that connect the inner portion to the ring portion, and (ii) sections of the conductive frame that connect the first ring portion to the first bar portion.2. The method of claim 1 , further comprising exposing claim 1 , on an external surface of the casing claim 1 , a face of the ring portion and a ...

CIRCUIT BOARD STRUCTURE AND FABRICATION THEREOF

A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board. 1. A fabrication method of a circuit board structure , comprising the steps of:providing a carrying board having a first and an opposite second surface and having at least one through cavity formed therein;placing a semiconductor chip in the through cavity of the carrying board, wherein the semiconductor chip has an active surface and an opposite inactive surface, and the active surface has a plurality of electrode pads thereon;filling with an adhesive material in a gap between the through cavity of the carrying board and the semiconductor chip to fix in position the semiconductor chip in the through cavity; andforming a reinforcing layer on the second surface of the carrying board and the inactive surface of the semiconductor chip, wherein the reinforcing layer is made of a thermoplastic resin.2. The fabrication method of claim 1 , wherein the carrying board is selected from the group consisting of a metal board claim 1 , a ceramic board claim 1 , and an insulating board.3. The fabrication method of claim 1 , wherein the adhesive material is one of an adhesive resin and a prepreg material.4. The fabrication method of claim 1 , wherein the reinforcing layer is formed by one of coating and laminating.5. The fabrication method of claim 1 , further comprising forming an opening in ...

COAXIAL PLATED THROUGH HOLES (PTH) FOR ROBUST ELECTRICAL PERFORMANCE

In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. in this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed. 1. A method comprising:drilling a through hole in a substrate core;plating the drilled through hole;filling the plated through hole with dielectric material and a coiled copper wire;patterning a surface of the substrate core to route the plated through hole and the copper wire; andforming build-up layers on the patterned surface to form a substrate.2. The method of claim 1 , further comprising coupling an integrated circuit device to the substrate.3. The method of claim 2 , further comprising routing the plated through hole to couple with a ground contact of the integrated circuit device.4. The method of claim 2 , further comprising routing the plated through hole and the copper wire to couple with differential pair contacts of the integrated circuit device.5. The method of claim 1 , wherein filling the plated through hole with dielectric material and a coaxial copper wire comprises placing a preformed encapsulant containing a copper wire into the plated through hole.6. The method of claim 1 , wherein filling the plated through hole with dielectric material and a coaxial copper wire comprises:plugging the plated through hole with dielectric material;laser drilling a hole through a length of the dielectric material; andplating the laser drilled hole.7. A method comprising:drilling a through hole in a substrate core;plating the drilled through hole;filling the plated through hole with dielectric material and a preformed encapsulant containing a conductor into ...

PACKAGED MICRODEVICES AND METHODS FOR MANUFACTURING PACKAGED MICRODEVICES

Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die. The first conductive elements are attached to the second conductive elements at corresponding interfaces such that the interconnects connect the contacts of the substrate directly to corresponding pads on the die within the gap. 1. A packaged microdevice , comprising:a substrate including a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts;a die across from the mounting area and spaced apart from the substrate by a gap, wherein the die has an integrated circuit and pads electrically coupled to the integrated circuit; andfirst conductive elements in the gap electrically connected to contacts on the substrate and second conductive elements in the gap electrically coupled to corresponding pads of the die, wherein the first conductive elements are attached to the second conductive elements at corresponding diffusion joints such that the first and second conductive elements form direct interconnects in the gap between the contacts and corresponding pads.2. A method of packaging a microelectronic device , comprising:forming a plurality of first conductive elements on contacts of a substrate, wherein the ...

METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SYSTEM

A method, system and apparatus for connecting multiple memory device dies - to a substrate which requires no trace between dies. A first embodiment assigns the connections of a memory device die to be matched with other memory device dies - when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses between memory device dies are reduced. The number of vias is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. arranges the dies in a closed loop. 1. A multidie package comprising:a substrate; and,a plurality of memory dies mounted to one side of said substrate, and; a second plurality of memory dies mounted to the opposite side of said substrate in staggered formation relative to said plurality of memory dies.2. A multidie package as in claim 1 , wherein there are four dies connected in serial.3. A multidie package as in claim 1 , further comprising a controller mounted to one side of said substrate configured to connect said dies in a closed loop.4. A method for constructing a multidie package comprising the steps of; providing a plurality of dies claim 1 , mounting a plurality of dies to one side of a substrate claim 1 , and claim 1 , mounting a second plurality of dies on the other side of the substrate staggered and in opposite orientation to the first plurality of dies in the other side of the substrate.5. A memory system comprising: a substrate claim 1 , and a plurality of memory dies mounted to one side of said substrate claim 1 , and claim 1 , a second plurality of dies mounted to the other side of said substrate and staggered from said first plurality of dies claim 1 , and a controller connected to said first and said second pluralities of dies configured to control the operation of dies.6. A memory system as in claim 5 , wherein said controller is ...

Power Semiconductor Module with Pressed Baseplate and Method for Producing a Power Semiconductor Module with Pressed Baseplate

A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate. 1. A power semiconductor module , comprising:a baseplate having a top side, an underside, and a depression formed in the baseplate, the depression extending into the baseplate proceeding from the top side, a thickness of the baseplate being locally reduced in a region of the depression; anda circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.2. The power semiconductor module as claimed in claim 1 , wherein the baseplate has a thickness of 2 mm to 10 mm.3. The power semiconductor module as claimed in claim 2 , wherein the depression has a depth between 5% and 95% of the thickness of the baseplate.4. The power semiconductor module as claimed in claim 1 , wherein the circuit carrier is connected by a cohesive connection to the top side of the baseplate using a connecting means arranged between the circuit carrier and the baseplate.5. The power semiconductor module as claimed in claim 4 , wherein the cohesive connection is a soldered connection claim 4 , a sintered connection claim 4 , or an adhesive-bonded connection.6. The power semiconductor module as claimed in claim 4 , wherein the connecting means extends into the depression and completely fills the depression at least at one location completely from a deepest point of the depression as far as the top side of the baseplate.7. The power semiconductor module as claimed in claim 1 , wherein ...

STRESS-ENGINEERED INTERCONNECT PACKAGES WITH ACTIVATOR-ASSISTED MOLDS

A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive. 1. A method , comprising:providing a pad chip having contact pads;providing a spring chip having micro-springs;applying a chemical activator to one of either the pad chip or the spring chip;applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip;aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads; andpressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.2. The method of claim 1 , wherein the chemical activator is applied to the pad chip and the adhesive is applied to the spring chip.3. The method of claim 1 , wherein applying the chemical activator comprises one of painting claim 1 , spraying or spinning the chemical activator.4. The method of claim 1 , wherein the chemical activator completely cures the adhesive.5. The method of claim 1 , further comprising exposing the adhesive to UV light to completely cure the adhesive.6. The method of claim 1 , further comprising placing one of spacer pillars or spacer walls on one of either the pad chip or the spring chip.7. The method of claim 1 , further comprising etching alignment pits into at least one of the pad chip or the spring chip claim 1 , and placing spacer beads into the alignment pits. This is a Division of co-pending U.S. patent application Ser. No. 12/471,188, filed May 22, 2009, entitled Stress-Engineered Interconnect Packages with ...

ELECTRONIC COMPONENT MODULE AND METHOD FOR PRODUCING SAME

An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame. 1. An electronic component module , comprising:a double-sided mounting board having a front surface and a back surface;components mounted on the front surface and the back surface of the double-sided mounting board;an insulating resin sealing the components mounted on the front surface and the back surface; anda lead frame bonded to the back surface of the double-sided mounting board,wherein the back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin; andwherein a thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to a thickness of the lead frame.2. The electronic component module as claimed in claim 1 , wherein a first contact surface of the lead frame bonded to the back surface of the double-sided mounting board and a second contact surface of the lead frame to be bonded to a main board overlap each other in a vertical direction.3. The electronic component module as claimed in claim 1 , wherein the lead frame includesleads configured to connect the components mounted on the back surface to a main board;a frame that is monolithically formed with the leads; anda radiating part ...

SEMICONDUCTOR DEVICE, HEAT RADIATION MEMBER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device has a substrate having a front surface, and a rear surface including a fin forming region and a peripheral region surrounding the fin forming region. An insulating substrate is disposed on the front surface of the substrate. A semiconductor chip is disposed on the insulating substrate. A plurality of fins is formed in the fin forming region, and a reinforcing member is formed on the substrate through a bonding member, so as to overlap the peripheral region. 1. A semiconductor device comprising:a substrate having a front surface, and a rear surface including a fin forming region and a peripheral region surrounding the fin forming region;an insulating substrate disposed on the front surface;a semiconductor chip disposed on the insulating substrate;a plurality of fins formed in the fin forming region; anda first reinforcing member formed on the substrate through a bonding member, so as to overlap the peripheral region.2. A semiconductor device according to claim 1 , wherein the first reinforcing member is made of a different material than that of the substrate.3. A semiconductor device according to claim 2 , wherein the first reinforcing member is made of a harder material than that of the substrate.4. A semiconductor device according to claim 2 , wherein the substrate is made of a material with a higher thermal conductivity than that of forming the first reinforcing member.5. A semiconductor device according to claim 1 , wherein the first reinforcing member is formed in the peripheral region through the bonding member.6. A semiconductor device according to claim 5 , wherein the first reinforcing member comprises an opening claim 5 , andthe first reinforcing member is formed in the peripheral region to expose the fin forming region through the opening.7. A semiconductor device according to claim 5 , wherein the first reinforcing member comprises a plurality of through-holes claim 5 ,the first reinforcing member is formed in the peripheral region ...

Method for Producing a Composite and a Power Semiconductor Module

A composite is produced by providing a first and a second joining partner, a connecting means, a sealing means, a reactor having a pressure chamber, and a heating element. The two joining partners and the connecting means are arranged in the pressure chamber such that the connecting means is situated between the first joining partner and the second joining partner. A gas-tight region is then produced, in which the connecting means is arranged. Afterward, a gas pressure of at least 20 bar is produced in the pressure chamber outside the gas-tight region. The gas pressure acts on the gas-tight region and presses the first joining partner, the second joining partner and the connecting means together. The joining partners and the connecting means are then heated by means of the heating element to a predefined maximum temperature of at least 210° C. and then cooled. 1. A method for producing a composite , wherein at least two joining partners are fixedly connected to one another , the method comprising:providing a first joining partner and a second joining partner;providing a connecting means;providing a sealing means;providing a reactor having a pressure chamber;providing a heating element;arranging the first joining partner, the second joining partner and the connecting means in the pressure chamber such that the connecting means is interposed between the first joining partner and the second joining partner;producing a gas-tight region in which the connecting means is arranged;producing a gas pressure in the pressure chamber outside the gas-tight region such that the gas pressure acts on the gas-tight region and presses the first joining partner, the second joining partner and the connecting means together with at least 20 bar;heating the first joining partner, the second joining partner and the connecting means by means of the heating element to a predefined maximum temperature of at least 210° C.; andsubsequently cooling the first joining partner, the second joining ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. 1. A semiconductor device comprising a semiconductor chip having a principal surface and a plurality of MIS type FETs formed over said principal surface and a plurality of metal plate wires , each of which has a pectinate shape , formed so as to cover said principal surface ,wherein said plural metal plate wires cover said principal surface so that the pectinate parts may be allocated alternately in a planar view; and said plural metal plate wires are electrically coupled to a plurality of terminals located outside said semiconductor chip.2. A semiconductor device according to claim 1 ,wherein said plural metal plate wires include a first metal plate wire, a second metal plate wire, and a third metal plate wire; said plural terminals include an input terminal, an output terminal, and a ground terminal; said first metal plate wire is electrically coupled to said input terminal, said second metal plate wire is electrically coupled to said output terminal, and said third metal plate wire is electrically coupled to said ground terminal, respectively; and said input terminal, said output terminal, and said ground terminal are located outside said semiconductor chip, respectively.3. A semiconductor device according to claim 2 , wherein said semiconductor device has source pads and drain pads of strip-shapes in a planar view claim 2 , which are located under said pectinate first claim 2 , second claim 2 , and third metal plate wires over said principal surface of said semiconductor chip claim 2 , extend in the direction crossing said first claim 2 , second claim 2 , and third metal plate wires claim 2 , and are electrically coupled to said first claim 2 , second claim 2 , and third metal plate wires.4. A semiconductor device according to claim ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid. 1. A semiconductor package comprising:a semiconductor chip comprising an inactive surface;an adhesive interface material coupled to an adhesive region of the inactive surface;a thermal interface material coupled to a heat transfer region of the inactive surface; anda heat emitting lid coupled to the inactive surface by the adhesive interface material and the thermal interface material.2. The semiconductor package of wherein the adhesive interface material has a greater bonding strength than the thermal interface material.3. The semiconductor package of wherein the thermal interface material has a higher heat transmission efficiency than the thermal interface material.4. The semiconductor package of wherein the adhesive region and the heat transfer region form the entire inactive surface.5. The semiconductor package of further comprising:a substrate; andbumps coupling an active surface of the semiconductor chip to the substrate.6. The semiconductor package of wherein the heat emitting lid comprises:a flat plate coupled to the inactive surface; andlegs coupled to the substrate.7. The semiconductor package of further comprising:an adhesive substrate interface material coupling the legs to the substrate.8. The semiconductor package of wherein the adhesive substrate interface material and the adhesive interface material are the same type of material.9. The semiconductor package of claim 1 , wherein the adhesive region comprises corner regions ...

DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. 1. A microelectronic workpiece , comprising:a substrate having a front side and a backside;a first circuit and a second circuit carried by the substrate;an interconnect extending through the substrate and electrically coupled to the first circuit, the interconnect having a metal layer electrically coupling the front side of the substrate with the backside of the substrate;a dielectric liner along the interconnect between the interconnect and the substrate wherein the dielectric liner electrically isolates the first circuit from the second circuit; andan electrostatic discharge (ESD) device electrically coupled to the second circuit such that the ESD device is electrically isolated from the interconnect.2. The microelectronic workpiece of wherein the dielectric liner separates the interconnect from the second circuit.3. The microelectronic workpiece of wherein the first circuit includes an integrated circuit and the second circuit includes a component of the integrated circuit.4. The ...

METHOD FOR DIRECTLY ADHERING TWO PLATES TOGETHER, INCLUDING A STEP OF FORMING A TEMPORARY PROTECTIVE NITROGEN LAYER

To avoid problems of hydrolysis of the silicon oxide formed by PECVD at the surface of at least one wafer, it is proposed to cover, in the vacuum deposition chamber used to deposit the silicon oxide, said oxide with a temporary protective layer containing nitrogen. The protective layer thus protects the silicon oxide against the outer environment and especially against humidity when the wafer provided with the silicon oxide is stored outside of the vacuum deposition chamber. Afterwards, the protective layer is removed, for example, by chemical-mechanical. polishing, just before the two wafers are placed into contact. The protective layer may be formed by a PECVD silicon nitride deposition, by plasma nitriding or nitrogen doping of a superficial portion of the silicon oxide. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. A method for direct bonding of first and second wafers , comprising successively:forming at the surface of the first wafer, a first silicon oxide layer by plasma enhanced chemical vapor deposition in situ, in a vacuum deposition chamber;forming on the first silicon oxide layer a first protective layer comprising nitrogen in the vacuum deposition chamber before the first wafer has exiting the vacuum deposition chamber;stocking up the first wafer out of the vacuum deposition chamber;freeing the first silicon oxide layer by removing the first protective layer;contacting the first silicon oxide layer with the surface of the second wafer for direct bonding the two wafers together at an interface between the first silicon oxide layer and the second wafer.10. The method of claim 9 , wherein the first protective layer is formed by plasma-enhanced chemical vapor deposition of silicon nitride on the first silicon oxide layer.11. The method of claim 9 , wherein the first protective layer is formed by plasma-enhanced nitriding of a superficial portion of the first silicon oxide layer.12. The method of ...

Method for the production of a substrate comprising embedded layers of getter material

A method for producing a substrate with buried layers of getter material, including: making a first stack including one layer of a first getter material, arranged on a first support; making a second stack including one layer of a second getter material, arranged on a second support; and bringing the first stack into contact with the second stack and performing thermocompression, the layers of the first and of the second getter material being arranged between the first and the second support, at a temperature greater than or equal to a lowest temperature among thermal activation temperatures of the first and of the second getter material, to bond the layers of the first and second getter materials together.

System in Package and Method for Manufacturing The Same

A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step. 1. A system in package comprising:a laminate body;a substrate arranged inside the laminate body;at least one contact pad on the substrate; anda semiconductor die embedded in the laminate body, wherein at least one contact area of the semiconductor die is bonded to the at least one contact pad of the substrate via a sintered bonding layer.2. The system in package according to claim 1 , wherein the contact area of the semiconductor die is made from or plated with a metal or a metal alloy which is more noble than copper when considered in a galvanic series.3. The system in package according to claim 1 , wherein the contact pad of the substrate is made from or plated with a metal or a metal alloy which is more noble than copper when considered in a galvanic series.4. The system in package according to claim 2 , wherein the contact area of the semiconductor die have a copper basis and a metal coating claim 2 , which is arranged on the copper basis claim 2 , the metal coating.5. The system in package according to claim 2 , wherein contact pad of the substrate have a copper basis and a metal coating claim 2 , which is arranged on the copper basis claim 2 , the metal coating.6. The system in package according to claim 4 , wherein the metal coating comprising silver.7. The system in package according to claim 4 , wherein the metal coating comprising gold.8. The system in package according to claim 5 , wherein the metal coating comprising silver.9. The system ...

SEMICONDUCTOR PACKAGE, COOLING MECHANISM AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate with a first surface on which a semiconductor device is mounted and a second surface opposite to the first surface, and a loop heat pipe including an evaporator and attached to the second surface of the substrate, wherein the substrate has a groove structure in the second surface, the groove structure being in contact with a porous wick provided in the evaporator. 1. A semiconductor package comprising:a substrate with a first surface on which a semiconductor device is mounted and a second surface opposite to the first surface; anda loop heat pipe including an evaporator and attached to the second surface of the substrate,wherein the substrate has a groove structure in the second surface, the groove structure being in contact with a porous wick provided in the evaporator.2. The semiconductor package according to claim 1 , further comprising:a board configured to mount the substrate,wherein the board has an opening in which the evaporator is accommodated.3. The semiconductor package according to claim 1 , wherein the groove structure is a part a fluid channel of the loop heat pipe.4. The semiconductor package according to claim 1 , wherein the groove structure has multiple areas with different groove widths and/or different groove spacing.5. The semiconductor package according to claim 4 ,wherein two or more of the semiconductor devices are mounted on the substrate, and the groove structure has a different groove width and/or a different groove spacing according to a quantity of heat generated by each of the semiconductor devices.6. The semiconductor package according to claim 1 , wherein the groove structure is formed directly in the substrate.7. The semiconductor package according to claim 1 , wherein the groove structure is formed of a different material from the substrate.8. The semiconductor package according to claim 7 , wherein the groove structure has a partition wall separating adjacent grooves claim 7 , and a ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer of a first thickness having a first main surface, a plurality of chip regions provided over the first main surface, a cutting region provided between two of the chip regions adjacent to each other, and a second main surface on the side opposite to the first main surface;(b) grinding the second main surface of the semiconductor wafer with a grinding material to reduce the thickness of the semiconductor wafer into a second thickness while leaving a plurality of grinding grooves on the second main surface;(c) dicing the semiconductor wafer along the cutting region while leaving the grinding grooves on the second main surface of the semiconductor wafer to obtain semiconductor chips;(d) providing a mother substrate made of a metal and having a plurality of chip mounting regions having a first electrode plate and a second electrode plate placed apart from the first electrode plate;(e) placing the semiconductor chip over the upper surface of the first electrode plate via a conductive resin paste to face the back surface of the semiconductor chip and the upper surface of the ...

PHOTOELECTRIC COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

There is provided a photoelectric composite substrate including: a wiring substrate comprising a first region and a second region; an optical waveguide disposed on the first region of the wiring substrate and including: a first cladding layer on the wiring substrate; a core layer on the first cladding layer; a second cladding layer on the core layer; a wiring layer on the second region of the wiring substrate; and an insulating layer having an opening portion on the wiring layer such that the wiring layer is exposed through the opening portion, wherein the insulating layer is made of the same material as that of the core layer. 1. A photoelectric composite substrate comprising:a wiring substrate comprising a first region and a second region; a first cladding layer on the wiring substrate;', 'a core layer on the first cladding layer;', 'a second cladding layer on the core layer;, 'an optical waveguide disposed on the first region of the wiring substrate and comprisinga wiring layer on the second region of the wiring substrate; andan insulating layer having an opening portion on the wiring layer such that the wiring layer is exposed through the opening portion, wherein the insulating layer is made of the same material as that of the core layer.2. The substrate according to claim 1 , further comprising:a dummy wiring layer on the first region of the wiring substrate,wherein the first cladding layer is formed on the wiring substrate via the dummy wiring layer.3. The substrate according to claim 1 , wherein a groove which is substantially formed in V-shape is formed in a certain position of the first cladding layer claim 1 , the core layer and the second cladding layer.4. The substrate according to claim 1 , wherein the insulating layer is continuously formed with the core layer.5. A photoelectric composite apparatus comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the photoelectric composite substrate according to ;'}an optical component on the ...

MICROFABRICATED PILLAR FINS FOR THERMAL MANAGEMENT

An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. 1. A method of fabricating a die , comprising:fabricating a die on a wafer;forming the cross-sectional shape of a pillar fin on a surface of the die;forming the pillar fin integrally with the surface of the die; anddicing the wafer to separate the die.2. The method of claim 1 , wherein the pillar fin is formed using photolithography claim 1 ,3. The method of claim 1 , further comprising fabricating a microbump on the surface of the die.4. The method of claim 1 , wherein the forming the cross-sectional shape of a pillar fin comprises depositing a photo resist on the surface of the die.5. The method of claim 4 , wherein the forming the cross-sectional shape of a pillar fin comprises exposing the photo resist to ultraviolet light through a mask.6. The method of claim 5 , wherein the mask has a pattern and the cross-section of the pillar fin is formed by the pattern of light that passes through the mask.7. The method of claim 4 , wherein the forming the pillar fin comprises dipping the photo resist into an electrolytic bath.8. The method of claim 7 , further comprising controlling the current of the bath and the amount of time the photo resist is dipped into the bath.9. The method of claim 8 , wherein the height of the formed pillar fin is determined by the current of the bath and the amount of time the photo resist is dipped into the bath claim 8 ,10. The method of claim 4 , further comprising removing the photo resist from the surface.11. The method of claim 1 , further comprising forming a thermal contact on the surface.12. The method of ...

Device and Method for Chip Pressing

Disclosed are embodiments related to chip pressing devices. One such chip pressing device includes a bottom portion and a top portion, which is configured to be attached to or separated from the bottom portion, and has a compartment portion, an upper chamber, and a lower chamber, wherein the upper chamber is spaced apart from the lower chamber by the compartment portion. The upper chamber has one or more gas passages, the lower chamber has one or more gas inlets and one or more gas outlets, and the compartment portion has one or more through-holes. One or more pressing heads movably fit into the through-holes; one or more gas pressure sources connected to at least one of the gas passages of the upper chamber, wherein the upper chamber is pressurized, and one or more heated gas sources are connected to the one or more gas inlets of the lower chamber.

Card Lamination

Described herein are RFID structures and methods of manufacturing RFID structures. An antenna substrate is provided. A first stack layer is provided. An antenna assembly including an antenna track, and at least two contact pads, are formed on a first surface of the antenna substrate. An integrated circuit unit is coupled to the at least two contact pads. A first surface of the first stack layer, the first surface of the antenna substrate, or both are coated with a unidirectional thermally expansive coating material. The first surface of the antenna substrate is positioned to be adjacent to the first surface of the first stack layer. 1. A method of manufacturing an RFID structure , the method comprising:providing an antenna substrate;providing a first stack layer;forming, on a first surface of the antenna substrate, an antenna assembly including an antenna track, and at least two contact pads;coupling an integrated circuit unit to the at least two contact pads;coating a first surface of the first stack layer, the first surface of the antenna substrate, or both with a unidirectional thermally expansive coating material; andpositioning the first surface of the antenna substrate to be adjacent to the first surface of the first stack layer.2. The method of claim 1 , further comprising:providing a second stack layer;coating a first surface of the second stack layer or a second surface of the antenna substrate opposite the first surface of the antenna substrate with the thermally expansive coating material; andpositioning the first surface of the second stack layer to be adjacent to the second surface of the antenna substrate.3. The method of claim 1 , further comprising forming claim 1 , on the second surface of the antenna substrate claim 1 , a second antenna assembly including a second antenna track.4. The method of claim 1 , further comprising heating the coating material claim 1 , wherein gaps formed by the antenna track or integrated circuit unit between the antenna ...

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material

A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a containment structure over a surface of the substrate within a cover attach area of the substrate;providing a cover;depositing an adhesive material over the cover or substrate; anddisposing the cover over the substrate within the cover attach area to press the adhesive material into or against the containment structure.2. The method of claim 1 , further including disposing a semiconductor die over a die attach area of the substrate.3. The method of claim 2 , further including depositing an underfill material between the semiconductor die and substrate.4. The method of claim 1 , wherein forming the containment structure includes forming one or more channels in the surface of the substrate within the cover attach area.5. The method of claim 1 , wherein forming the containment structure includes forming one or more dam materials over the surface of the substrate within the cover attach area.6. The method of claim 1 , further including forming an interconnect structure over the substrate opposite the cover.7. A method of making a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip. 1. A semiconductor device comprising:a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side;an electrically conductive frame provided on a side periphery of the chip;a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip; andan insulation side portion provided between the electrically conductive frame and the side periphery of the chip.2. The semiconductor device of claim 1 , wherein an electrical connection from the one side to the second chip electrode is enabled via the electrically conductive frame and the rewiring.3. The semiconductor device of claim 2 , wherein the semiconductor device is configured as a semiconductor package device claim 2 ,a third chip electrode is formed on the second surface of the chip,the semiconductor package device includes:a rewiring configured to electrically connect the third chip electrode and the electrically conductive frame on the other side of the chip; andan insulation portion provided between a rewiring of the second chip electrode and a rewiring of the third chip electrode,each of the first to third chip electrodes is any one of a source, a gate and a drain, andan electrical connection to the first to third chip electrodes is enabled from the one side.4. The semiconductor device of claim 1 , further comprising:a first rewiring ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side. 1. A method of fabricating a semiconductor package , the method comprising:forming a plurality of sheets where a conductive pattern and a via are formed;attaching semiconductor chips to at least a portion of the sheets;forming a package body by stacking the plurality of sheets in a first direction; andforming an external connection terminal on a first side of the package body,wherein the first side is parallel to the first direction.2. The method of claim 1 , wherein the forming of the sheets comprises forming a chip mounting region for mounting the semiconductor chips on the sheets.3. The method of claim 2 , wherein the forming of the chip mounting region comprises recessing the sheets through laser processing or punching.4. The method of claim 1 , wherein the forming of the package body further comprises forming an adhesive layer between the sheets.5. The method of claim 4 , wherein the forming of the package body further comprises performing a firing process on the sheets before the forming of the adhesive layer.6. The method of claim 1 , further comprising performing a firing process after the stacking of the sheets.7. The method of claim 1 , wherein the first side exposes the conductive patterns and the conductive patterns are electrically connected to the external connection terminal.8. The method of claim 7 , further comprising claim 7 , before the forming of the external connection terminal claim 7 , forming a connection member by performing a plating process on the exposed conductive patterns.9. The method of claim 1 , further comprising claim 1 , before the forming of the external connection terminal ...

Semiconductor device and method for manufacturing the same

An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.

Manufacturing method of semiconductor device

A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE 1 c of a first lead, a tip portion LE 2 c of a second lead, and a tip portion LE 3 c of a third lead by using a spanking die SDM 1 , the tip portion LE 1 c of the first lead, the tip portion LE 2 c of the second lead, and the tip portion LE 3 c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD 1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU 1 , and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD 1 and a flat pressing surface of the upper die SU 1.

STACKED PACKAGE AND METHOD OF MANUFACTURING STACKED PACKAGE

According to an embodiment, there are provided a semiconductor chip having a semiconductor element formed thereon, a pad electrode formed on the semiconductor chip and connected to the semiconductor element, a resin layer formed on the semiconductor chip, a foundation insulating layer on which an electronic element and an internal electrode are formed, a hollow body formed on the foundation insulating layer to cover the electronic element and having a top surface side embedded in the resin layer, an opening portion formed on the foundation insulating layer and configured to expose a back surface of the internal electrode, and a conductive layer configured to connect the pad electrode and the internal electrode through the opening portion. 1. A stacked package comprising:a semiconductor chip having a semiconductor element formed thereon;a pad electrode formed on the semiconductor chip and connected to the semiconductor element;a resin layer formed on the semiconductor chip;a foundation insulating layer on which an electronic element and an internal electrode are formed;a hollow body formed on the foundation insulating layer to cover the electronic element and having a top surface side embedded in the resin layer; anda conductive layer formed on the foundation insulating layer and configured to connect the pad electrode and the internal electrode through a first opening portion for exposing a back surface of the internal electrode.2. The stacked package according to claim 1 , wherein the electronic element is an MEMS element.3. The stacked package according to claim 1 , further comprising an electromagnetic shielding layer formed between the semiconductor element and the hollow body.4. The stacked package according to claim 1 , wherein the resin layer covers the pad electrode.5. The stacked package according to claim 4 , further comprising a second opening portion formed on the resin layer and configured to expose the pad electrode.6. The stacked package according to ...

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF

A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. 1. A semiconductor packaging method at least comprising:providing a substrate having an upper surface and a plurality of pads disposed on the upper surface, wherein each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas;forming a conductible gel with anti-dissociation function on the upper surface and the pads of the substrate, wherein the conductible gel with anti-dissociation function includes a plurality of conductive particles and a plurality of anti-dissociation substances; andmounting a chip on the substrate, the chip comprises an active surface facing toward the upper surface of the substrate and a plurality of copper-containing bumps disposed at the active surface, wherein the conductible gel with anti-dissociation function covers the copper-containing bumps, each of the copper-containing bumps comprises a second coupling surface ...

METHOD FOR FABRICATING PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT

A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. 111-. (canceled)12. A method for fabricating a packaging structure having an embedded semiconductor element , comprising the steps of:providing a substrate having a first surface and an opposite second surface and at least an opening region predefined on the first surface;forming a first metallic frame around a periphery of the predefined opening region on the first surface of the substrate;forming an opening inside the first metallic frame by laser ablation, in a manner that the opening penetrates the first surface and the second surface of the substrate;disposing a semiconductor chip in the opening, the semiconductor chip having an active surface with a plurality of electrode pads and an opposite inactive surface;respectively forming a first dielectric layer on the first surface of the substrate and the active surface of the semiconductor chip and on the second surface of the substrate and the inactive surface of the semiconductor chip;forming a first wiring layer on the first dielectric layer on the first surface of the substrate and the active surface ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer. 1. A method , comprising:providing an electrically conductive carrier;placing a semiconductor chip over the carrier;applying an electrically insulating layer over the carrier and the semiconductor chip, the electrically insulating layer having a first face facing the carrier and a second face opposite to the first face;selectively removing the electrically insulating layer; andapplying solder material to places where the electrically insulating layer is removed and on the second face of the electrically insulating layer.2. The method of claim 1 , comprising soldering the semiconductor chip to the carrier.3. The method of claim 1 , comprising selectively removing the electrically insulating layer by at least one of etching claim 1 , photostructuring and laser structuring.4. The method of claim 1 , comprising heating the solder material.5. The method of claim 1 , comprising applying at least one metal layer to the carrier claim 1 , the semiconductor chip claim 1 , and the electrically insulating layer after selectively removing the electrically insulating layer.6. The method of claim 5 , comprising applying the solder material to the at least one metal layer.7. The method of claim 5 , comprising applying the at least one metal layer by sputtering.8. The method of claim 1 , comprising exposing portions of the carrier and the semiconductor chip after selectively removing the electrically ...

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

THERMAL INTERFACE MATERIAL FOR SEMICONDUCTOR CHIP AND METHOD FOR FORMING THE SAME

Disclosed is a method for forming a thermal interface material for a semiconductor chip, comprising the steps of forming an initial layer on a substrate, the initial layer including carbon nanotubes and nano metal powder; arranging a semiconductor chip on the initial layer; and heat-treating the initial layer with a sintering temperature of the nano metal powder to obtain a thermal interface material of the carbon nanotubes and the nano metal powder. 1. A method for forming a thermal interface material for a semiconductor chip , the method comprising:forming an initial layer comprising carbon nanotubes and nano metal powder on a substrate;disposing a semiconductor chip on the initial layer; andheat-treating the initial layer at a sintering temperature of the nano metal powder to form the thermal interface material, applying a paste comprising the carbon nanotubes and the nano metal powder to the substrate; and', 'aligning the carbon nanotubes orthogonally to the plane of the substrate by applying one of an electric field and a magnetic field to the paste., 'wherein forming the initial layer comprises25-. (canceled)6. The method of claim 1 , further comprising forming the paste by mixing the carbon nanotubes and the nano metal powder with a binder claim 1 , a dispersing agent claim 1 , and a solvent.78-. (canceled)9. The method of claim 1 , wherein the binder claim 1 , the dispersing agent claim 1 , and the solvent are removed at a temperature below the sintering temperature.10. A thermal interface material claim 1 , comprising:a sintered product made of sintered nano metal powder and carbon nanotubes,wherein the sintered product is disposed between a substrate and a semiconductor chip.11. The thermal interface material of claim 10 , wherein the carbon nanotubes are disposed on the substrate in a vertical direction and spaced apart from each other to form a carbon nanotube array claim 10 , and the nano metal powder in a paste state is infiltrated into the carbon ...

INTER-DIE CONNECTION WITHIN AN INTEGRATED CIRCUIT FORMED OF A STACK OF CIRCUIT DIES

An integrated circuit is formed of a plurality of circuit dies having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks. 1. An integrated circuit comprising:a plurality of circuit dies stacked together, each of said plurality of circuit dies having a substrate layer with a layer of processing circuitry formed thereupon; whereinat least one of said plurality of circuit dies has a plurality of vias extending to a face of said at least one of said plurality of dies;at least one of said plurality of circuit dies has an inter-die routing layer providing a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via position at which one of said vias extends to said face and a connection position at which a conductive connection is made to an adjacent circuit die of said plurality of circuit dies; andsaid vias in said at least one of said plurality of circuit dies have a via placement pattern, said connection positions in said adjacent circuit die have a connection position placement pattern, said via placement pattern is different from said connection position placement pattern and said inter-die routing layer provides said conduction paths to bridge gaps between via positions and connection positions.2. An integrated circuit as claimed in claim 2 , wherein said plurality of vias extend through one of: (i) said substrate layer; (ii) said layer of processing circuitry; and (iii) said substrate layer and said layer of processing circuitry.3. An integrated circuit as claimed in claim 1 , wherein ...

Semiconductor chip stack package and manufacturing method thereof

The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity

INTEGRATED COLD PLATE FOR ELECTRONICS

A cold plate has a base plate connected to a cover to form an enclosure, with an inlet and outlet nozzle penetrating the enclosure for coolant flow. The base plate includes a top surface opposite a bottom surface, Where the top surface includes enhancements positioned within the enclosure under the cover. The base plate has an inlet trough and an outlet trough that serve as headers, so the inlet nozzle connects to the inlet trough, and coolant from the inlet trough can flow through the enhanced surface, collect in the outlet trough, and then exit the cold plate through the outlet nozzle. The enhanced surface includes enhancements that begin at a point in between the bottom surface and the top surface, and the enhancements extend to a point above the top surface. 1. A cold plate comprising: a plurality of enhancements on the top surface, where the enhancements are monolithic with the base plate;', 'ii. an inlet trough formed in the base plate adjacent to the enhancements;', 'iii. an outlet trough formed in the base plate adjacent to the enhancements;', 'iv. a base plate inlet nozzle indent formed in the base plate, where the base plate inlet nozzle indent extends from the edge to the inlet trough;', 'v. a base plate outlet nozzle indent formed in the base plate, where the base plate outlet nozzle indent extends from the edge to the outlet trough, 'a. a base plate with a top surface, a bottom surface, and an edge, where the base plate further comprises i. a dome extending over the base plate to form an enclosure, and where the enhancements are within the enclosure;', 'ii. a cover inlet nozzle indent aligned with the base plate nozzle indent;', 'iii. a cover outlet nozzle indent aligned with the base plate outlet nozzle indent;, 'b. a cover connected to the base plate, where the cover further comprises;'}c. an inlet nozzle connected to the base plate and cover, where the inlet nozzle is positioned between the base plate inlet nozzle indent and the cover inlet nozzle ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section. 1. A method for manufacturing a semiconductor device , wherein a wafer is mounted to a dicing frame using a holding tape , a plurality of semiconductor devices are provided on a center portion of a major surface of the wafer , and a ring-like reinforcing section is provided on a periphery of the major surface , the method comprising:adhering the holding tape to the major surface; andheating the holding tape to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.2. The method according to claim 1 , wherein the holding tape is heated by lamp heating.3. The method according to claim 1 , wherein the holding tape is adhered on the major surface by differential pressure of an atmosphere and a vacuum of 1000 Pa or below. 1. Field of the InventionThe present invention relates to a method for mounting a wafer, wherein a plurality of semiconductor devices are provided on the center portion of the major surface, and a wafer, wherein a ring-like reinforcing section is provided, is mounted on the periphery of the major surface with a holding tape. In particularly, the present invention relates to a method for manufacturing a semiconductor device wherein a holding tape can be adhered to the steps of the ring-like reinforcing section without air bubbles.2. Background ArtIn LSI, the densification of packages by three-dimensional mounting or the like is performed, and wafer thinning to approximately 10 μm when the process is ...

PACKAGE FOR A MICROELECTRONIC DIE, MICROELECTRONIC ASSEMBLY CONTAINING SAME, MICROELECTRONIC SYSTEM, AND METHOD OF REDUCING DIE STRESS IN A MICROELECTRONIC PACKAGE

A package for a microelectronic die () includes a first substrate () adjacent to a first surface () of the die, a second substrate () adjacent to the first substrate, and a heat spreader () adjacent to a second surface () of the die. The heat spreader makes contact with both the first substrate and the second substrate. 1. A package for a microelectronic die , the package comprising:a first substrate adjacent to a first surface of the die;a second substrate adjacent to the first substrate; anda heat spreader adjacent to a second surface of the die, wherein the heat spreader makes contact with both the first substrate and the second substrate.2. The package of wherein:the first surface of the die defines a first plane;the heat spreader makes contact with the first substrate at a first substrate contact area and makes contact with the second substrate at a second substrate contact area; andthe first substrate contact area is located in the first plane and the second substrate contact area is located in a second plane that is parallel to the first plane.3. The package of wherein:the first substrate comprises a first surface and an opposing second surface, where the first surface of the first substrate is adjacent to the first surface of the die and the second surface of the first substrate is adjacent to the second substrate;the first substrate comprises a first plurality of interconnects having a first pitch at the first surface of the first substrate and a second plurality of interconnects having a second pitch at the second surface of the first substrate; andthe first pitch is smaller than the second pitch.4. The package of wherein:the first surface of the first substrate comprises a first side, a second side opposite the first side, a third side extending between the first side and the second side, and a fourth side opposite the third side;the second substrate comprises a first surface and an opposing second surface, where the first surface of the second substrate ...

Semiconductor memory modules and methods of fabricating the same

The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other; and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed. 1. A manufacturing method of a semiconductor device comprising the steps of:(a) preparing a first frame in which a plurality of heat sinks are tied together through tying portions;(b) preparing a second frame in which a plurality of lead portions each having a plurality of leads and a chip placement portion are tied together;(c) forming the second frame so that the front surface of each the chip placement portion is positioned lower than the front surfaces of the leads;(d) placing a semiconductor chip over the front surface of each the chip placement portion;(e) electrically coupling together each the semiconductor chip and the leads; and(f) sealing part of each the heat sink, part of each the lead portion, and each the semiconductor chip,wherein the step (f) includes the steps of:(f1) positioning and setting the first frame and the second frame in molding dies so that each the chip placement portion overlaps with each the heat sink from above as viewed in a plane,(f2) filling resin in the molding dies using the tying portions formed in the first frame as a resin stopper; and(f3) taking the molded first frame and second frame out of the molding dies.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein at the step ...

STACKED INTERPOSER LEADFRAMES

A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening. 1. A method of manufacturing integrated circuit (IC) devices , the method comprising the steps of:providing a first frame that comprises one or more openings each comprising a plurality of shaped notches;placing with a pick-and-place machine a first die in at least one of the one or more openings;placing a second frame over the first frame, the second frame comprising one or more first partial dam bars each comprising a first shaped tip that fits into a first shaped notch of the first frame; andplacing a third frame over the second frame, the third frame comprising one or more second partial dam bars each comprising a second shaped tip that fits into a second shaped notch of the first frame;wherein each of the one or more openings of the first frame and the respective first and second partial dam bars of the second and third frames cooperate to form a continuous dam completely encircling the die within the respective opening.2. The method of claim 1 , wherein:the first frame comprises a carrier film disposed across a portion of the at least one of the one or more openings; andthe step of placing a die in the at least one of the one or more openings comprises placing each die on the carrier film disposed across ...

METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY SUBSTRATE MANUFACTURED THEREBY

The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a coreless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump and a portion of the flange to form a cavity and expose a conductive via of the coreless build-up circuitry from a closed end of the cavity, wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the conductive via. The coreless build-up circuitry provides signal routing for the semiconductor device while the stiffener can provide adequate mechanical support for the coreless build-up circuitry and the semiconductor device. 1. A method of making a cavity substrate , comprising:providing a supporting board that includes a sacrificial carrier, a stiffener and an adhesive, wherein (i) the sacrificial carrier includes a bump and a flange, (ii) the bump is adjacent to and integral with the flange and extends from the flange in a first vertical direction, (iii) the flange extends laterally from the bump in lateral directions orthogonal to the first vertical direction, and (iv) the stiffener is attached to the sacrificial carrier via the adhesive between the stiffener and the flange and between the stiffener and the bump;forming a coreless build-up circuitry that covers the bump and the stiffener in the first vertical direction and includes a conductive via that is covered by the bump in a second vertical direction opposite the first vertical direction; andremoving the bump and a portion of the flange adjacent to the bump to form a cavity and expose the conductive via of the coreless build-up circuitry from a closed end of the cavity, ...

VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES

A particular method of making a stacked multi-die semiconductor device includes forming a stack of at least two dies. Each die includes a chip identifier structure that includes a first set of at least two through vias that are each hard wired to a set of external electrical contacts. Each die further includes chip identifier selection logic coupled to the chip identifier structure. Each die further includes a chip select structure that includes a second set of at least two through vias coupled to the chip identifier selection logic. The method further includes coupling each external electrical contact to a voltage source or ground. Each of the first set of through vias has a pad that is coupled to an adjacent through via and each of the second set of through vias is coupled to its own respective pad. 1. A method of making a stacked multi-die semiconductor device , the method comprising: a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts;', 'chip identifier selection logic coupled to the chip identifier structure; and', 'a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one; and, 'forming a stack of N dies, wherein each die comprisescoupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of N through vias has a pad that is coupled to an adjacent through via and each of the second set of N through vias is coupled to its own respective pad.2. The method of claim 1 , wherein each die further comprises a common access channel structure that comprises a plurality of through vias.3. The method of claim 1 , wherein the stack of the N dies is formed on a package substrate that supplies the voltage source and the ground and the package substrate has a plurality of package balls formed on a ...

STACKED WAFER STRUCTURE AND METHOD FOR STACKING A WAFER

A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided. 1. A stacked wafer structure , comprising:a substrate;at least a dam provided on the substrate and having protrusions on a surface thereof; anda wafer provided on the dam, with the protrusions embedded into the wafer.2. The stacked wafer structure of claim 1 , wherein the substrate is a silicon substrate or a glass substrate.3. The stacked wafer structure of claim 1 , wherein the protrusions are wedged into the wafer.4. The stacked wafer structure of claim 1 , wherein the dam at least includes a first layer coupled to the substrate and a second layer coupled to the wafer.5. The stacked wafer structure of claim 4 , wherein the first layer and the second layer are made of the same or different material.6. The stacked wafer structure of claim 4 , wherein the first layer and the substrate are made of the same material claim 4 , and the second layer and the wafer are made of the same material.7. The stacked wafer structure of claim 4 , wherein the first layer is the protrusions.8. The stacked wafer structure of claim 4 , wherein the second layer is the protrusions.9. A method for stacking a wafer claim 4 , comprising:forming on a substrate at least a dam having protrusions thereon, andcombining a wafer onto the dam, with the protrusions embedded into the wafer.10. The method of claim 9 , wherein the substrate is a silicon substrate or a glass substrate.11. The method of claim 9 , wherein the protrusions are wedged into the wafer.12. The method of claim 9 , wherein the ...

METHOD FOR MANUFACTURING ELECTRONIC DEVICES

A support structure includes a support cell with a support substrate, junction sacrificial portions surrounding the support substrate, and pin blocks extending from the junction sacrificial portion toward the support substrate. A semiconductor chip is mounted to the support substrate and electrically wire bonded to the pin blocks. An encapsulating body covers the chip, with the pin blocks extending from the body. A transversal groove is formed in each pin block. Surfaces of the pin block and groove are electroplated with solder material. Each pin block is sectioned at the groove to define a pin having a first end corresponding to a portion of the groove surface of the groove and a second end corresponding to the sectioned portion of the pin block that is not electroplated with solder material. Sectioning causes the separation of the chip-insulating body assembly from the junction sacrificial portions. 1. A method , comprising:forming a groove extending transversal to a leadframe pin block, said leadframe pin block extending away from a side of an encapsulated semiconductor device, said groove including a side wall;covering surfaces of the pin block including said side wall with a solder material layer;sectioning the pin block at the groove to define a pin for the encapsulated semiconductor device having an outer end formed in part by said solder material layer covered side wall and in part by a sectioned portion of the pin block not covered by said solder material layer.2. The method of claim 1 , further comprising:providing a leadframe support structure including a support cell having a support substrate, junction sacrificial portions surrounding the substrate support, and pin blocks which extend from the junction sacrificial portions towards the support substrate, each pin block having a first end connected to a junction sacrificial portion and a second end opposite to the first end.3. The method of claim 2 , further comprising: connecting a semiconductor material ...

Method for producing semiconductor device

A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided. 17-. (canceled)8. A manufacturing method of a semiconductor device comprising the steps of:forming a post electrode on a semiconductor wafer;flip-chip bonding a second semiconductor chip onto the semiconductor wafer;forming a groove in an upper surface of the semiconductor wafer;forming a resin portion on the semiconductor wafer for sealing to cover the post electrode and the second semiconductor chip;performing one of grinding and polishing of the resin portion and the second semiconductor chip such that an upper surface of the post electrode and an upper surface of the second semiconductor chip are exposed;performing one of grinding and polishing of a lower surface of the semiconductor wafer such that the semiconductor wafer is thinner than a depth of the groove, so as to form a first semiconductor chip from the semiconductor wafer; andcutting the resin portion along the groove to separate the first semiconductor chip.9. The manufacturing method according to claim 8 , wherein the step for separating the first semiconductor chip includes a step for cutting the semiconductor wafer such that the resin portion remains on a side surface of the first semiconductor chip.10. The manufacturing method according to claim 8 , further comprising a step for forming an embedded electrode which is embedded in the semiconductor wafer claim 8 , wherein:in the step for forming the post electrode, the post electrode is ...

PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES

A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. 1. A method of fabricating a semiconductor package , comprising:providing a semiconductor chip including at least one electrical connection terminal;providing a package substrate including a first opening portion to be coupled to the at least one electrical connection terminal and that extends beyond a region coupled to the electrical connection terminal;mounting the semiconductor chip on the package substrate to couple the at least one electrical connection terminal through the first opening portion to the package substrate; andproviding a molding resin by a pressure and vacuum environment to form a molding layer molding the semiconductor chip,wherein the molding resin is provided through a gap between the package substrate and the semiconductor chip to form an underfilling layer that fills the gap while simultaneously forming the molding layer.2. The method of claim 1 , wherein the forming of the underfilling layer comprises flowing the molding resin claim 1 , which flowed into the gap claim 1 , in the first opening portion claim 1 ,wherein the extended region of the first opening portion causes the flow resistance of the molding resin in the first opening portion to become lower than the flow resistance of the molding resin in the gap.3. The method of claim 1 , wherein the forming of the underfilling layer comprises:forming a cavity, which is not filled with the molding resin, ...

MULTI-CHIP FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A multi-chip flip chip package includes multiple dies. Each die comprises several pads for coupling with pads of the other die and for coupling with pins of the multi-chip flip chip package through conducting elements. A dielectric element is positioned between the dies and the conducting elements, and positioned between the dies for providing the electrical insulation. The dies and the conducting elements between the dies are coated with a packaging element for preventing physical damage and corrosion. 1. A method for manufacturing a multi-chip flip chip package , comprising:attaching a second surface of a first die and a second surface of a second die to a second substrate;positioning a first dielectric element between the first die and the second die;coupling a plurality of conducting elements of a first conducting group with at least part of pads on a first surface of the first die, and with at least part of pads on a first surface of the second die;coupling at least part of the pads on the first surface of the first die with at least part of the pads on the first surface of the second die by utilizing a plurality of conducting elements of a second conducting group;coupling at least part of the conducting elements of the first conducting group with strips of a lead frame; andcoating the first die, the second die, and the conducting elements of the second conducting group with a packaging element.2. The method of claim 1 , further comprising:attaching the second surface of the first die and the second surface of the second die to the second substrate after the first surface of the first die and the first surface of the second die were attached to a first substrate; andremoving the first substrate after the first die and the second die were attached to the second substrate.3. The method of claim 1 , further comprising:coating the first die, the second die, and the conducting elements of the second conducting group with the packaging element after the second ...

Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby

The present invention relates to a method of making a semiconductor assembly. In accordance with a preferred embodiment, the method includes: preparing a dielectric layer and a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier and the dielectric layer covers the supporting board; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; then mounting a semiconductor device into the cavity; and then forming a build-up circuitry that includes a first conductive via in direct contact with the semiconductor device and provides signal routing for the semiconductor device. Accordingly, the direct electrical connection between the semiconductor device and the build-up circuitry is advantageous to high I/O and high performance, and the stiffener can provide adequate mechanical support for the build-up circuitry and the semiconductor device.

MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE

First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. 1. A microelectronic assembly , comprising:a semiconductor chip having a first face, a second face, and a plurality of chip contacts exposed at the first face;a substrate including a dielectric element, the dielectric element having a face juxtaposed with one of the first or second faces, the substrate having a plurality of substrate contacts exposed at the face of the dielectric element; anda first electrically conductive bond element and a second electrically conductive bond element, the first and second bond elements each being one of a bond ribbon or a bond wire, the first and second bond elements electrically connecting a first chip contact of the plurality of chip contacts with a corresponding first substrate contact of the plurality of substrate contacts and providing parallel conductive paths between the first chip contact and the first substrate contact, the first bond element having a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact, the second bond element being metallurgically joined to the first or second ends of the first bond element,wherein the second bond element does not touch the first chip contact and does not touch the first substrate contact.2. The microelectronic assembly of claim 1 , wherein the first electrically conductive bond element is a first bond wire and the second ...

PASSIVATION FOR WAFER LEVEL - CHIP-SCALE PACKAGE DEVICES

Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size. 1. A method comprising:connecting a silicon wafer to a sawing foil;dicing the silicon wafer and producing therefrom a plurality of self-contained chip-scale device packages in which each device package is separated from other ones of the device packages by a gap defined by sidewalls of the device packages, is connected to the sawing foil, and has an active side and a non-active side between which the sidewalls extend; andwhile the device packages are coupled to a common foil, concurrently depositing an electrically isolating coating on the sidewalls and at least a portion of the non-active side of all of the plurality of device packages.2. The method of claim 1 , wherein dicing the silicon wafer and producing therefrom a plurality of self-contained chip-scale device packages includes forming chip-scale device packages of different sizes and geometries.3. The method of claim 1 , whereindicing the silicon wafer includes using a plasma to remove portions of the silicon wafer to form the gaps, anddepositing an electrically isolating coating on the sidewalls and the non-active sides includes depositing the coating from a plasma.4. The method of claim 1 , whereindicing the silicon wafer includes using a plasma to remove portions of the silicon wafer to form the gaps, anddepositing an electrically isolating coating on the sidewalls and the non-active sides includes depositing the coating from the same plasma used to removed portions of the silicon wafer.5. The method of claim 1 ,further including providing an etch mask and etching a portion of the non-active side of the device packages under the mask, andwherein ...

PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.