ИЗГОТОВЛЕНИЕ СВОБОДНОГО ОТ ДЕФЕКТОВ УСТРОЙСТВА НА ОСНОВЕ РЕБРА В ОБЛАСТИ ПОПЕРЕЧНОГО ЭПИТАКСИАЛЬНОГО НАРАЩИВАНИЯ

VERFAHREN UND VORRICHTUNG ZUM NASSÄTZEN VON HALBLEITERSUBSTRATEN

GRABENFÜLLUNG DURCH AUFSCHMELZEN DES FÜLLMATERIALS

Ein Verfahren umfasst das Bilden einer ersten vorstehenden Finne und einer zweiten vorstehenden Finne über einer Basisstruktur, wobei sich zwischen der ersten vorstehenden Finne und der zweiten vorstehende Finne ein Graben befindet, das Abscheiden eines Grabenfüllmaterials, das sich in den Graben erstreckt, und das Durchführen eines Laseraufschmelzprozesses an dem Grabenfüllmaterial. Bei dem Aufschmelzprozess weist das Grabenfüllmaterial eine Temperatur auf, die höher als ein erster Schmelzpunkt des Grabenfüllmaterials und niedriger als ein zweiter Schmelzpunkt der ersten vorstehenden Finne und der zweiten vorstehenden Finne ist. Nach dem Laseraufschmelzprozess wird das Grabenfüllmaterial verfestigt. Das Verfahren umfasst ferner das Strukturieren des Grabenfüllmaterials, wobei ein verbliebener Abschnitt des Grabenfüllmaterials einen Teil eines Gate-Stapels bildet, und das Bilden eines Source/Drain-Bereichs an einer Seite des Gate-Stapels.

Halbleiterstruktur und Verfahren

Verfahren zum Herstellen eines Halbleiterbauelements, wobei das Verfahren umfasst: Kombinieren eines Halbleiterrohmaterials und eines leerstellenverstärkenden Rohmaterials, um eine kombinierte Rohmaterialmischung auszubilden; und Schmelzen der Rohmaterialmischung und Kristallisieren der dabei entstehenden Halbleiterschmelze zu einem Halbleiter-Ingot mit einer Lehrstellenkonzentration von 1010/cm3 bis 1015/cm3; Trennen eines Halbleiterwafers oder mehrerer Halbleiterwafer von dem Halbleiter-Ingot; Ausbilden von Isolierbereichen innerhalb eines der Halbleiterwafer durch Abscheiden eines dielektrischen Materials innerhalb eines Grabens in dem Halbleiterwafer; und Tempern des Halbleiterwafers mit dem dielektrischen Material, wobei der Halbleiterwafer in einer Umgebung von Wasserstoff, Helium, Argon oder Kombinationen derselben gehalten wird und das Tempern des dielektrischen Materials bulk micro defects innerhalb des Halbleiterwafers erzeugt, wobei das Tempern die Schritte aufweist: – Erhöhen ...

Verfahren zum Bilden von Halbleitervorrichtungen, bei dem elektrolysierte Schwefelsäure (ESA) verwendet wird

Ein Verfahren zum Bilden einer Halbleitervorrichtung kann ein Bilden einer Metallschicht (51) auf einem Siliziumbereich eines Substrats (10) und Reagieren der Metallschicht (51) mit dem Siliziumbereich zum Bilden eines Metallsilizids (53) aufweisen. Nach einem Reagieren der Metallschicht (51) kann ein nichtreagierter Rest (52) der Metallschicht (51) durch Verwenden einer elektrolysierten Schwefelsäurelösung entfernt werden. Insbesondere kann ein Volumen von Schwefelsäure in der elektrolysierten Schwefelsäurelösung in einem Bereich von ungefähr 70% bis ungefähr 95% des Gesamtvolumens der elektrolysierten Schwefelsäurelösung liegen, eine Konzentration von Oxidationsmittel in der elektrolysierten Schwefelsäurelösung kann in einem Bereich von ungefähr 7 g/L bis ungefähr 25 g/L liegen und eine Temperatur der elektrolysierten Schwefelsäurelösung kann in einem Bereich von ungefähr 130 Grad Celsius bis ungefähr 180 Grad Celsius liegen.

Das Integrieren VLSI-kompatibler Rippen-Strukturen mit selektivem Epitaxialwachstum und das Fertigen von Vorrichtungen darauf

Unterschiedliche n- und p-Typen von Vorrichtungs-Rippen werden durch epitaxiales Wachsenlassen erster Epitaxialbereiche eines Materials eines ersten Typs aus einer Substratoberfläche an einer Unterseite von ersten Gräben ausgebildet, die zwischen flachen-Grabenisolations(STI)-Bereichen ausgebildet sind. Die STI-Bereiche und erste-Graben-Höhen sind mindestens 1,5 mal deren Breite. Die STI-Bereiche werden weggeätzt, um die obere Fläche des Substrats zur Ausbildung von zweiten Gräben zwischen den ersten Epitaxialbereichen freizulegen. Eine Abstandsmaterialschicht ist in den zweiten Gräben auf Seitenwänden der ersten Epitaxialbereiche ausgebildet. Zweite Epitaxialbereiche eines Materials eines zweiten Typs werden aus der Substratoberfläche an einer Unterseite der zweiten Gräben zwischen den ersten Epitaxialbereichen wachsen gelassen. N- und p-Typ-Rippen-Paare können aus dem ersten und zweiten Epitaxialbereich gebildet werden. Die Rippen werden miteinbezogen und weisen verminderte Defekte aus ...

ISOLATION MIT GLASHARZ GEFUELLTEN TIEFEN GRAEBEN.

Verfahren zur Herstellung einer Planarisolierung

Halbleiterbauelement mit verspanntem aktiven Gebiet

Halbleiterbauelement mit einem aktiven Halbleiterbereich (11) und einem den aktiven Halbleiterbereich (11) lateral begrenzenden Isolatorbereich (13), der auf den aktiven Halbleiterbereich (11) eine entweder teilweise oder vollständig lateral gerichtete Kraft ausübt, dadurch gekennzeichnet, dass der lateral begrenzende Isolatorbereich (13) hinsichtlich des Materials oder seiner lateralen Erstreckung oder beider so gewählt ist, dass im aktiven Halbleiterbereich eine uniaxiale oder eine biaxiale, tensile oder kompressive Gitterdilatation mit einem vorbestimmten Betrag ε von entweder 0,01 oder mehr als 0,01 vorliegt.

Integrierte Schaltung mit im Wesentlichen durch das Substrat verlaufenden Isolationsbereichen

... raben-Isolationsbereiche enthält. Das Substrat trägt eine Vorrichtung. Die Graben-Isolationsbereiche sind konfiguriert, um die Vorrichtung seitlich zu isolieren. Die Graben-Isolationsbereiche erstrecken sich im Wesentlichen durch das Substrat.

Preparation of trench structures with oxidation layers including cladding of trench inner region formed in semiconductor region, deposition of a further layer and oxidation

Preparation of trench structures with oxide cladding involving: (a) formation of a semiconductor region; (b) formation of a trench (30); (c) cladding of the trench inner region with a first oxidation layer; (d) formation or deposition of a material layer (50) inside the trench; and (e) use of a second oxidation step with deposition of a second oxidation layer. Independent claims are included for: (1) an integrated arrangement or chip with at least one trench structure; and (2) a semiconductor element, especially a trench structure transistor device, trench transistor or field plate transistor.

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Halbleitervorrichtung (200), die Folgendes umfasst:einen ersten aktiven Bereich (205) benachbart zu einer ersten Seite (256) eines Grabenisolierungsbereichs, eines STI-Bereichs (209), wobei der erste aktive Bereich (205) Folgendes umfasst:- einen ersten proximalen Grat (252) benachbart zu dem STI-Bereich (209), der eine erste proximale Grathöhe (226) aufweist; und- einen ersten distalen Grat (254) benachbart zu dem ersten proximalen Grat (252), der eine erste distale Grathöhe (224) aufweist;einen zweiten aktiven Bereich (207) benachbart zu einer zweiten Seite (258) des STI-Bereichs (209), wobei der zweite aktive Bereich (207) Folgendes umfasst:- einen zweiten proximalen Grat (253) benachbart zu dem STI-Bereich (209), der eine zweite proximale Grathöhe (227) aufweist; und- einen zweiten distalen Grat (255) benachbart zu dem zweiten proximalen Grat (253), der eine zweite distale Grathöhe (225) aufweist; undein Oxid (230) des STI-Bereichs (209), das in einer Öffnung in einer Oberseite einer ...

Verfahren und Herstellung eines Halbleiterbauelements

Ein Verfahren zur Herstellung eines Halbleiterbauelements umfasst Bereitstellen eines monokristallinen Halbleitersubstrats (10) mit einer ersten Seite; Bilden mehrerer Aussparungsstrukturen (12a) in dem Halbleitersubstrat (10) auf der ersten Seite; Füllen der Aussparungsstrukturen (12a) mit einem dielektrischen Material zum Bilden von dielektrischen Inseln (12) in den Aussparungsstrukturen (12a); Bilden einer Halbleiterschicht (13) auf der ersten Seite des Halbleitersubstrats (10) zum Bedecken der dielektrischen Inseln (12); und Aussetzen der Halbleiterschicht (13) einer Wärmebehandlung und Rekristallisieren der Halbleiterschicht (13). Die Kristallstruktur der rekristallisierten Halbleiterschicht passt sich an die Kristallstruktur des Halbleitersubstrats an. Das Halbleitersubstrat (10) und die Halbleiterschicht (13) bilden zusammen einen Verbundwafer, wobei die dielektrischen Inseln (12) zumindest teilweise in dem Halbleitermaterial des Verbundwafers vergraben sind.

Struktur und Verfahren für einen Feldeffekttransistor

Die vorliegende Offenbarung liefert eine Ausführungsform einer Halbleiterstruktur, die ein Halbleitersubstrat, eine STI(Shallow Trench Isolation)-Struktur, die in dem Halbleitersubstrat ausgebildet ist, wobei die STI-Struktur eine kontinuierliche Isolierungsstruktur ist und einen ersten Abschnitt in einem ersten Gebiet und einen zweiten Abschnitt in einem zweiten Gebiet enthält und der erste Abschnitt der STI-Struktur relativ zum zweiten Abschnitt der STI-Struktur abgesetzt ist, ein aktives Gebiet in dem Halbleitersubstrat, das von der STI-Struktur umrahmt wird, einen Gate-Schichtenstapel, der auf dem aktiven Gebiet angeordnet und in einer ersten Richtung zum ersten Gebiet der STI-Struktur verlängert ist, Source- und Drain-Strukturen, die in dem aktiven Gebiet ausgebildet und durch den Gate-Schichtenstapel getrennt sind, und einen Kanal enthält, der in dem aktiven Gebiet ausgebildet ist und sich in einer zweiten Richtung zwischen den Source- und Drain-Strukturen erstreckt, wobei sich die ...

Integrierter Transistor

Es ist ein integrierter Transistor für eine elektrische Vorrichtung, etwa eine DRAM-Speicherzelle, und ein Verfahren zur Herstellung desselben vorgesehen. Ein Graben wird in einem Substrat ausgebildet und ein Gate-Dielektrikum und eine Gate-Elektrode werden in dem Graben des Substrats ausgebildet. Source/Drain-Bereiche werden in dem Substrat auf gegenüberliegenden Seiten des Grabens ausgebildet. In einer Ausführungsform wird der Source- oder der Drain-Bereich mit einem Speicherknoten verbunden und der andere des Sourüce- und des Drain-Bereichs wird mit einer Bitleitung verbunden. In dieser Ausführungsform kann die Gate-Elektrode mit einer Wortleitung verbunden werden, um eine DRAM-Speicherzelle auszubilden. Ein dielektrischer Wachstumsmodifikator kann in Seitenwände des Grabens implantiert werden, um die Dicke des Gate-Dielektrikums einzustellen.

Verfahren zum Bilden von FinFET-Halbleitervorrichtungen unter Verwendung einer Austauschgatetechnik und die resultierenden Vorrichtungen

Ein hierin offenbartes Verfahren umfasst unter anderem ein Bilden einer gehobenen Isolationsstruktur zwischen einem ersten Fin und einem zweiten Fin, wobei die gehobene Isolationsstruktur teilweise einen ersten Raum und einen zweiten Raum zwischen dem ersten Fin bzw. dem zweiten Fin festlegt, und ein Bilden einer Gatestruktur um den ersten Fin und den zweiten Fin und die gehobene Isolationsstruktur, wobei wenigstens Bereiche der Gatestruktur in dem ersten Raum und dem zweiten Raum angeordnet sind. Eine anschauliche Vorrichtung umfasst unter anderem einen ersten Fin und einen zweiten Fin, eine gehobene Isolationsstruktur, die zwischen dem ersten Fin und dem zweiten Fin angeordnet ist, erste und zweite Räume, die durch die Fins und die gehobene Isolationsstruktur festgelegt werden, und eine Gatestruktur, die um einen Bereich der Fins und die Isolationsstruktur herum angeordnet ist.

ZENERDIODEN UND ZUGEHÖRIGE HERSTELLUNGSVERFAHREN

In einem allgemeinen Gesichtspunkt kann eine Halbleitervorrichtung ein hochdotiertes Substrat eines ersten Leitfähigkeitstyps, eine niedrigdotierte Epitaxialschicht eines zweiten Leitfähigkeitstyps, die auf dem hochdotierten Substrat angeordnet ist, und eine hochdotierte Epitaxialschicht des zweiten Leitfähigkeitstyps einschließen, die auf der niedrigdotierten Epitaxialschicht angeordnet ist. Die hochdotierte Epitaxialschicht kann eine Dotierungskonzentration aufweisen, die größer ist als eine Dotierungskonzentration des niedrigdotierten Epitaxialschicht. Mindestens ein Abschnitt des hochdotierten Substrats kann in einer ersten Anschlussklemme einer Zenerdiode eingeschlossen sein, und mindestens ein Abschnitt der niedrigdotierten Epitaxialschicht und mindestens ein Abschnitt der hochdotierten Epitaxialschicht können in einer zweiten Anschlussklemme der Zenerdiode eingeschlossen sein. Die Halbleitervorrichtung kann ferner einen Abschlussgraben einschließen, der sich durch die hochdotierte ...

Fin-Feldeffekttransistor (Finfet) - Bauelementstruktur mit unebenem Gate und Verfahren zur Ausbildung derselben

Es wird eine FinFET-Bauelementstruktur geschaffen. Die FinFET-Bauelementstruktur umfasst eine Isolationsstruktur auf, die über einem Substrat ausgebildet ist, und eine Fin-Struktur, die über dem Substrat ausgebildet ist. Die FinFET-Bauelementstruktur umfasst eine erste Gate-Struktur und eine zweite Gate-Struktur, die über der Fin-Struktur ausgebildet sind, und die erste Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine erste Breite auf, die zweite Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine zweite Breite auf, und die erste Breite ist kleiner als die zweite Breite. Die erste Gate-Struktur umfasst eine erste Austrittsarbeit-Schicht, die eine erste Höhe aufweist. Die zweite Gate-Struktur umfasst eine zweite Austrittsarbeit-Schicht, die eine zweite Höhe aufweist, und eine Lücke zwischen der ersten Höhe und der zweiten Höhe liegt in einem Bereich von circa 1 nm bis zu circa 6 nm.

Herstellungsverfahren für eine Halbleiterstruktur und enstprechende Halbleiterstruktur

Making a defect free fin based device in lateral epitaxy overgrowth region

A method of fabricating a SOI substrate

PROBLEM TO BE SOLVED: To form a silicon device layer with a uniform thickness without a process for forming an etching stopping film separately by forming a silicon device layer by using an isolation film as an etching stopping film and etching a device substrate. SOLUTION: Buried oxide films 24A, 24B of a specified thickness are formed on a device silicon board 20 and a handling board 25. The device silicon board 20 and the handling board 25 are bonded to bring the buried oxide films 24A, 24B into contact with it. The device silicon board 20 is subjected to grinding and lapping to have a specified thickness. Successively, the field oxide film 23 is used for an etching stopping film and the remaining device silicon board 20 is polished chemically and mechanically to expose a surface of the field oxide film 23. Thereby, a silicon device layer 20A with a fixed thickness is formed.

Method of etching silicon nitride

Method of forming a shallow trench isolation structure without divots in a semiconductor substrate

A method of forming a shallow trench isolation structure in a substrate (2) is described. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion (12), extending laterally over a silicon oxide film (4) and a silicon nitride film (6), and a lower portion (10) extending in a trench in a silicon substrate (2); and carrying out an isotropic etching to said upper portion (12) of the isolation silicon oxide film and the silicon oxide film (4), thereby forming an isolation trench structure without divots (Fig. 5G) in said trench in said silicon substrate. The process may involve lateral etching of the silicon nitride film (6) or involve forming sloped portions in the silicon nitride film (16) by sputter etching.

Trench isolation using doped sidewalls

Method of manufacturing semiconductor device structure

Flash memory array and a method and system of fabrication thereof

Semiconductor integrated circuit fabrication

A method of forming a semiconductor integrated circuit such as a BiCMOS integrated circuit comprises the steps of: (a) forming a first portion of a bipolar device in a first region of a substrate; (b) forming a first protective layer over the first region to protect the first portion of the bipolar devices; (c) forming field effect transistor devices in second regions of the substrate; (d) forming a second protective layer over the second regions of the substrate to protect the field effect transistor devices; (e) removing the first protective layer; (f) forming a second portion of the bipolar devices in the first region of the substrate; and (g) removing the second protective layer.

Mode converter and method of fabricating thereof

Method for fabricating silicon-on-insulator substrate

Semiconductor device and method of making same

... 1,133,376. Semi-conductor rectifiers. RADIO CORPORATION OF AMERICA. 23 May, 1966 [9 June, 1965], No. 22856/66. Heading H1K. A plurality of junction-containing semiconductor wafers are bonded in series in a stack by intervening conductive layers, the lateral surfaces of the wafers being protected by oxidic insulating material overlying which is a different insulating material. Suitable semi-conductors are silicon, germanium, and AIIIBV compounds such as gallium arsenide. Junction-containing wafers 10 may be produced from wafers of one conductivity type by single or double diffusion or by epitaxial growth. Conductive material 24 may be applied as a foil to one side of each wafer, or a conductive layer may be formed by evaporation, plating, spraying on a suspension of powdered material, or by dipping the wafer in powdered material. Conductive materials mentioned are chromium, niobium, palladium, platinum, silver, tantalum, titanium, or zirconium, and germanium and germaniumsilicon ...

A structure and method for guarding a low voltage region of a semiconductor device from a high voltage region of the semiconductor device

PROCEDURE FOR RECEIVING A THIN LAYER WITH A SMALL DENSITY FROM LÍCHERN

PROCEDURE FOR FILLING GAPS AND PROCEDURE FOR THE SEPARATION OF MATERIALS USING A HIGH-DENSITY CHEMICAL ORIFICE GAS PHASE SEPARATION

PROCEDURES FOR THE PRODUCTION OF A BURIAL, LATERAL ISOLATED ZONE OF INCREASED CONDUCTIVITY IN A SEMICONDUCTOR SUBSTRATE

Methods for regulating surface sensitivity of insulating films in semiconductor devices

Method of isolating semiconductor device

Electronic devices and methods of manufacture

PLANARIZATION PROCESS FOR ORGANIC FILLING OF DEEP TRENCHES

Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density ...

RESIN GLASS FILLED DEEP TRENCH ISOLATION

A method of forming trench/dielectric by coating trench walls and substrate surface with MgO followed by filling the trenches with a resin glass. The MgO layer is used for RIE planarization etchback of the resin glass to level of the trenches.

METHOD OF FORMING SHALLOW TRENCH ISOLATION IN SILICON

A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches (17) are formed in a silicon wafer (11) at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches (17) are then filled with an insulative material, such as oxide.

METHOD OF MAKING A PLANAR TRENCH SEMICONDUCTOR STRUCTURE

DIELECTRIC FILMS FOR NARROW GAP-FILL APPLICATIONS

A colloidal suspension of nanoparticles composed of a dense material dispersed in a solent is used in forming a gap-filling dielectric material with low thermal shrinkage. The dielectric material is particularly useful for pre- metal dielectric and shallow trench isolaiton applications. According to the mehtods of forming a dielectric material, the colloidal suspension is deposited on a substrate and dried to form a porous intermediate layer. The intermediate layer is modified bz infiltration with a liquid phase matrix material, such as a spin-on polymer, followed by curing, by infiltration with a gas phase matrix material, followd by curing, or by curing alone, to provide a gap-filling, thermally stable, etch resistant dielectric material.

ISOLATION STRUCTURE USING LIQUID PHASE OXIDE DEPOSITION

A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

Verfahren zur Herstellung von neuen Isochinolobenzodiazepin-Derivaten

Integrierte Halbleitervorrichtung

Verfahren zur Herstellung neuer Isochinolin-Derivate

Verfahren zur Herstellung neuer Diazepin-Derivate

Verfahren zur Herstellung neuer Diazepin-Derivate

Verfahren zur Herstellung neuer Isochinolin-Derivate

Fin type diode and manufacturing method thereof

METHOD FOR CREATING THE HIGH VOLTAGE COMPLEMENTARY BJT WITH LATERAL COLLECTOR ON BULK SUBSTRATE WITH RESURF EFFECT

METHOD FOR MANUFACTURING SEMINCONDUCTOR DEVICE

Method for forming shallow-trench isolating structure

The invention provides a method for forming a shallow-trench isolating structure, which comprises the components of: providing a semiconductor substrate, and forming a hard mask layer with a plurality of shallow-trench isolating structure patterns on the semiconductor substrate; forming a plurality of shallow-trench isolating structures in the semiconductor substrate; eliminating partial hard mask layer; performing oxygen plasma treatment on the part of each of the plurality of shallow-trench isolating structures, which is higher than the hard mask layer; performing annealing treatment, and forming a compact oxide layer on the top and side wall area of the part of each of the plurality of shallow-trench isolating structures, which is higher than the semiconductor substrate; and removing the residual hard mask layer. According to the method of the invention, because all compact oxide layer has higher corrosion resistance and a same mass characteristic, before a grid dielectric layer is formed ...

Semiconductor device

At least a part of an element isolating region other than a gate insulating film (silicon dioxide film), an interlayer insulating film and a protection insulating film is formed of a carbon fluoride (CFx, 0.3 Подробнее

Substrate processing method and substrate processing apparatus

Used for integrating capacitor of the FinFET structure and method

Fin structure of the semiconductor device

Semiconductor device

Method of filling large deep trench with high quality oxide for semiconductor devices

A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

The invention discloses a semiconductor device comprising a substrate and a shallow trench isolation in the substrate. The device is characterized in that a stress release layer is arranged between the substrate and the shallow trench isolation. According to the semiconductor device and a manufacturing method of the semiconductor device, through adding the soft stress release layer between the substrate and the STI, the accumulated stress in the formation process of the STI is released, the substrate leakage current of the device is reduced, and the reliability of the device is raised.

Method for forming isolation layer

The isolation structure, the semiconductor device having the same and method of manufacturing the isolation structure

Integrated circuit technology with different device epitaxial layers

Symmetrical high frequency SCR structure and method

双极型器件及其制造方法

... 一种双极型半导体器件例如双极型晶体管或二极管及其制造方法，利用例如底扩散区的内层电气连接，该内层具有良好的电导率，位于槽隔离双极型半导体器件的内部，并形成NPN晶体管的子集电极，使用了槽中的孔。孔中填充导电材料，孔由器件表面延伸到底扩散区，孔中的导电材料与其接触。孔利用选择刻蚀工艺与槽的侧壁对准。在制备金属化接触孔的同时，制作孔，然后在金属化步骤中填充孔，以便与底扩散区接触。对于横向PNP晶体管，孔制作为闭合的沟，该沟构成基极区域的外限制区，越过所有的晶体管。该闭合槽的外侧壁倾斜45°，这样在槽中没有角度很小的内角，这便于填充氧化物。 ...

制造外延双极器件和互补金属氧化物半导体器件的方法

... 一种形成BiMCOS集成电路的方法，该方法包括以步骤：(a)在衬底的第一区形成双极器件的第一部分；(b)在所说第一区上形成第一保护层，保护所说双极器件的所说第一部分；(c)在所说衬底的第二区上形成场效应晶体管；(d)在所说衬底的所说第二区上形成第二保护层，以保护所说场效应晶体管器件；(e)去掉所说第一保护层；(f)在所说衬底的所说第一区上形成所说双极器件的第二部分；(g)去掉所说第二保护层。 ...

Semiconductor device and method for producing the same

FABRICATION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP

METHOD FOR REALIZATION Of a JUST ELECTRONICS COMPONENT AND ELECTRIC DEVICE INCORPORATING a COMPONENT INTEGRATES THUS OBTAINED

Un procédé de réalisation d'un composant électronique comprend le recouvrement d'un substrat (100) par une portion (P) délimitant avec le substrat un volume (V) rempli au moins partiellement d'un matériau temporaire, l'évacuation du matériau temporaire par une cheminée (C) d'accès audit volume, et le dépôt d'un matériau de remplissage (7) dans ledit volume à partir de précurseurs amenés par la cheminée. Le procédé est particulièrement adapté pour la réalisation d'une grille d'un transistor de type MOS. Dans ce cas, le matériau de remplissage est conducteur, et un matériau isolant électrique de revêtement (8) peut aussi être déposé dans ledit volume avant le matériau de remplissage conducteur.

IMPROVED FORMATION OF STRAINED SILICON ON INSULATOR BY AMORPHIZATION VOLTAGE AND THEN RECRYSTALLIZATION

Procédé d'une structure de silicium contraint, dans lequel on forme une couche de silicium Germanium sur la couche de silicium, puis une autre couche de concentration en germanium plus faible avant d'effectuer une amorphisation sélective de la couche de silicium et de silicium germanium par rapport à cette autre couche avant de recristalliser l'ensemble de sorte à mettre en contrainte la couche semi-conductrice (3) en silicium. Du fait de l'amorphisation sélective on améliore la qualité du silicium contraint obtenu après recristallisation.

CONTACTS FOR ELECTRONIC COMPONENT

BIPOLAR TRANSISTOR

SEMICONDUCTOR HAS CHARACTERISTIC IV NOT SATURATES AND INTEGRATED CIRCUIT COMPRISING SUCH A SEMICONDUCTOR

METHOD OF MAKING TRANSISTORS, IN PARTICULAR TRANSISTORS FOR SELECTION FOR NON-VOLATILE MEMORIES, AND CORRESPONDING DEVICE.

DEVICE HAS JUST CIRCUITS HAS SEMICONDUCTORS INCLUDING/UNDERSTANDING a DEEP THROAT FILLED With an INSULATING MATERIAL AND MANUFACTORING PROCESS From SUCH a DEVICE

Semiconductor structure e.g. silicon on insulator structure, forming method, involves forming insulating zone in semiconductor substrate up to level of lower surface of mask, in controlled manner before/during removal of mask

L'invention concerne un procédé de réalisation d'une structure semi-conductrice, comportant : - la formation contrôlée, à travers un masque (31), dans un premier substrat (30) en un matériau semi-conducteur, d'au moins une première zone en un matériau isolant (36), jusqu'au niveau de la surface inférieure (35) du masque, avant ou pendant le retrait du masque.

PROCEDE POUR FABRIQUER UN DISPOSITIF SEMI-CONDUCTEUR COMPORTANT DE TRES PETITS TRANSISTORS COMPLEMENTAIRES, ET DISPOSITIF FABRIQUE DE LA SORTE

Procédé pour fabriquer un dispositif semi-conducteur comportant de très petits transistors complémentaires. Suivant l'invention, sans devoir respecter des tolérances de masques, on élabore deux zones de surface adjacentes 11 et 14, la formation d'une seule de celles-ci 11 ayant lieu par diffusion depuis une mince de silicium 6. La distance entre les deux zones de surface est déterminée par la largeur d'une bande d'oxyde 10 qui est formée sur la surface et sur le bord de la couche en silicium. La bande d'oxyde résulte d'un sous décapage et de l'emploi d'un masque en nitrure de silicium précipite à effet d'ombre. Application aux circuits intégrés monolithiques.

COMPRISING DEVICE OF THE ELECTRONICS COMPONENTS IN AREAS MUTUALLY INSOLEES Of a LAYER OF MATERIAL SEMICONDUCTOR AND MANUFACTORING PROCESS Of SUCH a DEVICE

L'invention concerne un procédé de fabrication d'un dispositif comprenant des composants électroniques (20a, 20b) dans des régions (32a, 32b) d'une couche de matériau semi-conducteur (12), ces régions étant mutuellement isolées. Le procédé comporte les étapes suivantes : a) formation de composants électroniques (30) des régions d'une couche de matériau semi-conducteur (12) formée par une couche isolante électrique (14), b) formation de tranchées traversant la couche de matériau semi-conducteur (12) de part en part afin de séparer les régions (32a, 32b), c) remplissage des tranchées (30) avec un matériau de remplissage, fluide, et d) durcissement dudit matériau de remplissage. Application à la fabrication de circuits intégrés comportant des composants de puissance.

SEMICONDUCTOR DEVICE AND RADIO FREQUENCY MODULE FORMED ON HIGH RESISTIVITY SUBSTRATE

Disclosed are a semiconductor device formed on a high resistivity substrate, and a radio frequency (RF) module including the same. A first deep well area with first conductivity is formed within a high resistivity substrate; a second deep well area with second conductivity is formed on the first deep well area; a first well area with first conductivity is formed on the second deep well area; and a transistor is formed on the first well area. COPYRIGHT KIPO 2016 ...

A FINFET DEVICE AND METHOD OF MANUFACTURING SAME

METHOD FOR FORMING AN ISOLATION FILM IN A SEMICONDUCTOR DEVICE, TO SIMPLIFY THE PROCESS BY PERFORMING DEPOSITION AND ETCHING OF AN HDP OXIDE LAYER IN ONE CHAMBER

PURPOSE: A method for forming an isolation film in a semiconductor device is provided to improve a process margin of a trench isolation layer by using a fluorine component of an NF3 gas as an isotropic etching gas. CONSTITUTION: Trenches(111) are formed in a semiconductor substrate(100), and then the substrate is loaded in an HDP(High Density Plasma) chamber. The HDP chamber is supplied with an HDP deposition source to deposit an HDP oxide layer. The chamber is supplied with a fluorine-based etching gas to etch overhang portions. The chamber is supplied with the HDP deposition source together with an inert gas to deposit a liner HDP oxide layer on the HDP oxide layer. Isotropic etching is performed on overhang portions formed on a side of the HDP oxide layer. An HDP capping layer(120) is formed on the liner HDP oxide layer. © KIPO 2008 ...

LOW POWER FLASH MEMORY CELL AND METHOD

Method for fabricating non-volatile memory device having trench isolation

SEMICONDUCTOR DEVICE HAVING SALICIDE LAYERS AND METHOD OF FABRICATING THE SAME

Semiconductor device and manufacturing method

Voids in STI regions for forming bulk FinFETs

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

SEMICONDUCTOR MANUFACUTIRNG METHOD

The device is mfd. including (a) forming a buried layer (2) in a semiconductor substrate; (b) forming a epitaxial layer (3) on the substrate; (c) selectively oxidising the epitaxial layer to form an oxide film (7) except in portions to be active regions and isolation regions; (d) forming a groove extending through the buried layer in isolation regions; (e) covering the groove surface with an insulating film (14); and (e) filling the groove with filler material (15). ADVANTAGE- The structure has dielectric isolation and a flat junction between the substrate and buried layer, reducing pn junction capacitance so avoiding a redn. in device speed and increasing breakdown voltage, esp. for bipolar devices. Copyright 1997 KIPO ...

피치 분할 패터닝 방법

... 본 발명의 실시예는 최소 피치를 초과하는 리소그래피 기술의 기능을 확장시키는 피치 분할 기술을 포함한다. 본 명세서에서 설명되는 피치 분할 기술은 피치 분할된 라인들이 단락 문제점을 방지하기 위해 필요한 공간 절연을 갖는 것을 보장한다. 또한, 본 명세서에서 설명되는 피치 분할 기술은 높은 종횡비 형상의 구조적 견고성을 증가시키는 처리 동작을 사용한다.

METHOD FOR FORMING TRENCH ISOLATION IN SEMICONDUCTOR DEVICE

GAP FILL METHOD OF THE SEMICONDUCTOR DEVICE TO FILLING THE SMALL GAP

PURPOSE: The small gap of the size can completely filled without generating voids in the semiconductor device of 45nm or less. The very small gap of the aspect ratio higher than 10:1 can be filled by performing repetitive evaporation -CMP- etching. CONSTITUTION: The gap fill method of the semiconductor device is provided. The method for filling the gap(220) of the ultra large scale integrated semiconductor device is provided. The first step is for filling a filling material in a gap. The second step is for removing the filling material as the maximum depth and width of the void formed in the gap. The filling of the first step is performed using the high density plasma chemical vapor deposition. © KIPO 2009 ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PURPOSE: To provide a method for manufacturing a semiconductor device, wherein trenches which are formed in a manufacturing process of the semiconductor device and have high aspect ratios can be filled by using a high density plasma(HDP) method. CONSTITUTION: Formation of first silicon oxide films is started on the inner surfaces of the trenches formed on a surface or an upper part of a semiconductor substrate by using the HDP method. Before aperture parts of the trenches are plugged with the first silicon oxide films, formation of the first silicon oxide films is stopped. The first silicon oxide films deposited in the vicinities of the apertures are etched, and second silicon oxide films are formed by using the HDP method on the first silicon oxide films deposited on the bottoms of the trenches. As a result, the first on the second silicon oxide films can be laminated on the bottoms of the trenches. © KIPO & JPO 2003 ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent divot and voids in a trench by forming a groove between the first and second oxide layer using a pull-back process and filling entirely the groove and the trench using the third oxide layer and a gap-fill oxide layer. CONSTITUTION: A multilayer dielectric is formed by depositing sequentially the first oxide layer(11), a nitride layer(13) and the second oxide layer(15) on a semiconductor substrate(10). The substrate is partially exposed by forming an opening portion through the multilayer dielectric. A trench(17) is formed under the opening portion by etching the exposed substrate. A groove(18) is formed by wet-etching the nitride layer of the multilayer dielectric to the lateral direction using a pull-back process. The third oxide layer(21) is formed on the resultant structure including the trench and the groove by using an ALD(Atomic Layer Deposition). Then, a gap-fill oxide layer(23) is entirely filled in ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRENCH ISOLATION

PURPOSE: To provide a method of manufacturing a semiconductor device having the trench isolation which is so improved that a transistor may be operated normally. CONSTITUTION: A resist pattern 104, having openings even on a printing area to form trenches 105 for trench isolation, is formed on a semiconductor wafer 101. Using the resist pattern 104 as a mask, the surface of the semiconductor wafer 101 is etched to form trenches 105 for trench isolation. After removing the resist pattern 104, an oxide film 106 is formed on the semiconductor wafer 101, so as to fill in the trenches 105 for trench isolation. Then, the oxide film 106 is polished by CMP to form the trench isolation 108. © KIPO & JPO 2002 ...

METHOD FOR FORMING SILICON OXIDE FILM, PLASMA PROCESSING APPARATUS AND STORAGE MEDIUM

A silicon oxide film, which has excellent dielectric strength, improves a yield of a semiconductor device and has excellent film quality, is formed without deteriorating merits of plasma oxidation process. Plasma is formed under first processing conditions with an oxygen ratio of 1% or less in a processing gas at a pressure of 133Pa or less, and silicon on the surface of an object to be processed is oxidized by the plasma and the a silicon oxide film is formed (first oxidation process step). Subsequent to the first oxidation process step, plasma is formed under second processing conditions with an oxygen ratio of 20% or more in the processing gas at a pressure of 400-1,333Pa, the surface of the object to be processed is oxidized by the plasma and another silicon oxide film is formed (second oxidation process step). © KIPO & WIPO 2009 ...

OXIDE ETCH WITH NH3-NF3 CHEMISTRY CAPABLE OF ETCHING SELECTIVELY OXIDES ACCORDING TO THE SAME ETCH RATIO

PURPOSE: An oxide etch with NH3-NF3 chemistry is provided to remove uniformly and/or selectively one or more oxides from a surface of a substrate using an etch gas mixture. CONSTITUTION: A loading process is performed to load a substrate(110) into a vacuum chamber(100). A surface of the substrate has a structure including the oxide. A cooling process is performed to cool the substrate to the first temperature. Active species of an etching gas mixture are generated within the vacuum chamber. The etching gas mixture includes a first gas and a second gas. A ratio of the first gas and the second gas is determined by a desired removal rate. An exposure process is performed to expose the structure on the surface of the substrate to the active species to form a film on the structure. A heating process is performed to heat the substrate in order to vaporize the film formed on the structure. A removing process is performed to remove the vaporized film from the vacuum chamber. © KIPO 2008 ...

METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device. © KIPO & WIPO 2007 ...

Method of manufacturing non-volatile memory device

A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate

A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

N-well/p-well strap structures

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Plasma etching apparatus, plasma etching method, and semiconductor device manufacturing method

There is provided a plasma etching apparatus provided for performing an etching in a desirable shape. The plasma etching apparatus includes a processing chamber 12 for performing a plasma process on a target substrate W; a gas supply unit 13 for supplying a plasma processing gas into the processing chamber 12; a supporting table positioned within the processing chamber 12 and configured to support the target substrate thereon; a microwave generator 15 for generating a microwave for plasma excitation; a plasma generation unit for generating plasma within the processing chamber 12 by using the generated microwave; a pressure control unit for controlling a pressure within the processing chamber 12; a bias power supply unit for supplying AC bias power to the supporting table 14; and a control unit for controlling the AC bias power by alternately repeating supply and stop of the AC bias power.

Two silicon-containing precursors for gapfill enhancing dielectric liner

Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

Semiconductor component with isolation trench intersections

A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Method for forming a semiconductor device with stressed trench isolation

A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S 11 ); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S 12 ); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S 13 ); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S 14 ). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Methods of forming fine patterns and methods of fabricating semiconductor devices

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Semiconductor device manufacturing method and semiconductor device

A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.

Stress-generating structure for semiconductor-on-insulator devices

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Insulating region for a semiconductor substrate

An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.

Method for manufacturing a strained channel mos transistor

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Integrated circuit and method of fabricating same

A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

Non-volatile memory and fabricating method thereof

A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Semiconductor device and method for manufacturing the same

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Non-volatile finfet memory array and manufacturing method thereof

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Semiconductor device manufacturing method

In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O( 1 D 2 ) radicals produced using a processing gas that contains oxygen are dominant.

Semiconductor device

A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.

Silicon germanium film formation method and structure

Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

Semiconductor device and method for fabricating the same

A semiconductor device includes a trench formed in a substrate and defining a plurality of active regions, a punch-through prevention layer filling a part of the trench and coupled to a ground, and an isolation layer formed over the punch-through prevention layer and filling the other part of the trench.

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.

Through-silicon via and method for forming the same

A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Method for producing a semiconductor component

Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×10 8 W/cm 2 .

Cross-Point Memory Structures

Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Plasma processing method and device isolation method

A plasma processing method for use in device isolation by shallow trench isolation in which an insulating film is embedded in a trench formed in silicon and the insulating film is planarized to form a device isolation film, the method includes a plasma nitriding the silicon of an inner wall surface of the trench by using a plasma before embedding the insulating film in the trench. The plasma nitriding is performed by using a plasma of a processing gas containing a nitrogen-containing gas under conditions in which a processing pressure ranges from 1.3 Pa to 187 Pa and a ratio of a volumetric flow rate of the nitrogen-containing gas to a volumetric flow rate of the entire processing gas ranges from 1% to 80% such that a silicon nitride film is formed on the inner wall surface of the trench to have a thickness of 1 to 10 nm.

Semiconductor device and method for making same

A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Chemical mechanical polishing process

A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.

Method of Fabricating Isolated Capacitors and Structure Thereof

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.

Semiconductor structure with suppressed sti dishing effect at resistor region

A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.

Method of Protecting STI Structures From Erosion During Processing Operations

Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.

Method of manufacturing semiconductor device

The present invention provides a method of manufacturing a semiconductor device. An insulating-separating portion, which surrounds an electrode penetrating a substrate, is filled with a stacked structure of at least two stages, including a first stage of insulating film and a second stage of insulating film. When at least one of the first and second stages of insulating films has a seam, the seam is stopped by the region in the bottom of the second stage of insulating film that does not have a seam in at least the bottom thereof, thereby increasing mechanical strength. It is possible to prevent the inner region of the insulating-separating portion from being isolated.

Integrated process modulation for psg gapfill

A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.

Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Semiconductor devices structures including an isolation structure

A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.

Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate

A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Countermeasure method and device for protecting data circulating in an electronic microcircuit

The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Semiconductor device and method for making same

A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Integrated circuit device and method for manufacturing same

An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Method for producing a deep trench in a microelectronic component substrate

A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.

Nonvolatile memory device and method of manufacturing the same

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Method of isolating nanowires from a substrate

A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Semiconductor device including an n-well structure

A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.

Discontinuous thin semiconductor wafer surface features

A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other. 144.-. (canceled)45. A semiconductor device comprising , in an active region surrounded by a device isolation portion formed on a main surface of a semiconductor layer on a substrate , a field-effect transistor including:a source region formed along a first direction;a terrace insulating film formed in a periphery of the source region with a predetermined distance away from the source region;a drain region formed along the first direction on both sides of the source region in a second direction that is orthogonal to the first direction via the terrace insulating film; anda gate electrode formed on the main surface of the semiconductor layer between the source region and the drain region via a gate insulating film so as to partially override the terrace insulating film,wherein, in an outermost periphery of the active region, a semiconductor region is formed on the semiconductor layer between the terrace insulating film and the device isolation portion in the first direction and between the terrace insulating film and the device isolation portion in the second direction,wherein the device isolation portion and the terrace insulating film are isolated from each other,wherein the terrace insulating film is formed by LOCOS, andwherein the device isolation portion is formed by STI which includes an insulating film embedded in a groove formed in the semiconductor layer.46. The ...

3-d nonvolatile memory device and method of manufacturing the same

A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

Semiconductor Device and Method of Manufacture

A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

FLASH MEMORY CELL WITH FLAIR GATE

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. 120.-. (canceled)21. A method of forming a memory cell , the method comprising:etching a trench in a substrate;filling the trench with an oxide to form a shallow trench isolation (STI) region, wherein a portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge;forming a gate structure over the active region of the substrate and over the STI region wherein the gate structure comprises a charge trapping layer; andforming a wordline structure having first and second widths and having portions of the wordline structure of the first width centered above a bit line and portions of the wordline structure of the second width centered above the STI region and formed to extend across the STI region over the bitline-STI edge, wherein the second width is greater than the first width and wherein portions of adjacent wordline structures of the second width extend across separate portions of the same bitline.22. The method as recited in wherein said forming of the gate structure comprises:forming a preliminary gate structure over the substrate;applying a mask over the memory cell, wherein the mask has the first width substantially over the center of the active region of the substrate and the second width substantially over the bitline-STI edge; andetching the ...

Method of making lower parasitic capacitance finfet

An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

STRUCTURE FOR PICKING UP A BURIED LAYER AND METHOD THEREOF

A structure for picking up a buried layer is disclosed. The buried layer is formed in a substrate and has an epitaxial layer formed thereon. One or more isolation regions are formed in the epitaxial layer. The structure for picking up the buried layer includes a contact-hole electrode formed in each of the isolation regions. A bottom of the contact-hole electrode is in contact with the buried layer. As the structure of the present invention is formed in the isolation region without occupying any portion of the active region, its size is much smaller than that of a sinker region of the prior art. Therefore, device area is tremendously reduced. Moreover, as the contact-hole electrode picks up the buried layer by a metal contact, the series resistance of the device can be greatly reduced. A method of forming the above structure is also disclosed. 1. A structure for picking up a buried layer , the buried layer being formed in a substrate and having an epitaxial layer formed thereon , the epitaxial layer having one or more isolation regions formed therein , the structure comprising a contact-hole electrode formed in each of the isolation regions , a bottom of the contact-hole electrode being in contact with the buried layer.2. The structure according to claim 1 , wherein the contact-hole electrode is formed of tungsten.3. The structure according to claim 2 , wherein the contact-hole electrode further comprises a titanium and/or titanium nitride barrier layer formed on its bottom.4. The structure according to claim 1 , wherein the buried layer has a doping concentration of higher than 1×10atoms/cm.5. A method of forming the structure for picking up a buried layer according to claim 1 , comprising:forming a doped region in a substrate by performing an ion implantation process;growing a single crystal silicon epitaxial layer on the doped region via an epitaxial process such that the doped region becomes a buried layer;forming one or more isolation regions in the epitaxial ...

BORON-CONTAINING HYDROGEN SILSESQUIOXANE POLYMER, INTEGRATED CIRCUIT DEVICE FORMED USING THE SAME, AND ASSOCIATED METHODS

A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is trivalent, wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween. 1. A composition , comprising: a boron-containing hydrogen silsesquioxane polymer having a structure that includes:', 'silicon-oxygen-silicon units, and', 'oxygen-boron-oxygen linkages in which the boron is trivalent,', 'wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween, and the boron-containing hydrogen silsesquioxane polymer has a cage structure or a partial cage structure., 'a base generator; and'}2. The composition as claimed in claim 1 , wherein boron is present in the boron-containing hydrogen silsesquioxane polymer in an amount of about 0.5 to about 5 mol %.3. (canceled)4. The composition as claimed in claim 1 , wherein the boron-containing hydrogen silsesquioxane polymer is substantially free of carbon.5. The composition as claimed in claim 1 , wherein the boron-containing hydrogen silsesquioxane polymer is substantially free of nitrogen.6. The composition as claimed in claim 1 , further comprising a solvent.7. A method of fabricating an integrated circuit claim 1 , the method comprising:providing a substrate for the integrated circuit;{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'coating the composition of on the substrate; and'}after coating the composition on the substrate, curing the composition.8. The method as claimed in claim 7 , wherein the curing the composition includes heating the substrate having the composition thereon in an oxidizing atmosphere.9. The method as claimed in claim 7 , wherein the curing the composition includes heating the substrate having the composition thereon in an inert atmosphere.10. The method as claimed in claim 7 , wherein the curing the composition ...

Reverse Tone STI Formation

A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Method for forming high mobility channels in iii-v family channel devices

Provided is a method of fabricating a semiconductor device. The method includes forming a buffer layer over a surface of a silicon substrate. The method further includes forming openings that extend into the buffer layer. The method includes forming a shallow trench isolation (STI) structures in each of the openings. The method includes removing a predetermined amount of a top surface of the buffer layer relative to a top surface of the STI structures. The method includes forming an insulator layer over the top surface of the buffer layer and forming a channel layer over the insulator layer.

Forming Structures on Resistive Substrates

A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. 1. A semiconductor device comprising:a semiconductor substrate including a base, an insulating layer on the base, and a semiconductor layer on the insulating layer;a semiconductor element formed to the semiconductor layer; andan isolation film buried in a groove formed in the semiconductor layer and the insulating layer in an isolation region,wherein an oxidation resistant film is interposed between the insulating layer and the isolation film.2. The semiconductor device according to claim 1 , wherein the insulating layer and the isolation film each include a silicon oxide film.3. The semiconductor device according to claim 2 ,wherein the oxidation resistant film includes a silicon nitride film.4. The semiconductor device according to claim 1 ,wherein a portion of the semiconductor layer is directly in contact with the isolation film.5. The semiconductor device claim 1 ,wherein the insulating layer is set back from a side surface of the groove, andthe oxidation resistant film is interposed between the insulating layer being set back and the isolation film, and also sandwiched by the semiconductor layer and the base from the top and bottom.6. The semiconductor device according to ...

Semiconductor device and integrated circuit with high-k/metal gate without high-k direct contact with sti

A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.

Integrated Circuit and IC Manufacturing Method

Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed. 1. An integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures , a plurality of serially connected polysilicon resistors carried by at least some of the isolation structures , wherein the respective portions of the active substrate underneath the isolation structures carrying said polysilicon resistors are electrically insulated from said components.2. (canceled)3. (canceled)4. (canceled)5. The integrated circuit die of any of claim 1 , wherein the active substrate is formed on an electrically insulating layer.6. The integrated circuit die of any of claim 1 , wherein each of the isolation structures carrying a further component is surrounded by an electrically insulating guard ring extending through the active substrate.7. The integrated circuit die of claim 6 , wherein the guard ring is a medium trench isolation structure.8. The integrated circuit die of claim 1 , wherein the respective portions of the active substrate are connected to ground.9. The integrated circuit die of claim 1 , wherein the active substrate further comprises a contact terminal claim 1 , said contact terminal being electrically insulated from said respective portions.10. An electronic device comprising the integrated circuit die of .11. A method of manufacturing an integrated circuit die claim 1 , comprising:providing a carrier;forming an active substrate on said carrier;forming a plurality of isolation structures in ...

Method and system for fabricating edge termination structures in gan materials

A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Integrated Nanostructure-Based Non-Volatile Memory Fabrication

Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask. 1. A method of manufacturing a semiconductor device , the method comprising:forming an isolation portion in a groove of a substrate;forming a projection portion in which an upper portion of the isolation portion projects from a surface of the substrate;forming a sidewall spacer covering a side surface of the projection portion and part of the surface of the substrate along the side surface of the projection portion; andforming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask.2. A method of manufacturing a semiconductor device , the method comprising:forming isolation portions in grooves of a substrate;forming at least a pair of projection portions in which upper portions of the isolation portions project from a surface of the substrate;forming sidewall spacers covering side surfaces of the projection portions and part of the surface of the substrate along the side surfaces of the projection portions; andforming a first trench in the substrate by etching the substrate using the sidewall spacers as a mask,wherein the forming of the sidewall spacers includes forming a window to expose the surface of the substrate between the sidewall spacers of the at least the pair of projection portions facing each other.3. A method of manufacturing a semiconductor device , the method comprising:forming isolation portions in grooves of a substrate;forming at least a pair of projection portions in ...

STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region. 1. A semiconductor structure comprising:a semiconductor-on-insulator (SOI) substrate including a handle substrate, at least one buried insulator portion abutting said handle substrate, and at least one top semiconductor portion abutting said at least one buried insulator portion;a trench extending from a top surface of said at least one top semiconductor portion to a depth below a top surface of said at least one buried insulator portion; anda stack of an insulator stressor plug and a silicon oxide plug located in said trench, wherein said insulator stressor plug abuts a bottom surface of said trench and said silicon oxide plug is substantially coplanar with said top surface of said at least one top semiconductor portion, wherein an interface between said insulator stressor plug and said silicon oxide plug is located between a top surface of said at least one buried insulator portion and said bottom surface of said at least one buried insulator portion, or at said bottom surface of said at least one buried insulator portion, or the interface between said insulator ...

METHOD FOR FABRICATING AN ISOLATION STRUCTURE

A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. 1. A method of fabricating an isolation structure , the method comprising:forming a trench in a top surface of a substrate; forming a liner layer in the trench;', 'forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C.;, 'partially filling the trench with a first oxide, wherein the first oxide is a pure oxide, and partially filling the trench comprisesproducing a solid reaction product in a top portion of the first oxide;sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C.;removing the sublimated solid reaction product by flowing a carrier gas over the substrate; andfilling the trench with a second oxide.2. The method of claim 1 , further comprising increasing a density of the first oxide.3. The method of claim 2 , wherein increasing the density of the first oxide comprises annealing the first oxide at a temperature of about 1000° C. in an environment containing nitrogen gas or an inert gas.4. The method of claim ...

METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS AND ELECTRONIC EQUIPMENT

In the method of manufacturing a semiconductor apparatus of the present invention, after forming trench isolation regions , and on a surface of a semiconductor substrate so as to isolate element regions on which the semiconductor elements are to be formed, a silicon nitride film (antioxidant film) is formed so as to cover the trench isolation regions and to stick out from the trench isolation regions with partially overlapping element regions adjacent to the trench isolation regions, and a thermal oxide film that is thicker than a thermal oxide film required in a semiconductor element of a predetermined size among a plurality of semiconductor elements, is formed on the element region using the antioxidant film as a mask. 110-. (canceled)11. A method of manufacturing a semiconductor apparatus in which a plurality of semiconductor elements formed on a semiconductor substrate are isolated by a trench isolation region , comprising:forming a trench isolation groove on a surface of the semiconductor substrate so as to isolate element regions on which the semiconductor elements are to be formed;embedding a dielectric material in the trench isolation groove to form the trench isolation region;selectively forming an antioxidant film on the surface of the semiconductor substrate so as to cover the trench isolation region; andforming a thick thermal oxide film that is thicker than a thickness of a thermal oxide film required in a semiconductor element of a predetermined size other than the maximum size among the plurality of semiconductor elements in an element region of the semiconductor element of the predetermined size, with the antioxidant film as a mask.12. A method of manufacturing a semiconductor apparatus according to claim 11 , whereinthe semiconductor apparatus comprises a high voltage semiconductor element that operate at a high voltage and a low voltage semiconductor element that operates at a low voltage as the plurality of semiconductor elements,the low voltage ...

Method of fabricating memory device

A method of fabricating a memory device comprises forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.

TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION

Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench. 1. A method , comprising:(a) forming a trench in a silicon region of a substrate, said silicon region adjacent to a top surface of said substrate, said trench extending from said top surface of said substrate into said silicon region;(b) forming a stopping layer on sidewalls and a bottom of said trench;(c) removing said stopping layer from said bottom of said trench;(d) filling remaining space in said trench with a dielectric fill material, said dielectric fill material not including any materials found in said stopping layer;(e) performing an N-type ion implantation on a first side of said trench into a first region of said silicon region abutting said first side of said trench and into a first region of said dielectric material abutting said stopping layer on said first side of said trench; and(f) performing a P-type ion implantation on an second side of said trench into a second region of said silicon region abutting said second side of said trench and into a second region of said dielectric material abutting said stopping layer on said second side of said trench, said second side of said trench opposite said ...

Sram integrated circuits and methods for their fabrication

SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

METHOD FOR FORMING ISOLATION STRUCTURE

[Problem] To provide a method for forming an isolation structure having a low shrinkage percentage and a low tensile stress. 1. A method for forming an isolation structure , comprisinga coating step, in which a first polysilazane composition containing a porogen is cast on the surface of a substrate to form a coat;a first firing step, in which said coat is fired to form a porous siliceous film having a refractive index of 1.35 or less;an impregnating step, in which said porous siliceous film is impregnated with a second polysilazane composition; anda second firing step, in which said porous siliceous film is fired to form an isolation structure of a siliceous film having a refractive index of 1.4 or more;whereinat least one of the first and second firing steps is carried out in an inert gas or oxygen atmosphere containing water vapor.2. The method according to claim 1 , wherein said first and second polysilazane compositions contain perhydropoly-silazane.3. The method according to claim 1 , wherein said porogen is polyaminosilazane.4. The method according to claim 1 , wherein both or either of the first and second firing steps are carried out in an inert gas or oxygen atmosphere containing water vapor.5. The method according to claim 1 , wherein at least one of the first and second firing steps is carried out at a temperature of 200 to 1000° C.6. The method according to claim 1 , wherein said substrate has a surface provided with grooves in which the isolation structure of the siliceous film is formed to form a shallow trench isolation structure.7. An insulating film formed by the method according to .8. A substrate provided with an isolation structure formed by the method according to .9. The method according to claim 2 , wherein said porogen is polyaminosilazane.10. The method according to claim 2 , wherein both or either of the first and second firing steps are carried out in an inert gas or oxygen atmosphere containing water vapor.11. The method according to ...

Methods for fabricating semiconductor devices with isolation regions having uniform stepheights

Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.

Fabricating method of non-volatile memory

A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.

Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing

Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.

Method of Manufacturing a Semiconductor Device

Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME

A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved. 1. A trench isolation structure , comprising:a semiconductor substrate; andtrenches, which are formed on the semiconductor substrate and filled with a dielectric layer, wherein,the material of the dielectric layer is a crystalline material.2. The trench isolation structure according to claim 1 , wherein the semiconductor substrate is a silicon substrate claim 1 , a silicon-germanium substrate claim 1 , a III-V compound substrate claim 1 , a silicon carbide substrate claim 1 , a silicon-on-insulator structure claim 1 , a diamond substrate claim 1 , or a multi-layer structure comprising any one or more layers selected from the group consisted of a silicon layer claim 1 , a silicon-germanium layer claim 1 , a III-V compound layer claim 1 , and a silicon carbide layer.3. The trench isolation structure according to claim 1 , wherein the material of the dielectric layer is crystalline gadolinium oxide or crystalline neodymium oxide.4. The trench isolation structure according to claim 1 , wherein the dielectric layer is ion-doped such that the dielectric layer has a lattice constant larger or smaller than a lattice constant of the semiconductor substrate.5. The trench isolation structure according to claim 4 , wherein a P-type Metal Oxide Semiconductor (PMOS) transistor is formed on the semiconductor substrate between the trenches claim 4 , the trenches are on respective sides of the PMOS transistor in the channel length direction claim 4 , and the lattice constant of the dielectric layer is larger than the lattice constant of the semiconductor ...

Semiconductor device, wafer assembly and methods of manufacturing wafer assemblies and semiconductor devices

A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls.

Semiconductor device having vertical channels and method of manufacturing the same

A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Integrated circuit structure having air-gap trench isolation and related design structure

A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring. 1. A method of fabricating a semiconductor device , comprising:patterning a substrate to form a plurality of line-shaped first grooves extending along a first direction and active lines protruding from the substrate to delimit sidewalls of the first grooves;forming first device isolation layers to fill the first grooves;forming a plurality of line-shaped first mask patterns extending along a second direction on the substrate, the first and second directions crossing each other;etching the first device isolation layers and the active lines using the first mask patterns as an etch mask to form a plurality of second grooves;removing portions of the active lines exposed by the second grooves and spaced apart from each other to form bar-shaped active portions and first holes therebetween, the removing portions of the active lines exposing sidewalls of the first device isolation layers and extending along the first direction;forming second device isolation layers to fill at least portions of the first holes; andforming word lines in the second grooves.2. The method of claim 1 , further comprising:recessing a portion of the first device isolation layers at bottoms of the second grooves to expose sidewalls of the active lines.3. The method of claim 1 , wherein the forming of the active portions and the first hole comprises:conformally forming an etch stop layer on the structure, in which the second grooves are formed;forming a second mask pattern with second holes on the etch stop layer, the second holes overlapped with the first holes to expose the etch stop layer;performing an anisotropic ...

INTRENCH PROFILE

A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. 1. A method of etching a recess in a semiconductor substrate , the method comprising:forming a dielectric liner layer in a trench of the substrate, wherein the liner layer has a first density;depositing a second dielectric layer at least partially in the trench on the liner layer, wherein the second dielectric layer is initially flowable following the deposition, and wherein the second dielectric layer has a second density that is less than the first density of the liner layer;exposing the substrate to dry etchant, wherein the etchant removes a portion of the first liner layer and the second dielectric layer to form the recess, wherein the dry etchant comprises a fluorine-containing compound and molecular hydrogen, and wherein an etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.2. The method of claim 1 , wherein the first dielectric liner layer comprises a high-density plasma formed silicon oxide layer.3. The method of claim 1 , wherein the second dielectric layer comprises a silicon oxide layer deposited by FCVD.4. ...

Structure and method for finfet integrated with capacitor

The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T 1 and a second portion disposed in the second region and having a second thickness T 2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.

Method of manufacturing semiconductor device

According to one embodiment, the method of manufacturing a semiconductor device includes contacting a film formed on a semiconductor substrate with a rotating polishing pad which is supported on a turntable, and feeding polishing foam to a region of the polishing pad with which the film is contacted, thereby polishing the film. The polishing foam is obtained by turning the aqueous dispersion into a foamy body. The aqueous dispersion includes 0.01-20% by mass of abrasive grain and 0.01-1% by mass of foam forming and retaining agent, all based on a total mass of the aqueous dispersion.

Methods of Forming Semiconductor Devices

In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE

A diode () is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes () are formed on the sidewalls () of a mesa region (). The mesa region () is a cathode of the Schottky diode (). The current path through the mesa region () has a lateral and a vertical current path. The diode () further comprises a MOS structure (), p-type regions (), MOS structures (), and p-type regions (). MOS structure () with the p-type regions () pinch-off the lateral current path under reverse bias conditions. P-type regions (), MOS structures (), and p-type regions () each pinch-off the vertical current path under reverse bias conditions. MOS structure () and MOS structures () reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region () can have a uniform or non-uniform doping concentration. 114-. (canceled)15. A method of forming a semiconductor device comprising the steps of:forming more than one trench to a first depth in a semiconductor substrate to form at least one mesa region of a first conductivity type;placing dopant of a second conductivity type into a sidewall of the at least one mesa region to form a first region of the second conductivity type, where the dopant is located a first predetermined distance below a major surface of the at least one mesa region;forming a barrier metal overlying a portion of the sidewall of the at least one mesa region to form a Schottky diode; andforming a MOS structure overlying the major surface of the at least one mesa region, where the gate of the MOS structure is coupled to the barrier metal.16. The method of further including the steps of:forming an insulating layer overlying the major surface of the at least one mesa region;forming an insulating layer overlying sidewalls of the at least one mesa region to a first depth;exposing major surfaces of the more than one trench;forming the more than one trench to a second depth;forming an ...

SHALLOW TRENCH FORMING METHOD

A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiOlayer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiOlayer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiOlayer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiOlayer; depositing a second silicon nitride layer and filling the trench with SiO; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed. 1. A method for forming a trench filled with an insulator in a wafer comprising a silicon support coated with a first silicon oxide layer and with a single-crystal silicon layer , the trench crossing the silicon and silicon oxide layers and penetrating into the support , this method comprising the steps of:forming on the silicon layer a second silicon oxide layer and a first silicon nitride layer, masking and etching to form the trench while leaving in place the second oxide layer and the first nitride layer outside of the trench, and performing a first oxidizing processing to form a third silicon oxide layer on the exposed silicon surfaces;performing a second oxidizing processing in the presence of an oxygen plasma to form on the exposed surfaces of the first silicon nitride layer a fourth silicon oxide layer;depositing a second silicon nitride layer and filling the trench with silicon oxide; andremoving the upper portion of the structure until the upper surface of the silicon layer is exposed.2. The method of claim 1 , wherein the step of removal of the upper portion of the structure comprises the steps of:removing by chem.-mech. etching the portions of layers formed above the first silicon nitride layer;removing by selective wet etching the first silicon nitride layer; and{'b': '20', 'removing by ...

CORNER TRANSISTOR SUPPRESSION

The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners. 1. A method comprising:forming a trench, having side surfaces and a bottom surface, in a substrate;forming an oxide liner on the side surfaces and bottom surface of the trench; andforming a layer of high-K dielectric material on the oxide liner.2. The method according to claim 1 , comprising forming the trench by reactive ion etching (RIE).3. The method according to claim 1 , comprising forming the trench to a width of 500 to 1000 and a depth of 1500 Å to 4000 Å.4. The method according to claim 1 , comprising forming the oxide liner to a thickness of 10 Å to 40 Å.5. The method according to claim 1 , comprising forming the high-K dielectric layer to a thickness of 20 Å to 80 Å.6. The method according to claim 1 , further comprising filling the trench with an insulating material.7. The method according to claim 6 , comprising filling the trench by a high aspect ratio process.8. The method according to claim 1 , wherein the substrate comprises a semiconductor material claim 1 , the method further comprising:forming a pad oxide layer on an upper surface of the substrate; andforming a pad nitride layer on the pad oxide layer, both prior to forming the trench in the substrate; andforming the layer of high-K dielectric material on an upper surface of the pad nitride layer and on side surfaces of the pad oxide and pad nitride layers concurrently with forming the layer of high-K dielectric material on the oxide liner.9. The method according to claim 8 , comprising:forming the pad ...

Memory device and method for manufacturing memory device

A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area that comprises source and drain regions. The first and second trench isolations extend parallel to each other. The plurality of line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area. The first word line is formed in the substrate and adjacent to the first trench isolation. The first word line defines a first segment of the active area with the first trench isolation. The second word line extends across the active area. The second word line is formed in the substrate and adjacent to the second trench isolation. The second word line defines a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.

METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES

Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. 1. A method for fabricating a semiconductor device , the method comprising:forming at least two trenches in a substrate through apertures defined in a mask material overlying the substrate;forming a dielectric material in the at least two trenches;defining another aperture in the material to expose a region of the substrate, the region disposed between two of the at least two trenches; andforming a recess in the region of the substrate.2. The method of claim 1 , wherein:forming at least two trenches in a substrate through apertures defined in a material overlying the substrate comprises forming the at least two trenches in the substrate through the apertures defined in a mask overlying the substrate; andforming a recess in the region of the substrate comprises utilizing portions of the dielectric material as another mask to selectively etch the mask and the region of the substrate.3. The method of claim 2 , further comprising removing portions of the dielectric material in the at least two trenches to recess the dielectric material in the at least two trenches relative to a lower recess surface of the recess in the region of the substrate.4. The method of claim 1 , wherein forming the at least two trenches ...

METHOD FOR PRODUCING SILICON DIOXIDE FILM

[Problem] To provide a method capable of forming an insulating film suffering less from both shrinkage and stress. 1. A method for forming a silicon dioxide film , comprising(A) a coating step, in which a substrate is coated with a polysilazane composition to form a coat; and(B) an oxidation step, in which the coat is oxidized in a hydrogen peroxide atmosphere at a temperature of 50 to 200° C.2. The method according to for forming a silicon dioxide film claim 1 , wherein the oxidation step is carried out at a temperature of 100 to 200° C.3. The method according to for forming a silicon dioxide film claim 1 , wherein the hydrogen peroxide atmosphere contains 5 to 50 mol % of hydrogen peroxide in the oxidation step.4. The method according to for forming a silicon dioxide film claim 1 , wherein the hydrogen peroxide atmosphere contains 5 to 50 mol % of water vapor in the oxidation step.5. The method according to for forming a silicon dioxide film claim 1 , wherein the heating time ranges from 0.5 to 60 minutes in the oxidation step.6. The method according to for forming a silicon dioxide film claim 1 , further comprisinga step of removing the solvent after the coating step and before the oxidation step.7. The method according to for forming a silicon dioxide film claim 1 , furthermore comprisinga step of oxidation with water vapor, in which the coat is heated in a water vapor atmosphere at a temperature of 300 to 1000° C. after the oxidation step.8. The method according to for forming a silicon dioxide film claim 1 , wherein the polysilazane composition contains solid content in an amount of 1 to 40 wt % based on the total weight of the composition.9. The method according to for forming a silicon dioxide film claim 1 , wherein the coat formed in the coating step has a thickness of 5 to 10000 nm.10. The method according to for forming a silicon dioxide film claim 1 , wherein the substrate is made of plastics.11. A method for forming an isolation structure; wherein the ...

Fully Isolated LIGBT and Methods for Forming the Same

A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

Semiconductor device and method of fabricating the same

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Process for fabricating an integrated circuit having trench isolations with different depths

A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer. 1. A process for fabricating an integrated circuit , said process comprising , in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer , etching first trenches into said silicon substrate , depositing a silicon nitride layer on said silicon layer so as to fill said first trenches and form first trench isolations , forming a mask on said silicon nitride layer , etching second trenches into said silicon substrate , in a pattern defined by said mask , to a depth greater than a depth of said first trenches , filling said second trenches with an electrical insulator so as to form second trench isolations , carrying out a chemical etch until said silicon layer is exposed , and forming a field-effect transistor by forming a channel , a source , and a drain of said field effect transistor in said silicon layer.2. The process of claim 1 , wherein said buried insulating layer overlaid with said silicon layer is between 10 nanometers and 50 nanometers in thickness.3. The process of claim 1 , wherein said buried insulating layer is made of silicon oxide.4. The process of claim 1 , wherein etching first trenches comprises ...

METHOD FOR FORMING INSULATING FILM

[Problem] To provide a method capable of forming an insulating film having homogeneous and high bulk density and less suffering defects. 1. A method for forming an insulating film , comprising(1) a step of coating with silicon dioxide fine particles, in which a substrate is coated with a silicon dioxide dispersion containing silicon dioxide fine particles, a polymer, a surfactant and a dispersion medium;(2) a step of coating with polysilazane, in which the substrate surface coated with the silicon dioxide dispersion is further coated with a polysilazane composition; and(3) step of heating, in which the substrate coated with the polysilazane composition is heated, so as to covert the polysilazane into silicon dioxide and thereby to form an insulating film made of the silicon dioxide fine particles and the silicon dioxide derived from the polysilazane.2. The method according to for forming an insulating film claim 1 , wherein the step of heating is carried out at a temperature of 200 to 1500° C.3. The method according to for forming an insulating film claim 1 , wherein the step of heating is carried out in an atmosphere containing water vapor.4. The method according to for forming an insulating film claim 1 , wherein the weight ratio between the silicon contained in the coated silicon dioxide dispersion and that in the coated polysilazane composition is in the range of 1:15 to 6:1 per unit area of the substrate.5. The method according to for forming an insulating film claim 1 , further comprisinga step of additional heating, in which the substrate is further heated in an inert gas atmosphere after the step of heating.6. The method according to for forming an insulating film claim 1 , furthermore comprisinga step of preliminary heating, in which the substrate is heated to evaporate at least a part of the dispersion medium after the step of coating with silicon dioxide fine particles and before the step of coating with polysilazane.7. The method according to for forming ...

SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT

A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench. 1. A method for producing a semiconductor component , comprising:providing a semiconductor body,producing at least one protective trench in the semiconductor body,producing an insulation layer on the sidewalls and at the bottom of the protective trench,producing an electrically conductive layer having a thickness D on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.2. The method according to claim 1 , wherein the protective trench is produced together with a cell trench in the semiconductor body.3. The method according to claim 1 , wherein the electrically conductive layer is produced in such a way that at least one partial region of the layer surface runs parallel to a main surface of the semiconductor body.4. The method according to claim 1 , wherein the electrically conductive layer is provided with a dopant at least locally.5. The method according to claim 4 , wherein the dopant is implanted into the layer and subsequently activated.6. The method according to claim 1 , wherein the electrically conductive layer is firstly at least also partly produced on a main surface of the semiconductor body and the layer on the main surface of the semiconductor body is subsequently removed again.7. The method according to claim 6 , wherein the removal of the electrically conductive layer on the main surface is effected by means of chemical mechanical polishing.8. The method according to claim 1 , wherein a protective layer is at least partly applied on the electrically conductive layer in the protective ...

Method of semiconductor integrated circuit fabrication

A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

SEMICONDUCTOR COMPONENT WITH VERTICAL STRUCTURES HAVING A HIGH ASPECT RATIO AND METHOD

A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric. 1. A method for producing a semiconductor component comprising:providing a semiconductor body having a first side, into which a trench extends proceeding from the first side;conformally depositing at least one semiconductor layer at least on the sidewalls of the trench; andproducing a dielectric layer on the semiconductor layer in a trench remaining after the production of the semiconductor layer.2. The method of claim 1 , comprising producing the semiconductor layer such that it has a varying doping.3. The method of claim 2 , comprising forming the at least one semiconductor layer such that a doping concentration of the semiconductor layer changes continuously in a direction of the dielectric layer until an extremum is reached claim 2 , wherein the extremum is reached at a distance from the dielectric layer claim 2 , and changes continuously in a direction of the dielectric layer proceeding from the extremum.5. The method of claim 1 , comprising forming the at least one semiconductor layer with a doping that is complementary to a doping of the semiconductor body along sidewalls of the trench.6. The method of claim 1 , comprising producing the semiconductor layer such that it has a varying material composition.7. The method of claim 1 , comprising composing the semiconductor layer at least partly of silicon-germanium.8. The method of claim 7 , comprising forming the at least one semiconductor layer such that a germanium content decreases in a direction of the dielectric layer.9. The method of claim ...

METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE

A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate. 1. A method , comprising:forming a plurality of nanowires on a top surface of a substrate; andforming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.2. The method of claim 1 , wherein forming the oxide layer comprises:forming a plurality of silicon fins on the substrate; andselectively oxidizing each of the plurality of silicon fins formed on the substrate.3. The method of claim 2 , wherein forming the plurality of nanowires comprises condensing an epitaxially grown silicon germanium layer disposed on a top surface of each of the plurality of silicon fins.4. The method of claim 3 , wherein the plurality of nanowires comprise germanium.5. The method of claim 2 , further comprising:forming a plurality of trenches adjacent to each of the plurality of fins; anddepositing a trench oxide layer within each of the plurality of trenches.6. The method of claim 5 , further comprising:selectively etching portions of the trench oxide layer to expose each of the plurality of fins; anddisposing a nitride spacer on a top surface of each of the exposed fins.7. The method of claim 6 , further comprising:etching portions of the trench oxide layer adjacent to a bottom surface of the nitride spacer to form exposed portions of silicon; andoxidizing the exposed portions of silicon to form the oxide layer.8. The method of claim 7 , further comprising removing the nitride spacer to form the oxide layer adjacent to the bottom surface of each of the plurality of nanowires.9. A device claim 7 , comprising:a substrate;a plurality of nanowires disposed on a top surface of the ...