VERFAHREN ZUR HERSTELLUNG VON MONOLITHISCH INTEGRIERTEN HALBLEITERSCHALTUNGEN MIT DURCH IONENBOMBARDEMENT HERVORGERUFENEN DIELEKTRISCHEN ISOLATIONSZONEN

Semiconductor circuit appts. for high power and high frequency module

The semiconductor substrate (101) includes two doped regions (104,105) and a control electrode device (106). The two doped regions form the source and drain of a power transistor. The regions lie in an active region surrounded by an insulation structure (102,1012) adjacent to a substrate main surface (103). A current flow between the two doped regions is controllable via the control electrode device. The electrode device is provided with several control electrode elements (1061), e.g. Schottky contact or MOS-gate, which extend orthogonally to the main surface and from it up to the insulation structure. They are next to each other such that the current flow between the two doped regions takes place between adjacent electrode elements.

HERSTELLUNGSVERFAHREN EINES SOI SUBSTRATS

Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer

Methods of preventing bending of SOI layer during trench refill

Shallow trenches (STI) isolate active regions of a silicon on insulator (SOI) device. The trenches extend down to the underlying insulating layer 11, and are refilled with a CVD oxide. Diffusion of oxygen atoms along the interface between the silicon layer 23' and the insulating layer 11 is prevented during the refill process, thereby preventing a birds beak effect which would cause the active silicon layer to bend 24 at the edges of the trench. The diffusion of oxygen atoms along the silicon/insulator interface may be prevented by, prior to the oxide refill process, forming a nitrogen implant region at in the interface, at least in the region of the trench. Alternatively, an amorphous silicon layer, or a rapid thermal oxide layer may be formed on the sidewalls of the trench as a diffusion blocking layer.

Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers

INTEGRATED CIRCUIT

... 1442726 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 20 Feb 1974 [12 March 1973] 7649/74 Heading H1K Dielectric isolation between device-containing Si pockets of an integrated circuit is provided by a dielectric-surfaced substrate 42 supporting the Si layer from which the pockets are formed and by regions 51 of SiO 2 extending through the layer and laterally surrounding the pockets. The SiO 2 regions 51 are formed by selective oxidation of the Si layer before the substrate is applied and while the layer is still located on a subseuqently-removed body of highly conductive Si, the upper surface of the regions 51 being arranged to be substantially coplanar with the surface of pockets by the selective removal of part of the thickness of the to-beoxidized regions of the Si layer prior to oxidation. After application of the substrate 42 the highly conductive Si body is removed by preferential anodic etching, and devices are formed in the pockets, e.g. by diffusion. The substrate may ...

Substrate for integrated circuit and forming method thereof

A substrate for an integrated circuit and a forming method thereof are provided. The method includes forming a hard mask layer on a bulk silicon material (1); etching the hard mask layer and the bulk silicon material to form first parts of trenches (4); forming a dielectric film on sidewalls of the trenches; etching the bulk silicon material further, so as to deepen the trenches and form second parts of the trenches; completely oxidizing or nitridizing the bulk silicon material parts positioned between the second parts of trenches and between the second parts of the trenches and the exterior of the bulk silicon substrate; filling the first parts and the second parts of the trenches with dielectric materials (5); and removing the hard mask layer, wherein, the first parts of the trenches is used for achieving shallow trench isolation.

NOTCH-FREE CORRODING OF SOI STRUCTURES WITH HIGH ASPECT RATIO BY USE OF A TEMPORALLY GEMULTIPLEXTEN PROCESS AND HF-VORMODULATION

ON SOI DISKS MANUFACTURE SEMICONDUCTOR ARRANGEMENTS.

CMOS COMPATIBLE SOI PROCESS

TRENCH INSULATION IN SUBSTRATE DISKS COMPRISING LOGIC SEMICONDUCTORS AND POWER SEMICONDUCTORS

METHOD FOR LIMITING DIVOT FORMATION IN POST SHALLOW TRENCH ISOLATION PROCESSES

SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY TRANSISTOR STRUCTURES AND METHOD OF MANUFACTURING SAME

TOTAL DIELECTRIC ISOLATION

METHOD OF JOINING SEMICONDUCTOR SUBSTRATES

SUB-MICRON BONDED SOI BY TRENCH PLANARIZATION

A silicon on insulator substrate 8 provides islands of silicon 18 of uniform thickness by using a trench etch process and a silicon nitride layer 20 to provide a thickness control and polish stop for the silicon islands 18.

SOI SUBSTRATE FABRICATION

A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etchstop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried ...

Substrate processing method and substrate processing apparatus

Bipolar transistor

Device structure for silicon-on-insulator substrate with high-resistance operation wafer

SEMICONDUCTOR DEVICE ON SOI SUBSTRATE AND METHOD OF MANUFACTURE

SEMICONDUCTOR DEVICE WITH STRUCTURES OF TRANSISTOR COMPLEMENTARY AND PROCEEDED FOR THE MANUFACTURE OF THIS DEVICE

TRANSISTOR AND MANUFACTORING PROCESS

INTEGRATED CIRCUIT

PROCEDE D'ISOLATION PAR DIELECTRIQUE DE STRUCTURES SEMI-CONDUCTRICES ET STRUCTURES EN RESULTANT

Procédé d'isolation par diélectrique de structures semi-conductrices et structures en résultant Un substrat silicium 10 de type P**- est successivement recouvert par une couche de type P** + 12 et N**- 14. On forme une configuration d'ouvertures selon une configuration désirée 18 grâce à une couche de masquage appropriée. On transforme la couche 12 de silicium en une couche de silicium poreux dans un bain anodique, puis on oxyde la structure. La région 12 se transforme totalement en oxyde tandis que les ouvertures 18 se remplissent également d'oxyde et que la surface de la couche supérieure s'oxyde simultanément. On définit ainsi des poches de silicium isolées totalement par diélectrique. Application à la fabrication des dispositifs intégrés à semi-conducteurs, notamment bipolaires.

MANUFACTORING PROCESS Of a SEMICONDUCTOR DEVICE

MANUFACTORING PROCESS Of a SUBSTRATE OF the INSULATING TYPE SUBSTRAT-SUR- OUSUBSTRAT-SUR-VIDE AND DEVICE OBTAINED

FABRICATION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP

A METHOD FOR PREVENTING THE CURVE OF LAYERS OF SEMICONDUCTOR AND DISPOSITIFA SEMICONDUCTOR FORMS BY THIS PROCESS

METHOD FOR PRODUCING A TRANSISTOR CHANNEL STRUCTURE IN UNI-AXIAL STRESS

Procédé de réalisation de transistor(s) à structure de canal contraint dans lequel on réalise au moins une implantation ionique amorphisante de la couche superficielle d'un substrat de type semi-conducteur sur isolant à travers des ouvertures d'un masquage, de sorte à rendre amorphe des zones (12b) de la couches superficielles et à induire une relaxation d'une zone (12a) destinée à former un canal et située entre les zones rendues amorphes, la relaxation étant réalisée dans une direction orthogonale à celle dans laquelle le courant du canal est destiné à circuler (figure 1C).

PROCESS IMPROVES OF REALIZATION OF DISTINCT Of INSULATION IN a SEMICONDUCTOR SUBSTRATE ON INSULATOR

METHOD OF FORMING COMPONENTS ON A SILICON GERMANIUM LAYER

L'invention concerne un procédé de fabrication de composants sur une couche de SOI (50) revêtue d'une couche de silicium-germanium (54) formée par dépôt épitaxial, dans lequel le bilan thermique des recuits réalisés après le dépôt épitaxial est tel que la concentration en germanium demeure plus élevée dans la couche épitaxiée que dans la couche de SOI.

IMPROVED FORMATION OF STRAINED SILICON ON INSULATOR BY AMORPHIZATION VOLTAGE AND THEN RECRYSTALLIZATION

Procédé d'une structure de silicium contraint, dans lequel on forme une couche de silicium Germanium sur la couche de silicium, puis une autre couche de concentration en germanium plus faible avant d'effectuer une amorphisation sélective de la couche de silicium et de silicium germanium par rapport à cette autre couche avant de recristalliser l'ensemble de sorte à mettre en contrainte la couche semi-conductrice (3) en silicium. Du fait de l'amorphisation sélective on améliore la qualité du silicium contraint obtenu après recristallisation.

DEVICE OF SEMICONDUCTOR HAS FILM Of INSULATION AND MANUFACTORING PROCESS

Dans un procédé de fabrication d'un dispositif à semiconducteur capable d'éviter des défauts occasionnés par la pollution par des métaux, on définit deux régions (NR, PR) par une pellicule d'oxyde d'isolation par tranchée (ST21), on forme sélectivement une pellicule de silicium polycristallin (PS21) sur la pellicule d'oxyde d'isolation par tranchée, on forme une couche de siliciure (SS2) sur la pellicule de silicium polycristallin et on forme un élément d'espacement de paroi latérale (SW2) sur une surface latérale de la pellicule de silicium polycristallin. La pellicule de silicium polycristallin (PS21) est formée dans une position correspondant à un sommet d'une partie de jonction PN (JP) d'une région de caisson de type P (WR11) et d'une région de caisson de type N (WR12) dans une couche SOI 3, à cheval sur les deux régions de caisson.

METHOD OF RELIEVING [...] MECHANICAL CROSS IN THE ACTIVE REGION OF A MOS TRANSISTOR, AND AN INTEGRATED CIRCUIT ARRANGEMENT

Procédé de relaxation des contraintes mécaniques transversales dans la région active d'un transistor MOS (TR). Le procédé comprend une réalisation d'au moins une incitation (IN01,... IN07) isolante dans la région active du transistor séparant en deux parties chacune des régions de drain (RD01,..., RD08), de source (RS08,..., RS08) et de canal du transistor. L'invention concerne également le circuit intégré comprenant le transistor.

TRANSISTOR AND MANUFACTORING PROCESS

Dispositif à semiconducteur, caractérisé en ce qu'il comprend : un substrat (4); un élément à semiconducteur incluant (a) une électrode de grille (79) formée sur une surface principale du substrat (4), avec une pellicule d'isolation de grille (78) interposée entre elles, et s'étendant dans une direction prédéterminée, (b) une première paroi latérale (83) formée sur chaque surface latérale de l'électrode de grille (79), (c) une région de corps (88) formée dans le substrat (4) sous l'électrode de grille (79), et (d) une paire de régions de source/drain (76) formées dans le substrat (4), avec la région de corps (48) disposée entre la paire de régions de source/ drain (76); une pellicule d'isolation inter-couche (90) formée sur le substrat (4) pour recouvrir l'élément à semiconducteur; et une ligne d'interconnexion de grille (92) en contact avec la surface supérieure de l'électrode de grille (79) et s'étendant dans la direction prédéterminée, cette ligne d'interconnexion de grille (92) étant ...

INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To improve an packaging density by minimizing a stress in a boundary of respective functional blocks, making an element forming surface uniform and suppressing the increase in the area of a chip in a system on chip type semiconductor device. CONSTITUTION: The semiconductor device comprises a support substrate, a bulk element region having a first element formed in a bulk growth layer on the substrate, an SOI element region having an element formed in a silicon layer on an embedding insulating film on the substrate, and a boundary layer disposed in the boundary of these regions. In this device, the element forming surface of the bulk element region having the element formed in the growth layer is substantially equal in height to the element forming surface of the SOI element region having the element formed in the silicon layer on the embedding insulating film. © KIPO & JPO 2004 ...

SEMICONDUCTOR DEVICE INCLUDING FET HAVING IMPROVED ISOLATION CHARACTERISTIC

PURPOSE: A semiconductor device including a FET having an improved isolation characteristic is provided to improve the isolation characteristic by forming a high-concentration impurity region between a gate electrode and the FET adjacent to the gate electrode. CONSTITUTION: One or more metal layers are used for forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. An impurity diffusion region is formed on the semi-insulating substrate or the insulating layer on the substrate. A high-concentration impurity region is formed at a region within a metal layer, which is adjacent to another metal layer or the impurity diffusion region, in order to suppress expansion of a depletion layer from the corresponding metal layer. © KIPO 2005 ...

METHOD OF FABRICATING TRENCH FOR SOI MERGED LOGIC DRAM

PURPOSE: High performance SOI merged logic DRAM devices are provided to etch deep trenches into an SOI substrate without etching through a buried oxide layer. CONSTITUTION: An SOI(Silicon-On-Insulator) substrate comprises a buried oxide layer and selected layers forming an array device and logic device. In a process for forming high performance SOI merged logic DRAM devices, first, an insulating layer is formed on the surface of the SOI substrate and a blockout photoresist pattern is formed on the insulating layer over the selected area of the logic device. Secondly, the insulating layer is etched in order to remove the insulating layer of the selected area of the array device and the SOI substrate is etched through the buried oxide layer in the selected area of the array device. Thirdly, the photoresist pattern disposed to the selected area of the logic device is removed and a silicon layer is formed to the etched area of the selected area of the array device. Thereafter, a deep trench ...

SEMICONDUCTOR DEVICE HAVING HOLLOW HOLE IN SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD THEREOF

The present invention relates to a semiconductor device having a hollow hole in a silicon-on-insulator (SOI) structure and a method thereof, and more specifically, to a semiconductor device which increases a performance index of a RF-SOI switch by forming a hollow hole on a buried oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor, and to a method thereof. COPYRIGHT KIPO 2016 ...

METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device. © KIPO & WIPO 2007 ...

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that 5 includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are 10 formed in the second area of the substrate.

BODY-TIED SILICON ON INSULATOR SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR

A silicon on insulator (SOI) device structure and method therefore in which the SOI device structure utilizes a conductive body contact region (220) under a partial trench isolation region (250) to connect a doped region (320), which is a conductive area, with the body region (380) of the device such that the desired potential within the body region (380) can be achieved. This is accomplished by patterning the silicon on insulator (SOI) substrate and etching away the portion of the substrate within which the partial trench isolation is to be formed. Following the etching operation, an implant step dopes the remaining portion of the silicon film underlying the partial trench isolation region (250) to achieve the desired conductivity. Full trench isolation regions (240) are then patterned and formed. Subsequent formation of contacts (710, 720) and other layers of interconnect (750) complete formation of the SOI device.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulating layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component ...

Semiconductor device

A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method

Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects ...

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes the following steps. A silicon oxide film having a predetermined film thickness is formed on a smooth major surface of a first silicon substrate of a first conductivity type having a first region wherein a power transistor is to be formed. The major surface of the first silicon substrate is bonded to a smooth major surface of a second silicon substrate having one of the first conductivity type and a second conductivity type. The other surface of the second silicon substrate bonded to the first silicon substrate is polished to form a silicon layer having a predetermined film thickness and a second region wherein a transistor constituting a control circuit for driving the power transistor is to be formed. The silicon layer and the silicon oxide film are removed from a predetermined portion in the first region. The power transistor of a vertical type is formed on the silicon substrate in the first region wherein the silicon layer and ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick film region. The thin film region includes a first semiconductor layer deposited on the support substrate, and the thick film region includes the first semiconductor layer and a second semiconductor layer deposited on a part of the first semiconductor layer. The first STI-type isolation region is disposed at the thin film region. The second STI-type isolation region is disposed at the thick film region. The alignment mark region is disposed at the thick film region. An alignment mark to be used for alignment of the second STI-type isolation region is disposed at the alignment mark region.

Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation

A process which utilizes an anodized porous silicon technique to form dielectric isolation on one side of a semiconductor device is described. Regions of silicon semiconductor are fully isolated from one another by this technique. The starting wafer typically is predominantly P with a P+ layer thereon. A P or N layer over the P+ layer is formed thereover such as by epitaxial growth. The surface of the silicon is oxidized and a photoresist layer applied thereto. Openings are formed in the photoresist. Openings are formed in the silicon dioxide using the photoresist as a mask and appropriate etching techniques. The openings in the silicon dioxide define the regions to be etched by reactive ion etching. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form porous silicon throughout the P+ layer. The structure is then placed in a thermal oxidation ambient until the ...

SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY TRANSISTOR STRUCTURES AND METHOD OF MANUFACTURING SAME

Method of forming a trench isolation

The present invention provides a method of forming a trench isolation in a substrate, which comprises the steps of: forming a trench groove in a substrate; forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, wherein the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove; and forming a second electrically insulating layer over the first electrically insulating layer, wherein the second electrically insulating layer fills the first hollow, and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove, and the second electrically insulating layer has a second surface migration smaller than the first surface migration.

Semiconductor device and method of manufacturing same

A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3a being adjacent to the channel region and a second part 3b formed to protrude in a channel width direction from the first part 3a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3b for connecting the source/drain regions 2 to source/drain wirings.

Semiconductor device isolation structure and fabrication method of semiconductor device using the same

A semiconductor device isolation structure includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, and an isolation layer formed in the field region of the substrate deeper than the buried insulation layer. A method for isolating a semiconductor device includes the steps of preparing a semiconductor substrate, defining an active region and a field region in the substrate, forming an insulation layer buried in the active region of the substrate, and forming an isolation layer in the field region of the substrate to be deeper than the buried insulation layer. The invention applies to an SOI (Silicon On Insulator) provided with a SIMOX (Separation by Implanted Oxygen) type, for effectively overcoming interfacial defects between a buried oxide film and a semiconductor substrate, and improves a reliability of the semiconductor device by planarizing the same.

Semiconductor power integrated circuit

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby ...

ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS

An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF

A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Formation of semiconductor devices with dual trench isolations

A method for fabricating a semiconductor device with dual trench isolations includes forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors, forming a first shallow trench located between transistors of the first array and a second shallow trench located between transistors of the second array, and forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

ESD PROTECTION STRUCTURE AND METHOD OF FABRICATION THEREOF

An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

Semiconductor integrated circuit device and manufacturing method thereof

A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor lid in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 1a to 11d can increase the withstand voltage of a semiconductor integrated circuit.

SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING

A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.

Method for forming a stressor structure

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer ( 224 ) disposed on a buried dielectric layer ( 222 ). A trench ( 229 ) is created in the semiconductor structure which exposes a portion of the buried dielectric layer. An oxide layer ( 250 ) is formed over the surfaces of the trench, and at least one stressor structure ( 255 ) is formed over the oxide layer.

SINGLE DIFFUSION BREAK DEVICE FOR FDSOI

The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

Deep trench isolation structure in semiconductor device

A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

ISOLATION PILLAR FIRST GATE STRUCTURES AND METHODS OF FORMING SAME

A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

DIODE

A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

Method for producing a semiconductor arrangement, semiconductor arrangement and its application

A semiconductor arrangement for an integrated circuit is provided that includes a first region in which a number of components are formed, a second region, a buried insulating layer for vertically insulating the first region, an insulating structure, which is formed between the first region and the second region for laterally insulating the first region from the second region. The insulating structure can have a trench structure with a dielectric and a conductor structure with a semiconductor material. Whereby the trench structure borders on the buried insulating layer, and the conductor structure is designed to conductively connect the first region to the second region.

Uniform height tall fins with varying silicon germanium concentrations

A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration.

Shallow trench isolation fill by liquid phase deposition of SiO2

To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO₂) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO₂ does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO₂ is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

METHOD FOR FABRICATING PARTIAL SOI SUBSTRATE

A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.

Semiconductor device and method of manufacturing the same

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

SEMICONDUCTOR STRUCTURE IMPLEMENTING SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAME

A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Integrated circuit with bulk and SOI devices connected with an epitaxial region

An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Inverted Trapezoidal Recess for Epitaxial Growth

A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Wafers and device structures with body contacts

Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

High Voltage Isolation Trench, Its Fabrication Method and MOS Device

A type of high voltage isolation trench, its fabrication method and an MOS device are disclosed. The isolation trench includes a trench extending to a buried oxide layer of a wafer, with high concentration N+ injected to a side wall of the trench, polysilicon being filled in the trench and oxides are being filled between the side wall of the trench and the polysilicon. Multiple composite structures are used to fill the vacant trench to reduce stress brought by trenching so as to improve performance of the device on one hand and to achieve the purpose of increasing breakdown voltage and improving superficial flatness on the other hand.

MULTI-FUNCTION SUBSTRATE

The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

Leave-behind protective layer having secondary purpose

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

A manufacturing method of an integrated circuit based on the semiconductor-on-insulator technology and a device so manufactured

Random layout of devices or active regions of the devices is allowed for a semiconductor integrated circuit based on an SOI technology using an anti-reflecting film (14). Openings (123) are provided for the anti-reflecting film (14) formed on a polycrystalline silicon layer (13), corresponding to the device regions wherein devices or active regions of the devices are to be formed. An orverlapped scan of a laser (LB) beam having diameter larger than the dimension of the openings (123) is applied on the silicon layer (13) through the openings and circumferential anti-reflecting film (14). Concaved temperature profile is achieved along everydirections (m) across the openings due to the enhanced beam (LB) absorption by the circumferential anti-reflecting film (14), hence recrystallization nucleation of the silicon layer initiates at the center of each opening during the laser beam scan. Thus, self-aligned single crystal regions (113) are fabricated in the polycrystalline silicon layer (13) ...

SEMICONDUCTOR AND METHOD OF PRODUCING SAME

Improving performance and reducing variation of narrow channel devices

A method of forming transistors 210, 220, such as narrow channel transistors, in which transistor regions 102a, 102b are created in a substrate, the transistor regions each being separated from the rest of the substrate by one or more shallow trench isolation (STI) regions 105 formed in the substrate; the STI regions having a height higher than the transistor regions of the substrate and channel regions of the transistors having gate stacks on top thereof; spacers 202 are formed at sidewalls of the STI regions above the transistor regions; recesses are created to form source and drain regions of the transistors with the spacers overhanging the substrate to preserve at least a portion of substrate material underneath the spacers along sidewalls of the STI regions; and source and drain stressor regions 204, 205 are epitaxially grown in the recesses.

Heterolithic voltage controlled oscillator

Semiconductor device

Semiconductor Device

... 1,164,724. Semi-conductor devices. RADIO CORPORATION OF AMERICA. 25 Sept., 1967 [18 Oct., 1966], No. 43520/67. Heading H1K. A semi-conductor device comprises an array of discrete chips 26, 28 and 29 of semi-conductor material embedded in a matrix of insulating material 34 consisting of a mixture of glass and an electrically insulating refractory ceramic material. The coefficients of thermal expansion of the semi-conductor material and of the insulating material are substantially equal, and the softening temperature of the insulating material is greater than the softening temperature of its glass constituent. The ceramic material forms between 20% and 70% by volume of the insulating material and is of mullite, zirconium silicate, cordierite, silicon carbide or silicon nitride. The glass is of an inorganic type which contains no sodium, lithium or copper ions. A layer 36 of silicon dioxide of 10,000 Š thickness may be applied from a vapour phase to shield the semiconductor chips from the ...

PROCEDURE FOR THE PRODUCTION OF THIN SINGLE CRYSTAL SILICON ISLANDS ON AN INSULATOR

MANUFACTURE OF ELECTROLUMINESCENT DISPLAY DEVICES

Shallow trench isolation process and structure

Semiconductor device with partial SOI structure and its manufacturing method

具应变通道的互补式金氧半导体及其制作方法

The CMOS includes a semiconductor substrate, multiple trench isolation zones on the substrate, a bedding layer of nitride, an ion planted bedding layer of nitride, an N type channel transistor and a P type channel transistor. Driving zone including one N type driving zone and one P type driving zone is defined between two adjacent trench isolation zones. Bedding layers of nitride are setup between two sides of N type driving zone and substrate in compliance. Ion planted bedding layer of nitride are setup between two sides of P type driving zone and substrate in compliance. N type channel transistor is above N type driving zone and P type channel transistor is above P type driving zone.

Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer

A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

Substrate Structure Having Buried Wiring And Method For Manufacturing The Same, And Semiconductor Device And Method For Manufacturing The Same Using The Substrate Structure

Provided are a substrate structure which may solve problems generated in a manufacturing process while having a relatively low resistance buried wiring, a method for manufacturing the substrate structure, and a semiconductor device and a method for manufacturing the same using the substrate structure. The substrate structure may include a supporting substrate, an insulating layer disposed on the supporting substrate, a line-shaped conductive layer pattern disposed in the insulating layer to extend in a first direction, and a line-shaped semiconductor pattern disposed in the insulating layer and on the conductive layer pattern to extend in the first direction and having a top surface exposed to the outside of the insulating layer.

Bipolar transistor with guard region

A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Method for manufacturing a strained channel mos transistor

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Semiconductor device and fabrication method

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Independently voltage controlled volume of silicon on a silicon on insulator chip

A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Method of Fabricating Isolated Capacitors and Structure Thereof

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit

A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

Borderless contact for ultra-thin body devices

After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

Shallow trench isolation structure having a nitride plug

A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.

Isolated zener diode

Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V b ) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the V b of the diode (e.g., increasing the length reduces V b of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Electrical Signal Isolation and Linearity in SOI Structures

Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

Method of producing insulation trenches in a semiconductor on insulator substrate

A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Reduced Corner Leakage in SOI Structure and Method

A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. 117-. (canceled)18. A method of forming a transistor of a semiconductor integrated circuit in an active layer overlying another layer or substrate , said method comprising steps of:etching through said active layer in a region of said active layer adjacent a transistor location to form a trench,applying a liner in said trench,etching said another layer or substrate to increase depth of said trench and undercut a portion of said active layer in said transistor location and expose said active layer in said transistor location to form a recessed and undercut region,etching said active layer exposed by said step of etching said another layer, anddepositing insulator material where material has been removed by said etching steps.19. The method as recited in claim 18 , wherein said step of etching said active layer is performed to shape a corner of a conduction channel of said transistor in a region opposite said gate structure20. The method as recited in claim 18 , wherein said method is performed on a SOI wafer.21. The method as recited in claim 18 , wherein said region adjacent said transistor is between a location of said transistor and a location of a storage ...

Semiconductor Structure and Method for Manufacturing the Same

The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.

Process for manufacturing a wafer by annealing of buried channels

A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a buried layer, a deep well having a first conductivity type being disposed on the buried layer, a first doped region having the first conductivity type and a well having the second conductivity type being disposed in the deep well, a first heavily doped region having the first conductivity type being disposed in the first doped region, a second heavily doped region having the first conductivity type being disposed in the well, a gate disposed between the first heavily doped region and the second heavily doped region, and a first trench structure and a second trench structure being disposed at the two sides of the gate in the semiconductor substrate. The first trench structure contacts the buried layer, and a depth of the second trench structure is substantially larger than a depth of the buried layer.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film. 1. A method of manufacturing a semiconductor device comprising the steps of:(a) providing a semiconductor substrate that is comprised of: a supporting substrate; a first insulating film formed over the supporting substrate; and a semiconductor layer formed over the first insulating film, and that includes a first region and a second region over the upper surface of the semiconductor layer;(b) exposing the upper surface of the first insulating film in the second region by forming a second insulating film over the semiconductor layer and by processing the semiconductor layer with the use of the second insulating film as a mask;(c) forming a third insulating film so as to cover the semiconductor layer, the second insulating film, and the first insulating film;(d) exposing the upper surface of the supporting substrate by opening the third insulating film and the first insulating film in the second region;(e) forming a first epitaxial layer in the opening of the first insulating film and the third insulating film;(f) exposing the upper surface of the semiconductor layer by polishing the first epitaxial layer, the third insulating film, and the second insulating film; and(g) after the (f) step, forming a semiconductor ...

Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor

A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

LOW HARMONIC RF SWITCH IN SOI

A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device. 1. A method of fabricating a semiconductor structure , comprising:forming a trench through an insulator layer, wherein the trench is adjacent a device formed in an active region on the insulator layer; andforming a cavity in a substrate under the insulator layer and extending laterally from the trench to underneath the device.2. The method of claim 1 , further comprising:forming a barrier layer over the active device and on walls of the trench after forming the cavity; andfilling the trench with dielectric material.3. The method of claim 1 , wherein the trench is one of a plurality of trenches around a perimeter of the device claim 1 , and further comprising providing a spacing between adjacent ones of the plurality of trenches of about ten to twenty times a width of one of the plurality of trenches.4. The method of claim 1 , wherein the device comprises a radio frequency switch comprising a plurality of polysilicon lines on the active region.5. The method of claim 1 , further comprising damaging regions of the substrate under a passive device or interconnect.6. The method of claim 5 , wherein the damaging regions of the substrate comprises:forming an other trench in the insulator layer; andimplanting an inert ion into the regions of the substrate.7. A method of fabricating a semiconductor structure claim 5 , comprising:forming a semiconductor-on-insulator (SOI) wafer including a silicon substrate, an insulator layer on the substrate, and an active semiconductor layer on the insulator layer;forming an active field ...

Methods for fabricating semiconductor devices with isolation regions having uniform stepheights

Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.

Wafer with Spacer including Horizontal Member

A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed.

Method for Manufacturing Semiconductor Device

The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a shallow trench in a substrate; forming a shallow trench filling layer in the shallow trench; forming a cap layer on the shallow trench filling layer; and implanting ions into the shallow trench filling layer and performing an annealing to form a shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, an insulating material is formed by implanting ions into the filling material in the shallow trench, and a compressive stress is applied to the active region of the substrate due to the volume expansion of the filling material, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved.

Methods of recessing an active region and sti structures in a common etch process

Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure.

Undercut insulating regions for silicon-on-insulator device

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

Post-gate isolation area formation for fin field effect transistor device

A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

MICROELECTRONIC DEVICE WITH ISOLATION TRENCHES EXTENDING UNDER AN ACTIVE AREA

A microelectronic device including: 1. A microelectronic device including at least:a substrate including a first semiconductor layer positioned on a dielectric layer, where the dielectric layer is positioned on a second semiconductor layer,an isolation trench made through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, including at least one dielectric material and delimiting, in the first semiconductor layer, at least one active area of the device,in which, in said part of the thickness of the second semiconductor layer, at least one portion of the dielectric material of the isolation trench is positioned under the active area, the active area being of roughly rectangular shape, and delimited by at least four side walls of the isolation trench which extend through the first semiconductor layer, the dielectric layer and said part of the thickness of the second semiconductor layer,and in which, in said part of the thickness of the second semiconductor layer, two of the four side walls which are roughly parallel with one another are positioned under the active area and the other two side walls are not positioned under the active area.2. The microelectronic device according to claim 1 , in which said dielectric material of the isolation trench is SiO.3. The microelectronic device according to claim 1 , in which said portion of the dielectric material of the isolation trench is in contact with a portion of the dielectric layer which is positioned under the active area.4. The microelectronic device according to claim 1 , also including at least one transistor produced in the active area claim 1 , and a gate of which is positioned on a portion of the active area and on a portion of said other two side walls.5116. The microelectronic device according to claim 1 , in which claim 1 , in the dielectric layer and the first semiconductor layer claim 1 , the side walls comprise at least one semiconductor nitride ...

Electrical isolation structures for ultra-thin semiconductor-on-insulator devices

After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

Semiconductor structure with integrated passive structures

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

SEMICONDUCTOR STRUCTURE IMPLEMENTING SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAME

A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure. 1. A semiconductor structure , comprising:a gate electrode and a resistor electrode disposed in a semiconductor substrate, wherein a dopant concentration of the gate electrode is greater than a dopant concentration of the resistor electrode;an isolation structure disposed in the semiconductor substrate, wherein the gate electrode and the resistor electrode are separated by the isolation structure;a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode; anda conductive structure disposed in the semiconductor substrate and over the isolation structure, wherein the conductive structure is in direct contact with the S/D region and the resistor electrode.2. The semiconductor structure of claim 1 , wherein a width of the resistor electrode is greater than a width of the gate electrode.3. The semiconductor structure of claim 1 , further comprising:a well region disposed in the semiconductor substrate, wherein the resistor electrode is disposed over the well region, and a conductivity type of the well region is the same as a conductivity type of the S/D region. ...

UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET. 1. A silicon-on-insulator (SOI) semiconductor device , comprising:an SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer;a field effect transistor (FET) device located on the top SOI layer; andan undercut isolation region located in the SOI substrate adjacent to the FET device, wherein the undercut isolation region extends through the top SOI layer and the BOX layer and into the bottom substrate underneath the BOX layer, such that a portion of the undercut isolation region is underneath a source/drain region of the FET, wherein the undercut isolation region comprises an undercut fill comprising an oxide material.2. The device of claim 1 , further comprising an oxidized region in the bottom substrate located between the undercut isolation region and the bottom substrate.3. The device of claim 1 , wherein the undercut isolation region further comprises an undercut isolation region liner located between the undercut fill and the bottom substrate.4. The device of claim 3 , wherein the undercut isolation region liner comprises one ...

Method for producing at least one device in compressive strained semiconductor

Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

WAFER REINFORCEMENT TO REDUCE WAFER CURVATURE

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure. 1. A wafer comprising:a silicon on insulator (SOI) layer formed directly upon a buried insulating layer, the buried insulating layer formed directly upon a substrate;a filled deep trench associated with a microdevice within the wafer, wherein the filled deep trench is filled with a trench material;filled dual reinforcement trenches separated by dielectric material within the wafer, each filled dual reinforcement trench comprising trench material directly upon the sidewalls and directly upon lower surfaces of each of the dual reinforcement trenches and reinforcing material directly upon the trench material;wherein the deep trench and filled dual reinforcing trenches extend through the SOI layer, through the buried insulating layer, and partially through the substrate;a first conductive contact directly upon at least the trench material that fills the deep trench; anda second conductive contact directly upon at least the trench material that is directly upon a sidewall of one of the dual reinforcing trenches.2. The wafer of claim 1 , wherein the reinforcing material differs from the trench material.3. The wafer of claim 2 , wherein the reinforcing material has a material strength measurement greater than the trench material.4. The wafer of claim 1 , wherein each dual reinforcement trench width is greater than the deep trench width.5. The wafer of claim 1 , wherein each ...

Production of semiconductor regions in an electronic chip

A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer. 1. An integrated circuit , comprising:a first transistor device region including a first gate structure, the first gate structure including a gate electrode, a gate dielectric, and a layer, the layer between the gate electrode and gate dielectric and being compositionally different from the gate electrode and gate dielectric, and the layer including first and second portions, the first and second portions being collinear with each other and compositionally different from one another; anda second transistor device region including a contact structure, the contact structure being one of a second gate structure, a source contact, or a drain contact;wherein the first and second transistor device regions are arranged in a vertically stacked configuration, and a conductive interconnect extends downward from the gate electrode of the first gate structure to contact the contact structure.2. The integrated circuit of claim 1 , wherein the first gate structure is part of a non-planar transistor that includes a body of ...

EMBEDDED MEMORY USING SOI STRUCTURES AND METHODS

An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate. 1. An integrated circuit (IC) comprising:a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;a logic device comprising a logic gate arranged over the semiconductor device layer, wherein the logic gate is arranged within a high κ dielectric layer; anda memory cell comprising a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer, wherein a charge-trapping layer underlies the control gate.2. The IC according to claim 1 , wherein the SOI substrate is a fully depleted SOI (FDSOI) substrate.3. The IC according to claim 1 , wherein the semiconductor device layer is a monocrystalline silicon layer having a thickness ranging from 5 nm to 40 nm claim 1 , the insulator layer is a silicon dioxide or sapphire layer having a thickness ranging from 10 nm to 60 nm.4. The IC according to claim 1 , wherein the semiconductor device layer has a thickness such that during operation of the memory cell or logic device claim 1 , a depletion region in a channel region of the memory cell or the logic device extends fully across the depths of the semiconductor device layer.5. The IC according to claim 1 , further comprising:an individual source/drain region disposed to a first side of the control gate;an intermediate source/drain region arranged laterally between ...

Integrated Circuit Structure and Method with Hybrid Orientation for FinFET

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES

Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. 1. A semiconductor structure comprising:a handle substrate comprising a single crystalline semiconductor material; andmaterial portions that are located on said handle substrate, wherein said material portions comprise:a first material portion located in a first region of said semiconductor structure and including a first buried insulator portion and a first semiconductor-on-insulator (SOI) portion comprising a first semiconductor material;a second material portion located in a second region of said semiconductor structure and including a second buried insulator portion and a second SOI portion comprising an alloy of said first semiconductor material and another semiconductor material; anda third material portion located in a third region of said semiconductor structure and including an epitaxial semiconductor material portion including a second semiconductor material that is epitaxially aligned to said single crystalline semiconductor material in said handle ...

DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS

A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. 2. The method of claim 1 , wherein a portion of said contact via structure is in direct contact with a topmost horizontal surface of said dielectric metal oxide liner and a topmost surface of said silicon nitride liner.3. The method of claim 1 , wherein said dielectric metal oxide liner is recessed to a depth between a top surface of said buried insulator portion and a bottom surface of said buried insulator portion.4. The method of claim 3 , wherein another portion of said contact via structure is formed directly on a vertical sidewall surface of said buried insulator portion.5. The method of claim 1 , further comprising recessing said silicon nitride liner to a depth below the horizontal plane of a bottom surface of said top semiconductor portion.6. The method of claim 5 , wherein said silicon nitride liner is recessed to a depth below the horizontal plane of a bottom surface of said buried insulator portion.7. The method of claim 6 , wherein said contact via structure is in direct contact with a vertical ...

Undercut insulating regions for silicon-on-insulator device

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

DUAL STRESS DEVICE AND METHOD

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. 1. A semiconductor structure , comprising:semiconductor material having a bend and a trench feature formed at the bend; anda gate structure at least partially disposed in the trench feature,wherein the semiconductor material comprises a fin having a first side and a second side opposite the first side.2. The semiconductor structure of claim 1 , further comprising a second gate structure claim 1 , wherein a first inversion channel region of the gate structure and a second inversion channel region of the second gate structure are at least partially disposed in an area of the fin that has tensile stress induced by the bend.3. The semiconductor structure of claim 2 , wherein the gate structure is included in a first NFET and the second gate structure is included in a second NFET.4. The semiconductor structure of claim 1 , further comprising a second gate structure claim 1 , wherein a first inversion channel region of the gate structure and a second inversion channel region of the second gate structure are at least partially disposed in an area of the fin that has compressive stress induced by the bend.5. The semiconductor structure of claim 4 , wherein the gate structure is included in a first NFET and the second gate structure is included in a second NFET.6. A semiconductor structure claim 4 , comprising:a semiconductor fin having a first side, a second side opposite the first side, and a bend; anda gate structure arranged at the first side of the ...

Radio frequency switches with air gap structures

The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

Semiconductor device and method of forming the semiconductor device

A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.

Spacers for Semiconductor Devices Including Backside Power Rails

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer. 1. A device comprising:a first transistor structure;a front-side interconnect structure on a front-side of the first transistor structure; and a first dielectric layer on the backside of the first transistor structure;', 'a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure;', 'a first conductive line electrically coupled to the first via; and', 'an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer., 'a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure comprising2. The device of claim 1 , wherein the first conductive line is a power line or an electrical ground line.3. The device of claim 1 , wherein an aspect ratio of a height of the air spacer to a width of the air spacer is from 1 to 2.4. The device of claim 1 , wherein the backside interconnect structure further comprises a second dielectric layer interposed between the air spacer and the first conductive line claim 1 , the second ...

Multilayer Isolation Structure for High Voltage Silicon-On-Insulator Device

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron. 1. A device comprising:a semiconductor-on-insulator substrate that includes a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer; and a first insulator sidewall spacer,', 'a second insulator sidewall spacer, and', 'a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer, wherein the multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion., 'an isolation structure that surrounds an active region of the semiconductor-on-insulator substrate, wherein the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate, and further wherein the isolation structure includes2. The device of claim 1 , wherein the top polysilicon portion has a first thickness claim 1 , the bottom silicon portion ...

SEMICONDUCTOR DEVICE AND METHOD FOR MONOLITHICALLY INTEGRATED POWER DEVICE AND CONTROL LOGIC

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region. 1. A method of making a monolithic semiconductor device , comprising:providing a substrate;forming an opening extending partially through the substrate;forming a semiconductor material within the opening;forming a power semiconductor device within the semiconductor material;forming a control logic circuit in a portion of the substrate outside the opening to control the power semiconductor device; andforming a first isolation trench in the semiconductor material to isolate the power semiconductor device and control logic circuit.2. The method of claim 1 , wherein the power semiconductor device includes a vertical power semiconductor device.3. The method of claim 1 , further including forming a second isolation trench in the portion of the substrate outside the opening to isolate a first control logic circuit from a second control logic circuit.4. The method of claim 1 , further including forming an interconnect structure over the power semiconductor device and control logic circuit.5. The method of claim 1 , wherein the substrate includes a ...

HIGH SPEED WAVEGUIDE INTEGRATED GE-BASED PHOTODIODE DESIGN FOR SILICON PHOTONICS

Methods of increasing the optical path length and bandwidth of a Ge-based photodiode while reducing the diode area and capacitance without compromising the optical responsivity and the resulting devices are provided. Embodiments include providing a Si substrate having a BOX layer over the Si substrate and a Si layer over the BOX layer; forming an oxide layer over the Si layer; forming a trench in the oxide layer, the trench having a center strip and a plurality of opposing fins; epitaxially growing Ge in the trench and above the oxide layer; and removing the oxide layer, a Ge center strip and a plurality of opposing fins remaining. 1. A method comprising:providing a silicon (Si) substrate having a buried oxide (BOX) layer over the Si substrate and a Si layer over the BOX layer;forming an oxide layer over the Si layer;forming a trench in the oxide layer, the trench having a center strip and a plurality of opposing fins;epitaxially growing germanium (Ge) in the trench and above the oxide layer; andremoving the oxide layer, a Ge center strip and a plurality of opposing fins remaining,wherein, in top view, the Ge center strip extends between the plurality of opposing fins in perpendicular direction.2. The method according to claim 1 , further comprising:forming an interlayer dielectric (ILD) over the Si layer and between the Ge fins;{'sub': '2', 'forming a silicon dioxide (SiO) layer over the ILD; and'}{'sub': '2', 'planarizing the SiOlayer down to the Ge.'}3. The method according to claim 1 , further comprising:forming the trench through the oxide layer and a portion of the Si layer.4. The method according to claim 1 , comprising forming the Si layer to a thickness of 200 nanometer (nm) to 240 nm.5. The method according to claim 1 , comprising forming the oxide layer to a thickness of 0.07 micrometer (μm) to 0.09 μm.6. The method according to claim 1 , comprising forming the oxide layer of deposited and grown oxides or nitride films.7. The method according to claim 1 , ...

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. 1. A method of forming a structure , comprising: a high-k dielectric material on a substrate;', 'a metal material on the high-k dielectric material; and', 'a semiconductor material over the metal material;, 'forming an active device comprisingforming a passive structure comprising a semiconductor layer in contact with an upper surface of a shallow trench isolation structure, adjacent to the active device; andforming a liner formed on a lower surface of the shallow trench isolation structure and between a sidewall of the shallow trench isolation structure and respective sidewalls of each of the substrate, the high-k dielectric material, the metal material and the semiconductor material.2. The method of claim 1 , wherein ion implanting dopant impurities penetrate into a substrate to form wells in the substrate of the active device.3. The method of claim 1 , wherein the semiconductor layer is directly on the shallow trench isolation structures.4. The method of claim 1 , wherein the semiconductor material is recessed in the active region.5. The method of claim 1 , wherein the semiconductor material is protruding in the active region.6. The method of claim 1 , wherein the metal material is a gate metal.7. The method of claim 1 , wherein the gate metal is one of TiN claim 1 , TaN claim 1 , Al claim 1 , ...

FIN CUT LAST METHOD FOR FORMING A VERTICAL FINFET DEVICE

A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric. 110-. (canceled)11. A vertical FinFET structure , comprising:a pair of fins disposed over a semiconductor substrate;a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each fins is in contact with the bottom source/drain region;a bottom spacer disposed over the bottom source/drain region; andan isolation structure comprising an isolation dielectric layer disposed between the pair of fins, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each fin, and a middle portion above the bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.12. The vertical FinFET structure of claim 11 , further comprising:a gate stack disposed over sidewalls of the fins, the gate stack extending laterally over the bottom spacer on opposing sides of each fin,a top spacer disposed over the gate stack;a first dielectric layer disposed over the top spacer; anda top source/drain region disposed over an upper portion of each of the fins.13. The vertical FinFET structure of claim 12 , wherein the gate stack and the top spacer are disposed between each fin and the middle portion of the isolation structure.14. The vertical FinFET structure of claim 12 , ...

Methods For Gapfill In High Aspect Ratio Structures

Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF FOR HIGH-VOLTAGE DEVICE IN A HIGH-VOLTAGE BCD PROCESS

The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process. Further, with a minimum thickness of the field oxide layer, the parasitical threshold voltage between the aluminum wiring and the silicon surface of the high-voltage device can be higher than V, thereby improving the planarization of oxide layer steps on the silicon surface in the whole high-voltage BCD process, and enhancing the reliability of the product. 1. A method for manufacturing an isolation structure for a high-voltage device in a high-voltage BCD process , comprising:providing a semiconductor substrate having a first type of doping;forming an epitaxial layer having a second type of doping over the semiconductor layer, and forming an isolation region having the first type of doping in the epitaxial layer, wherein the isolation layer extends through the epitaxial layer into the semiconductor substrate, wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer, and the first type of doping is opposite to the second type of doping; andforming a field oxide layer over the isolation region.2. The method for ...

ISOLATION REGIONS FOR SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches. 1. A method of forming a semiconductor structure having a substrate , the method comprising:forming a first layer over the substrate, the first layer comprising semiconductor material;etching first and second trenches, each of the first and second trenches extending through the first layer and into the substrate;introducing a wet etchant into the trenches, the wet etchant etching a first opening below the first trench and a second opening below the second trench, each of the first and second openings extending laterally below the first layer, the first and second openings being separated by a portion of the substrate adjoining the first and second openings;performing a diffusion oxidation process to oxidize the portion of the substrate adjoining the first and second openings;depositing an insulating material that fills the openings and the trenches; andforming a via that extends through the first layer and into the substrate, the via comprising a conductive material with sidewalls that are coated with an etch stop layer.2. The method of claim 1 , further comprising:forming one or more transistors ...

Finfets with various fin height

A method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation layer (STI) on top of a semiconductor substrate. A first Fin Field Effect Transistor (FinFET) comprises a first semiconductor fin including a first layer that extends from a common substrate level through the STI layer to a first height above a top surface of the STI layer. There is a second FinFET comprising a second semiconductor fin including the first layer that extends from the common substrate level through the STI layer to the first height above the top surface of the STI layer, plus a second layer having a second height, plus a third layer having a third height. The second semiconductor fin is taller than the first semiconductor fin.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

A semiconductor device according to an embodiment of the present disclosure includes: an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order; a first transistor provided on the semiconductor layer; a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and an element separation film provided between the first transistor and the second transistor, in which the element separation film includes a second insulating layer embedded in an opening that penetrates the semiconductor layer and the first insulating layer and reaches an inside of the silicon substrate layer, and a portion of the second insulating layer constitutes a gate insulating film of the second transistor. 1. A semiconductor device comprising:an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order;a first transistor provided on the semiconductor layer;a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; andan element separation film provided between the first transistor and the second transistor,the element separation film including a second insulating layer embedded in an opening, the opening penetrating the semiconductor layer and the first insulating layer and reaching an inside of the silicon substrate layer, anda portion of the second insulating layer constituting a gate insulating film of the second transistor.2. The semiconductor device according to claim 1 , wherein the second insulating layer has a thickness in a layered direction greater than a thickness of the first insulating layer.3. The semiconductor device according to claim 1 , wherein the element separation film has a protruding part that protrudes into the silicon substrate layer.4. The semiconductor device according to claim 1 , wherein the first transistor ...

SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING

Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type. 1. A structure formed using a silicon-on-insulator wafer , the structure comprising:a plurality of trench isolation regions extending through a device layer and a buried oxide layer of the silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer, the trench isolation regions arranged to surround an active device region of the device layer, and the active device region located over a portion of the buried oxide layer surrounded by the trench isolation regions;a well arranged in the substrate outside of the trench isolation regions, the well having a first conductivity type and a first electrical resistivity;a blocked region arranged in the substrate inside of the trench isolation regions and beneath the portion of the buried oxide layer, the blocked region having a second electrical resistivity that is greater than the first electrical resistivity; anda first doped region having the first conductivity type, the first doped region arranged in a first portion of the blocked region beneath the portion of the buried oxide layer and adjacent to one of the trench isolation regions,wherein the first doped region is more heavily doped with a dopant of the first conductivity type than the blocked region.2. The structure of further comprising: ...

Isolation scheme for bipolar transistors in bicmos technology

Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR

Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator. 1. A semiconductor device , comprising:a bulk semiconductor substrate;a transistor over the substrate, the transistor having a channel region as well as source and drain regions adjacent the channel region; anda semiconductor buffer layer disposed between the transistor and the substrate, and having an electrically insulating region between the channel region and the substrate.2. The semiconductor device of wherein the substrate is a bulk silicon substrate.3. The semiconductor device of wherein the channel region is included in an elongated semiconductor body having a height claim 1 , a width claim 1 , and a length that is greater than the width claim 1 , and in a cross-section perpendicular to the length of the semiconductor body claim 1 , the width of the semiconductor body is larger than a width of the electrically insulating region in the cross-section.4. The semiconductor device of wherein the channel region is included in an elongated semiconductor body having a height claim ...

Devices with Backside Metal Structures and Methods of Formation Thereof

A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material. 1. A method of fabricating a semiconductor device , the method comprising:forming trenches filled with a sacrificial material, the trenches extending into a semiconductor substrate from a first side;forming an epitaxial layer over the first side of the semiconductor substrate and the trenches;from a second side of the semiconductor substrate opposite to the first side, removing the sacrificial material in the trenches; andfilling the trenches with a conductive material, wherein a top portion of each of the trenches is filled with the epitaxial layer and a bottom portion of each of the trenches is filled with the conductive material.2. The method of claim 1 , further comprising forming a device region in the epitaxial layer.3. The method of claim 2 , wherein the device region comprises a source region of a transistor.4. The method of claim 1 , further comprising thinning the semiconductor substrate from the second side to expose the sacrificial material.5. The method of claim 4 , wherein a surface of the sacrificial material that is exposed is substantially planar.6. The method of claim 4 , wherein a vertical cross section of a surface of the sacrificial material that is exposed has a v-shape.7. The method of claim 4 , wherein thinning the semiconductor substrate comprises a chemical mechanical planarization process.8. The method of claim 4 , wherein thinning the semiconductor substrate comprises an anisotropic wet etching process.9. The method of claim 8 , wherein the anisotropic wet etching process comprises a ...

Method for forming a shallow trench isolation structure using a nitride liner and a diffusionless anneal

A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.

METHOD OF INTRODUCING LOCAL STRESS IN A SEMICONDUCTOR LAYER

The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer. 1. A method , comprising:forming stressor blocks over a silicon on insulator (SOI) structure, the SOI structure having a semiconductor layer in contact with an insulating layer, said stressor blocks being aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks locally stress said semiconductor layer; andin an annealing step, deforming second regions of said insulating layer adjacent to said first regions by temporarily decreasing a viscosity of said insulator layer.2. The method of claim 1 , wherein said stressor blocks are formed of a stressed material.3. The method of claim 1 , wherein said stressor blocks are each formed of SiN or SiGe.4. The method of claim 1 , further comprising further stressing said stressor blocks by forming a stress layer over said semiconductor layer and said stressor blocks.5. The method of claim 4 , wherein said stress layer has a thickness equal to at least 150% of a thickness of said semiconductor layer.6. The method of claim 4 , wherein said stress layer is SiN.7. The method of claim 1 , further comprising:removing said stressor blocks; andforming transistor gates over said first regions, respectively.8. The method of claim 7 , wherein each of said removed stressor blocks has a width equal to between 80% and 300% of a gate length of said transistor gate.9. The method of claim 7 , wherein ...

METHOD OF LOCALLY STRESSING A SEMICONDUCTOR LAYER

The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer. 1. A method of stressing a semiconductor layer , comprising:depositing a stress layer over a semiconductor on insulator (SOI) structure, the SOI structure having a semiconductor layer in contact with an insulating layer;locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; andin an annealing step, deforming second regions of said insulating layer adjacent to said first regions by temporarily decreasing a viscosity of said insulator layer.2. The method of claim 1 , further comprising:removing said stress layer; andforming transistor gates over said first regions, respectively.3. The method of claim 2 , wherein each of said openings has a width between 50% and 300% of a length of each transistor gate.4. The method of claim 2 , wherein said openings comprise a pair of adjacent openings having respective centers that are separated by a distance equal to between 80% and 120% of a distance separating centers of said transistor gates formed over the first regions with which said adjacent openings are aligned.5. The method of claim 2 , wherein each of said openings has a length of at least 80% of a width of one of said transistor gates.6. The method of claim 1 , wherein said stress layer has a thickness equal to at ...

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

Device isolation

A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.

FIN-TYPE FIELD EFFECT TRANSISTORS WITH UNIFORM CHANNEL LENGTHS AND BELOW-CHANNEL ISOLATION ON BULK SEMICONDUCTOR SUBSTRATES AND METHODS

Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods. 1. A semiconductor structure comprising:a semiconductor fin extending upward from a semiconductor substrate, the semiconductor fin comprising a lower semiconductor layer, a buried insulator on a top surface of the lower semiconductor layer and an upper semiconductor layer on a top surface of the buried insulator, wherein the buried insulator comprises a dielectric material layer between the lower semiconductor layer and the upper semiconductor layer and wherein the dielectric material layer comprises a dielectric material comprising silicon nitride, silicon oxynitride, or a low-K dielectric material having a dielectric constant of less than 3.9;shallow trench isolation on the semiconductor substrate and laterally surrounding the lower semiconductor layer of the semiconductor fin, wherein a top surface of the shallow trench isolation is below a level of the top surface of the buried insulator;a gate structure above the shallow trench isolation and positioned laterally ...

SOI WAFERS AND DEVICES WITH BURIED STRESSOR

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer. 1. A method for forming a semiconductor-on-insulator (SOI) structure with a buried stressor (BS) layer underlying a buried oxide (BOX) , the method comprising:growing a silicon germanium BS layer epitaxially on a substrate of a first silicon wafer;depositing a bonding layer (BL) comprising silicon on a surface of the BS layer;wafer bonding the first silicon wafer to a second wafer having a silicon oxide layer formed on a semiconductor substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first silicon wafer;exfoliating a layer of the semiconductor substrate of the second wafer adjacent the silicon oxide layer to form the SOI structure; andsubsequently applying a high temperature process to the SOI structure with the BS layer underlying the BOX to diffuse germanium from the silicon germanium BS layer into the BL.2. The method of wherein the high temperature process is applied until a distinct silicon bonding layer is not discernable in the SOI structure and the BS layer extends to the BOX layer.3. The method of wherein the high temperature process is applied as part of an SOI wafer production process.4. The method of wherein the high temperature process is applied during processing of semiconductor devices in the SOI structure. ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

An element isolation portion includes a projection portion that projects from an SOI substrate and comes into contact with a piled-up layer. The height of the upper surface of the projection portion is configured to be lower than or equal to the height of the upper surface of the piled-up layer and higher than or equal to a half of the height of the upper surface of the piled-up layer with reference to a surface of a silicon layer of the SOI substrate. 1. A semiconductor device comprising:an SOI substrate including a substrate layer, an insulating layer formed over the substrate layer, and a silicon layer formed over the insulating layer;an element isolation portion that penetrates the silicon layer and the insulating layer and reaches the substrate layer; anda field-effect transistor formed in an active region partitioned by the element isolation portion,wherein the field-effect transistor includesa channel region in the silicon layer,a gate insulating film formed over the channel region,a gate electrode formed over the gate insulating film, anda piled-up layer formed over the silicon layer,wherein the element isolation portion includes a projection portion that projects from the SOI substrate and comes into contact with the piled-up layer, andwherein a height of an upper surface of the projection portion is lower than or equal to a height of an upper surface of the piled-up layer and higher than or equal to a half of the height of the upper surface of the piled-up layer with reference to a surface of the silicon layer.2. The semiconductor device according to claim 1 ,wherein an end portion of the projection portion has a tapered shape.3. The semiconductor device according to claim 2 ,wherein a taper angle of the tapered shape is 45° or more.4. The semiconductor device according to claim 1 ,wherein an end surface of the projection portion is a vertical surface.5. The semiconductor device according to claim 4 ,wherein the height of the upper surface of the ...

Lateral Bipolar Junction Transistor With Multiple Base Lengths

A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask. 1. A structure , comprising:a substrate;a first bipolar junction transistor disposed on the substrate, the first bipolar junction transistor comprising a first emitter and a first collector, a first intrinsic base between the first emitter and the first collector, and a first extrinsic base on the first intrinsic base; anda second bipolar junction transistor disposed on the substrate, the second bipolar junction transistor comprising a second emitter and a second collector, a second intrinsic base between the second emitter and the second collector, and a second extrinsic base on the second intrinsic base;wherein a length of the first bipolar junction transistor is different from a length of the second bipolar junction transistor.2. The structure of claim 1 , further comprising an isolation structure between the first bipolar junction transistor and the second bipolar junction transistor.3. The structure of claim 2 , wherein the isolation structure comprises a dielectric material deposited in the ...

METHOD FOR FORMING TRANSISTOR STRUCTURES

According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:

EPITAXIAL GROWTH OF SILICON FOR FINFETS WITH NON-RECTANGULAR CROSS-SECTIONS

FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET. 1. A method comprising:forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate;epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region;forming a gate oxide over and perpendicular to each fin;forming a gate electrode over the gate oxide to form a FinFET; andperforming a well implantation between each pair of adjacent STI regions either prior to epitaxially growing the silicon-based layer, subsequent to epitaxially growing the silicon-based layer but prior to forming the gate oxide, or prior to anisotropically wet etching the silicon substrate,wherein the epitaxially grown silicon-based layer forms a fin with a diamond-shaped cross-section between each pair of adjacent STI regions, the diamond-shaped cross section comprising two sides meeting at a single point above the surface of the silicon substrate.2. The method of claim 1 , wherein the silicon substrate comprises a silicon-on-insulator (SOI) or bulk silicon substrate.3. The method of claim 1 , wherein the dielectric material is silicon dioxide (SiO).4. The method of claim 1 , wherein the epitaxially grown silicon-based layer is p-type or n-type doped silicon.5. The method of claim 1 , further ...

Field-effect transistors with a grown silicon-germanium channel

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first channel region containing a first semiconductor material and a second channel region containing a second semiconductor material are formed over a buried insulating layer of a silicon-on-insulator substrate. A first gate electrode of a first field-effect transistor is formed over the first channel region. A second gate electrode of a second field-effect transistor is formed over the second channel region. The first semiconductor material of the first channel region has a first germanium concentration. The second semiconductor material of the second channel region has a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region.

Shallow Trench Isolation for Integrated Circuits

The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners. 1. A structure , comprising:semiconductor structures formed on a substrate, wherein each semiconductor structure comprises sidewalls;an isolation structure between adjacent semiconductor structures comprising a first dielectric material embedded in a second dielectric material, wherein the first dielectric material is positioned along each sidewall of the semiconductor structures.2. The structure of claim 1 , further comprising an oxide layer interposed between the isolation structure and the sidewalls of the semiconductor structures.3. The structure of claim 1 , wherein the isolation structure further comprises a liner layer positioned at a bottom portion of the isolation structure in contact with the substrate and below the first dielectric material.4. The structure of claim 1 , wherein the semiconductor structures comprise a transistor structure formed thereon.5. The structure of claim 1 , wherein the isolation structure further comprises indentations on its top surface claim 1 , wherein each indentation is vertically aligned to the first dielectric material.6. The ...

Inverted Trapezoidal Recess for Epitaxial Growth

A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench. 1. A semiconductor device comprising:a semiconductor substrate;isolation trenches extending into the semiconductor substrate, wherein a recess in the semiconductor substrate extends between the isolation trenches, the recess having a bottom surface and sidewalls, the recess having sidewalls extending at an obtuse angle relative to the bottom surface of the recess, surfaces of the sidewalls having a (111) crystal orientation; anda compound semiconductor layer in the recess.2. The semiconductor device of claim 1 , wherein the semiconductor substrate has a (001) crystal orientation.3. The semiconductor device of claim 1 , wherein the compound semiconductor layer is a group III-V semiconductor layer.4. The semiconductor device of claim 3 , wherein the group III-V semiconductor layer comprises GaN.5. The semiconductor device of claim 1 , wherein the compound semiconductor layer comprises threading dislocations that extend from the sidewalls of the recess.6. The semiconductor device of claim 5 , wherein the threading dislocations terminate at sidewalls of the isolation trenches.7. The semiconductor device of claim 1 , wherein the sidewalls of the recess extend to a bottom of the isolation trenches.8. A method of forming a semiconductor device claim 1 , the method comprising:forming trenches in a substrate;filling the trenches with a dielectric material; ...

SEMICONDUCTOR DEVICE STRUCTURE WITH SELF-ALIGNED CAPACITOR DEVICE

A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode. 1. A semiconductor device structure , comprising:a semiconductor-on-insulator (SOI) substrate, said SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between said semiconductor layer and said substrate material;a trench isolation structure having a first uppermost surface positioned in at least a portion of said SOI substrate; a first electrode comprising a conductive layer portion positioned in said first region above said buried insulating material layer, the conductive layer portion at least partially replacing said semiconductor layer in said first region and having a first lowermost surface positioned at a depth lower than the first uppermost surface of said trench isolation structure and a second uppermost surface positioned at or below the first uppermost surface of said trench isolation structure;', 'a second electrode positioned above said first electrode; and', 'an insulating material formed between and contacting said first electrode and said second electrode., 'a capacitor device formed in a first region ...

SEMICONDUCTOR STRUCTURES INCLUDING STACKED DEPLETED AND HIGH RESISTIVITY REGIONS

Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent. 1. A structure comprising:a semiconductor substrate including a top surface, a first region and a second region each comprised of a single-crystal semiconductor material, and a third region comprised of a polycrystalline semiconductor material, the first region between the third region and the top surface, and the third region positioned relative to the top surface between the first region and the second region; anda first isolation band in the semiconductor substrate beneath the first region, the first isolation band comprising a first portion of the semiconductor substrate and a first concentration of a dopant in the first portion of the semiconductor substrate.2. The structure of wherein the first isolation band is positioned between the first region and the third region.3. The structure of wherein the first isolation band overlaps in part with the third region.4. The structure of wherein the second region is positioned beneath the third region claim 1 , and the first isolation band is positioned between the second region and the third region.5. The structure of wherein the first isolation band overlaps in part with the third region.6. The structure of wherein the first isolation band and the third region extend fully beneath an entirety of the first region.7. The structure of further comprising:trench isolation regions arranged to surround a device region representing a portion of the first region, ...

Isolation Structures

Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors. 1. A semiconductor structure , comprising:a first cell disposed over a first well doped with a first-type dopant, the first cell comprising a first plurality of transistors;a second cell disposed over the first well, the second cell comprising a second plurality of transistors; anda tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant, the tap cell being sandwiched between the first cell and the second cell.2. The semiconductor structure of claim 1 ,wherein the first cell comprises a first active region,wherein the second cell comprises a second active region,wherein the tap cell comprises a third active region,wherein the first active region, the second active region and the third active region are doped with the second-type dopant.3. The semiconductor structure of claim 2 , wherein the first-type dopant is n-type and the second-type dopant is p-type.4. The semiconductor structure of claim 2 , wherein the first-type dopant is p-type and the second-type dopant is n-type.5. The semiconductor structure of claim 1 , wherein the first well comprises a first shape that includes a base portion and at least one letter-shaped branch extending from the base portion.6. The semiconductor structure of claim 5 , wherein the second well comprises a second shape keyed to the first shape.7. The semiconductor structure of claim 5 , wherein each of the at least one letter-shaped branch is a T-shape portion.8 ...

Semiconductor structure with airgap

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

METAL GATE STRUCTURE AND METHODS OF FABRICATING THEREOF

A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer. 1. A semiconductor device , comprising:a first fin and a second fin each extending from a substrate, wherein the first fin and the second fin have a length extending in a first direction;a first metal gate over the first fin and a second metal gate over the second fin, wherein the first metal gate and the second metal gate having a length greater than a width, wherein the length extends in a second direction perpendicular the first direction;at least one dielectric layer adjacent the first metal gate and the second metal gate; anda cut region extending between the first and second metal gates, wherein the cut region has a first portion having a first width and a second portion having a second width, the second width greater than the first width and wherein the second portion interposes the first and second metal gates and the first portion is defined within the at least one dielectric layer, wherein the first width and the second width are measured from a top view.2. The semiconductor device of claim 1 , wherein a sidewall of the cut region that extends from the first portion to the second portion is disposed at an angle θ relative to a plane perpendicularly oriented to a length of the first fin and perpendicularly oriented to a top ...

INTEGRATED CIRCUITS WITH STRAINED SILICON AND METHODS FOR FABRICATING SUCH CIRCUITS

Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium. 1. An integrated circuit comprising:a stack comprising a surface layer, an intermediate layer, and a base layer, wherein the surface layer comprises crystalline silicon that is strained such that silicon atoms are stretched beyond a normal crystalline silicon interatomic distance, the intermediate layer comprises crystalline silicon germanium, and the base layer comprises crystalline silicon that is strained such that the silicon atoms are stretched beyond the normal crystalline silicon interatomic distance, wherein the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer, wherein the stack comprises a plurality of stack sides and a stack bottom;a support dielectric adjacent to the stack sides and the stack bottom, wherein the support dielectric comprises a gap.2. The integrated circuit of wherein the gap underlies the stack bottom.3. The integrated circuit of further comprising a shallow trench isolation dielectric claim 1 , wherein the support dielectric is positioned between the shallow trench isolation dielectric and the stack sides.4. The integrated circuit of wherein the shallow trench isolation dielectric comprises silicon oxide.5. The integrated circuit of wherein the shallow trench isolation dielectric comprises an etch resistant dopant.6. The integrated circuit of wherein the etch resistant dopant comprises carbon.7. The integrated circuit of wherein the support dielectric ...

BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region. 1. A structure comprising:a semiconductor substrate including a top surface, a first layer of polycrystalline semiconductor material, a second layer of polycrystalline semiconductor material, and a first layer of single-crystal semiconductor material, the first layer of polycrystalline semiconductor material arranged between the second layer of polycrystalline semiconductor material and the top surface, and the first layer of single-crystal semiconductor material separating the first layer of polycrystalline semiconductor material from the second layer of polycrystalline semiconductor material.2. The structure of wherein the semiconductor substrate includes a second layer of single-crystal semiconductor material that separates the first layer of polycrystalline semiconductor material from the top surface.3. The structure of further comprising:a field-effect transistor including a source/drain region arranged in the second layer of single-crystal semiconductor material.4. The structure of further comprising:a trench isolation region in the substrate;an interlayer dielectric layer arranged over the semiconductor substrate;a contact extending vertically through the interlayer dielectric layer to the source/drain region of the field-effect transistor; anda passive device arranged on the interlayer dielectric layer over the trench isolation region.5. The structure of further comprising:a trench isolation ...

MANUFACTURING METHOD OF ISOLATION STRUCTURE

A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer. 1. A manufacturing method of an isolation structure , comprising:providing a semiconductor substrate;forming a trench in the semiconductor substrate;performing a first film forming process to conformally form a first dielectric layer on the semiconductor substrate and in the trench;performing an annealing process to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; andperforming a second film forming process after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench, wherein the trench is filled with the second dielectric layer and the third dielectric layer.2. The manufacturing method of the isolation structure according to claim 1 , wherein the thickness of the first dielectric layer is larger than a thickness of the third dielectric layer.3. The manufacturing method of the isolation structure according to claim 1 , wherein the thickness of the second dielectric layer is larger than a thickness of the third dielectric layer.4. The manufacturing method of the isolation ...

Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method

A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.

INDUCTOR HEAT DISSIPATION IN AN INTEGRATED CIRCUIT

The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material. 1. A method comprising:forming a first dielectric layer on a semiconductor on insulator (SOI) layer of a SOI substrate, the SOI substrate comprising a buried insulator layer located between the SOI layer and a base substrate layer;forming a cavity trench through the first dielectric layer and the SOI layer, the cavity trench exposing the buried insulator layer;forming a cavity in the buried insulator layer;depositing a thermally conductive and electrically isolating material in the cavity;filling the cavity trench with the thermally conductive and electrically isolating material; andforming an inductor above the cavity.2. The method of claim 1 , further comprising:forming a back end of the line (BEOL) dielectric layer between the first dielectric layer and the inductor.3. The method of claim 1 , wherein the forming the cavity in the buried insulator layer comprises:removing a portion of the buried insulator layer between a first device and a second device selective to the base substrate layer and the SOI layer.4. The method of claim 1 , wherein the thermally conductive and electrically isolating material comprises aluminum nitride claim 1 , silicon claim 1 , silicon dioxide claim 1 , sapphire claim 1 , beryllium oxide claim 1 , or alumina.5. The method of claim 1 , wherein the ...

METHOD OF FABRICATING A TRANSISTOR CHANNEL STRUCTURE WITH UNIAXIAL STRAIN

Method for creation of stressed channel structure transistors wherein at least one amorphising ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows. 1. Method for creating stressed channel structure transistors comprising steps consisting of:forming a mask on a surface layer of a semiconductor-on-insulator type substrate comprising a support layer, an insulating layer separating the support layer from a surface layer, the surface layer being based on a semiconductor material stressed with a biaxial stress, the mask being formed from at least one block of elongated form arranged on a first zone of the surface layer, the first zone having a length measured parallel to a first direction and a width measured parallel to a second direction, the first zone being capable of forming a transistor channel structure wherein a current is meant to pass in the first direction, the mask being configured such that one or several openings of elongated form and which extend parallel to the first direction are arranged on either side of the masking block and respectively reveal the second zones of the surface layer arranged on either side of the first zone,execution of at least one ion implantation of the surface layer through the openings in the mask, so as to render the second zones amorphous and to induce relaxation of the first zone in the second direction,the method furthermore comprising a step consisting of transforming the second zones of the surface layer revealed by the openings of the mask into insulating zones.2. Method according to wherein the transformation of the second zones into insulating ...

FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE

Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate. 1. A method comprising:providing a silicon (Si) substrate having a buried oxide (BOX) layer formed over the substrate and a silicon-on-insulator (SOI) layer formed over the BOX layer;implanting a high current of dopants into at least one portion of the BOX layer;performing a high-temperature anneal of the BOX layer;forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, wherein the BOX layer below the first FDSOI transistors is either implanted with a first dopant, forming a high-k layer, or is non-implanted, and the BOX layer below the second FDSOI transistors is implanted with a second dopant, forming a high-k layer, the first and second dopants being different; andapplying a single voltage across a backside of the Si substrate,wherein the second dopant comprises hafnium (Hf), zirconium (Zr), titanium (Ti), or tantalum (Ta).2. The method according to claim 1 , comprising forming the BOX layer of silicon oxide (SiO claim 1 , 1 Подробнее

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region. 1. A manufacturing method of a semiconductor device comprising the steps of:(a) preparing a substrate that includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a semiconductor layer on the insulating layer, a first insulating film on the semiconductor layer, a trench penetrating the first insulating film, the semiconductor layer and the insulating layer so as to reach the semiconductor substrate, and an element isolation region embedded in the trench,the insulating layer, the first insulating film and the element isolation region being made of the same material as one another;(b) after the step (a), forming a first mask layer that covers the first insulating film in a first region of the substrate and exposes the first insulating film in a second region different from the first region of the substrate;(c) after the step (b), removing the first insulating film in the second region by dry etching with using the first mask layer as an etching mask, thereby exposing the semiconductor layer in the second region;(d) after the step (c), ...

METHOD OF JUNCTION CONTROL FOR LATERAL BIPOLAR JUNCTION TRANSISTOR

A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile. 1. A method , comprising:forming trench isolations in an intrinsic base semiconductor layer of a substrate, the substrate comprising the intrinsic base semiconductor layer located on a buried oxide layer, the buried oxide layer being located on a handle substrate;forming an extrinsic base layer on the intrinsic base semiconductor layer and the formed trench isolations;applying a mask to a portion of the extrinsic base layer;etching an exposed portion of the extrinsic base layer not masked;disposing a sidewall spacer on an exposed side of the extrinsic base layer and the mask;disposing a germanium layer adjacent the sidewall spacer;recessing the germanium layer and the intrinsic base semiconductor layer below the sidewall spacer to expose a vertical side of the intrinsic base semiconductor layer;implanting ions into an exposed vertical side of the intrinsic base semiconductor layer under the sidewall spacers to form a junction edge/profile;annealing the implanted ions; andepitaxially growing a doped Si or SiGe layer on the exposed vertical ...

Method Of Junction Control For Lateral Bipolar Junction Transistor

A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile. 1. A method , comprising:forming trench isolations in an intrinsic base semiconductor layer of a substrate, the substrate comprising the intrinsic base semiconductor layer located on a buried oxide layer, the buried oxide layer being located on a handle substrate;forming an extrinsic base layer on the intrinsic base semiconductor layer and the formed trench isolations;applying a mask to a portion of the extrinsic base layer;etching an exposed portion of the extrinsic base layer not masked;disposing a sidewall spacer on an exposed side of the extrinsic base layer and the mask;disposing a germanium layer adjacent the sidewall spacer;recessing the germanium layer and the intrinsic base semiconductor layer below the sidewall spacer to expose a vertical side of the intrinsic base semiconductor layer;implanting ions into an exposed vertical side of the intrinsic base semiconductor layer under the sidewall spacers to form a junction edge/profile;annealing the implanted ions; andepitaxially growing a doped Si or SiGe layer on the exposed vertical ...

SWITCH WITH LOCAL SILICON ON INSULATOR (SOI) AND DEEP TRENCH ISOLATION

The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures. 1. A structure comprising an air gap located within semiconductor material under a device region and bounded by an upper etch stop layer above the semiconductor material and deep trench isolation structures extending within the semiconductor material.2. The structure of claim 1 , wherein the etch stop layer is SiGe and the air gap is provided in an underlying substrate material.3. The structure of claim 2 , wherein the underlying substrate material is a high resistivity wafer.4. The structure of claim 2 , wherein the deep trench isolation structures extend into the underlying substrate material to a depth below the air gap and also completely surrounds the air gap.5. The structure of claim 1 , wherein the device region includes at least one FET device over a well formed on an epitaxial substrate claim 1 , on top of the etch stop layer claim 1 , and the air gap is self-aligned with the at least one FET device.6. The structure of claim 5 , wherein the well has a thickness of about 0.05 to 1 micron.7. The structure of claim 5 , wherein the at least one FET device comprises one of a switch claim 5 , at least one or more FET stacks claim 5 , one or more FET fingers; an H-gate claim 5 , a T-Body claim 5 , an isolated body contact.8. The structure of claim 1 , further comprising at least one vent via aligned with the air gap and the deep trench isolation structures claim 1 , the at least one vent via being filled with silicon material or dielectric material.9. The structure of claim 1 , wherein the air gap is partially filled.10. The structure of claim 1 , wherein the air gap is lined with a deposited material.11. The ...

METHOD FOR FABRICATING SEMICONDUCTOR LAYERS INCLUDING TRANSISTOR CHANNELS HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR LAYERS

Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods. 1. A method of forming a semiconductor structure , comprising: a base substrate;', 'a stressor layer above the base substrate comprising a crystallographically strained material;', 'a surface semiconductor layer; and', 'a dielectric layer disposed between the stressor layer and the surface semiconductor layer;, 'providing a semiconductor-on-insulator (SOI) substrate, the SOI substrate includingimplanting ions into or through at least a first region of the stressor layer without implanting ions into or through at least a second region of the stressor layer;forming an additional semiconductor material on the surface semiconductor layer above the at least a first region of the stressor layer;altering a strain state in a first region of the surface semiconductor layer above the at least a first region of the stressor layer;forming a trench structure through the surface semiconductor layer into at least a portion of the base substrate; andaltering a strain state in a second region of the surface semiconductor layer above the at least a second region of the stressor layer.2. The ...

UNIFORM HEIGHT TALL FINS WITH VARYING SILICON GERMANIUM CONCENTRATIONS

A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration. 1. A method of making a semiconductor device , the method comprising:forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; andforming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration;wherein the first concentration is different than the second concentration.2. The method of claim 1 , wherein the element is silicon.3. The method of claim 1 , wherein the element is germanium.4. The method of claim 1 , wherein the first fin and the second fin have substantially the same height.5. The method of claim 1 , wherein the first fin and the second fin are formed over a buried oxide layer disposed over the substrate.6. The method of claim 5 , wherein the substrate comprises silicon.7. The method of claim 1 , wherein the first fin has a height in a range from about 20 to about 150 nanometers (nm).8. The method of claim 7 , wherein the second fin has a height in a range from about 20 to about 150 nm.9. The method of claim 1 , further comprising growing a first epitaxial layer comprising silicon germanium over silicon and thermal mixing to form the first semiconducting material layer.10. The method of claim 9 , further comprising disposing a second ...

SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF

The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure. 1. A method of manufacturing a FINFET , comprising:forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation;oxidizing the fin structure and the layer to transform the layer into a first oxide layer;filling insulating material between adjacent fin structures; andetching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.2. The method of manufacturing a FINFET in claim 1 , wherein the oxidizing the fin structure and the layer to transform the layer into a first oxide layer transforms at least a portion of the fin structures into a second oxide layer.3. The method of manufacturing a FINFET in claim 1 , wherein the forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation comprises:depositing a silicon layer on the layer;patterning the silicon layer into the plurality of fin structures; andexposing a portion of the layer from a coverage of the silicon layer.4. The method of manufacturing a FINFET in claim 1 ...

DEEP TRENCH ISOLATION STRUCTURE IN SEMICONDUCTOR DEVICE

A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure. 1. A method , comprising:forming an isolation region between a plurality of active regions of a semiconductor substrate;forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate; andforming an interlayer dielectric layer over the semiconductor substrate, wherein the interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.2. The method of claim 1 , wherein the forming the isolation region between the active regions comprises:forming a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region is spaced apart by a dummy active region.3. The method of claim 2 , wherein the forming the deep trench comprises:etching at least the dummy active region and the semiconductor substrate to form the deep trench.4. The method of claim 3 , wherein the dummy active region is entirely removed by the etching.5. The method of claim 1 , wherein the semiconductor substrate comprises a handle substrate claim 1 , a semiconductor layer over the handle substrate claim 1 , and a buried insulator layer between the handle substrate and the semiconductor layer; andwherein the forming the deep trench comprises:etching at least the isolation region, the buried insulator layer, and the handle substrate to form the deep trench.6. The method of claim 1 , wherein the deep trench has an aspect ratio larger than about 4.5.7. The method of ...

OXIDE SPACER IN A CONTACT OVER ACTIVE GATE FINFET AND METHOD OF PRODUCTION THEREOF

A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures. 1. A device comprising:first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin, wherein the first gate structures comprise: a high-k/metal gate (HKMG) layer; and a sidewall spacer on each sidewall of the HKMG layer, wherein upper surface of the sidewall spacers is substantially coplanar to upper surface of the metal layer;a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures;a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures;a metal layer over the metal liner; andan interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.2. The device according to claim 1 , wherein the first and second gate structures comprises:a high-k/metal gate (HKMG) layer;a cap layer over the HKMG layer; anda sidewall spacer on each sidewall of the HKMG layer and the cap layer, wherein upper surface of the sidewall spacers adjacent to the first and second RSD is substantially coplanar to upper surface of the metal layer.3. ...

METHOD FOR MANUFACTURING A HYBRID SOI/BULK SEMICONDUCTOR WAFER

A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings. 1. A method for manufacturing a hybrid SOI/bulk substrate , comprising the steps of:a) starting from an SOI wafer comprising a single-crystal semiconductor SOI layer, on an insulating layer, on a single-crystal semiconductor substrate;b) depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate;c) growing, without forming spacers, by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material, up to the desired final level; andd) etching insulating trenches surrounding said openings filled with semiconductor material while encroaching inwards over the periphery of the openings.2. The method of claim 1 , wherein step c) is carried on until the central portion of the upper surface of the semiconductor material is at the same level as the upper surface of the SOI layer.3. The method of claim 1 , wherein the semiconductor material of the substrate and that of the SOI layer are silicon.4. The method of claim 1 , wherein the thickness of the SOI layer ranges between 3 and 10 nm.5. The method of claim 1 , wherein the thickness of the insulating layer ranges between 5 and 50 nm.6. The method of claim 3 , wherein the masking layer comprises a stack of a layer of a silicon ...

Transistor structure with overlying gate on polysilicon gate structure and related method

Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

INTEGRATED CIRCUIT DEVICE

An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.