PROCEDURE FOR THE PRODUCTION OF A FILM WITH EXTREME OF LOW DIELECTRIC CONSTANT

GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

A method to obtain thin (<300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. <106 cm-2. The approach begins with the growth of a pseudomorphic Si1-x Gex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

CARBON NANOSTRUCTURE DEVICE FABRICATION UTILIZING PROTECT LAYERS

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing. 114-. (canceled)15. A device structure comprising:an insulating substrate;a first patterned layer of carbon-based nanostructure layer on said substrate;a first patterned layer of a first metal on said first patterned carbon based-nanostructure layer; anda plurality of spaced apart contacts having a portion on said patterned metal layer and a portion on said insulating substrate, said first patterned carbon-based nanostructure layer having regions not covered by said first patterned layer of a first metal.16. The device structure of wherein said carbon-based nanostructure layer is selected from the group consisting of carbon-nanotubes and graphene.17. The device structure of further including a gate dielectric positioned above said carbon-based nanostructure layer claim 15 , anda gate electrode positioned above said gate dielectric.18. The device structure of further including a gate dielectric positioned below said carbon-based nanostructure layer claim 15 , and a gate electrode positioned below said gate dielectric.19. A method for forming a device structure comprising:selecting an insulating substrate having a carbon-based nanostructure layer on an upper surface;forming a first layer of a first metal on said carbon-based nanostructure layer;forming a first patterned layer having a first pattern on said first layer of a first metal;transferring said first pattern to said first layer of a first metal and said carbon-based nanostructure layer to form a first patterned layer of a first metal and a first patterned carbon-based nanostructure layer there under;removing said first patterned layer;forming a layer of first material over said insulating substrate and said first patterned layer of a first metal, ...

MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

OPTICAL MEMORY DEVICE

PROBLEM TO BE SOLVED: To obtain an optical memory medium based on completely novel memory principle and to obtain an optical memory device using this medium by recording data corresponding to characteristics of an amorphous solid selected from a group of materials each having refractive index and reflectance. SOLUTION: The amorphous solid is selected from a group of diamond-like carbon, silicon carbide, boron carbide, boron nitride, amorphous silicon and amorphous germanium, and the solid contains hydrogen by up to 50 atm% with covalent bonds. A specified region of the amorphous solid having a first refractive index and having atoms with covalent bonds is heated with laser light to change the refractive index in the heated area to a second refractive index. Thus, two states can be produced to correspond the memory of data without dissolving or crystallizing the amorphous solid. The density of the solid is changed by heating, which accompanies changes in the refractive index and reflectance ...

Doppelschicht-Gate-Dielektrikum mit geringer äquivalenter Oxiddicke für Graphen-Bauelemente

Auf einer Oberseite einer Graphenschicht wird eine Siliciumnitridschicht bereitgestellt, und dann wird auf einer Oberseite der Siliciumnitridschicht eine Hafniumdioxidschicht bereitgestellt. Die Siliciumnitridschicht wirkt als ein Benetzungsmittel für die Hafniumdioxidschicht und verhindert dadurch die Bildung von diskontinuierlichen Hafniumdioxidsäulen über der Graphenschicht. Die Siliciumnitridschicht und die Hafniumdioxidschicht, die zusammen ein Doppelschicht-Gate-Dielektrikum mit geringer äquivalenter Oxiddicke (EOT) bilden, weisen über der Graphenschicht eine kontinuierliche Morphologie auf.

STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge- ON-INSULATOR PHOTODETECTOR

The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high- quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge ...

Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD

A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <10²⁰ cm^-3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

ULTRA LOW k PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES USING A SINGLE BIFUNCTIONAL PRECURSOR CONTAINING BOTH A SiCOH MATRIX FUNCTIONALITY AND ORGANIC POROGEN FUNCTIONALITY

A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6-Si-O-Si-R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12-Si-O-Si-R13R14-O-Si-R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.

CONTROL OF CARBON NANOTUBE DIAMETER USING CVD OR PECVD GROWTH

The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.

MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE

The present invention provides a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD. The inventive composite material is also characterized by the substantial absence of the broad distribution of larger sized pores which is prevalent in prior art porous composite materials. The porous composite material includes a first solid phase having a first characteristic dimension and a second solid phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.

RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING

THIN FILM MAGNETIC HEAD HAVING A PROTECTIVE COATING AND METHOD FOR MAKING SAME

LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES

Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure. 1. A semiconductor device comprising:a semiconductor body;a gate stack disposed atop the semiconductor body; anda boron nitride spacer in direct contact with sidewalls of the gate stack and at least a portion of the semiconductor body.2. The semiconductor device of claim 1 , wherein the boron nitride spacer has a hexagonal textured structure claim 1 , and the boron nitride spacer either includes an amorphous region which is less than or equal to 5 nm thick or includes no amorphous region.3. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises stoichiometric boron nitride.4. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises boron nitride that has an oxygen content less than or equal to five atomic percent claim 1 , and boron nitride that claim 1 , after performing reactive ion etching claim 1 , has a dielectric constant greater than or equal to 3 and less than or equal to 4.5.5. The semiconductor device of claim 1 , wherein the semiconductor body comprises at least one of the following: silicon germanium (SiGe) claim 1 , germanium (Ge) claim 1 , and a III-V compound.6. The semiconductor device of claim 1 , wherein the semiconductor body comprises a silicon layer claim 1 , atop a silicon-on-insulator (SOI) layer having a buried oxide ( ...

Self-aligned composite M-MOx/dielectric cap for Cu interconnect structures

An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes an interconnect dielectric material having a dielectric constant of about 4.0 or less. The interconnect dielectric material has at least one opening therein that is filled with a Cu-containing material. The Cu-containing material within the at least one opening has an exposed upper surface that is co-planar with an upper surface of the interconnect dielectric material. The interconnect structure further includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal. The interconnect structure further includes a dielectric ...

DIELECTRIC MATERIAL, INTERCONNECT STRUCTURE, ELECTRONIC STRUCTURE, ELECTRONIC SENSING STRUCTURE AND ITS MAKING METHOD (SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME)

PROBLEM TO BE SOLVED: To provide a low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures. SOLUTION: The low-k dielectric material includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si-CH3 functional groups, and another fraction of the C atoms are bonded as Si-R-Si, wherein R is phenyl, -[CH2]n-, (n is greater than or equal to 1), HC=CH, C=CH2, C≡C or a [S]n linkage, (n is as defined above). COPYRIGHT: (C)2006,JPO&NCIPI ...

High dielectric constant capacitor electrode structure for Gbit or higher integrated DRAM

The electrode structure (10) includes a substrate (26) with a free surface semiconductor layer (27), metal (31) and metal oxide (32) layers. The metal layer is formed from a chosen one of the group Ru, Ir, Re, Rh, Os, Pd. The metal oxide layer is chosen from the same metallic group as the initial metal. A further metallic layer (33) over the oxide layer is formed of metal from the same group. The semiconductor layer is of Silicon or Germanium. Included above the metal and metal oxide layers is a further layer having a high dielectric constant (16). The dielectric material is an oxide of ferroelectric or para-electric material such as BaxSr(1-x)TiO3 or PbZr3Ti(1-x)O3 and a fifth layer of conducting material.

STRUCTURE AND PROCEDURE FOR THE PRODUCTION OF A CMOS-COMPATIBLE HIGH-SPEED GEO INSULATOR PHOTODETECTOR

THIN FILM MAGNETIC HEAD HAVING A PROTECTIVE COATING AND METHOD FOR MAKING SAME

A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer and a thin layer of amorphous hydrogenated carbon. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.

AN ULTRALOW DIELECTRIC CONSTANT MATERIAL AS AN INTRALEVEL OR INTERLEVEL DIELECTRIC IN A SEMICONDUCTOR DEVICE

There is provided a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms and having a covalently bonded tri-dimensional network structure and a dielectric constant of not more than 2.6. The dielectric constant film may additionally have a covalently bonded ring network. The covalently bonded tri-dimensional (i.e., three dimensional) network structure comprises Si-O, Si-C, Si-H, C-H and C-C covalent bonds and may optionally contain F and N. In the film, the Si atoms may optionally be partially substituted with Ge atoms. The dielectric constant film has a thickness of not more than 1.3 micrometers and a crackpropagation velocity in water of less than 10-10 meters per second. There is further provided a back- end-of-the-line (BEOL) interconnect structure comprising the inventive dielectric film as a BEOL insulator, cap or hardmask layer. © KIPO & WIPO 2007 ...

ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES

Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including ...

GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. 1. A method of forming a semiconductor structure comprising:providing at least one silicon carbide fin having at least bare sidewalls on a surface of a substrate;forming a graphene nanoribbon on each bare sidewall of said silicon carbide fin, wherein said forming said graphene nanoribbon includes annealing at a temperature from 1200° C. up to, but not beyond the melting point of said substrate; andforming at least a gate structure adjacent said graphene nanoribbon.2. The method of wherein said providing said at least one silicon carbide fin comprises:providing a silicon carbide-on-insulator substrate; andpatterning a silicon carbide layer on said silicon carbide-on-insulator substrate.3. The method of wherein said providing said at least one silicon carbide fin comprises:forming at least one silicon fin from a silicon layer of a silicon-on-insulator substrate, andepitaxial growing a silicon carbide fin on each sidewall of said silicon fin.4. The method of further comprising removing said silicon fin after said silicon carbide fin is grown.5. The method of wherein prior to forming said graphene nanoribbon a portion of said substrate located directly beneath said at least one silicon carbide fin is removed providing at least one suspended silicon carbide nanowire.6. The method of wherein ...

Graphene cap for copper interconnect structures

Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Carbon-on-insulator substrates by in-place bonding

An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.

Graphene nanoribbons and carbon nanotubes fabricated from sic fins or nanowire templates

Relaxed sige layers on si or silicon-on-insulator substrates by ion implantation and thermal annealing

Tunable and removable plasma deposited antireflective coatings

Disclosed is vapor deposited BARC and method of preparing tunable and removable antireflective coatings based on amorphous carbon films. These films can be hydrogenated, fluorinated, nitrogenated carbon films. Such films have an index of refraction and an extinction coefficient tunable from about 1.4 to about 2.1 and from about 0.1 to about 0.6, respectively, at UV and DUV wavelengths, in particular 365, 248 and 193 nm. Moreover, the films produced by the present invention can be deposited over device topography with high conformality, and they are etchable by oxygen and/or a fluoride ion etch process. Because of their unique properties, these films can be used to form a tunable and removable antireflective coating at UV and DUV wavelengths to produce near zero reflectance at the resist/BARC coating interface. This BARC greatly improves performance of semiconductor chips.

ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS

A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

FLIP FERAM CELL AND METHOD TO FORM SAME

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices

An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Bilayer gate dielectric including silicon nitride and hafnium oxide continuously covering graphene layer in semiconductor structure

A silicon nitride layer 16 is provided on an uppermost surface of a graphene layer 14 and then a hafnium dioxide layer 18 is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. The graphene layer can be epitaxially grown on a substrate which may be silicon carbide. The silicon nitride layer may be a tensile silicon nitride layer. A portion of the graphene layer may serve as a channel layer for a FET. The graphene layer may be in contact with source and drain regions of an FET 56, 58. A gate conductor 54 may be located on the hafnium oxide layer. The dielectric bilayer may cover the sides and the top of the source drain regions.

Transferable device-containing layer for silicon-on-insulator applications

A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a "transferable" device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least ...

Methods to mitigate plasma damage in organosilicate dielectrics

Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

LOW DIELECTRIC CONSTANT MATERIAL, ITS MANUFACTURING METHOD, AND INTERCONNECTION STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME

PROBLEM TO BE SOLVED: To provide a thermally stable low dielectric constant material having a low internal stress and a dielectric constant of not higher than 2.8. SOLUTION: A low dielectric constant material has a matrix made of Si, C, O, and H; a plurality of nanometre-scale holes, and a dielectric constant of not higher than 2.8. The low dielectric constant material has an FTIR spectrum which is divided into two peaks in absorption band of Si-O between 1,000 cm-1 and 1,100 cm-1, and has not absorption peak of Si-H between 2,150 cm-1 and 2,250 cm-1. COPYRIGHT: (C)2007,JPO&INPIT ...

Graphene nanoribbons and carbon nanotubes fabricated from sic fins or nanowire templates

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Method and materials for through-mask electroplating and selective base removal

Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited ...

Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same

A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcyclotetrasiloxane and cyclopentene oxide.

GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE

A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry. 1. A structure comprising a graphene layer including at least one graphene monolayer , wherein said graphene layer is located directly on a crystallographic surface having a non-hexagonal symmetry.2. The structure of claim 1 , wherein said crystallographic surface has a rectangular symmetry.3. The structure of claim 1 , wherein said crystallographic surface is a surface of a crystalline semiconductor carbide layer.4. The structure of claim 3 , wherein said crystalline semiconductor carbide layer is a single crystalline silicon carbide layer or a polycrystalline silicon carbide layer having grains claim 3 , wherein said grains have a same crystallographic orientation and a same surface orientation.5. The structure of claim 4 , wherein said single crystalline silicon carbide layer is a single crystalline silicon carbide layer in beta phase having zinc blende structure.6. The structure of claim 5 , wherein said crystallographic surface is a (100) surface of said single crystalline silicon carbide layer in said beta phase.7. The structure of claim 3 , wherein said crystalline semiconductor carbide layer ...

Hydrogenated oxidized silicon carbon material

A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same

A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made

A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

STRUKTUR UND VERFAHREN FÜR DIE HERSTELLUNG EINES CMOS-KOMPATIBLEN HOCHGESCHWINDIGKEITS-GE-ON-ISOLATOR-PHOTODETEKTORS

Ultralow dielectric constant layer with controlled biaxial stress

A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Method for fabricating an ultralow dielectric constant material

A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide. To stabilize plasma in the PECVD reactor and thereby improve uniformity of the deposited film, CO2 is added to TMCTS as a carrier gas, or CO2 or a mixture of CO2 and O2 are added to the PECVD reactor.

Bilayer gate dielectric with low equivalent oxide thickness for graphene devices

Method for forming dielectric film and dielectric film

An improved method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made

Accurate control of distance between suspended semiconductor nanowires and substrate surface

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Graphene-containing semiconductor structures and devices on a silicon carbide substrate having a defined miscut angle

A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.

Continuous metal semiconductor alloy via for interconnects

A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.

Multilayer interconnect structure containing air gaps and method for making

A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Graphene growth on a non-hexagonal lattice

A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

Multi component dielectric layer

An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, SiB+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.

ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES

A method for fabricating an ultra low dielectric constant material is disclosed. The method includes placing a substrate into a deposition reactor. A first precursor is flowed into the deposition reactor. The first precursor is a matrix precursor. A second precursor is flowed into the deposition reactor. The second precursor is a porogen precursor. A preliminary film is deposited onto the substrate based on the first and second precursors. The preliminary film includes Si, C, O, and H atoms. A first ultraviolet curing step is performed on the substrate including the preliminary film at a first temperature. At least a second ultraviolet curing step is performed on the substrate including the preliminary film at a second temperature.

Verfahren zur Herstellung von Speicherkondensatoren unter Verwendung von Materialien mit hoher Dielektrizitätskonstante

Methods to form SiCOH or SiCNH dielectrics and structures including the same

Methods of forming dielectric films comprising Si, C, O and H atoms (SiCOH) or Si, C, Nand H atoms (SiCHN) that have improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking , cu ingress, and other critical properties are provided. Electronic structures including the above materials are also included herein.

Low K and ultra low K SiCOH dielectric films and methods to form the same

Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Methods to mitigate plasma damage in organosilicate dielectrics

Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH

Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Kohlenstoffreiche Carbobornitriddielektrikum-Dünnschicht für die Verwendung in elektronischen Einheiten und Verfahren zur Herstellung der kohlenstoffreichen Carbobornitriddielektrikum-Dünnschicht

Dielektrikum-Dünnschicht mit einer Formel CBN, wobei x 35 Atomprozent oder mehr beträgt, y von 6 Atomprozent bis 32 Atomprozent beträgt und z von 8 Atomprozent bis 33 Atomprozent beträgt, wobei die Dielektrikum-Dünnschicht eine Porosität aufweist.

AN ULTRALOW DIELECTRIC CONSTANT MATERIAL AS AN INTRALEVEL OR INTERLEVEL DIELECTRIC IN A SEMICONDUCTOR DEVICE

Interconnection and its forming method

An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film maybe separated by an intermediate film.

Flip FERAM cell and method to form same

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS

Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. 1. A method for fabricating an interconnect structure comprising:forming an intermetal dielectric layer on a substrate;forming a hard mask directly on said intermetal dielectric layer;forming a via hole within said hard mask and within said intermetal dielectric layer and filling a lower portion of said via hole with a disposable via fill material;forming a line trench in said intermetal dielectric layer over said via hole;forming a sacrificial layer on sidewalls of said line trench and on sidewalls of an upper portion of said via hole, while keeping a bottom surface of said line trench nominally exposed, wherein said sacrificial layer includes a polymeric material containing carbon, hydrogen, fluorine, and silicon; andperforming a plasma strip to remove said disposable via fill material, while portions of said intermetal dielectric layer underneath said sidewalls of said line trench and underneath sidewalls of an upper portion of said via hole are protected by said sacrificial layer from damage during said plasma strip, wherein said sacrificial layer is consumed during said plasma strip.2. The method of claim 1 , wherein said sacrificial layer is formed by a ...

On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacity

An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.

EPITAXIAL GROWTH OF SILICON CARBIDE ON SAPPHIRE

remove impurities from an exposed surface in the ultrahigh vacuum environment. A high qualify single crystalline or polycrystalline silicon carbide film can be grown directly on the sapphire substrate by chemical vapor deposition employing a silicon-containing reactant and a carbon-containing reactant. Formation of single crystalline silicon carbide has been verified by x-ray diffraction, secondary ion mass spectroscopy, and transmission electron microscopy. 1. A method of forming a semiconductor-carbon alloy layer on a sapphire substrate , said method comprising:placing a sapphire substrate in a vacuum environment; andproviding a semiconductor-containing precursor and a carbon-containing precursor into said vacuum environment, wherein a single crystalline semiconductor-carbon alloy layer is epitaxially formed directly on a crystallographic surface of said sapphire substrate.2. The method of claim 1 , wherein an entirety of said sapphire substrate is single crystalline.3. The method of claim 1 , wherein said semiconductor-containing precursor includes silicon and said carbon-containing precursor includes carbon and hydrogen.4. The method of claim 3 , wherein said semiconductor-containing precursor is selected from SiH claim 3 , SiH claim 3 , SiHCl claim 3 , SiHCl claim 3 , SiHCl claim 3 , and SiCl.5. The method of claim 3 , wherein said carbon-containing precursor is selected from CH claim 3 , CH claim 3 , C claim 3 , and CH claim 3 , wherein n is an integer greater than 2.6. The method of claim 3 , wherein said vacuum environment is provided by an ultrahigh vacuum chamber having a base pressure less than 1.0×10Ton.7. The method of claim 1 , wherein said single crystalline semiconductor-carbon alloy layer is a single crystalline silicon-carbon alloy layer.8. The method of claim 7 , wherein said single crystalline semiconductor-carbon alloy layer has an atomic carbon concentration from 40% to 60%.9. The method of claim 8 , wherein said single crystalline ...

Multilayer dielectric structures for semiconductor nano-devices

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Magnetkopfgleitstück und sein Herstellungsverfahren

Verfahren zur Herstellung und Anordnung von Speicherkondensatoren unter Verwendung von Materialien mit hoher Dielektrizitätskonstante

FERAM CELL WITH INTERNAL OXYGEN SOURCE LAYER AND METHOD FOR OUTPUTTING OXYGEN

PURPOSE: A ferroelectric capacitor and a ferroelectric/CMOS integrated structure are provided to have high storage characteristics. CONSTITUTION: The structure comprises at least a ferroelectric material(22), a pair of electrodes(20, 24) contacting opposite surfaces of the ferroelectric material(20), and an oxygen source layer(26) contacting at least one of electrodes(22, 24). COPYRIGHT 2001 KIPO ...

Multiphase low dielectric constant material and method of deposition

A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.

LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT

A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CH)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond. 1. A method of fabricating a porous dielectric film comprising:forming a dielectric film comprises elements of Si, C, H and O on a surface of a substrate, said dielectric film having a dielectric constant of about 2.7 or less, a random covalently bonded tri-dimensional network and a multiplicity of nano-sized pores, wherein said pores include at least one of Si—OH groups and Si—H groups therein; and{'sub': x', '3, 'annealing said dielectric film in a gaseous ambient that includes at least one C—C double bond, at least one C—C triple bond or a combination of at least one C—C double bond and at least one C—C triple bond, wherein said annealing forms crosslinking —(CH)— chains within the pores, wherein x is 1, 2 or 3, that bond with at least one Si group that is formed by reaction between an unsaturated hydrocarbon with Si—OH groups originally present in said pores, wherein said gaseous ambient is selected from the group consisting of an organosilicon compound with fully hydrophobic bonds and with a low strained Si—O—Si bonding structure or with single vinyl double bond (C═C) groups, and a compound having an organosilicon group (R)—Si—OH with silanol group bonding wherein R is the same or ...

Aus SiC-Finnen oder Nanodrahtvorlagen gefertigte Graphennanobänder und Kohlenstoff-Nanoröhren

Halbleiterstrukturen, die parallele Graphennanobänder oder Kohlenstoff-Nanoröhren aufweisen, die entlang kristallographischer Richtungen ausgerichtet sind, werden aus einer Vorlage aus Siliciumcarbid(SiC)-Finnen oder -Nanodrähten bereitgestellt. Die SiC-Finnen oder -Nanodrähte werden zuerst bereitgestellt, und anschließend werden durch Tempern Graphennanobänder oder Kohlenstoff-Nanoröhren auf den freigelegten Flächen der Finnen oder der Nanodrähte ausgebildet. Bei Ausführungsformen, bei denen geschlossene Kohlenstoff-Nanoröhren ausgebildet werden, werden die Nanodrähte vor dem Tempern frei hängen gelassen. Der Ort, die Ausrichtung und die Chiralität der Graphennanobänder und der Kohlenstoff-Nanoröhren, die bereitgestellt werden, werden durch die entsprechenden Siliciumcarbidfinnen und -Nanodrähte bestimmt, aus denen sie ausgebildet werden.

Halbleiterstruktur mit Doppelschicht-Gate-Dielektrikum mit geringer äquivalenter Oxiddicke, Graphen-Halbleiterbauelemente und ein Verfahren

Halbleiterstruktur, aufweisend: eine Graphenschicht (14), die auf einer Oberseite (12) eines Grundsubstrats (10) angeordnet ist; und ein Doppelschicht-Gate-Dielektrikum, das auf einer Oberseite (12) der Graphenschicht (14) angeordnet ist, wobei das Doppelschicht-Gate-Dielektrikum, von unten nach oben, eine Siliciumnitridschicht (16) auf der Oberseite (12) der Graphenschicht (14) bereitstellt und eine auf einer Oberseite (12) der Siliciumsnitridschicht (16) bereitgestellte HfO2-Schicht (18) einschließt, wobei die Siliciumnitridschicht (16) und die HfO2-Schicht (18) über der Oberseite (12) der Graphenschicht (14) kontinuierlich vorhanden sind.

Low dielectric constant amorphous fluorinated carbon and method of preparation

An amorphous fluorinated carbon film for use as a dielectric insulating layer in electrical devices is formed from a fluorinated cyclic hydrocarbon precursor. The precursor may be selected from the group consisting of hexafluorobenzene, 1,2-diethynyltetrafluorobenzene and 1,4-bis(trifluoromethyl) benzene. The film is deposited by a radiation or beam assisted deposition technique such as an ion beam assisted deposition method, a laser assisted deposition method, or a plasma assisted chemical vapor deposition method. The film is thermally stable in non-oxidizing environment at temperatures up to 400° C. and has a low dielectric constant of less than 3.0. The film can be suitably used as an insulator for spacing apart conductors in an interconnect structure.

Method of forming a graphene cap for copper interconnect structures

Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Low k and ultra low k SiCOH dielectric films and methods to form the same

Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Advanced low k cap film formation process for nano electronic devices

A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. The inventive dielectric film is highly robust to UV curing and remains compressively stressed after UV curing. Moreover, the inventive dielectric film has good oxidation resistance and prevents metal diffusion into an interconnect dielectric layer. The present invention also provides an interconnect structure including the inventive dielectric film as a dielectric cap. A method of fabricating the inventive dielectric film is also ...

On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacityy

An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.

On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacityy

Graphene growth on a carbon-containing semiconductor layer

A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

Flip FERAM cell and method to form same

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

Interlevel dielectric stack for interconnect structures

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

Structure and fabrication method for non-planar memory elements

Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

Ionic liquid composition

The present invention relates to an ionic liquid comprising (i) one or more nitrogen-free organic cations, each comprising a central atom or cyclic system having a cationic charge and a plurality of pendant hydrocarbyl substituents, and (ii) one or more halogen-free and boron-free organic anions, each comprising an aromatic ring bearing a carboxylate function and another heteroatom-containing function, the functional groups are conjugated to an aromatic ring and the conjugated system is anionic charged, and the aromatic ring additionally carries one or more hydrocarbyl substituents. The ionic liquid can be used as an additive to extend the service life of hydrocarbon liquids exposed to nitrogen dioxide contamination and provide friction and wear reduction.

RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING

A method to obtain thin (less than 300 nm) strain-relaxed SiGe buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10cm. The approach begins with the growth of a pseudomorphic or nearlypseudomorphic SiGe layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/SiGe interface, parallel to the Si(001) surface.621-xx1-xx1-xx © KIPO & WIPO 2007 ...

Enhanced T-gate structure for modulation doped field effect transistors

A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

CARBON NANOSTRUCTURE DEVICE FABRICATION UTILIZING PROTECT LAYERS

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same

A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si-CH₃ functional groups, and another fraction of the C atoms are bonded as Si-R-Si, wherein R is phenyl, -[CH₂]_n- where n is greater than or equal to 1, HC-CH, C-CH₂, C-C or a [S]_n linkage, where n is a defined above.

Multiphase low dielectric constant material and method of deposition

A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.

MICROWAVE PLASMA AND ULTRAVIOLET ASSISTED DEPOSITION APPARATUS AND METHOD FOR MATERIAL DEPOSITION USING THE SAME

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

MULTIPHASE LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF DEPOSITION

A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed. © KIPO & WIPO 2007 ...

Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device

There is provided a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms and having a covalently bonded tri-dimensional network structure and a dielectric constant of not more than 2.6. The dielectric constant film may additionally have a covalently bonded ring network. The covalently bonded tri-dimensional (i.e., three dimensional) network structure comprises Si-O, Si-C, Si-H, C-H and C-C covalent bonds and may optionally contain F and N. In the film, the Si atoms may optionally be partially substituted with Ge atoms. The dielectric constant film has a thickness of not more than 1.3 micrometers and a crack propagation velocity in water of less than 10<-10 >meters per second. There is further provided a back-end-of-the-line (BEOL) interconnect structure comprising the inventive dielectric film as a BEOL insulator, cap or hardmask layer.

ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES

A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.

Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

STRUCTURE AND METHOD FOR SICOH INTERFACES WITH INCREASED MECHANICAL STRENGTH

Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration. COPYRIGHT KIPO & WIPO 2010 ...

GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE

A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry. 1. A method of forming a graphene layer including at least one graphene monolayer , said method comprising forming a graphene layer directly on a crystallographic surface having a non-hexagonal symmetry.2. The method of claim 1 , wherein said crystallographic surface has a rectangular symmetry.3. The method of claim 1 , wherein said crystallographic surface is a surface of a crystalline semiconductor carbide layer.4. The method of claim 3 , wherein said crystalline semiconductor carbide layer is a crystalline silicon carbide layer.5. The method of claim 4 , wherein said crystalline semiconductor carbide layer is a polycrystalline silicon carbide layer having a beta phase and a plurality of (100) crystallographic surfaces.6. The method of claim 4 , wherein said crystalline semiconductor carbide layer is a single crystalline silicon carbide layer having a beta phase and a (100) crystallographic surface.7. The method of claim 3 , wherein said crystalline semiconductor carbide layer is formed directly on a single crystalline semiconductor layer prior to forming said graphene layer.8. The method of claim 7 , ...

MULTI COMPONENT DIELECTRIC LAYER

An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. 1. A method for forming a dielectric structure comprising:placing a substrate in a chamber for performing one of plasma enhanced chemical vapor deposition and plasma enhanced atomic layer deposition,flowing a vapor including at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, a N containing precursor, and an inert gas into said chamber,heating said substrate in said chamber in the range from 100° C. to 450°,initiating a plasma in said chamber to form a first component comprising at least one of SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH on said substrate,while maintaining said plasma, reducing the flow of said N containing precursor to substantially zero while maintaining said flow of said at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor and said inert gas, andflowing an oxidant gas into said chamber to form a second component adjacent said first component, said second component comprising at least one of SiCOH, p-SiCOH, p-SiCNH, p-BN, p-BNH, p-CBN and p-CBNH.2. The method of wherein said N containing precursor comprisesammonia, and said Si and C containing precursor is selected from the group consisting of trimethylsilane, tetramethylsilane, dimethylsilacyclopentane (DMSCP) and disilacyclobutane.3. The method of wherein said ...

Graphene nanoribbons, method of fabrication and their use in electronic devices

The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Formation of a graphene layer on a large substrate

A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS

Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion. 1. A method of forming a semiconductor structure comprising:providing at least one field effect transistor on a surface of a semiconductor substrate, said at least one field effect transistor including at least a gate electrode, a source region and a drain region;forming a semiconductor nanowire from at least a surface of said source region and a surface of said drain region;converting an upper portion of the source region and the drain region and the semiconductor nanowire into a continuous metal semiconductor alloy, said continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of said source and drain regions, and a vertical pillar portion extending upwardly from said lower portion; andforming a metal line on an upper surface of the vertical pillar portion.2. The method of wherein said forming said semiconductor nanowire includes forming a catalyst dot on at least said surfaces of said source region and said drain region and perpendicularly growing said semiconductor nanowires from a semiconductor nanowire precursor claim 1 , wherein during said growing a metallic semiconductor liquid alloy is formed on a tip of each growing semiconductor nanowire.3. The method of wherein said catalysts dot includes gold particles.4. The method of wherein after growing said semiconductor nanowires ...

SELF-ALIGNED COMPOSITE M-MOx/DIELECTRIC CAP FOR Cu INTERCONNECT STRUCTURES

An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal.

SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME

A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons. 1. A semiconductor structure comprising:a substrate having an upper surface; andan ordered array of parallel graphene nanoribbons located on the upper surface of the substrate.2. The semiconductor structure of wherein said substrate is a dielectric material claim 1 , and said dielectric material comprises glass claim 1 , SiO claim 1 , SiN claim 1 , organosilicate glass claim 1 , SC:H claim 1 , SiCN:H claim 1 , plastic claim 1 , diamond-like carbon claim 1 , boron nitride (BN) claim 1 , carbon boron nitride (CBN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride.3. The semiconductor structure of wherein dielectric material is a top layer of a multilayer stack.4. The semiconductor structure of wherein said substrate is a semiconductor material claim 1 , and said semiconductor material comprises Si claim 1 , SiGe claim 1 , SiGeC claim 1 , SiC claim 1 , Ge alloys claim 1 , GaAs claim 1 , InAs claim 1 , or InP.5. The semiconductor structure of wherein semiconductor material is a top layer of a multilayer stack.6. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 nm.7. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene nanoribbons is separated by a uniform width.8. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene ...

GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER

A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm. 1. A semiconductor structure comprising:a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material;a semiconductor carbide layer located on said semiconductor substrate and having a thickness less than 10 nm; anda graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.2. The semiconductor structure of claim 1 , wherein said semiconductor carbide layer is one of a silicon carbide layer claim 1 , a silicon-germanium carbide layer claim 1 , and a germanium carbide layer.3. The semiconductor structure of claim 2 , wherein said semiconductor carbide layer is located directly on said single crystalline silicon-containing semiconductor material claim 2 , and said semiconductor carbide layer is single crystalline.4. The semiconductor structure of claim 1 , further comprising a dielectric material portion ...

MULTILAYERED LOW k CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES

The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride. 1. A multilayered cap comprising , from bottom to top , a first layer comprising silicon nitride , and a second layer comprising at least one of boron nitride and carbon boron nitride.2. The multilayered cap of claim 1 , wherein said first layer and said second layer have a combined thickness of less than 30 nm.3. The multilayered cap of claim 2 , wherein said first layer has a thickness from 1 nm to 25 nm and said second layer has a thickness from 5 nm to 29 nm.4. The multilayered cap of claim 1 , wherein said second layer comprises boron nitride.5. The multilayered cap of claim 1 , wherein said second layer comprises carbon boron nitride.6. The multilayered cap of claim 1 , wherein said second layer comprises films of both boron nitride and carbon boron nitride.7. The multilayered cap of claim 6 , wherein said boron nitride is positioned between said silicon nitride and said carbon boron nitride.8. The multilayered cap of claim 6 , wherein said carbon boron nitride is positioned between said silicon nitride and said boron nitride.9. The multilayered cap of claim 1 , further comprising at least one other first layer comprising silicon nitride claim 1 , and at least one other second layer comprising one of boron nitride and carbon boron nitride claim 1 , atop the first and second layers.10. A semiconductor structure comprising:a dielectric material having at least one conductive region embedded therein; anda multilayered cap located at least on an upper surface of said at least one conductive region embedded in said dielectric material, wherein said ...

GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. 1. A semiconductor structure comprising:at least one silicon carbide fin located on a surface of a substrate;a graphene nanoribbon located on each bare sidewall of said at least one silicon carbide fin; anda gate structure oriented perpendicular to said at least one silicon carbide fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of said at least one silicon carbide fin, wherein the portion of the each graphene nanoribbon overlapped by said gate structure defines a channel region of the semiconductor structure.2. The semiconductor structure of wherein said structure includes a plurality of parallel oriented silicon carbide fins each having said graphene nanoribbon located on bare sidewalls thereof.3. The semiconductor structure of wherein each graphene nanoribbon has a width defined by a height of said at least one silicon carbide fin.4. The semiconductor structure of wherein one portion of each graphene nanoribbon not overlapped by said gate structure is a source region of the semiconductor structure claim 1 , and wherein another portion of each graphene nanoribbon not overlapped by said gate structure is a drain region claim 1 , and wherein source region and drain region are connected by the channel region.5. The semiconductor ...

MULTILAYERED LOW k CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES

The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride. 1. A method of forming a multilayered cap comprising:providing a substrate;forming a first layer comprising silicon nitride on an upper surface of said substrate; andforming a second layer comprising at least one of boron nitride and carbon boron nitride on an upper surface of the first layer, wherein said second layer is formed by at least one of plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition and atomic layer deposition.2. The method of claim 1 , wherein said providing the substrate includes providing a dielectric material having at least one conductive region embedded therein.3. The method of claim 1 , wherein said second layer is formed by plasma enhanced chemical vapor deposition claim 1 , said plasma enhanced chemical vapor deposition is performed at a temperature from 250° C. to 400° C.4. The method of claim 1 , wherein said second layer is formed by atomic layer deposition claim 1 , said atomic layer deposition is performed at a temperature from 50° C. to 500° C.5. The method of claim 1 , wherein said second layer is formed by atomic layer deposition claim 1 , and said atomic layer deposition is performed at a temperature from 20° C. to 500° C.6. The method of claim 1 , further comprising forming at least one other first layer comprising silicon nitride and at least one other second layer comprising one of boron nitride and carbon boron nitride atop the first and second layers. This application is a continuation of U.S. patent application Ser. No. 13/078,305, filed Apr. 1, 2011 the entire content and disclosure of ...

MULTIPHASE ULTRA LOW K DIELECTRIC MATERIAL

A multiphase ultra low k dielectric process incorporating an organo-silicon precursor including an organic porogen, high frequency radio frequency power just above plasma initiation in a PECVD chamber and energy post treatment. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa. A graded carbon adhesion layer of SiOand porous SiCOH. 1. A method for forming an ultra low k dielectric layer comprising:selecting a plasma enhanced chemical vapor deposition chamber;placing a substrate in said chamber;introducing an organo-silicon precursor including an organic porogen into said chamber;heating said substrate to a temperature in the range from 200° C. to 350° C.;controlling the amount of an oxidant gas in said chamber;forming a deposited layer by applying high frequency radio frequency power in said chamber to initiate a plasma and polymerization of said organo-silicon precursor and retain at least a fraction of said organic porogen in said deposited layer;after a period of time terminating said plasma in said chamber; andapplying to said deposited layer an energy post treatment selected from the group consisting of thermal anneal, ultra violet (UV) radiation, and electron beam irradiation to drive out said organic porogen and increase the porosity in said deposited layer to at least five percent.2. The method of wherein said applying an energy post treatment includes heating to a temperature above 200° C. for a time period to increase Si—CH—Si cross linking bonds in said deposited layer.3. The method of wherein said applying an energy post treatment includes heating to a temperature above 200° C. for a time period to cause adjacent Si—CHchemical bonds in said deposited layer to change to Si—CH—Si bonds to increase a modulus of elasticity and hardness of said deposited layer.4. The method of wherein said organo-silicon precursor is selected from the group consisting of octamethylcyclotetrasiloxane (OMCTS) and 1 claim ...

C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES

A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CBNwherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent. 1. A dielectric film having a formula of CBNwherein x is 35 atomic percent or greater , y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.2. The dielectric film of claim 1 , further comprising a dielectric constant of equal to claim 1 , or less than 3.6.3. The dielectric film of claim 2 , wherein said dielectric constant ranges from 2.5 to 3.2.4. The dielectric film of claim 1 , wherein x is from 35 atomic percent to 70 atomic percent claim 1 , y is from 15 atomic percent to 32 atomic percent claim 1 , and z is from 15 atomic percent to 33 atomic percent.5. The dielectric film of claim 1 , wherein said nitrogen is uniformly distributed throughout the dielectric film.6. The dielectric film of claim 1 , wherein said nitrogen is provided in selected regions within a depth of the dielectric film providing a graded film.7. An electronic device comprising:a substrate; and{'sub': x', 'y', 'z, 'a dielectric film located on a surface of said substrate, wherein said dielectric film has a formula of CBNwherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.'}8. The electronic device of claim 7 , wherein said substrate is an interconnect dielectric material having at least one conductive material located therein claim 7 , and wherein said dielectric film is located on at least an exposed surface of the at least one conductive material.9. The electronic device of claim 7 , wherein said substrate is a patterned gate stack claim 7 , and said ...

MULTI COMPONENT DIELECTRIC LAYER

An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si═C, B, Si═B, Si═B═C, and B═C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. 1. A dielectric structure comprising:a first component comprising at least one of SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH and a second component adjacent said first component wherein said second component has a dielectric constant less than 3.2.2. The dielectric structure of wherein said first component comprises at least one multilayer of SiN/SiCN claim 1 , BN/CBN and SiN/BN—CBN.3. The dielectric structure of wherein said second component comprises a porous component.4. The dielectric structure of wherein said second component comprises at least one of SiCOH claim 1 , p-SiCOH claim 1 , p-SiCNH claim 1 , p-BN claim 1 , p-BNH claim 1 , p-CBN and p-CBNH.5. The dielectric structure of wherein said first component comprises a random three dimensional covalently bonded network.6. The dielectric structure of wherein said second component comprises a random three dimensional covalently bonded network.7. An interconnect structure comprising at least one wiring level in an integrated circuit chip having conductors in said wiring level and a dielectric comprising a first component of at least one of SiCN claim 1 , SiCNH claim 1 , SiN claim 1 , SiNH claim 1 , BN claim 1 , BNH claim 1 , CBN claim 1 , CBNH claim 1 , BSiN claim 1 , BSiNH claim 1 , SiCBN and SiCBNH and a second component ...

SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME

A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons. 1. A semiconductor structure comprising:a substrate having an upper surface; andan ordered array of parallel graphene nanoribbons located on the upper surface of the substrate.2. The semiconductor structure of wherein said substrate is a dielectric material claim 1 , and said dielectric material comprises class claim 1 , SiO claim 1 , SiN claim 1 , organosilicate glass claim 1 , SC:H claim 1 , SiCN:H claim 1 , plastic claim 1 , diamond-like carbon claim 1 , boron nitride (BN) claim 1 , carbon boron nitride (CBN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride.3. The semiconductor structure of wherein dielectric material is a top layer of a multilayer stack.4. The semiconductor structure of wherein said substrate is a semiconductor material claim 1 , and said semiconductor material comprises Si claim 1 , SiGe claim 1 , SiGeC claim 1 , SiC claim 1 , Ge alloys claim 1 , GaAs claim 1 , InAs claim 1 , or InP.5. The semiconductor structure of wherein semiconductor material is a top layer of a multilayer stack.6. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 nm.7. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene nanoribbons is separated by a uniform width.8. The semiconductor structure of wherein each graphene nanoribbon of said ordered array of parallel graphene ...

C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES

A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CBNwherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent. 1. A method of forming a dielectric film comprising:providing a substrate into a reactor chamber;providing to the reactor chamber at least one precursor containing at least atoms of C, B and N; and{'sub': x', 'y', 'z, 'depositing a dielectric film on a surface of said substrate, wherein the dielectric film has a formula of CBNwherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.'}2. The method of claim 1 , wherein said at least one precursor includes at least a boron-containing gas precursor claim 1 , a nitrogen-containing gas precursor and a hydrocarbon-containing gas precursor.3. The method of claim 1 , wherein said at least one precursor includes a combined boron and nitrogen containing liquid precursor and a hydrocarbon-containing gas precursor.4. The method of claim 1 , wherein said depositing comprises plasma enhanced chemical vapor deposition claim 1 , chemical vapor deposition claim 1 , atomic layer deposition claim 1 , or a spin on process.5. The method of claim 1 , wherein further comprising treating the carbon-rich carbon boron nitride dielectric film claim 1 , wherein said treating is selected from the group consisting of thermal treatment claim 1 , chemical treatment claim 1 , UV treatment claim 1 , e-beam treatment claim 1 , microwave treatment claim 1 , plasma treatment and any combination thereof.6. The method of claim 1 , wherein said dielectric film has a dielectric constant of equal to claim 1 , or less than 3.6.7. The method of claim 1 , wherein said dielectric ...

DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH

A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH)—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen, a high frequency radio frequency power in a PECVD chamber and an energy post treatment including ultraviolet radiation. An ultra low k porous SiCOH dielectric material having at least one of a k in the range from 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, and 2.5 to 2.55 and a modulus of elasticity greater than 5, 6, 7.8 and 9 GPa, respectively and a semiconductor integrated circuit comprising interconnect wiring having porous SiCOH dielectric material as described above. 1. A method for forming an ultra low k dielectric layer comprising:selecting a plasma enhanced chemical vapor deposition reactor;placing a substrate in said reactor;{'sub': 2', 'n, 'introducing a gas mixture flow into said reactor; said gas mixture comprising an inert carrier gas, a first precursor gas comprising at least one of a carbosilane and alkoxycarbosilane molecules comprising atoms of Si, C, O and H and containing the group Si—(CH)—Si where n is an integer 1, 2 or 3 and a second precursor gas containing the group Si—R* comprising atoms of Si, C, O and H and where R* is an embedded organic porogen;'}heating said substrate to a temperature above 100° C.;forming a deposited layer by applying high frequency radio frequency power in said reactor;after a period of time terminating said high frequency radio frequency power in said reactor; andapplying to said deposited layer an energy post treatment comprising ultra violet (UV) radiation to drive out said embedded organic porogen, create porosity in said deposited layer and increase cross-linking in said deposited layer.2. The method of wherein said applying an energy post treatment includes irradiating with said ultraviolet radiation for a ...

Interlevel Dielectric Stack for Interconnect Structures

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC

Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect. 1. A semiconductor-on-insulator (SOI) structure comprising:a handle substrate comprising a first semiconductor material;a layer of boron nitride located atop an uppermost surface of the handle substrate; anda semiconductor-on-insulator (SOI) layer comprising a second semiconductor material located atop the layer of boron nitride.2. The SOI structure of claim 1 , further comprising a layer of insulating oxide located between the handle substrate and the layer of boron nitride.3. The SOI structure of claim 2 , further comprising another layer of insulating oxide located between said layer of boron nitride and said SOI layer claim 2 , wherein a bottommost surface of the another layer of insulating oxide is located on an uppermost surface of the layer of boron nitride claim 2 , and an uppermost surface of the another layer of insulating oxide is in direct contact with a bottommost surface of said SOI layer.4. The SOI structure of claim 1 , further comprising a layer of insulating oxide located between the layer of boron nitride and the SOI layer claim 1 , wherein a bottommost surface of the layer of insulating oxide is located on an uppermost surface of the layer of boron nitride claim 1 , and an uppermost surface of the layer of insulating oxide is in direct contact with a ...

SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC

Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect. 1. A method of forming a semiconductor-on-insulator (SOI) structure comprising:providing a handle substrate comprising a first semiconductor material;providing a layer of boron nitride atop a surface of a semiconductor wafer comprising a second semiconductor material;bonding the handle substrate to the layer of boron nitride to provide a bonded structure in which the semiconductor wafer represents a topmost layer of the bonded structure and the handle represents a bottommost layer of the bonded substrate; andremoving a portion of the semiconductor wafer to provide a semiconductor-on-insulator (SOI) layer of a silicon-on-insulator (SOI) structure, said SOI structure comprising said handle substrate, said layer of boron nitride located on an uppermost surface of the handle substrate and said SOI layer located atop the layer of boron nitride.2. The method of claim 1 , further comprising providing a layer of insulating oxide between said layer of boron nitride and said semiconductor wafer.3. The method of claim 2 , further comprising removing a portion of said SOI layer forming at least one SOI mesa atop said layer of insulating oxide.4. The method of claim 1 , further comprising removing a portion of said SOI layer forming at least one SOI mesa atop said layer of boron ...

SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP

A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device. 1. A method of forming a semiconductor structure comprising:providing a graphene layer onto at least an upper surface of a first dielectric material, said first dielectric material comprising at least one first conductive region contained therein;forming at least one semiconductor device using the graphene layer as an element of said at least one semiconductor device; andforming a second dielectric material covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material, wherein said second dielectric material includes at least one second conductive region contained therein, and wherein said at least one second conductive region is in contact with a conductive element of said at least one semiconductor device.2. The method of wherein said providing the graphene layer comprises forming the graphene layer on a handle substrate and transferring the graphene layer to the first dielectric material using a layer transfer process.3. The method of wherein said forming the graphene layer on the handle substrate includes epitaxial growth on SiC or a metal template.4. The method of wherein said forming the graphene layer ...

Bilayer gate dielectric with low equivalent oxide thickness for graphene devices

A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.

Formation of a graphene layer on a large substrate

A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES

Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. 1. An interconnect structure comprising:at least one copper structure contained within at least one opening present in a dielectric material, said at least one copper structure having an uppermost surface that is coplanar with an uppermost surface of the dielectric material; anda graphene cap located atop the uppermost surface of said at least one copper structure, wherein said graphene cap has edges that are vertically coincident with edges of said at least one copper structure.2. The interconnect structure of claim 1 , wherein a metal-containing cap is located between the graphene cap and the uppermost surface of said copper structure claim 1 , wherein said metal-containing cap has edges that are vertically coincident with edges of said graphene cap and edges of said copper structure.3. The interconnect structure of claim 1 , further comprising at least one U-shaped diffusion barrier material contained within said at least one opening and separating each edge of said copper structure from said dielectric material.4. The interconnect structure of claim 3 , wherein said at least one U-shaped diffusion barrier material comprises a first diffusion barrier material and a second diffusion barrier material claim 3 , wherein said first diffusion barrier material is selected from a metal nitride claim 3 , and said second diffusion barrier material is selected from a metal.5. The interconnect structure of claim 1 , wherein another dielectric material is located beneath said dielectric material containing said copper structure claim 1 , and wherein a bottommost ...

METHOD OF FORMING A GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES

Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. 13.-. (canceled)4. A method of forming an interconnect structure comprising:providing a structure comprising at least one copper structure contained within at least one opening present in a dielectric material, said at least one copper structure having an uppermost surface that is coplanar with an uppermost surface of the dielectric material; and forming a graphene cap atop the uppermost surface of said at least one copper structure, wherein said graphene cap has edges that are vertically coincident with edges of said at least one copper structure, and wherein said forming the graphene cap comprises:transferring graphene from a Cu foil and patterning the graphene so that its edges coincide with said vertical sidewall surfaces of said at least one copper structure.56.-. (canceled)7. A method of forming an interconnect structure comprising:providing a stack of, from bottom to top, at least one blanket layer of a diffusion barrier material and a blanket layer of copper or a copper alloy;patterning said stack forming at least one copper structure located atop at least one diffusion barrier material portion, wherein said at least one copper structure has edges that are vertically coincident with edges of said at least one diffusion barrier material portion; forming a graphene cap atop an uppermost surface and sidewall surfaces of said at least one copper structure; andforming a dielectric material portion adjacent each side of the at least one copper structure by deposition and etching, wherein each dielectric material portion is separated from one of the ...

MODULATED COMPOSITIONAL AND STRESS CONTROLLED MULTILAYER ULTRATHIN CONFORMAL SiNx DIELECTRICS USED IN NANO DEVICE FABRICATION

A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided. 1. A method comprising:providing a substrate, wherein said substrate has a plurality of steps;depositing on said substrate a layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers;carrying out a plasma nitridation process on said layer to densify and control stress of said layer; andrepeating said steps of depositing and carrying out plasma nitridation for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained;wherein said predetermined thickness of said layers conforms to said steps of said substrate with a conformality of at least seventy percent.2. The method of claim 1 , wherein said depositing comprises plasma enhanced chemical vapor deposition.3. The method of wherein said depositing is carried out at a temperature of less than 450 degrees Centigrade.4. The method of claim 1 , wherein said depositing is carried out at a radio frequency power of less than 2 watts per square centimeter claim 1 , with a radio frequency ranging from 400 KHz to 60 MHz.5. The method of claim 4 , ...

GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. 1. A semiconductor structure comprising:at least one silicon carbide fin located on a surface of a substrate;a graphene nanoribbon located on each bare sidewall of said at least one silicon carbide fin; anda gate structure oriented perpendicular to said at least one silicon carbide fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of said at least one silicon carbide fin, wherein the portion of the each graphene nanoribbon overlapped by said gate structure defines a channel region of the semiconductor structure.2. The semiconductor structure of wherein said structure includes a plurality of parallel oriented silicon carbide fins each having said graphene nanoribbon located on bare sidewalls thereof.3. The semiconductor structure of wherein each graphene nanoribbon has a width defined by a height of said at least one silicon carbide fin.4. The semiconductor structure of wherein one portion of each graphene nanoribbon not overlapped by said gate structure is a source region of the semiconductor structure claim 1 , and wherein another portion of each graphene nanoribbon not overlapped by said gate structure is a drain region claim 1 , and wherein source region and drain region are connected by the channel region.5. The semiconductor ...

MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE

A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less 1. A method comprising:providing a precursor combination consisting essentially of at least a first precursor and a second precursor into a reactor chamber, wherein said first precursor is selected from the group consisting of an alkoxysilane and alkoxycarbosilane and said second precursor is a porogen selected from the group consisting of a liner compound containing at least one C═C double bond and an alcohol;depositing a film from said precursor combination; andremoving said porogen from said film to provide a porous composite material comprising a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein said pores have a diameter of about 5 nm or less, a pore size distribution having a maximum that is less than about 1 nm, a full width at half maximum in the pore size distribution ranging from 1 to 3 nm, and with a fraction less than 0.1 of pores having a pore size of greater than about 1 nm.2. The method of claim 1 , wherein said removing said porogen comprises thermal treatment.3. The method of claim 1 , wherein said removing said porogen comprises UV treatment.4. The method of claim 1 , wherein said removing said porogen comprises treatment by electron beam irradiation.5. The method of claim 1 , wherein said removing said porogen comprises treatment with chemical energy.6. The method of claim 1 , wherein said removing said porogen comprises any combination of thermal treatment claim 1 ...

MICROWAVE PLASMA AND ULTRAVIOLET ASSISTED DEPOSITION APPARATUS AND METHOD FOR MATERIAL DEPOSITION USING THE SAME

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided. 1. A method for depositing a material on a substrate , the method comprising:feeding a precursor gas into a processing space in which the substrate is arranged;feeding a reactive gas into the processing space;operating an ultraviolet radiation assembly to emit ultraviolet radiation into the processing space in combination with operating a microwave radiation assembly to emit microwave radiation into the processing space to excite at least the reactive gas; anddepositing the material on the substrate in the processing space from a reaction of the excited reactive gas and the precursor gas.2. The method according to claim 1 , operating a gas feed assembly comprising a plurality of conduits, wherein each of the plurality of conduits comprises a coaxial inner conduit and outer conduit, wherein the inner conduit defines a port through which the precursor gas or the reactive gas is fed into the processing space,', 'wherein the operating the gas feed assembly comprises moving the inner conduit relative to the outer conduit to position the port at a variable position in the processing space ...

ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS

An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS

An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. 1. A method for forming an interfacial layer between a low-k dielectric material and a copper including structure comprising:forming a superlattice structure on the low-k dielectric material, wherein the superlattice structure includes a repeating sequence of a metal oxide layer, a metal layer and a metal nitride layer, wherein at least one of the metal oxide layer, the metal layer and the metal nitride layer comprise manganese (Mn), and a first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer; andforming the copper including structure on a metal nitride layer of said superlattice structure.2. The method of claim 1 , wherein forming the superlattice structure comprises deposting at least one of the metal nitride layer claim 1 , the metal layer and the metal oxide layer using atomic layer deposition (ALD) claim 1 , chemical vapor deposition (CVD) claim 1 , plasma enhanced atomic layer deposition (PEALD) or a combination thereof.3. The method of claim 1 , wherein a metal precursor for deposition at least one of the metal nitride layer claim 1 , the metal layer and the metal oxide layer comprises at least one of metal carbonyl claim 1 , metal amidinate claim 1 , metal carbo- ...

HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. 115-. (canceled)16. A dielectric film comprising:a first sublayer; anda second sublayer disposed on the first sublayer, wherein the first sublayer and second sublayer are hydrogen-free silicon-containing sublayers.17. The dielectric film of claim 16 , further comprising a third sublayer disposed on the second sublayer claim 16 , wherein the third sublayer is a hydrogen-free silicon-containing sublayer.18. The dielectric film of claim 17 , wherein the first sublayer is comprised of silicon nitride claim 17 , the second sublayer is comprised of silicon oxide claim 17 , and the third sublayer is comprised of SiNxOy.19. The dielectric film of claim 17 , wherein the first sublayer is comprised of silicon oxide claim 17 , the second sublayer is comprised of silicon nitride claim 17 , and the third sublayer is comprised of silicon oxide.20. The dielectric film of claim 17 , wherein the first sublayer is comprised of silicon oxide claim 17 , the second sublayer is comprised of SiCNx claim 17 , and the third sublayer ...

METHOD OF FORMING A GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES

Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. 1. A method of forming an interconnect structure comprising:providing a structure comprising at least one copper structure contained within at least one opening present in a dielectric material, said at least one copper structure having an uppermost surface that is coplanar with an uppermost surface of the dielectric material; andforming a graphene cap directly on the uppermost surface of said at least one copper structure, wherein said graphene cap has edges that are vertically coincident with edges of said at least one copper structure.2. The method of claim 1 , wherein said forming said graphene cap comprises a selective deposition process that is performed at a temperature not exceeding 400° C.3. The method of claim 2 , wherein said selective deposition process includes selecting a carbon source and growing a layer of graphene using said carbon source.4. The method of claim 3 , wherein said carbon source is selected from the group consisting of benzene claim 3 , propane and ethane.5. The method of claim 2 , wherein said selective deposition process is selected from the group consisting of chemical vapor deposition claim 2 , plasma enhanced chemical vapor deposition claim 2 , and ultra-violet assisted chemical vapor deposition.6. The method of claim 2 , wherein said temperature of said selective deposition process is from 200° C. to 400° C.7. The method of claim 1 , wherein said structure further comprises at least one U-shaped diffusion barrier material contained within said at least one opening and separating each edge of said copper structure from ...

HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. 129-. (canceled)30. A semiconductor device comprising: a first layer of dielectric containing conductors embedded therein;', 'a second layer of hydrogen-free dielectric comprising SiCxNy and covering at least partially the surface of said first layer and containing conductor regions embedded therein; and', 'a third layer of hydrogen free dielectric comprising SiCvNw and covering at least partially the surface of said second layer and containing conductor regions embedded therein, wherein x is unequal to v and y is unequal to w., 'an interconnect wiring structure comprising31. The semiconductor structure of claim 30 , further comprising a plurality of interconnect wiring levels claim 30 , wherein each wiring level of the plurality of wiring levels comprises:a first layer of hydrogen-free dielectric comprising SiCxNy and containing conductor regions embedded therein; anda second layer of hydrogen free dielectric comprising SiCvNw and covering at least partially the surface of said first layer and containing ...

HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. 17-. (canceled)8. A method of forming a multilayer dielectric film comprising:introducing a hydrogen-free precursor into a chamber of a deposition tool;introducing a first hydrogen-free reactive gas in said chamber;applying a first hydrogen-free plasma in the chamber to form a first sublayer;removing the first hydrogen-free plasma in the chamber;removing the first hydrogen-free reactive gas from the chamber;introducing a second hydrogen-free reactive gas in said chamber, different from the first hydrogen-free reactive gas;applying a second hydrogen-free plasma in the chamber to form a second sublayer;removing the second hydrogen-free plasma in the chamber; andremoving the second hydrogen-free gas from the chamber.9. The method of where additional inert gases are introduced into the chamber of said deposition tool.10. The method of claim 8 , wherein introducing a hydrogen-free precursor comprises introducing tetraisocyanatosilane.11. The method of claim 8 , wherein applying the first hydrogen-free plasma ...

BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES

A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. 1. A semiconductor-on-insulator (SOI) structure comprising:a handle substrate comprising a first semiconductor material;an insulator layer located over the handle substrate;a cap layer located over the insulator layer, the cap layer comprising a boron-rich compound selected from the group consisting of silicon boron nitride (SiBN), carbon boron nitride (CBN), boron silicon (BSi), and boron silicon oxide (BSiO); andan SOI layer comprising a second semiconductor material and located over the cap layer.2. The SOI structure of claim 1 , wherein the boron-rich compound comprises an excess amount of boron.3. The SOI structure of claim 2 , wherein the boron is uniformly distributed throughout the cap layer.4. The SOI structure of claim 2 , wherein the boron has a gradient distribution with an amount of boron being greater at an interface between the cap layer and the insulator layer.5. The SOI structure of claim 1 , wherein each of the first semiconductor material and the second semiconductor material comprises silicon claim 1 , germanium claim 1 , a silicon-germanium alloy claim 1 , a silicon carbon alloy claim 1 , a silicon-germanium-carbon alloy claim 1 , an III-V compound semiconductor material claim 1 , an II-VI compound semiconductor material claim 1 , or an organic semiconductor material.6. The SOI structure of claim 1 , wherein the insulator layer comprises an oxide or a nitride.7. The SOI structure of claim 6 , wherein the insulator layer comprises silicon oxide.8. The SOI structure of claim 6 , ...

HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. 122-. (canceled)23. A semiconductor structure , comprising:a semiconductor substrate;a gate dielectric layer disposed on the semiconductor substrate;a gate disposed on the gate dielectric layer;a self-aligned contact cap formed on the gate, wherein the wherein the self-aligned contact cap comprises a hydrogen-free dielectric film.24. The semiconductor structure of claim 23 , further comprising a plurality of spacers formed adjacent to the gate claim 23 , wherein the plurality of spacers are comprised of a hydrogen-free multilayer dielectric film.25. The semiconductor structure of claim 24 , wherein the hydrogen-free multilayer dielectric film comprises:a first sublayer; anda second sublayer disposed on the first sublayer.26. The semiconductor structure of claim 25 , wherein the hydrogen-free multilayer dielectric film further comprises a third sublayer disposed on the second sublayer claim 25 , wherein the third sublayer is a hydrogen-free silicon-based sublayer.27. The semiconductor structure of claim 26 , ...

ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed. 1. A method of forming a semiconductor device comprising:providing a structure comprising, from bottom to top, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer;patterning a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration into said top semiconductor layer;suspending each semiconductor nanowire of said plurality of semiconductor nanowires by removing a portion of said buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed;forming a gate dielectric surrounding each semiconductor nanowire and located directly on a top surface and a bottom surface of each semiconductor nanowires; ...

ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed. 1. A semiconductor device comprising:a first buried oxide layer portion and a second buried oxide layer portion each located on an uppermost surface of a buried boron nitride layer, wherein a portion of said uppermost surface of said buried boron nitride layer between said first and second buried oxide layer portions is exposed;a first semiconductor pad located atop said first buried oxide layer portion;a second semiconductor pad located atop said second buried oxide layer portion;a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration and suspended above said exposed portion of said uppermost surface of said buried boron nitride layer;a gate dielectric surrounding each semiconductor nanowire and located directly on a top surface and a bottom surface of each semiconductor nanowire;a gate surrounding each semiconductor nanowire and located directly on a surface of each gate dielectric; anda gate dielectric portion located directly on a surface of said exposed portion of ...

CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS

A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. 1. A semiconductor structure comprising:a substrate comprising a first semiconductor material having a first crystallographic orientation located on portions of a second semiconductor material having a second crystallographic orientation that differs from said first crystallographic orientation;at last one field effect transistor located on other portions of said second semiconductor material not including said first semiconductor material, wherein said at least one field effect transistor includes at least a gate dielectric, a gate electrode, a source region and a drain region, said gate dielectric has a bottom surface in contact with an upper surface of the second semiconductor material, an upper surface that is coplanar with an upper surface of said first semiconductor material, and vertical edges that are in contact with vertical edges of said first semiconductor material;a continuous metal semiconductor alloy including a lower portion that is contained within an upper surface of each of said source and drain regions, and a vertical pillar portion extending upwardly from said lower portion; anda metal line located on an upper surface of said vertical pillar portion of the continuous metal semiconductor alloy.2. The semiconductor structure of wherein said metal semiconductor alloy is a metal silicide.3. The semiconductor structure ...

ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES

A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. 1. A method of forming a dielectric film comprising:providing at least a carbon-rich carbosilane precursor into a reactor chamber; anddepositing a dielectric film comprising atoms of at least Si, C and H having a dielectric constant of less than, or equal to, about 4.5 from the carbon-rich carbosilane precursor onto a surface of a substrate, said dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C.2. The method of wherein said dielectric film further comprises nitrogen.3. The method of wherein said nitrogen is present in said dielectric film in a concentration of less than claim 2 , or equal claim 2 , to about 5 atomic % nitrogen.4. The method of wherein said nitrogen is provided by utilizing a nitrogen-containing second precursor.5. The method of wherein said reactor chamber is a reactor chamber of a plasma enhanced chemical vapor deposition apparatus.6. The method of wherein said carbon-rich carbosilane precursor comprises a compound of the general formula CSiHwhere x>=3 and y>=8.7. The method of wherein said carbon-rich carbosilane precursor comprises dimethylsilacyclopentene and said nitrogen-containing precursor comprises NH.8. The method of wherein said dielectric film consists of atoms of Si claim 1 , C and H.9. The method of further comprising performing a post deposition treatment on said dielectric film claim 1 , wherein after said post deposition treatment said dielectric film remains compressively stressed.10. The method of wherein said nitrogen is uniformly distributed ...

ADHESION LAYER AND MULTIPHASE ULTRA-LOW k DIELECTRIC MATERIAL

A dielectric material incorporating a graded carbon adhesion layer whereby the content of C increases with layer thickness and a multiphase ultra low k dielectric comprising a porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is described. A semiconductor integrated circuit incorporating the above dielectric material in interconnect wiring is described and a semiconductor integrated circuit incorporating the above multiphase ultra low k dielectric in a gate stack spacer of a FET is described.

ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS

An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. 1. An electrical device comprising:an opening in a dielectric material;a metal including structure present within the opening for transmitting electrical current; anda liner between the dielectric material and the metal including structure, the liner comprising a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer, wherein a first layer of the superlattice structure that is in direct contact with the dielectric material is one of said metal oxide layer, a final layer of the superlattice structure that is in direct contact with the copper including structure is one of said metal nitride layer, and at least one of the metal oxide layer, the metal layer and the metal nitride layer comprise manganese (Mn).2. The electrical device of claim 1 , wherein at least one of the metal oxide layer in the superlattice structure obstructs the metal from the metal including structure from diffusing into the dielectric material.3. The electrical device of claim 1 , wherein the metal oxide layer includes a metal element selected from the group consisting of manganese (Mn) claim 1 , tantalum (Ta) claim 1 , aluminum (Al) claim 1 , cobalt (Co) claim 1 , ...

CARBON NANOSTRUCTURE DEVICE FABRICATION UTILIZING PROTECT LAYERS

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing. 1. A method for forming a device structure comprising:selecting an insulating substrate having a carbon-based nanostructure layer on an upper surface;forming a first layer of a first metal on said carbon-based nanostructure layer;forming a first patterned layer having a first pattern on said first layer of a first metal;transferring said first pattern to said first layer of a first metal and said carbon-based nanostructure layer to form a first patterned layer of a first metal and a first patterned carbon-based nanostructure layer there under;removing said first patterned layer;forming a second patterned layer of a second metal over said insulating substrate and said first patterned layer of a first metal; said second patterned layer of a second metal having a second pattern comprising a plurality of contacts spaced apart from one another wherein respective contacts have a portion on said first patterned layer of a first metal and a portion on said insulating substrate; andremoving said first patterned layer of a first metal where not covered by said plurality of contacts whereby said first patterned carbon-based nanostructure layer has regions not covered by said first patterned layer of first metal.2. The method of wherein said carbon-based nanostructure layer is selected from the group consisting of carbon-nanotubes and graphene.3. The method of wherein forming said second patterned layer of a second metal includes forming a patterned photoresist lift-off stencil over said insulating substrate and said first patterned layer of a first metal;forming a layer of second metal over said photoresist lift-off stencil, over said insulating substrate and over said first patterned layer of a first metal; ...

MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

MICROWAVE PLASMA AND ULTRAVIOLET ASSISTED DEPOSITION APPARATUS AND METHOD FOR MATERIAL DEPOSITION USING THE SAME

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided. 2. The apparatus according to claim 1 , wherein the ultraviolet radiation assembly comprises:an ultraviolet source housing arranged to the processing chamber body; andan ultraviolet source arranged within the ultraviolet source housing and configured to emit ultraviolet radiation into the processing space.3. The apparatus according to claim 1 , wherein the microwave radiation assembly comprises:a microwave power source configured to generate microwave radiation for exciting the reactive gas; anda microwave applicator configured to propagate the microwave radiation generated by the microwave power source and to emit the microwave radiation into the processing space.4. The apparatus according to claim 3 , wherein the microwave applicator comprises:an annular waveguide arranged to the chamber body, the annular waveguide having a plurality of slots through which microwave radiation propagated through the annular waveguide is emitted into the processing space; andone or more dielectric windows between the plurality of slots of the annular waveguide and the processing chamber body to seal ...

INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity. 1. An interconnect structure comprising:a device level;at least a first wiring level and a second wiring level;at least one via and one conductive line connecting the first wiring level and the second wiring level; anda dielectric stack in at least one of the first and second wiring level comprising a first layer of silicon, carbon, nitrogen and hydrogen, and a second layer of silicon, carbon, nitrogen and hydrogen, wherein the first layer is dense and the second layer is porous.2. The interconnect structure of further comprising a substrate.3. The interconnect structure of claim 1 , further comprising a third wiring level connected to the first wiring level and the second wiring level by the via and the conductive line.4. The interconnect structure of wherein the substrate is comprised of one of silicon and silicon-on-insulator.5. The interconnect structure of wherein the device level includes at least one of an n-type field effect transistor claim 1 , a p-type field effect transistor claim 1 , an n-type bipolar transistor claim 1 , a p-type bipolar transistor and memory.620-. (canceled) 1. Field of the InventionThe present invention relates to interconnect structures in semiconductor devices. More specifically, the present invention relates to an interlevel dielectric stack containing a ...

ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS

An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

INTERCONNECT STRUCTURE INCLUDING AIRGAPS AND SUBSTRACTIVELY ETCHED METAL LINES

Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing. 1. An integrated circuit comprising:a surface of the integrated circuit;at least two electrically conductive interconnect lines separated by a space of less than 90 nm on the surface, each of the at least two electrically conductive interconnect lines comprising a metal cap, a subtractively etched copper conductor having an average grain size greater than a line width of the electrically conductive interconnect line prior to formation of the electrically conductive interconnect line, and a liner layer, wherein the metal cap is on an upper surface of the copper conductor, wherein the liner layer is on a bottom surface and sidewalls of the copper conductor, and on sidewalls of the metal cap, and wherein the liner layer and the metal cap collectively encapsulate the subtractively etched copper conductor; anda dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.2. The integrated circuit of claim 1 , wherein the metal cap comprises tantalum claim 1 , titanium ...

GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER

A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm. 1. A semiconductor structure comprising:a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material;a semiconductor carbide layer located on said semiconductor substrate and having a thickness less than 10 nm; anda graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.2. The semiconductor structure of claim 1 , wherein said semiconductor carbide layer is one of a silicon carbide layer claim 1 , a silicon-germanium carbide layer claim 1 , and a germanium carbide layer.3. The semiconductor structure of claim 2 , wherein said semiconductor carbide layer is located directly on said single crystalline silicon-containing semiconductor material claim 2 , and said semiconductor carbide layer is single crystalline.4. The semiconductor structure of claim 1 , further comprising a dielectric material portion ...

LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES

Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure. 1. A semiconductor device comprising:a semiconductor body;a gate stack disposed atop the semiconductor body; anda boron nitride spacer in direct contact with sidewalls of the gate stack and at least a portion of the semiconductor body, wherein the boron nitride spacer has a thickness greater than or equal to 1 nm and less than or equal to 20 nm and has a hexagonal bonding configuration.2. The semiconductor device of claim 1 , wherein the boron nitride spacer has a hexagonal textured structure claim 1 , and the boron nitride spacer either includes an amorphous region which is less than or equal to 5 nm thick or includes no amorphous region.3. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises stoichiometric boron nitride.4. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises boron nitride that has an oxygen content less than or equal to five atomic percent claim 1 , and boron nitride that claim 1 , after performing reactive ion etching claim 1 , has a dielectric constant greater than or equal to 3 and less than or equal to 4.5.5. The semiconductor device of claim 1 , wherein the semiconductor body comprises at least one of the following: silicon germanium (SiGe) claim 1 , germanium (Ge) claim 1 , and a III-V compound.6. The ...

BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES

A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. 1. A semiconductor-on-insulator (SOI) structure comprising:a handle substrate comprising a first semiconductor material;an insulator layer located atop an uppermost surface of the handle substrate;a cap layer comprising a boron-rich compound or doped boron nitride located atop the insulator layer; andan SOI layer comprising a second semiconductor material and located atop the cap layer.2. The SOI structure of claim 1 , wherein the cap layer is a boron-rich compound comprising boron-rich boron nitride (BN) claim 1 , boron-rich silicon boron nitride (SiBN) claim 1 , boron-rich carbon boron nitride (CBN) claim 1 , boron-rich boron silicon (BSi) claim 1 , or boron-rich boron silicon oxide (BSiO).3. The SOI structure of claim 2 , wherein the boron is uniformly distributed throughout the cap layer.4. The SOI structure of claim 2 , wherein the boron has a gradient distribution with an amount of boron being greater at an interface between the cap layer and the insulator layer.5. The SOI structure of claim 1 , wherein the cap layer is doped boron nitride and dopants in the doped boron nitride comprise tungsten claim 1 , tantalum claim 1 , cobalt claim 1 , molybdenum claim 1 , or titanium.6. The SOI structure of claim 5 , wherein the doped boron nitride has a dopant concentration greater than 1×10atoms/cm.7. The SOI structure of claim 5 , wherein the dopants are uniformly distributed throughout the cap layer.8. The SOI structure of claim 5 , wherein the dopants have a gradient distribution with an amount of ...

Interconnect with Self-Forming Wrap-All-Around Barrier Layer

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

COMPOSITE DIELECTRIC MATERIALS WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES

A low k dielectric material with enhanced electrical and mechanical properties is provided which, in some applications, can also reduce the capacitance of a semiconductor device. The low k dielectric material includes CNT nanotubes that are randomly dispersed within a low k dielectric material matrix. The low k dielectric material can be used in a variety of electronic devices including, for example, as an insulator layer within a back end of line interconnect structure. 1. A method for forming a dielectric material comprising:providing, in any order, a solution containing a low dielectric constant material and another solution containing carbon nanotubes (“CNTs”); anddepositing the solutions on a surface of a substrate to provide a composite dielectric material, said composite dielectric material having a dielectric constant of 3.5 or less and comprising a first dielectric material, and a second dielectric material comprising said carbon nanotubes (CNTs), wherein said second dielectric material is randomly dispersed in said first dielectric material.2. The method of claim 1 , wherein said solution containing the low dielectric constant material and said another solution containing said CNTs are pre-mixed together prior to introduction into a reactor.3. The method of claim 1 , wherein said solution containing the low dielectric constant material and said another solution containing said CNTs are individually and sequentially deposited on said surface of said substrate.4. The method of claim 3 , wherein said solution containing said low dielectric constant material is deposited prior to depositing said another solution containing said CNTs.5. The method of claim 1 , further comprising curing said composite dielectric material.6. The method of claim 1 , wherein said low dielectric constant material comprises atoms of silicon claim 1 , carbon claim 1 , oxygen and hydrogen.7. The method of claim 1 , wherein said CNTs in said another solution have a diameter from 1 nm to ...

ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers. 1. A process comprising: (a) forming wire embedded in a dielectric layer on a semiconductor substrate , said wire comprising a copper core comprising sidewalls and a bottom of said copper core , a top surface of said wire coplanar with a top surface of said dielectric layer; (b) forming an electrically conductive alloy liner on said sidewalls based on Mn , with at least one of Co and/or W to minimize or eliminate EM and/or TDDB; (c) without exposing said substrate to oxygen , forming a dielectric liner over said alloy liner , any exposed portions of said alloy liner , and said dielectric layer.2. The process of claim 1 , wherein: (b) and (c) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber; or (b) and (c) are performed in a different chamber or chambers of a second deposition tool without removing said substrate from said tool.3. The process of claim 1 , wherein said liner is formed by either selective ...

ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers. 115-. (canceled)16: A deposition tool comprising: a load/unload chamber; a mechanism for transferring a substrate between said load/unload chamber and a deposition chamber , said deposition chamber connected to said load/unload chamber by a port; and wherein said deposition chamber is (i) configured to selectively form a metal layer or layers on copper by chemical vapor deposition or by atomic layer deposition and (ii) is configured to form a dielectric layer by chemical vapor deposition , and additionally comprising further downstream chambers selected from at least one of a UV and a Low rf stream plasma or thermal cure means in at least one of a reducing environment ambient to enhance the reaction/intermixing between said layer or layers and said copper.17: The deposition tool of having from about 4 to about 5 chambers including a lower chamber claim 16 , said chambers being employed for depositing multilayer metals claim 16 , metal alloys and dielectrics and ...

ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers. 1. A process comprising: (a) forming wire embedded in a dielectric layer on a semiconductor substrate , said wire comprising a copper core comprising sidewalls and a bottom of said copper core , a top surface of said wire coplanar with a top surface of said dielectric layer; (b) forming an electrically conductive alloy liner on said sidewalls based on Mn , with at least one of Co and/or W to minimize or eliminate EM and/or TDDB; (c) without exposing said substrate to oxygen , forming a dielectric liner over said alloy liner , any exposed portions of said alloy liner , and said dielectric layer.2. The process of claim 1 , wherein: (b) and (c) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber; or (b) and (c) are performed in a different chamber or chambers of a second deposition tool without removing said substrate from said tool.3. The process of claim 1 , wherein said liner is formed by either selective ...

HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. 1. A method of forming a dielectric film comprising:introducing a substrate into a chamber of a deposition tool;heating the substrate at a process temperature;introducing a hydrogen-free precursor into said chamber of the deposition tool; andactivating a plasma in the chamber.2. The method of where at least one additional hydrogen-free reactive gas is introduced into the chamber of said deposition tool.3. The method of wherein at least one additional inert gas is introduced into the chamber of said deposition tool.4. The method of claim 1 , wherein introducing a hydrogen-free precursor comprises introducing tetraisocyanatosilane.5. The method of claim 1 , wherein the substrate is preheated at a process temperature ranging from about 100 degrees Celsius to about 400 degrees Celsius.6. The method of claim 1 , wherein the hydrogen-free precursor is introduced to the chamber at a total gas flow rate ranging from about 30 sccm to about 350 sccm.7. The method of claim 2 , wherein the at least one additional hydrogen ...

GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES

Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Ultrathin Multilayer Metal Alloy Liner for Nano Cu Interconnects

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers. 1. A process comprising: (a) forming wire embedded in a dielectric layer on a semiconductor substrate , said wire comprising a copper core comprising sidewalls and a bottom of said copper core , a top surface of said wire coplanar with a top surface of said dielectric layer; (b) forming an electrically conductive alloy liner on said sidewalls based on Mn , with at least one of Co and/or W to minimize or eliminate EM and/or TDDB; (c) without exposing said substrate to oxygen , forming a dielectric liner over said alloy liner , any exposed portions of said alloy liner , and said dielectric layer.2. The process of claim 1 , wherein: (b) and (c) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber; or (b) and (c) are performed in a different chamber or chambers of a second deposition tool without removing said substrate from said tool.3. The process of claim 1 , wherein said liner is formed by either selective ...

MICROWAVE PLASMA AND ULTRAVIOLET ASSISTED DEPOSITION APPARATUS AND METHOD FOR MATERIAL DEPOSITION USING THE SAME

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided. 1. An apparatus for depositing a material on a substrate , the apparatus comprising:a processing chamber defining a processing space in which the substrate is arranged;a remote excitation chamber that defines an excitation space, wherein the excitation space is provided remotely from the processing space, a precursor gas into the processing space, and', 'a reactive gas into the excitation space,, 'a gas feed assembly configured to feedan ultraviolet radiation assembly arranged to the remote excitation chamber, wherein the ultraviolet radiation assembly is configured to emit ultraviolet radiation into the excitation space to excite the reactive gas;a microwave radiation assembly arranged to the remote excitation chamber, wherein the microwave radiation assembly is configured to emit microwave radiation into the excitation space to excite the reactive gas; anda conduit communicating the excitation space and the processing space to facilitate diffusion of excited reactive gas from the excitation space to the processing space,2. The apparatus according to claim 1 , wherein the ...

MICROWAVE PLASMA AND ULTRAVIOLET ASSISTED DEPOSITION APPARATUS AND METHOD FOR MATERIAL DEPOSITION USING THE SAME

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided. 1. A method for depositing a material on a substrate , the method comprising:feeding a precursor gas into a processing space in which the substrate is arranged;feeding a reactive gas into the processing space;operating an ultraviolet radiation assembly to emit ultraviolet radiation into the processing space in combination with operating a microwave radiation assembly to emit microwave radiation into the processing space, wherein the emitted ultraviolet radiation and the emitted microwave radiation that enter into the processing space containing the substrate collectively excite at least the reactive gas that is fed into the processing space containing the substrate; anddepositing the material on the substrate in the processing space from a reaction of the excited reactive gas and the precursor gas.2. The method according to claim 1 , wherein the feeding of the precursor gas into the processing space and the feeding of the reactive gas into the processing space comprises:operating a gas feed assembly comprising a plurality of conduits, wherein each of the plurality of conduits ...

Diamond-like carbon for use in VLSI and ULSI interconnect systems

The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon (20) as an insulator for spacing apart one or more levels of a conductor (16,22) on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer (20) from a substrate (12) containing such a layer.

Diamond-like carbon for use in VLSI and ULSI interconnect systems

The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

Diamond-like carbon for use in VLSI and ULSI interconnect systems

The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

Diamond-like carbon for use in VLSI and ULSI interconnect systems

The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

Multiphase low dielectric constant material

A low dielectric constant, multiphase material which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a multiphase low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of the multiphase low dielectric constant materials that are prepared by the method are further disclosed.

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

A method to obtain thin (less than 300 nm) strain-relaxed Si 1−x Ge x buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 6 cm 2 . The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si 1−x Ge x layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si 1−x Ge x interface, parallel to the Si(001) surface.

Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector

The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Enhanced T-gate structure for modulation doped field effect transistors

A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Electric device and manufacture thereof

(57)【要約】 【課題】 ノン・プレーナー・コンデンサおよび強誘電 体のメモリ・セルの内部に、誘電体構造を形成する製造 方法、およびこれらの製造方法を用いたメモリ・デバイ ス構造を提供する。 【解決手段】 強誘電性のまたは高誘電率の誘電材料を 付着して、幾何学的な幅が、最終デバイスにおける強誘 電体または高誘電率誘電体の電気的活性部分の厚さの唯 一の決定要素となる凹部を、完全に充填する製造方法で ある。好適な実施例においては、誘電体が付着される凹 部は、誘電体の付着の前のスルー・マスクめっき工程 で、付着されパターニングされる、プレート電極とスタ ック電極との間のギャップによって画成される。

Hydrogenated oxidized silicon carbon material

A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

Electronic structures with reduced capacitance

An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.

Ultrathin multilayer metal alloy liner for nano Cu interconnects

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacity

An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.

Ultralow dielectric constant layer with controlled biaxial stress

A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Ultra low k (ulk) sicoh film and method

The present invention provides a multiphase, ultra low k film exhibiting improved elastic modulus and hardness, and various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, represented by (104), (103), (102) and (101) respectively, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred film includes atoms of Si, C, O and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater. These films consist of a first phase (100) of “host” matrix that is a random network of hydrogenated oxidize silicon carbon material (SiCOH), and a second phase (105) consisting essentially of C and H atoms.

Electrode structure and capacitor with materials with high dielectric constant

Method for fabricating an ultralow dielectric constant material

A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide. To stabilize plasma in the PECVD reactor and thereby improve uniformity of the deposited film, CO 2 is added to TMCTS as a carrier gas, or CO 2 or a mixture of CO 2 and O 2 are added to the PECVD reactor.

Magnetic head slider and its manufacturing process

Formation of a vicinal semiconductor-carbon alloy surface and a graphene layer thereupon

A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material. Once all semiconductor material is consumed, graphitization occurs in which graphene layers can be formed on the vicinal surfaces having atomic level surface flatness.

Methods to form SiCOH or SiCNH dielectrics and structures including the same

Methods of forming dielectric films comprising Si, C, O and H atoms (SiCOH) or Si, C, N and H atoms (SiCHN) that have improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties are provided. Electronic structures including the above materials are also included herein.

Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same

A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the adhesion between different dielectric is enhanced by an intermediate a-Si, a-Ge, or alloys thereof bonding layer. The thin a-Si, a-Ge, or alloys thereof layer may be hydrogenated or non-hydrogenated, or even partially oxidized.

Flip FERAM cell and method to form same

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Flip feram cell and method to form same

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Thin film magnetic head having a protective coating and method for making same

A MAGNETIC HEAD SLIDER HAVING A PROTECTIVE COATING ON THE RAILS THEREOF, THE PROTECTIVE COATING COMPRISING A THIN ADHESION LAYER AND A THIN LAYER OF AMORPHOUS HYDROGENATED CARBON. THE PROTECTIVE COATING IS DEPOSITED ON THE AIR BEARING SURFACE OF THE SLIDER AFTER THE THIN FILM MAGNETIC HEADS ARE LAPPED TO A CHOSEN DIMENSION, BUT BEFORE THE PATTERN OF RAILS IS PRODUCED ON THE AIR BEARING SURFACE. THE PROTECTIVE COATING PROTECTS THE MAGNETIC HEAD DURING THE RAIL FABRICATION PROCESS AND IN USAGE IN A MAGNETIC RECORDING SYSTEM PROTECTS THE MAGNETIC HEAD FROM WEAR AND CORROSION DAMAGE.(FIG. 5)

Tunable vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and applications thereof

A lithographic structure and method of fabrication and use thereof having a plurality of layers at least one of which is a an RCHX layer which comprises a material having structural formula R:C:H:X, wherein R is selected from the group consisting of Si, Ge, B, Sn, Fe, Ti and combinations thereof and wherein X is not present or is selected from the group consisting of one or more of O, N, S, and F and a layer of an energy active material. The RCHX layers are useful as hardmask layers, anti-reflection layers and hardmask anti-reflection layers. The RCHX layer can be vapor-deposited and patterned by patterning the energy active material and transferring the pattern to the RCHX layer.