Способ разъединения полупроводниковой пластины, включающей несколько стопок солнечных элементов

Изобретение относится к технологии производства полупроводниковых приборов. Согласно изобретению предложен способ разъединения полупроводниковой пластины, включающей несколько стопок солнечных элементов, вдоль по меньшей мере одной разделительной линии, который включает по меньшей мере следующие стадии: предоставление полупроводниковой пластины с верхней стороной, нижней стороной, слоем адгезива, неразъемно соединенным с верхней стороной, и покровным стеклянным слоем, неразъемно соединенным со слоем адгезива, причем полупроводниковая пластина включает несколько стопок солнечных элементов, каждая из которых имеет германиевую подложку, образующую нижнюю сторону полупроводниковой пластины, германиевый частичный элемент и по меньшей мере два частичных элемента из элементов III-V групп; выполнение посредством лазерной абляции вдоль разделительной линии разделительной канавки, проходящей от нижней стороны полупроводниковой пластины насквозь через полупроводниковую пластину и слой адгезива по ...

УСТРОЙСТВО ДЛЯ ХИМИЧЕСКОГО РАЗДЕЛЕНИЯ ПОЛУПРОВОДНИКОВЫХ ПЛАСТИН НА КРИСТАЛЛЫ

Изобретение относится к устройствам для химического жидкостного разделения полупроводниковых пластин на кристаллы без использования механических устройств и электроэнергии. Устройство для химического разделения полупроводниковых пластин на кристаллы содержит рабочую емкость, перфорированные элементы и съемный набор масок, в котором расположение пазов совпадает с расположением областей разделения на кристаллы, перфорированные элементы - основание и крышка, крышка посажена на основание, а диаметр отверстия перфорации и расстояние от нижней плоскости крышки до верхней плоскости полупроводниковой пластины либо верхней плоскости съемных масок не превышает минимальный размер грани кристалла. Изобретение обеспечивает повышение выхода годных кристаллов, сокращает потребление энергии, повышает эргономичность устройства, осуществляет возможность формирования кристаллов различной формы. 1 з.п. ф-лы, 5 ил.

Verfahren zur Herstellung von Halbleiterelementen

A process is disclosed for manufacturing semiconductor components, in particular diodes. The following steps are successively carried out: bonding two semiconductor bodies (wafer 1, 2) having different conductivity types (p, n) according to the silicon fusion bonding process; separating a plurality of semiconductor elements (chips 8) by generating wells (9) whose depth extends at least down to the pn-junctions; overetching and passivating the pn-junctions laterally exposed by the wells (9); metallizing the surfaces (10, 11) of the semiconductor bodies and cutting out the semiconductor elements from the semiconductor bodies.

VERFAHREN ZUM HERSTELLEN INTEGRIERTE SCHALTUNGSANORDNUNGEN

LASER-BEHANDLUNG

Chipgehäuse und Verfahren zum Herstellen eines Chipgehäuses

Ein Verfahren zum Herstellen eines Chipgehäuses wird bereitgestellt. Das Verfahren aufweisend: Halten eines Trägers (402), aufweisend eine Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden einer Separation zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n) mittels Entfernens eines oder mehr Bereiche (422) des Trägers (402) von dem Träger (402) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden eines Verkapselungsmaterials (434) in dem einen oder den mehreren entfernten Bereichen (428) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n Vereinzeln der Dies (4041, 4042, 4043, ..., 404n-1, 404n) durch das Verkapselungsmaterial (434).

Semiconductor device production process for producing a laser cut device with a rear plated heat sink

A semiconductor device production process comprises forming metal-covered front and back face separation trenches, the back face trench being formed by etching using a plated heat sink as mask. A semiconductor device production process comprises: (1) applying a first metal layer to cover the surface of a first separation trench in a semiconductor substrate surface; (2) thinning the substrate from its back face; (3) forming a second separation trench at the back face of the first trench to expose the first metal layer and covering the second trench surface with a second metal layer; and (4) laser cutting the first and second metal layers from the first metal layer side. The novelty is that the second trench is formed by etching using a plated heat sink formed in a back face region beyond the back face surface of the first trench, the two metal layers having a reflection capacity of <= 80% with respect to laser light. An Independent claim is also included for a device produced by the above ...

Gepackte Halbleitervorrichtung und Verfahren zum Packen der Halbleitervorrichtung

Mechanismen zum Ausbilden einer Formmasse auf einem Halbleitervorrichtungssubstrat zum Ermöglichen von Fan-Out-Strukturen beim Wafer-Level-Packaging (WLP) werden bereitgestellt. Die Mechanismen umfassen das Bedecken von Abschnitten von Oberflächen einer Isolierschicht, die ein Kontaktpad umgibt. Die Mechanismen verbessern die Zuverlässigkeit der Packung und der Prozesssteuerung des Packprozesses. Die Mechanismen reduzieren außerdem das Risiko von Delaminieren an Grenzflächen und übermäßiges Ausgasen der Isolierschicht während nachfolgender Verarbeitung. Die Mechanismen verbessern ferner den Endpunkt einer Planarisierung. Durch Verwenden einer Schutzschicht zwischen dem Kontaktpad und der Isolierschicht kann Kupferaußendiffusion reduziert werden, und die Haftung zwischen dem Kontaktpad und der Isolierschicht kann ebenfalls verbessert werden.

Method for processing disk-shaped semiconductor wafer utilized for producing semiconductor chips, involves applying adhesive to outer peripheral portion of wafer semiconductor, so that additional processing of wafer is performed

The method involves attaching a protective tape on a front side (11a) of a semiconductor wafer (11). A backside (11b) of the wafer is sharpened in a central portion corresponding to a device region (17) to form a circular recess and an annular protrusion. The tape is removed from the wafer front side after the sharpening process. Heat-resistant adhesive is applied to an outer peripheral portion of the wafer in order to bond a substrate on the front side of the wafer after the removing process. An additional processing of the wafer is performed after performing the adhesive applying process.

Substrat und Verfahren zur Bruchvorbereitung eines Substrats für mindestens ein Leistungshalbleiterbauelement

Die Erfindung betrifft ein Verfahren zur Bruchvorbereitung eines Substrats (1) für mindestens ein Leistungshalbeiterbauelement mit folgenden Verfahrensschritten: a) Bereitstellen des Substrats (1), wobei das Substrat (1) einen elektrisch nicht leitenden Isolierstoffkörper (2) aufweist, b) Materialabtrag am Isolierstoffkörper (2) entlang gewünschter Bruchkanten (A, B, C, D, E) des Substrats (1), wobei der Materialabtrag derart durchgeführt wird, dass in Eckbereichen (14) an denen mindestens zwei gewünschte (A, B, C, D, E) Bruchkanten zusammentreffen, ein gegenüber dem Materialabtrag, welche in den übrigen Bereichen (17) der gewünschten Bruchkanten (A, B, C, D, E) durchgeführt wird, höherer Materialabtrag durchgeführt wird. Weiterhin betrifft die Erfindung ein diesbezügliches Substrat (1). Die Erfindung ermöglicht die Reduktion von unerwünschten Ausbrüche am Isolierstoffkörper (2) beim Brechen eines Substrats (1) für mindestens ein Leistungshalbeiterbauelement.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

Laserbearbeitungsvorrichtung

Eine Fokussiereinheit einer Laserbearbeitungsvorrichtung beinhaltet: eine Fokuslinse, die einen Laserstrahl, der durch eine Oszillationseinheit für einen Laserstrahl oszilliert wird, fokussiert; und eine sphärische Aberrationsverlängerungslinse, welche die sphärische Aberration der Fokussierlinse verlängert. Ein gepulster Laserstrahl wird von der Fokussiereinheit auf einem Werkstück aufgebracht, das an einem Einspanntisch gehalten wird, um Abschirmtunnel auszubilden, von denen jeder aus einem feinen Loch und einem amorphen Bereich, der das feine Loch abschirmt, besteht, wobei die Abschirmtunnel sich von einer oberen Oberfläche zu einer unteren Oberfläche des Werkstücks erstrecken.

VORRICHTUNG ZUM ABHOLEN VON IC"S VON EINEM WAFER

Verfahren zum Bearbeiten eines Wafers und Waferbearbeitungssystem

Die Erfindung betrifft ein Verfahren zum Bearbeiten eines Wafers (2), der an einer Seite (4) einen Bauelementbereich mit mehreren Bauelementen, die durch mehrere Trennlinien abgetrennt sind, aufweist. Das Verfahren umfasst ein Anbringen der einen Seite (4) des Wafers (2) oder der Seite (6) des Wafers (2), die der einen Seite (4) gegenüberliegt, an einem durch einen ersten ringförmigen Rahmen (10) gehaltenen Haftband (8), ein Teilen des Wafers (2) entlang der Trennlinien in mehrere Chips (20), und ein Anordnen des an dem Haftband (8) angebrachten Wafers (2) an einer Halteoberfläche (14) eines Halteelements (16) vor oder nach dem Teilen des Wafers (2), wobei ein äußerer Durchmesser des Halteelements (16) in der Ebene der Halteoberfläche (14) kleiner als ein innerer Durchmesser des ersten ringförmigen Rahmens (10) ist. Das Verfahren umfasst ferner, nach dem Teilen des Wafers (2) den ersten ringförmigen Rahmen (10) und zumindest einen Umfangsteil des Halteelements (16) relativ zueinander in ...

Wasser-Bearbeitungsverfahren

Es wird ein Wafer-Bearbeitungsverfahren zum Aufteilen eines Wafers in einzelne Bauelemente entlang von Trennlinien offenbart, die an der Vorderseite des Wafers ausgebildet sind. Das Wafer-Bearbeitungsverfahren schließt einen Schutzbandanbringschritt zum Anbringen eines Schutzbands, das eine Haftschicht aufweist, an der Vorderseite einer Funktionsschicht des Wafers in einem Zustand ein, in dem die Haftschicht des Schutzbands mit der Vorderseite der Funktionsschicht in Kontakt ist, und einen Wafer-Teilungsschritt zum Halten des Wafers mit dem Schutzband an einer Haltefläche eines Spanntischs in dem Zustand, in dem das Schutzband mit der Haltefläche in Kontakt ist, und als nächstes Aufbringen eines Laserstrahls, der eine Absorptionswellenlänge für das Substrat und die Funktionsschicht des Wafers aufweist, entlang jeder Trennlinie von der Rückseite des Substrats aus, um eine laserbearbeitete Nut mit einer Tiefe auszubilden, welche das Schutzband entlang jeder Trennlinie erreicht, wodurch der ...

Method of producing a semiconductor device

The invention relates to a method of producing a semiconductor device from a semiconductor wafer containing a multiplicity of semiconductor devices. According to the invention, a grid-type partitioning which corresponds to the grid-type partitioning of the front is applied to the back of the semiconductor wafer. Gold contact layers separated from one another by the grid-type partitioning are deposited inside the units of the grid. Finally, the semiconductor wafer is divided up along the gold-free grid lines between the individual elements.

HALBLEITERVORRICHTUNG MIT UMLAUFENDER STRUKTUR UND VERFAHREN ZUR HERSTELLUNG

Eine umlaufende eingebettete Struktur wird durch Laserbestrahlung in einem Halbleitersubstrat ausgebildet, welches aus einem Halbleitermaterial besteht. Die eingebettete Struktur umfasst eine polykristalline Struktur des Halbleitermaterials und umgibt einen zentralen Bereich eines Halbleiterdie. Das Halbleiterdie, das die eingebettete Struktur enthält, wird von dem Halbleitersubstrat getrennt.

Verfahren, Vorrichtung und Beugungsgitter zum Trennen von Halbleiterelementen, die auf einem Substrat gebildet werden, durch Änderung besagten Beugungsgitters

Verfahren zum Trennen von Halbleiterelementen, die auf einem Substrat gebildet werden, wie Halbleiterelementen, die in einem Wafer aus Halbleitermaterial gebildet werden, unter Verwendung eines Lasers, der mindestens einen primären Laserstrahl produziert, wobei besagter mindestens ein primäre Laserstrahl in eine Vielzahl von sekundären Laserstrahlen unter Verwendung eines ersten Beugungsgitters aufgetrennt wird, das eine erste Gitterstruktur besitzt und durch Auftreffen lassen des besagten mindestens einen primären Laserstrahls auf besagte erste Beugungsstruktur, und wobei mindestens eine erste Rille durch Bewegen des besagten Lasers relativ zu besagtem Substrat in eine erste Richtung gebildet wird, besagtes Verfahren ferner umfassend einen Schritt zur Bildung mindestens einer zweiten Rille durch Bewegen des besagten Lasers relativ zu besagtem Substrat in eine zweite Richtung, charakterisiert dadurch, dass besagte zweite Gitterstruktur durch besagtes erstes Beugungsgitter umfasst ist, und ...

Herstellungsverfahren von elektronischen Komponenten

EINRICHTUNG ZUM EXTRAHIEREN ELEKTRONISCHER KOMPONENTEN

Halbleiterwafer mit nichtrechteckig geformten Chips

Halbleiterwafer, der umfasst: eine Mehrzahl von auf dem Wafer gebildeten Chips, wobei die Mehrzahl von Chips nichtrechteckige Formen mit mindestens einer gekerbten Ecke aufweisen; und eine Mehrzahl von zwischen der Mehrzahl von Chips definierten Sägegassen, wobei an einer Kreuzung von zwei der Mehrzahl von Sägegassen ein Abstand zwischen zwei Ecken von zwei benachbarten Chips definiert wird, der größer ist als ein minimaler Abstand zwischen den zwei benachbarten Chips.

Gruppe III/Nitrid-basierte Verbindungshalbleitervorrichtung und dessen Herstellungsverfahren

Die Erfindung betrifft ein Verfahren zur Herstellung einer Gruppe III/Nitrid-basierten Verbindungshalbleitervorrichtung mit dem Trennen der Vorrichtung in individuelle Chips mittels eines Rohchipzerteilungsmessers. Ein Abschnitt einer Epitaxieschicht, wo ein Rohchipzerteilungsmesser anzuordnen ist, wird teilweise oder vollständig durch einen Ätzvorgang entfernt, um dadurch einen Graben auszubilden. Eine isolierende Schicht wird auf dem Boden und auf den Seitenoberflächen des Grabens ausgebildet. Ein Wafer wird in Chips derart zerteilt, dass der Boden des Grabens mittels des Rohchipzerteilungsmessers entfernt wird, ohne die Seitenoberflächen der isolierenden Schicht vollständig zu entfernen. Die isolierende Schicht wird auf den Seitenoberflächen des Grabens derart ausgebildet, dass die Schicht eine p-Schicht bis zu einer n-Schicht bedeckt, die in Gruppe III/Nitrid-basierten Verbindungshalbleiterschichten enthalten sind, so dass ein Kurzschluss zwischen der p-Schicht und der n-Schicht vermieden ...

Waferprodukt und Herstellungsverfahren dafür

Waferprodukt, das aufgrund einer Multiphotonenabsorption durch Schneiden mit einem umgestalteten Bereich (R) geschnitten und getrennt wird, der durch ein Laserlicht (L) ausgebildet wird, das an einen lichtkonvergierenden Punkt (P) aufgebracht wird, der als Startpunkt zum Schneiden angeordnet ist, wobei das Waferprodukt aufweist: einen Wafer (10) mit zwei Flächen (10a, 10b), von welchen eine eine Laserlichteinfallsfläche (10b) ist, dadurch gekennzeichnet, dass eine andere Fläche (10a), welche der Laserlichteinfallsfläche (10b) gegenüberliegend angeordnet ist, derart aufgeraut ist, dass sie gleichförmige Erhebungen und Vertiefungen (10c) daran aufweist, und eine maximale Höhe von Erhebungen und Vertiefungen einer Oberflächenrauheit gleich oder größer als eine Wellenlänge des Laserlichts (L) ist.

Herstellverfahren für Chips mit Metallschichten

Herstellverfahren für mehrere Chips, die jeweils eine Metallschicht an der Rückseite aufweisen, umfassend:einen Trennlinienerfassungsschritt zum Abbilden eines Werkstücks von dessen Rückseite aus durch Verwendung einer Infrarotkamera, wobei die Vorderseite des Werkstücks durch mehrere Trennlinien in mehrere Chipbereiche unterteilt ist, wodurch die Positionen der an der Vorderseite des Werkstücks ausgebildeten Trennlinien erfasst werden;einen ersten Nutausbildungsschritt zum Ausbilden mehrerer erster Nuten an der Rückseite des Werkstücks an den Positionen, die jeweils den Positionen der Trennlinien entsprechen, nach dem Durchführen des Trennlinienerfassungsschritts;einen Metallschichtausbildungsschritt zum Ausbilden der Metallschicht an der Rückseite des Werkstücks, so dass die Positionen der ersten Nuten bestimmt werden können, nach dem Durchführen des ersten Nutausbildungsschritts;einen zweiten Nutausbildungsschritt zum Ausbilden mehrerer zweiter Nuten an der Rückseite des Werkstücks an ...

Schichtbauelement-Herstellungsverfahren

Schichtbauelement-Herstellungsverfahren zur Herstellung eines Schichtbauelements unter Verwendung eines verstärkten Wafers (20), bei dem der verstärkte Wafer (20) durch auf einer vorderen Oberfläche (20a) in einem Gittermuster angeordnete Straßen (21) in mehrere Bereiche unterteilt ist und einen mit Bauelementen (22) in den so abgeteilten Bereichen ausgebildeten Bauelementbereich (23) und einen äußeren Umfangsüberschussbereich (24), der den Bauelementbereich (23) umgibt, beinhaltet, ein Bereich einer hinteren Oberfläche (20b), der dem Bauelementbereich (23) entspricht, so geschliffen wird, dass der Bauelementbereich (23) so ausgebildet werden kann, dass er eine vorgegebene Dicke aufweist, und ein Bereich, der dem äußeren Umfangsüberschussbereich (24) entspricht, belassen werden kann, um einen ringförmigen verstärkten Abschnitt (24b) zu bilden, wobei das Verfahren umfasst:einen Waferschichtungsschritt, bei dem ein unten liegender Wafer (200), der einen Durchmesser aufweist, der geringfügig ...

VERFAHREN ZUM VEREINZELN VON WAFERN IN CHIPS

WAFERBEARBEITUNGSVERFAHREN

Es wird ein Waferbearbeitungsverfahren zum Bearbeiten eines Wafers offenbart, der eine Vielzahl von Bauelementen in Bereichen angeordnet aufweist, die durch vorbestimmte Trennlinien begrenzt sind und an dessen Vorderseite ausgebildet sind, wobei das Wafer Bearbeitungsverfahren einen Schutzelementplatzierungsschritt mit einem Platzieren eines Schutzelements zum Schützen der Vorderseite des Wafers an der Vorderseite des Wafers, der in einzelne Bauelementchips unterteilt ist, einen Harzauftragsschritt mit einem Aufbringen eines Chipbindeharzes auf den Rückseiten der einzelnen Bauelementchips durch Aufbringen eines flüssigen Chipbindeharzes auf der Rückseite des Wafers und Härten des aufgebrachten flüssigen Chipbindeharzes und einen Abtrennschritt mit einem Abtrennen der Bauelementchips, die das auf deren Rückseiten aufgetragene Chipbindeharz aufweisen, von dem Wafer einschließt.

Verfahren und Herstellung eines Halbleiterbauelements

Ein Verfahren zur Herstellung eines Halbleiterbauelements umfasst Bereitstellen eines monokristallinen Halbleitersubstrats (10) mit einer ersten Seite; Bilden mehrerer Aussparungsstrukturen (12a) in dem Halbleitersubstrat (10) auf der ersten Seite; Füllen der Aussparungsstrukturen (12a) mit einem dielektrischen Material zum Bilden von dielektrischen Inseln (12) in den Aussparungsstrukturen (12a); Bilden einer Halbleiterschicht (13) auf der ersten Seite des Halbleitersubstrats (10) zum Bedecken der dielektrischen Inseln (12); und Aussetzen der Halbleiterschicht (13) einer Wärmebehandlung und Rekristallisieren der Halbleiterschicht (13). Die Kristallstruktur der rekristallisierten Halbleiterschicht passt sich an die Kristallstruktur des Halbleitersubstrats an. Das Halbleitersubstrat (10) und die Halbleiterschicht (13) bilden zusammen einen Verbundwafer, wobei die dielektrischen Inseln (12) zumindest teilweise in dem Halbleitermaterial des Verbundwafers vergraben sind.

Haltetisch und Verwendung des Haltetischs

Haltetisch (5) zum Halten eines Wafers (W), der einen Bauelementbereich (83), an dem mehrere Bauelemente ausgebildet sind, und einen Umfangsrandbereich (84), der den Bauelementbereich (83) umgibt, an einer Vorderseite (80) des Wafers (W) aufweist, wobei der Wafer (W) ferner einen an einer Rückseite (81) des Umfangsrandbereichs (84) ausgebildeten ringförmigen Verstärkungsabschnitt (85) aufweist; der Haltetisch (5) eine obere Oberfläche aufweist, die mit einer ringförmigen Austrittsnut (53) zum Ermöglichen des Austritts eines Laserstrahls ausgebildet ist, wobei die ringförmige Austrittsnut (53) so ausgebildet ist, dass sie einem Grenzabschnitt (86) zwischen dem Bauelementbereich (83) und dem ringförmigen Verstärkungsabschnitt (85) des an der oberen Oberfläche des Haltetischs (5) gehaltenen Wafers (W) entspricht, und ein unteres Ende (54) der Austrittsnut (53) angeschrägt und mit feinen Unebenheiten zum Streuen des Laserstrahls ausgebildet ist.

VERFAHREN ZUM HERSTELLEN EINER SUPERJUNCTION-HALBLEITERVORRICHTUNG UND SUPERJUNCTION-HALBLEITERVORRICHTUNG

Ein Ausführungsbeispiel eines Verfahrens zum Herstellen einer Halbleitervorrichtung in einem Halbleiterkörper (106) eines Wafers umfasst ein Bilden einer Maske (102) auf einer Oberfläche (104) des Halbleiterkörpers (106). Die Maske (102) umfasst eine Vielzahl von ersten Maskenöffnungen (108) in einem Transistorzellgebiet (110) und ein Maskenöffnungsdesign (109) außerhalb des Transistorzellgebietes (110). Das Maskenöffnungsdesign (109) umfasst eine zweite Maskenöffnung (1091) oder eine Vielzahl von zweiten Maskenöffnungen (1092), das Transistorzellgebiet (110) umgebend. Die Vielzahl von zweiten Maskenöffnungen (1092) ist aufeinanderfolgend unter lateralen Abständen kleiner als eine Breite der Vielzahl von zweiten Maskenöffnungen (1092) angeordnet. Eine Vielzahl von ersten Trenches (111) ist in dem Halbleiterkörper bei den ersten Maskenöffnungen (108) gebildet. Ein oder eine Vielzahl von zweiten Trenches (1121, 1122) ist bei der einen oder der Vielzahl von zweiten Maskenöffnungen (1091, 1092 ...

Waferherstellungsverfahren

Ein Waferherstellungsverfahren zum Herstellen eines Wafers aus einem Lithiumtantalat-Ingot beinhaltet einen Schritt zum Bestrahlen von einer Endfläche eines Lithiumtantalat-Ingots, der ein Ingot mit einem um 42° gedrehten Y Schnitt ist, der eine Orientierungsfläche aufweist, die parallel zu einer Y Achse ausgebildet ist, mit einem Laserstrahl, der eine Wellenlänge aufweist, für die Lithiumtantalat transparent ist, wobei ein Fokuspunkt des Laserstrahls im inneren des Ingots positioniert ist, um eine modifizierte Schicht in dem Inneren des Ingots auszubilden, während der Ingot für eine Verarbeitung zugeführt wird, und einen Schritt zum Aufbringen einer äußeren Kraft auf dem Ingot, um ein plattenförmiges Material von dem Ingot abzulösen, um einen Wafer herzustellen. Bei dem Schritt zum Ausbilden einer modifizierten Schicht wird der Ingot für eine Bearbeitung relativ in einer Richtung parallel oder senkrecht zu der Orientierungsfläche zugeführt.

Verfahren zum Damage-Ätzen der Rückseite einer Halbleiterscheibe bei geschützter Scheibenvorderseite

Package für Hochleistungs-Halbleitervorrichtungen

Verfahren und Einrichtungen zum Bilden eines Package für Hochleistungshalbleitervorrichtungen sind hierin beschrieben. Ein Package kann eine Mehrzahl von einzelnen thermischen Verteilerschichten aufweisen, die zwischen einem Chip und einem Metallträger angeordnet sind. Andere Ausführungsformen sind beschrieben und beansprucht.

Mesa semiconductor device with insulating surface film - has at least one pn-junction provided at chip surface and support element on one main surface

The chip of the mesa semiconductor device has one main surface, with at least one p-n junction (12) reaching the surface. The latter is coated by an insulating film (18). A supporting element is fastened to the other main surface. The insulating film (18) thickness increases with the distance from the chip main surface. Preferably, the semiconductor chip has two opposite mesa sections, succh as grooves and the insulating film covers a peripheral or edge surface of each mesa section. The insulating film may be of low melting point glass.

OPTOELEKTRONISCHES BAUELEMENT MIT EINER MARKIERUNG UND VERFAHREN ZUM HERSTELLEN VON OPTOELEKTRONISCHEN BAUELEMENTEN

Ein Verfahren zum Herstellen von optoelektronischen Bauelementen (100) umfasst folgende Schritte: Bereitstellen von mehreren optoelektronischen Halbleiterchips (12), die in eine Trägerschicht (20) eingebettet sind, wobei eine Konversionsschicht (21) auf den optoelektronischen Halbleiterchips (12) und der Trägerschicht (20) aufgebracht ist, Erzeugen von Markierungen (25) in und/oder auf der Konversionsschicht (21), und Durchtrennen der Trägerschicht (20), um optoelektronische Bauelemente (100) zu erhalten, wobei die optoelektronischen Bauelemente (100) jeweils mindestens eine der Markierungen (25) aufweisen.

HALBLEITER-BAUELEMENTCHIP UND HERSTELLUNGSVERFAHREN FÜR EINEN HALBLEITER-BAUELEMENTCHIP

Ein Halbleiter-Bauelementchip beinhaltet ein Halbleiter-Substrat, das eine erste Oberfläche und eine zweite Oberfläche gegenüber der ersten Oberfläche aufweist, ein Halbleiter-Bauelement, das an der ersten Oberfläche des Halbleiter-Substrats angeordnet ist, eine Verbindungsanordnung, die ein Ende verbunden mit dem Halbleiter-Bauelement und ein anderes Ende freiliegend an einer Oberfläche einer Funktionsschicht aufweist, die an der ersten Oberfläche des Halbleiter-Substrats angeordnet ist, mehrere externe Verbindungselektroden, die an der Oberfläche der Funktionsschicht montiert sind und elektrisch mit dem anderen Ende der Verbindungsanordnung verbunden sind, einen Abschirmfilm für eine elektromagnetische Welle zum Abschirmen elektromagnetischer Wellen, der an der zweiten Oberfläche des Halbleiter-Substrats und seitlichen Oberflächen der Funktionsschicht angeordnet ist, und eine Erdungsverbindung, die elektrisch mit dem elektromagnetischen Abschirmfilm verbunden und an der Funktionsschicht ...

Druckempfindliche Klebefolie

HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Miniaturisiertes SMD-Diodenpaket und Herstellungsverfahren dafür

Miniaturisiertes SMD-Diodenpaket (10), umfassend:einen Diodenchip (30a, 30b, 30c) mit einer TVS-Diode, einer Schottkydiode, einer Schaltdiode, einer Zenerdiode oder einer Gleichrichterdiode, der eine Bodenfläche aufweist, die mit einer positiven Elektrode (31) und einer negativen Elektrode (31) versehen ist;eine Bodenleiterplatte (50) aus einer Keramikplatte, einer Kunststoffplatte, einer Verbundplatte oder einer wärmeableitenden Platte;zwei Schaltkreiselektroden (56a, 56b), die separat auf der Bodenleiterplatte (50) aufgebracht sind und elektrisch mit der jeweiligen positiven Elektrode und negativen Elektrode (31) an der Bodenfläche des Diodenchips (30a, 30b, 30c) verbunden sind;eine Kapselung (75) aus einem Keramikmaterial oder einem Kunststoffmaterial zur Bildung einer integrierten Struktur mit der Bodenleiterplatte (50), um den Diodenchip (30a, 30b, 30c) und die zwei Schaltkreiselektroden (56a, 56b) zu kapseln, derart dass sich jeweils ein Ende der zwei Schaltkreiselektroden (56a, 56b ...

IN SCHNITTFUGENGEBIETEN ZUR DIE-VEREINZELUNG AUSGEBILDETE VORBEREITENDE GRÄBEN

Vorgesehen wird ein Halbleiter-Wafer (100), der eine Hauptoberfläche (102) und eine der Hauptoberfläche (102) entgegengesetzte rückwärtige Oberfläche (104) aufweist. Ein Schritt zur Vorbereitung einer Die-Vereinzelung wird in Schnittfugengebieten (108) des Halbleiter-Wafers (100) ausgeführt. Die Schnittfugengebiete (108) umschließen eine Vielzahl von Die-Stellen (106). Der Schritt zur Vorbereitung einer Die-Vereinzelung umfasst ein Ausbilden eines oder mehrerer vorbereitender Schnittfugengräben (112) zwischen zumindest zwei unmittelbar benachbarten Die-Stellen (106). Ferner umfasst das Verfahren ein Ausbilden aktiver Halbleitervorrichtungen in den Die-Stellen (106) und ein Vereinzeln des Halbleiter-Wafers (100) in den Schnittfugengebieten (108), wodurch aus den Die-Stellen (106) eine Vielzahl separater Halbleiter-Dies (110) gebildet wird. Der eine oder die mehreren vorbereitenden Schnittfugengräben (112) sind während des Vereinzelns nicht gefüllt, und das Vereinzeln umfasst ein Entfernen ...

SiC-SUBSTRATBEARBEITUNGSVERFAHREN

Es wird ein SiC-Substratbearbeitungsverfahren zum Herstellen eines SiC-Substrats aus einem SiC-Ingot offenbart. Das SiC-Substratbearbeitungsverfahren umfasst einen Trennschichtausbildungsschritt mit einem Einstellen eines Brennpunkts eines Laserstrahls, der eine Transmissionswellenlänge für SiC aufweist auf eine von der oberen Fläche des SiC-Ingots aus vorbestimmte Tiefe im Inneren des SiC-Ingots und als Nächstes einem Aufbringen eines Laserstrahls LB auf den SiC-Ingot, um dadurch eine Trennschicht zum Trennen des SiC-Substrats von dem SiC-Ingot auszubilden, einen Substratanbringschritt mit einem Anbringen eines Substrats an der oberen Fläche des SiC-Ingots und einen Trennschritt mit einem Aufbringen einer äußeren Kraft auf die Trennschicht, um dadurch das SiC-Substrat mit dem Substrat von dem SiC-Ingot entlang der Trennschicht zu trennen.

Verfahren zum Vereinzeln von Wafern in Chips

The invention relates to a method for subdividing a wafer (1) into chips. To this end, the wafer is provided on its back (6) with recesses (7) that weaken the wafer (1) in the points of fracture, thereby allowing for the production of chips whose longitudinal dimensions are smaller than double the thickness of the chips.

Methods of plasma etching and plasma dicing

MANUFACTURING SEMICONDUCTOR DEVICES

... 1383165 Making semi-conductor devices MITSUBISHI DENKI KK 30 April 1973 [28 April 1972] 20482/73 Heading HIK During one or more processing steps semiconductor wafers under treatment remain attached to a parent semi-conductor body. The wafers are separated only at the stage when individual treatment is necessary to continue manufacture. The Figure shows a cylindrical rod of monoerystalline silicon in which wafers 22 have been defined by saw cuts 18 (or other slits) extending nearly through the rod. The end portions 24 are made more substantial and are used as handling bodies and may have apertures 16 to receive the chucks of an etching or cleaning apparatus &c. The wafers 18 in a set need not all have the same thickness. The spine 20 of the rod may be provided with a plane surface so that the wafer set does not roll. Lot identification numbers (not shown) may be marked on the end faces of the handling bodies 24. In alternative arrangements (Figs. 5 and 6, not shown) the wafers may lie parallel ...

Self-aligned contacts for field effect transistor devices

Apparatus for laser beam machining , machining mask, method for laser beam machining, method for manufacturing a semiconductor and semiconductor device

An apparatus for laser beam machining includes a scanning system (9) configured to move an object (20) in a scanning direction from a first edge of the object to another edge of the object; a beam shaping unit (4) configured to convert a laser beam to an asymmetrical machining laser beam in the scanning direction on a plane orthogonal to an optical axis of the laser beam; and an irradiation optical system (6) configured to irradiate the machining laser beam emitted from the beam shaping unit (4) onto the object (20).

A method of dicing wafers to give high die strength

Method of fabrication for electro-optical devices

Laser-based termination of passive electronic components

Semiconductor device structures

A plurality of microwave semiconductor devices is provided by plating a thin heat sink layer on a surface of a wafer of semiconductor material, masking selected portions of the heat sink layer, and plating unmasked portions of the heat sink layer to form a support layer. Substantial portions of the semiconductor material are removed to form a plurality of mesa shaped diodes, at least one semiconductor mesa shaped diode being formed in each region of the semiconductor material disposed on the masked portions of the heat sink layer. Thus each mesa shaped diode, or sets of mesa shaped diodes, has formed on one surface thereof a thin heat sink layer while the mesa shaped diodes are supported by the support layer for subsequent processing. Upper electrodes for the diodes are formed interconnecting the mesa shaped diodes. The individual diodes, or sets thereof, are then separated from the support structure to provide individual single diode, or multiple diode devices.

Semiconductor device with at least one truncated corner and/or side cut-out

A method of producing a substantially rectangular semiconductor device 11 having at least one corner truncation 21 or corner cut-out 22 or side cut-out 31, comprises: a) providing a semiconductor substrate; b) making at least one opening 4 through the substrate by means of etching; and c) cutting the substrate along a first pair 5 of parallel lines, and along a second pair 6 of parallel lines perpendicular to the first pair. At least one of the dicing lines of the first/second pair passes through said opening 4. The etching may be any combination of existing isotropic/anisotropic front/back etching techniques. The through hole 22, cut-out or truncation may be performed by two different etching steps. The cut-out substrate may be used in a transistor outline package and may have elongated legs, which correspond to internal wire connection points 72. This method allows for the fabrication of MEMS semiconductor devices, wherein the substrate is shaped around obstructions by positioning them ...

Laser machining using an active assist gas

A method and apparatus for use in the manufacture of a display element

In a micro-assembly method of manufacture of a display element, a pickup tool (PUT) is used for selective picking of a subset of LED dies from a handle layer. The strength of adhesion of the subset of devices to be picked from the handle layer has been modified, so that the strength of adhesion of the dies to the handle layer is less than the force applied by the pickup tool. The handle layer may be UV tape which is selectively irradiated with a UV light only below the subset of devices to be picked; a thermal release tape; or a multiple layer tape. The devices may be micron scale directional parabolic inorganic LED devices. The subset of devices may be transferred to a substrate of a display element. A computer program may comprise instructions for executing the method.

A QFN with wettable flank

Methods of fabricating a QFN with wettable flank are described. In an embodiment, a leadframe 506 is used which comprises regions of reduced thickness dam bar which extend across an edge of a kerf width 508 and the QFN are formed using film assisted molding with a shaped mold chase 504 that comprises raised portions which correspond in shape and position to the one or more regions of reduced thickness in the leadframe. The shaped mold chase prevents mold compound from filling recesses under the regions of reduced thickness of leadframe and once diced, each QFN has an edge structure which comprises a small step 510, 534, into which solder will wet where there are exposed plated leads. The steps or lips around the peripehery of the QFN allow the solder joints to be inspected.

Method of Dividing Semiconductor Wafers.

... 1,189,582. Etching. LICENTIA PATENTVERWALTUNGS G.m.b.H. 17 May, 1968 [26 July, 1967], No. 23583/68. Heading B6J. [Also in Division Hl] A semi-conductor wafer, e.g. of Si, Ge or a III-V compound, is subdivided into smaller dice by etching through a vapour-deposited metal mask, e.g. of Cr. After etching the wafer, the metal mask may be removed by further etching with dilute HCl activated with Zn.

Semiconductor device and method of making same

... 1,133,376. Semi-conductor rectifiers. RADIO CORPORATION OF AMERICA. 23 May, 1966 [9 June, 1965], No. 22856/66. Heading H1K. A plurality of junction-containing semiconductor wafers are bonded in series in a stack by intervening conductive layers, the lateral surfaces of the wafers being protected by oxidic insulating material overlying which is a different insulating material. Suitable semi-conductors are silicon, germanium, and AIIIBV compounds such as gallium arsenide. Junction-containing wafers 10 may be produced from wafers of one conductivity type by single or double diffusion or by epitaxial growth. Conductive material 24 may be applied as a foil to one side of each wafer, or a conductive layer may be formed by evaporation, plating, spraying on a suspension of powdered material, or by dipping the wafer in powdered material. Conductive materials mentioned are chromium, niobium, palladium, platinum, silver, tantalum, titanium, or zirconium, and germanium and germaniumsilicon ...

SEMICONDUCTOR WAFERS AND PLLETS

... 1314267 Semi-conductor devices GENERAL ELECTRIC CO 4 May 1970 [5 May 1969] 21373/70 Heading H1K Plural semi-conductive assemblies formed in a single crystal wafer of, e.g. silicon (Fig. 3) comprise element 51 with spaced parallel major surfaces 52, 54 separated by N-type central zone 56; a first P-type zone 58 being interposed between zone 56 and major surface 52 to form junction, having central parallel portion 60a and peripheral portion 60b angularly extending toward the second major surface 54. A second P-type zone 62 separates the central zone from the second major surface and a third N+ zone is interposed between the second major surface and a portion of the second zone to form junctions 66, 68. Grooves 70 inwardly spaced from the element edge extend inwardly from the second major surface to intersect the edges of junctions 60b, 66. A dielectric glass passivant 72 is inserted in the grooves to cover the exposed junction edges. An ohmic contact layer 74 is imposed on the first ...

Optoelectronic device

TRIACS

... 1480116 Semi-conductor devices GENERAL ELECTRIC CO 30 Sept 1974 [11 Oct 1973] 42449/74 Heading H1K Spillover of charge carriers between the two oppositely conducting parts of a peripherally glass-passivated triac is reduced by doping the boundary between the parts with a recombination-stimulating impurity such as Au or Pt. In the manufacture of the device illustrated, which is one of many formed in a common wafer and subsequently divided, the oppositely conducting parts 32, 33 are defined by conventional diffusion steps, as is a gate part 34 which includes a junction gate emitter region 27 of the same conductivity type as the main emitter region 26 on the same surface. Au is diffused from a vapour-deposited layer into a generally Y-shaped area of each device defined by an oxide mask and located over the boundaries between the three device parts 32, 33, 34. A control region 28 lies within this area. Suitable conventional masking techniques are then used in the etching of grooves on both ...

SEMICONDUCTOR DEVICES

METHOD OF MAKING A SEMICONDUCTOR DEVICE

SEMICONDUCTORS

... 1493826 Semiconductor devices GENERAL ELECTRIC CO 28 Oct 1974 [30 Oct 1973] 46537/74 Heading H1K [Also in Division B1] An array of columnar recrystallized zones is formed along the length of a semiconductor rod 10 by the temperature-gradient thermomigration of droplets of a solution of the semiconductor material and a metal initially deposited in recesses at most 30 microns deep at one end of the rod, and the rod is then cut into slices, e.g. by scoring and cleaving, so that each slice contains an identical cross-section of the recrystallized zone(s). As shown in Fig. 4 the slices may themselves be diced. Fig. 2 shows an apparatus in which the body 10 is moved continuously or intermittently through a heating station 17 and a cooling station to establish the desired temperature gradient. Migration of Ga through GaP may be used to manufacture light-emitting diodes. Al migration in Si is also referred to, and other semiconductors mentioned are Ge, SiC, GaAs and II-VI compounds.

Passivation technique

Optoelectronic device

Method of processing wafer

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

SEMICONDUCTOR COMPONENT WITH ELECTRICAL CONTACTS AND PROCEDURE FOR THE PRODUCTION OF SUCH CONTACTS

METHOD FOR THE SEPARATION FROM SUBSTRATES

DEVICE FOR FETCHING FROM ICßS FROM a WAFER

MANUFACTURING PROCESS FOR SEMICONDUCTOR CHIPS

PROCEDURE FOR THE PRODUCTION OF COPLANAR CHIP HOUSINGS IN WAFER SIZE

CUT PROCEDURE FOR A TAPE AND DEVICE FOR CUTTING A TAPE

WAFER WITH IMPROVED DIRECTION LOOPS WITHIN THE CUTTING FRAMEWORK

PROCEDURE FOR THE SEPARATION FROM MATERIAL LAYERS

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR COMPONENT

WAFER PROCESSING METHOD

Offenbart ist ein Wafer-Bearbeitungsverfahren zum Entfernen eines ringförmigen Verstärkungsbereichs, wobei der ringförmige Verstärkungsbereich um einen Wafer-Bauteilbereich ausgebildet ist. Das Verfahren umfasst das Stützen des Wafers durch ein Klebeband an einem ringförmigen Rahmen, das Bilden einer Kennzeichnung, die einer Kerbe entspricht, an einer Position radial innerhalb eines Grenzbereichs zwischen dem Verstärkungsbereich und dem Bauteilbereich, das Schneiden des Grenzbereichs gemeinsam mit dem Klebeband auf, um dadurch den Verstärkungsbereich vom Bauteilbereich zu entfernen, und das Bewegen des ringförmigen Verstärkungsbereichs, der durch das Klebeband am ringförmigen Rahmen gestützt wird, von einem Haltetisch weg, um dadurch den ringförmigen Verstärkungsbereich vom Wafer zu entfernen.

PROCESSING DEVICE

Eine Verarbeitungsvorrichtung schließt einen Spanntisch zum Halten eines Werkstücks, eine Verarbeitungseinheit zur Verarbeitung des auf dem Spanntisch gehaltenen Werkstücks, während dem Werkstück Prozesswasser zugeführt wird, und eine an dem Boden der Verarbeitungsvorrichtung befestigte Wasserwanne zur Aufnahme des Prozesswassers bei Wasserleckage ein.

Apparatus and method for releasing a first substrate

Die vorliegende Erfindung betrifft eine Vorrichtung zum Lösen eines Trägerwafers (8) von einem Produktwafer (6) in einer Löserichtung (L) mit mindestens zwei quer zur Löserichtung (L) und in einer Radialrichtung (R) zum Trägerwafer (8) geführten Klemmelementen (1, 1', 1", 1'''), die vorzugsweise an die Außenkontur des Trägerwafers angepasst sind, zur Klemmung des Trägerwafers (8) quer zur Löserichtung (L), wobei die Klemmelemente (1, 1', 1", 1"') elastische Konturaufnahmeelemente (3, 3') zur Aufnahme und Fixierung einer jeden Waferkante aufweisen sowie einer Substrathalterung (11, 11') zum Halten des Produktwafers (6) und Mitteln zum Lösen des Trägerwafers (8) vom Produktwafer (6) durch Bewegung der Substrathalterung (11, 11') entgegen der Löserichtung (L). Weiterhin betrifft die vorliegende Erfindung ein korrespondierendes Verfahren zum Lösen der Wafer voneinander.

LASER BEAM PROCESSING PROCEDURE

PROCEDURE FOR CUTTING USING A FOCUSED RADIATION POINT WITH MORE VARIABLE ASTIGMATIK

SEMICONDUCTOR COMPONENT WITH ELECTRICAL CONTACTS AND PROCEDURE FOR THE PRODUCTION OF SUCH CONTACTS

LASER WORKING ON MECHANISM AND - PROCEDURES USING A POLYGONALI MIRROR WITH SIMULTANEOUSLY DIVERSION POLYGONFACETTEN

ANCHORAGE OF THIN SECTION SAMPLES BY LATERAL OXIDATION FOR PREVENTING THE DEHUMIDIFYING EFFECT

DUAL LASER CUTTINGS OF DISKS

PROCEDURE FOR MANUFACTURING INTEGRATED SWITCHING CONFIGURATIONS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

LASERBEARBEITUNG WITH AN ACTIVE AUXILIARY GAS

SECURE INTEGRATED CIRCUIT CHIP WITH CONDUCTIVE SHIELD

Wafer coating and singulation method

METHOD AND DEVICE FOR MACHINING A WAFER, IN ADDITION TO A WAFER COMPRISING A SEPARATION LAYER AND A SUPPORT LAYER

Semiconductor wafer fabrication of die-bottom contacts for electronic devices

Forming defect prevention trenches in dicing streets

Wafer dividing method

A method of dividing a wafer having devices formed in a plurality of regions demarcated by a plurality of streets formed in a grid pattern on a surface of the wafer, along the streets and into the individual devices. The wafer dividing method includes the steps of: forming grooves from the face side of the wafer along the streets and in a depth corresponding to the finished thickness of the devices; coating the surface of the wafer with an acrylic liquid resin curable by irradiation with UV rays to fill the grooves with the acrylic liquid resin and disposing a protective film on the acrylic liquid resin; performing irradiation with UV rays from the protective film side so as to cure the acrylic liquid resin; grinding the back side of the wafer so as to expose the grooves on the back side and divide the wafer into the individual devices; adhering the back side of the wafer to a surface of an adhesive tape adhered to an annular frame; and peeling the acrylic resin from the surface of the wafer together with the protective film.

Support structures for various apparatuses including opto-electrical apparatuses

Present embodiments generally relate to support structures for thin film components and methods for fabricating the support structures. In one embodiment, an apparatus comprises a device structure including portions of an electronic device; a support structure coupled to the device structure; wherein the support structure supplements features of the device structure and the support structure includes: a metal component coupled to the device structure; and a non-metal component coupled to the metal component. The support component can supplement structural and mechanical integrity of the device structure and functional operations of the device structure. In one embodiment, the metal component includes at least one layer of metal material and the non-metal component includes at least one layer of non metal material (e.g., polymeric material, etc.). The metal component can have greater stiffness characteristics with respect to the device structure and the non-metal component can have greater flexibility characteristics with respect to the metal layer component. The support structure can be configured to reflect light towards the device structure. The support structure can also be configured to conduct electricity from the device structure.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Film for flip chip type semiconductor back surface, process for producing strip film for semiconductor back surface, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface having a ratio of A/B falling within a range of 1 to 8×10 3 (%/GPa), in which A is an elongation ratio (%) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing and B is a tensile storage modulus (GPa) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Sapphire wafer dividing method

A sapphire wafer dividing method including a cut groove forming step of forming a plurality of cut grooves on the back side of a sapphire wafer along a plurality of crossing division lines formed on the front side where a light emitting layer is formed, a modified layer forming step of forming a plurality of modified layers inside the sapphire wafer along the division lines, and a dividing step of dividing the sapphire wafer into individual light emitting devices along the modified layers as a division start point, thereby chamfering the corners of the back side of each light emitting device owing to the formation of the cut grooves in the cut groove forming step.

Semiconductor component with marginal region

A semiconductor wafer is disclosed. One embodiment provides at least two semiconductor components each having an active region, and wherein at least one zone composed of porous material is arranged between the active regions of the semiconductor components.

Chip package and manufacturing method thereof

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Workpiece dividing method

A workpiece has a substrate and a film formed on the front side of the substrate. A first laser beam applied to the film from the front side of the workpiece along streets formed on the film, thereby forming a plurality of laser processed grooves along the streets. An adhesive tape is attached to the front side of the workpiece. Thereafter, a second laser beam is applied to the substrate from the back side of the workpiece along the streets, with the focal point of the second laser beam set inside the substrate, forming a plurality of modified layers along the streets. Thereafter, the adhesive tape is expanded to divide the substrate along the streets, thereby obtaining a plurality of individual devices. The back side of the substrate of each device is then ground to remove the modified layers and reduce the thickness of each device to a predetermined thickness.

Methods of manufacturing semiconductor chips

A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Reticle set modification to produce multi-core dies

A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Method and apparatus for depositing phosphor on semiconductor-light emitting device

A method and apparatus for depositing a phosphor using transfer molding. The method includes: forming a plurality of light-emitting devices on a wafer and rearranging the light-emitting devices on a carrier substrate according to luminance characteristics of the plurality of light-emitting devices by examining the luminance characteristics of the plurality of light-emitting devices; depositing the phosphor on the rearranged light-emitting devices using transfer molding; and separating the light-emitting devices on the carrier substrate.

Peeling apparatus and manufacturing apparatus of semiconductor device

To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid.

Semiconductor device and manufacturing method thereof

A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

Wafer dicing press and method and semiconductor wafer dicing system including the same

In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices. This increased efficiency is achieved without increasing the likelihood of damaging the wafer.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Semiconductor device and method of producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Wafer dividing method

In a wafer dividing method, a wafer is held by a chuck table of a laser beam processing apparatus. A modified layer is formed by radiating a laser beam having a wavelength that transmits the laser beam through the wafer, while adjusting the beam convergence point to a position inside of the wafer, so as to form a pair of modified layers the interval of which is greater than the width of a cutting edge of a cutting blade and smaller than the width of planned dividing lines, on the back side of the wafer at both sides of each of the planned dividing lines. The wafer is adhered to a dicing tape and divided into individual devices by cutting along the dividing lines.

Method and system for template assisted wafer bonding

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Semiconductor device, manufacturing method thereof, and mobile telephone

Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.

Laser beam processing method for a wafer

A processing method for a wafer which has, on a surface thereof, a device region in which a plurality of devices are formed and partitioned by division lines and an outer periphery excess region surrounding the device region, includes a dividing groove formation step of irradiating a laser beam of a wavelength having absorbability by a wafer along the division lines to form dividing grooves serving as start points of cutting, and a dividing step of applying external force to the wafer on which the dividing grooves are formed to cut the wafer into the individual devices. At the dividing groove formation step, the dividing grooves are formed along the division lines in the device region while a non-processed region is left in the outer periphery excess region on extension lines of the division lines.

Water soluble mask for substrate dicing by laser and plasma etch

Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off.

In-situ deposited mask layer for device singulation by laser scribing and plasma etch

Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.

Laser and plasma etch wafer dicing using water-soluble die attach film

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

Etching a laser-cut semiconductor before dicing a die attach film (daf) or other material layer

Semiconductor die break strength and yield are improved with a combination of laser dicing and etching, which are followed by dicing an underlying layer of material, such as die attach film (DAF) or metal. A second laser process or a second etch process may be used for dicing of the underlying layer of material. Performing sidewall etching before cutting the underlying layer of material reduces or prevents debris on the kerf sidewalls during the sidewall etching process. A thin wafer dicing laser system may include either a single laser process head solution or a dual laser process head solution to meet throughput requirements.

Method for controlled removal of a semiconductor device layer from a base substrate

A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

Method of processing optical device wafer

A method of processing an optical device wafer having an optical device layer including an n-type semiconductor layer and a p-type semiconductor layer stacked over a sapphire substrate, a buffer layer therebetween, allowing peeling of the sapphire substrate. The method includes joining a transfer substrate to the optical device layer, breaking the buffer layer by irradiation with a pulsed laser beam from the sapphire substrate side of the wafer with the transfer substrate joined to the optical device layer, and peeling the sapphire substrate from the optical device wafer with the buffer layer broken, transferring the optical device layer onto the transfer substrate. The pulsed laser beam has a wavelength longer than an absorption edge of the sapphire substrate and shorter than an absorption edge of the buffer layer, and a pulse width set so that a thermal diffusion length will be not more than 200 nm.

Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies

A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Optoelectronic integrated circuit substrate and method of fabricating the same

An optoelectronic integrated circuit substrate may include a first region and a second region. The first region and the second region each include at least two buried insulation layers having different thicknesses. The at least two buried insulation layers of the first region are formed at a greater depth and have a greater thickness as compared to the at least two buried insulation layers of the second region. A micro-electromechanical systems (MEMS) structure may be formed in a third region that does not include a buried insulation layer.

Method and system for wafer level singulation

A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Substrate Dicing

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Method and Apparatus for Plasma Dicing a Semi-conductor Wafer

The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. 1. A method for plasma dicing a substrate , the method comprising:providing a process chamber having a wall;providing a plasma source adjacent to the wall of the process chamber;providing a work piece support within the process chamber;placing the substrate on a carrier support to form a work piece;loading the work piece onto the work piece support;providing a cover ring disposed above the work piece;generating a plasma through the plasma source; andetching the work piece through the generated plasma.2. The method according to further comprising placing the substrate onto a support film on a frame to form the work piece.3. The method according to further comprising providing an RF power source coupled to the work piece support.4. The method according to wherein the work piece support further comprising an electrostatic chuck.5. The method according to further comprising a lifting mechanism within the work piece support claim 4 , the work piece being loaded onto the lifting mechanism.6. The method according to further comprising a filler ring extending from an outer diameter of the electrostatic chuck to the lifting mechanism.7. The method according to further comprising providing a mechanical partition between the high density source and the work piece.8. The method according to further comprising controlling the temperature of the cover ring during the etching step.9. The method according to wherein the cover ring ...

Method for manufacturing semiconductor apparatus

A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

Method Of Manufacturing Package-On-Package (Pop)

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Ablation method for die attach film

An ablation method of applying a laser beam to a die attach film to perform ablation. The ablation method includes a protective film forming step of applying a liquid resin containing a fine powder of oxide having absorptivity to the wavelength of the laser beam to at least a subject area of the die attach film to be ablated, thereby forming a protective film containing the fine powder on at least the subject area of the die attach film, and a laser processing step of applying the laser beam to the subject area coated with the protective film, thereby performing ablation through the protective film to the subject area of the die attach film after performing the protective film forming step.

Method for Slicing a Substrate Wafer

A method for slicing a monocrystalline semiconductor layer () from a semiconductor single crystal () comprising: providing a semiconductor single crystal () having a uniform crystal structure; locally modifying the crystal structure within a separating plane () in the semiconductor single crystal () into an altered microstructure state by means of irradiation using a laser (); and removing the modified separating plane () by means of selective etching. 1. A method for slicing a mono crystalline semiconductor layer from a semiconductor single crystal comprising:providing a semiconductor single crystal having a uniform crystal structure;locally modifying the crystal structure within a separating plane in the semiconductor single crystal into an altered microstructure state by means of irradiation using a laser; andremoving the modified separating plane by means of selective etching.2. The method as claimed in patent comprising:polishing a surface of the semiconductor layer which adjoins the separating plane.3. The method as claimed in claim 1 , wherein modifying is effected by focused incidence of laser radiation emitted by the laser via the top side of the semiconductor single crystal.4. The method as claimed in claim 3 , wherein laser radiation comprises a picosecond or femtosecond laser radiation.5. The method as claimed in claim 1 , wherein a focus of the laser radiation is introduced in a raster-like fashion over the entire separating plane.6. The method as claimed in claim 1 , wherein the laser radiation is focused into the region of the separating plane via an optical unit having a numerical aperture of more than 0.5.7. The method as claimed in claim 1 , wherein the laser radiation is focused into a punctiform region in the separating plane.8. The method as claimed in claim 1 , wherein removing the modified separating plane is effected by means of a wet-chemical method.9. The method as claimed in claim 8 , wherein the wet-chemical method comprises the use of a ...

Multilayer adhesive sheet and method for manufacturing electronic component

Provided is a multilayer adhesive sheet which enables easy separation between an adhesive layer and a die attach film during the pick-up even in cases where an acrylate ester copolymer is used in the die attach film, thereby making the pick-up work of semiconductor chips after the dicing easy. The multilayer adhesive sheet comprises a base film, an adhesive layer that is disposed on one surface of the base film, and a die attach film that is disposed on an exposed surface of the adhesive layer. The adhesive that constitutes the adhesive layer contains: (A) a (meth)acrylate ester copolymer; (B) an ultraviolet polymerizable compound; (C) a multifunctional isocyanate curing agent; (D) a photopolymerization initiator; and (E) a silicone polymer.

WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS

A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. 1. A method of manufacturing semiconductor package from a wafer having at least one integrated circuit (IC) formed on an active surface , said method comprising:a) attaching a stiffener to an inactive surface of said wafer;b) forming substantially rectangular under bump metallization (UBM) pads, each one of said UBM pads in communication with said IC, said UBM pads comprising at least a first UBM pad, and a second UBM pad larger than said first UBM pad;c) forming solder bumps extending from each of said UBM pads; andd) separating said wafer into semiconductor packages.2. The method of claim 1 , further comprising forming a compliant layer on said active surface of said wafer prior to said forming said UBM pads.3. The method of claim 2 , wherein said compliant layer comprises a dielectric material.4. The method of claim 1 , further comprising thinning said wafer by grinding claim 1 , prior to said attaching said stiffener.5. The method of claim 1 , wherein said first UBM pad is formed near a periphery of said semiconductor chip package.6. The method of claim 5 , wherein said second UBM pad is formed near a center of said semiconductor chip package.7. The method of claim 1 , wherein said stiffener is made of one of organic and metallic materials.8. The method of claim 2 , further comprising forming conductive rerouting to interconnect each of a plurality of die pads corresponding to each IC claim 2 , to a corresponding one of ...

FILM FOR BACK SURFACE OF FLIP-CHIP SEMICONDUCTOR, DICING-TAPE-INTEGRATED FILM FOR BACK SURFACE OF SEMICONDUCTOR, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP-CHIP SEMICONDUCTOR DEVICE

The present invention relates to a film for back surface of flip-chip semiconductor, which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend, wherein an amount of shrinkage of the film for back surface of flip-chip semiconductor due to thermal curing is 2% by volume or more and not more than 30% by volume relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing. According to the film for back surface of flip-chip semiconductor according to the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, in the film for back surface of flip-chip semiconductor according to the present invention, since an amount of shrinkage due to thermal curing is 2% by volume or more relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing, a warp of a semiconductor element to be generated at the time of flip-chip connecting the semiconductor element onto an adherend can be effectively suppressed or prevented. 1. A film for back surface of flip-chip semiconductor , which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend ,wherein an amount of shrinkage of the film for back surface of flip-chip semiconductor due to thermal curing is 2% by volume or more and not more than 30% by volume relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing.2. The film for back surface of flip-chip semiconductor according to claim 1 , which contains at least a thermosetting resin.3. The film for back surface of flip-chip semiconductor according to claim 2 , wherein a content of the thermosetting resin is 40% by weight or more and not more than 90% by weight relative to whole resin components in the film for ...

FILM FOR BACK SURFACE OF FLIP-CHIP SEMICONDUCTOR

The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented. 1. A film for back surface of flip-chip semiconductor , which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend ,wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa.2. The film for back surface of flip-chip semiconductor according to claim 1 , wherein the film for back surface of flip-chip semiconductor is formed of at least a thermosetting resin component.3. The film for back surface of flip-chip semiconductor according to claim 2 , which comprises at least a layer formed of at least a thermosetting resin component and a thermoplastic resin component having a glass transition temperature of 25° C. or higher and not higher than 200° C.4. The film for back surface of flip-chip semiconductor according to claim 3 , wherein a blending proportion of the thermoplastic resin component having a glass transition temperature of 25° C. or higher and not higher than 200° C. falls within ...

HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING

A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop. 1. A method for fabricating an integrated circuit having at least a tri-gate FinFET and a dual-gate FinFET , the method comprising:providing a semiconductor on insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer overlying an insulator layer, the semiconductor layer having a surface region;implanting impurities into the semiconductor layer for a threshold voltage adjustment;forming a hard mask overlying the surface region;patterning the hard mask to form a first hard mask cap portion and a second hard mask cap portion;etching the semiconductor layer using the patterned hard mask as an etch mask to form a first fin and a second fin;removing the second hard mask cap portion overlying the second fin;forming a gate dielectric layer over side surfaces of the first fin and side surfaces and a top surface of the second fin;forming a conductive layer overlying the gate dielectric layer;selectively etching the conductive layer to form a first gate structure for the first fin and a second gate structure for the ...

MULTIPLE SEAL RING STRUCTURE

The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures, A semiconductor device fabricated by such a method is also provided. 120-. (canceled)21. A method of fabricating a semiconductor device , the method comprising:providing a substrate having a seal ring region and a circuit region;forming a first seal ring structure disposed over the seal ring region;forming a second seal ring structure disposed over the seal ring region and adjacent to the first seal ring structure, wherein the first and second seal ring structures are physically separated and continuously formed around the circuit region and have no contact or pad structure portion;forming a third seal ring structure between the first and second seal ring structures at a corner section, the third seal ring structure having a triangular shape, wherein the third seal ring structure is the only ring structure present between the first and second seal ring structures at the corner section; andforming a first passivation layer disposed over the first, second, and third seal ring structures.22. The method of claim 21 , wherein the first and second seal ring structures are each formed to be a stack of metal layers disposed around the circuit region.23. The method of claim 21 , wherein the first and second seal ring structures are each formed to have a line-shaped metal layer.24. The method of claim 21 , wherein the second seal ring structure is formed to be concentric to the first seal ring structure.25. The method of claim 21 , wherein the first seal ring structure is formed to be adjacent the circuit region and the second seal ring ...

RESIN COMPOSITION, RESIN FILM, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF

A resin composition which can be formed into a film for use in molding a large diameter thin film wafer is provided. The composition comprises components (A) a silicone resin containing repeating units represented by the following formulae (1-1), (1-2), and (1-3) and having a weight average molecular weight as measured by GPC in terms of polystyrene of 3,000 to 500,000, 4. A resin composition according to wherein the amount of the component (B) is 5 to 100 parts by weight in relation to 100 parts by weight of the component (A) claim 1 , and the weight ratio of the component (C) in relation to the entire weight is 30 to 85% by weight.5. A resin composition according to wherein the thermosetting resin is an epoxy resin.6. A resin composition according to further comprising at least one member selected from epoxy resin curing agents and epoxy resin curing accelerators.7. A resin composition according to wherein the filler is a silica.8. A resin film prepared by using the resin composition of .9. A method for producing a semiconductor device comprising the steps of attaching the resin composition or the resin film of to a semiconductor wafer to mold the semiconductor wafer claim 1 , and singulating the molded semiconductor wafer.10. A semiconductor device having a heat cured film claim 1 , which is produced by singulating a semiconductor wafer molded with a heat cured film prepared by heat curing the resin composition or the resin film of . This non-provisional application claims priority under 35 U.S.C. §119 (a) on Patent Application No. 2011-243359 filed in Japan on Nov. 7, 2011, the entire contents of which are hereby incorporated by reference.This invention relates to a resin composition and a resin film. This invention also relates to a semiconductor device produced by using such resin film and its production method.Recently, wafers used in the production of a semiconductor device have increased diameter and reduced thickness, and there is a high demand for a ...

Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof

A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

Method for separating a plurality of dies and a processing device for separating a plurality of dies

A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies

COMPOSITE SUBSTRATE, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Provided are a composite substrate which includes a silicon substrate having improved crystallinity, a method for manufacturing a composite substrate, and a method for manufacturing an electronic component. A composite substrate is formed by bonding a semiconductor substrate onto a support substrate having electric insulating properties. The semiconductor substrate is formed of silicon. The semiconductor substrate includes a plurality of first regions on each of which an element portion which functions as a semiconductor device is formed, and a second region which is positioned between the plurality of first regions. In the semiconductor substrate, an oxidized portion which is composed of silicon oxide is formed on a bottom surface of the second region. 1. A composite substrate , comprising:a support substrate having electric insulating properties; anda silicon substrate disposed on the support substrate, the silicon substrate comprising a plurality of first regions and a second region positioned between the plurality of first regions,an oxidized portion containing silicon oxide as a main component, the oxidized portion being disposed on a main surface of the second region closer to the support substrate side.2. The composite substrate according to claim 1 ,wherein the support substrate is a single crystal containing aluminum oxide as a main component.3. The composite substrate according to claim 1 ,wherein the oxidized portion surrounds circumference of the plurality of first regions.4. The composite substrate according to claim 1 ,wherein the oxidized portion penetrates the silicon substrate in a thickness direction thereof.5. The composite substrate according to claim 1 ,wherein the oxidized portion is exposed from a side surface of the silicon substrate.6. The composite substrate according to claim 1 ,wherein the oxidized portion is positioned inside other surfaces excluding a main surface of the silicon substrate closer to the support substrate side.7. The ...

SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS

The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment. 1. A method of producing a composite structure composed of a silicon-containing material bonded to a substrate , the method comprising:implanting ions into silicon-containing material to a depth;engaging the silicon-containing piece into contact with the substrate; andirradiating/treating the silicon-containing piece with a laser having a wavelength of between about 350 nm to about 1070 nm.2. The method of wherein the substrate is a borosilicate/borofloat glass or a soda-lime glass.3. The method of further comprising cleaving the silicon-containing material along a surface established at about the depth at which the ions are implanted.4. The method of wherein the irradiation step is performed with a laser having a wavelength between about 500 nm and about 600 nm.5. The method of wherein the irradiation step is performed with a laser having a wavelength of about 515 nm or about 532 nm.6. The method of wherein the substrate includes a base portion composed of glass claim 1 , plastic or metal.7. The method of wherein the substrate comprises one or more layers including a film of SiN/SiO2/Si coated on a base portion.8. The method of further comprising of a step of annealing at a temperature between about 200° C. to about 450° C.9. The method of further comprising of a step of annealing at a temperature between about 200° C. to about 450° C. for a period of less than about 45 minutes.10. The method of wherein the step of annealing is performed after a step of laser irradiation/treatment.11. (canceled)12. A method of producing a composite solar cell structure composed of a silicon-containing material bonded to a glass substrate claim 8 , the method comprising: ...

LASER SCRIBING SYSTEMS, APPARATUS, AND METHODS

Scribing apparatus are disclosed. In one aspect, a dual-stage scribing apparatus has a first stage adapted to receive a first substrate, a second stage adapted to receive a second substrate, and one or more lasers adapted to emit a laser beam towards the first stage and the second stage and adapted to scribe the substrates. Scribing can be undertaken on the first stage while an orientation process may take place on the other. In another aspect, as dual-laser scribing apparatus is disclosed. Electronic device processing systems and methods including scribing apparatus are described, as are numerous other aspects. 1. A scribing apparatus , comprising:a first stage adapted to receive a first substrate,a second stage adapted to receive a second substrate, andone or more lasers adapted to emit a laser beam towards the first stage and the second stage and adapted to scribe the substrates.2. The scribing apparatus of claim 1 , wherein the first stage and the second state are arranged in a side-by-side orientation.3. The scribing apparatus of claim 1 , wherein the first stage comprises a rotary stage.4. The scribing apparatus of claim 1 , wherein the first and second stages comprise rotary stages.5. The scribing apparatus of claim 1 , wherein the first and second stages comprise side-by-side R-Theta stages configured to rotate the first and second substrates in Theta and translate the first and second substrates in R.6. The scribing apparatus of claim 1 , wherein the one or more lasers comprise two lasers whose laser beams are combined to form a scribing laser beam.7. The scribing apparatus of claim 1 , wherein the two lasers utilize free space optics.8. The scribing apparatus of claim 1 , wherein the scribing apparatus is configured to have a first operational configuration where the first substrate on the first stage is located to undergo an orientation process while the second substrate on the second stage is located to undergo a laser scribing process.9. The scribing ...

PRESSURE-SENSITIVE ADHESIVE SHEET FOR DICING AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING PRESSURE-SENSITIVE ADHESIVE SHEET FOR DICING

An object of the present invention is to provide a pressure-sensitive adhesive sheet for dicing that is capable of preventing scratching of an adsorption stage when laser-scribing a semiconductor wafer. Provided is a pressure-sensitive adhesive sheet for dicing having a base and a pressure-sensitive adhesive layer provided on the base, in which 0.02 to 5 parts by weight of an ultraviolet absorber is contained in the pressure-sensitive adhesive layer with respect to 100 parts by weight of resin solid content, and in which the light transmittance at a wavelength of 355 nm of the pressure-sensitive adhesive sheet for dicing is 30% to 80%. 1. A pressure-sensitive adhesive sheet for dicing having a base and a pressure-sensitive adhesive layer provided on the base , wherein0.02 to 5 parts by weight of an ultraviolet absorber is contained in the pressure-sensitive adhesive layer with respect to 100 parts by weight of resin solid content, andthe light transmittance at a wavelength of 355 nm of the pressure-sensitive adhesive sheet for dicing is 30% to 80%.2. The pressure-sensitive adhesive sheet for dicing according to claim 1 , wherein the light transmittance at a wavelength of 355 nm of the base is 70% to 100%.3. The pressure-sensitive adhesive sheet for dicing according to claim 1 , wherein the base is multi-layered.4. The pressure-sensitive adhesive sheet for dicing according to claim 1 , wherein the specific heat of the base is 1.0 J/gK to 3.0 J/gK.5. The pressure-sensitive adhesive sheet for dicing according to claim 1 , wherein the melting point of the base is 90° C. or more.6. A method of manufacturing a semiconductor device comprising:{'claim-ref': [{'@idref': 'CLM-00001', 'claims 1'}, {'@idref': 'CLM-00005', '5'}], 'a step of applying the pressure-sensitive adhesive sheet for dicing according to any one of to to a back side of a semiconductor wafer in which a low dielectric material layer is formed on a front side; and'}a laser scribing step of irradiating the ...

Manufacturing method for semiconductor integrated device

In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.

PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER

A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer. 1. A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer , comprising:scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface;depositing a metal on the first surface of the plurality of dies;scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch; wherein the first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other.2. The method of claim 1 , wherein a saw that is utilized for scribing the notch is wider than the saw utilized for scribing the second side of the wafer to provide an undercut ledge on each of the die.3. The method of wherein the first side comprises a back side of the wafer and the second side comprises the front side of the wafer.4. The method of wherein the first surface comprises a bottom surface and the second surface comprises a top surface.5. The method of wherein the metal comprises Ti/Pt/Au.6. A method ...

Method and Machine for Producing a Semiconductor, of the Photovoltaic or Similar Electronic Component Type

The invention relates to a method for producing a semiconductor, of the photovoltaic cell type, or similar electronic components. According to the invention, at least one silicon wafer is cut from the cross-section of a silicon rod and, after doping, a substrate is assembled on either side of the silicon wafer and the latter is cut into two parts through the thickness of the silicon, so as to form two semiconductor units each comprising a substrate and a thin silicon film. 1. A method for manufacturing semiconducting units , comprising:providing a silicon bar;cutting out at least one silicon wafer in the cross section of said silicon bar;assembling a substrate on each side of said silicon wafer; andcutting in the thickness in the middle of said silicon wafer, in order to form two semiconducting units each including a substrate and a thin silicon layer.2. The method according to claim 1 , wherein said silicon bar has a circular or square section with a width of about 300 mm claim 1 , and a length of about 500 mm to 1 claim 1 ,300 mm.3. The method according to claim 1 , wherein cutting out at least one silicon wafer is achieved by sawing with a steel wire with an abrasive lubricant.4. The method according to claim 1 , wherein cutting in the middle of the silicon wafer is achieved by sawing with a steel wire with abrasive lubricant.5. The method according to claim 3 , wherein said steel wire has a diameter comprised between 80 μm and 130 μm.6. The method according to claim 1 , wherein said at least one silicon wafer has a thickness between 180 and 200 μm claim 1 , and the thin silicon layer of each semiconducting unit has a thickness between 40 μm and 80 μm.7. The method according to claim 1 , wherein said substrate is a metal or insulating substrate with a thickness between 100 μm and 300 μm.8. The method according to claim 7 , wherein the substrate is in an iron and nickel alloy with an expansion coefficient close to that of silicon.9. The method according to claim 7 ...

CHIP PACKAGE AND FABRICATION METHOD THEREOF

The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region. 1. A method for fabricating a chip package , comprising:providing a semiconductor wafer defined with a plurality of scribe line regions, bonding pad regions, and device regions;performing an ion implanting process to form a plurality of heavily doped regions in the bonding pad regions;forming a plurality of conductive pad structures over the bonding pad regions, wherein the conductive pad structures correspond to the heavily doped regions;forming a plurality of openings along the scribe line regions to expose the heavily doped regions; andforming a conductive pattern in the openings to electrically contact with the heavily doped regions.2. The method for fabricating the chip package as claimed in claim 1 , further comprising dicing the semiconductor wafer along the scribe line regions to divide a plurality of chip packages comprising a semiconductor substrate.3. The method for fabricating the chip package as claimed in claim 1 , further comprising forming an insulating wall between two of the heavily doping regions for isolation therebetween.4. The method for fabricating the chip package as claimed in claim 3 , wherein the semiconductor wafer further comprises an insulating layer claim 3 , and the insulting wall extends to the insulating layer.5. The method for fabricating the chip package as claimed in claim 4 , wherein the insulating layer extends to a bottom portion ...

SEMICONDUCTOR CHIPS HAVING GUARD RINGS AND METHODS OF FABRICATING THE SAME

Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer. 1. A method of fabricating a semiconductor chip , comprising:forming an insulating layer over a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region; andforming an insulating guard ring in the insulating layer in the scribe lane region, the insulating guard ring surrounding at least a portion of the main chip region,wherein the insulating guard ring vertically penetrates the insulating layer to contact the semiconductor substrate and wherein the insulating guard ring is formed of a material layer having a brittleness greater than a brittleness of the insulating layer.2. The method of claim 1 , wherein the insulating guard ring is formed of a porous insulating layer.3. The method of claim 2 , wherein the porous insulating layer comprises at least one of carbon (C) claim 2 , hydrogen (H) claim 2 , nitrogen (N) claim 2 , and fluorine (F).4. The method of claim 3 , wherein the porous insulating layer is one of a Fluorosilieate Glass (FSG) layer claim 3 , a SiOC layer claim 3 , a SiOCH layer claim 3 , and a SiN layer.5. The method of claim 1 , wherein the forming of the guard ring comprises:patterning the insulating layer to form a groove exposing the semiconductor substrate in the scribe lane region;forming a porous insulating layer filling the groove and covering the insulating layer; andplanarizing the porous insulating layer to expose an upper surface of the insulating layer.6. The method of claim 5 , wherein the porous insulating layer is ...

Dicing Sheet and a Production Method of a Semiconductor Chip

A dicing sheet includes a base, an intermediate layer on one face of the base, and an pressure sensitive adhesive layer provided on the intermediate layer and having the thickness of 8 to 30 μm. The pressure sensitive adhesive layer includes a compound having an energy ray curable double bond in a molecule, and a storage elasticity G′ at 23° C. of the pressure sensitive adhesive layer before curing is larger than 4 times of a storage elasticity at 23° C. of the intermediate layer. When the dicing sheet is laminated via the adhesive sheet on a wafer formed with a cylinder shape electrodes having a height of 15 μm and a diameter of 15 μm at a pitch of 40 μm having 3 rows 3 columns in equal spacing, at a center of the electrode of the cylinder shape electrodes formed in 3 rows 3 columns, the pressure sensitive adhesive layer does not contact at a part of a height of 7.5 μm or less of the electrode. 1. A dicing sheet comprising a base , an intermediate layer on one face of said base , and an pressure sensitive adhesive layer provided on the intermediate layer and having the thickness of 8 to 30 μm , whereinthe pressure sensitive adhesive layer comprises a compound having an energy ray curable double bond in a molecule, and a storage elasticity G′ at 23° C. of the pressure sensitive adhesive layer before curing is larger than 4 times of a storage elasticity at 23° C. of the intermediate layer, andwhen the dicing sheet is laminated via the adhesive sheet on a wafer formed with a cylinder shape electrodes having a height of 15 μm and a diameter of 15 μm at a pitch of 40 μm having 3 rows 3 columns in equal spacing, at a center of the electrode of the cylinder shape electrodes formed in 3 rows 3 columns, the pressure sensitive adhesive layer does not contact at a part of a height of 7.5 μm or less of the electrode.2. The dicing sheet as set forth in wherein said compound having the energy ray curable double bond in the molecule includes an energy ray curable adhesive polymer ...

UNDER-FILL MATERIAL AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a usable material by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.: 1. An under-fill material , wherein a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.:{'br': None, 'i': 'E′×α<', '250000 [Pa/K]\u2003\u2003(1).'}2. The under-fill material according to claim 1 , wherein the storage elastic modulus E′ is 100 to 10000 [MPa] and the thermal expansion coefficient α is 10 to 200 [ppm/K].3. The under-fill material according to claim 1 , wherein the storage elastic modulus E′ [MPa] and the thermal expansion coefficient α [ppm/K] satisfy the following formula (2):{'br': None, 'i': 'E′×α<', '10000<250000 [Pa/K]\u2003\u2003(2).'}4. The under-fill material according to claim 1 , wherein the under-fill material contains a thermoplastic resin and a thermosetting resin.5. The under-fill material according to claim 4 , wherein the thermoplastic resin contains an acrylic resin.6. The under-fill material according to claim 4 , wherein the thermosetting resin contains an epoxy resin and a phenol resin.7. A sealing sheet comprising:a back surface grinding tape; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the under-fill material according to ,'}wherein the under-fill material is laminated on the back surface grinding tape.8. A method for producing a semiconductor device comprising an adherend claim 4 , a ...

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

There is provided a method for producing a semiconductor device, which is capable of suppressing voids during mounting of a semiconductor element to produce a semiconductor device with high reliability. A method for producing a semiconductor device of the present invention includes the steps of: providing a sealing sheet having a base material and an under-fill material laminated on the base material; bonding the sealing sheet to a surface of a semiconductor wafer on which a connection member is formed; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; retaining the semiconductor element with the under-fill material at 100 to 200° C. for 1 second or more; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element with the under-fill material. 1. A method for producing a semiconductor device having an adherend , a semiconductor element electrically connected to the adherend , and an under-fill material for filling a space between the adherend and the semiconductor element , wherein the method comprises:a providing step of providing a sealing sheet having a base material and an under-fill material laminated on the base material;a bonding step of bonding the sealing sheet to a surface of a semiconductor wafer on which a connection member is formed;a dicing step of dicing the semiconductor wafer to form a semiconductor element with the under-fill material;a retention step of retaining the semiconductor element with the under-fill material at 100 to 200° C. for 1 second or more; anda connection step of electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material.2. The method for producing a semiconductor device according to claim 1 , wherein the minimum melt viscosity of the ...

METHOD FOR THE PREPARATION OF A MULTI-LAYERED CRYSTALLINE STRUCTURE

This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure. 1. A method for the preparation of a multi-layered crystalline structure , the method comprising:{'b': '1', 'implanting ions selected from the group consisting of hydrogen, helium and combinations thereof into a donor structure, wherein the donor structure comprises a central axis, a device layer having an implantation surface and device surface which are generally perpendicular to the central axis and an average thickness, t, extending in the axial direction from the implantation surface to the device surface of the device layer, a handle layer, and an intervening layer which is positioned along the central axis of the donor structure between the device surface and the handle layer, wherein the ions are implanted into the donor structure through the implantation surface to an implantation depth D which is greater than the thickness, t, of the device layer to form in the implanted donor structure a damage layer which is generally perpendicular to the axis and located in the intervening layer and/or in the handle layer;'}bonding the implanted donor structure to a second structure to form a bonded structure;cleaving the donor structure along the damaged layer to form a multi-layered crystalline structure comprising the second structure, the device layer and residual material, the residual material comprising at least a portion of the intervening layer and optionally a portion of the handle layer; and, removing the residual material from the multi-layered crystalline structure.2. The method of wherein at least about 1×10ions/cmare3. The method of wherein at least about 1×10ions/cmare ...

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

DICING/DIE BONDING INTEGRAL FILM, DICING/DIE BONDING INTEGRAL FILM MANUFACTURING METHOD, AND SEMICONDUCTOR CHIP MANUFACTURING METHOD

A dicing/die bonding integral film of the present invention includes a base film, a pressure-sensitive adhesive layer which is formed on the base film and to which a wafer ring for blade dicing is bonded, and a bonding layer formed on the adhesive layer and having a central portion to which a semiconductor wafer to be diced is bonded, wherein a planar shape of the bonding layer is circular, an area of the bonding layer is greater than an area of the semiconductor wafer and smaller than an area of each of the base film and the adhesive layer, and a diameter of the bonding layer is greater than a diameter of the semiconductor wafer and less than an inner diameter of the wafer ring, and a difference in diameter between the bonding layer and the semiconductor wafer is greater than 20 mm and less than 35 mm, 1. A dicing/die bonding integral film , comprising:a base film;a pressure-sensitive adhesive layer which is formed on the base film and to which a wafer ring to be used in blade dicing is bonded; anda bonding layer formed on the adhesive layer and having a central portion to which a semiconductor wafer to be subjected to blade dicing is bonded,wherein a planar shape of the bonding layer is circular,an area of the bonding layer is greater than an area of the semiconductor wafer and smaller than an area of each of the base film and the adhesive layer, anda diameter of the bonding layer is greater than a diameter of the semiconductor wafer and less than an inner diameter of the wafer ring, and a difference in diameter between the bonding layer and the semiconductor wafer is greater than 20 mm and less than 35 mm.2. A dicing/die bonding integral film manufacturing method , comprising:a dicing film preparation step of preparing a dicing film in which an adhesive layer is formed on a base film;a die bonding film preparation step of preparing a die bonding film in which a bonding layer is formed on a peelable base;a bonding layer cutting step of cutting the bonding layer ...

Structure for Reducing Integrated Circuit Corner Peeling

A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers. 1. A device comprising: a first plurality of dielectric layers of a first material disposed over the semiconductor substrate;', 'a second plurality of dielectric layers of a second material different than the first material disposed over the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface;', 'a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers; and', 'a bond/bump pad structure disposed in a passivation layer overlying the first and second plurality of dielectric layers, the bond/bump pad structure being coupled with a topmost metal structure of the plurality of metal structures., 'a plurality of semiconductor dies disposed between scribe lines, wherein the scribe lines include at least one crack prevention structure disposed over a semiconductor substrate, the at least one crack prevention structure comprising2. The device of claim 1 , further comprising a seal ring disposed between one of the semiconductor dies and the at least one crack prevention structure.3. The device of claim 1 , wherein the at least ...

METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT

Provided is a method of manufacturing a semiconductor element having at a cut portion with excellent quality, which minimizes a region on a silicon substrate necessary for cutting, and which prevents cutting water used when cutting by dicing is carried out from entering the semiconductor element. The method of manufacturing a semiconductor element includes: arranging, on the silicon substrate, multiple semiconductor element portions so as to be adjacent to one another; bonding the silicon substrate and a glass substrate together using the resin; and cutting the silicon substrate and the glass substrate, respectively, in a region in which the resin is provided, the cutting the silicon substrate and the glass substrate including: half-cutting the silicon substrate by dicing; cutting the glass substrate by scribing; and dividing the silicon substrate, the glass substrate, and the resin. 1. A method of manufacturing a semiconductor element , a silicon substrate;', 'a semiconductor element portion provided on the silicon substrate; and', 'a sealing member for sealing the semiconductor element portion,', 'the sealing member comprising a glass substrate provided so as to be opposed to a surface of the silicon substrate having the semiconductor element portion provided thereon, and a resin for bonding the silicon substrate and the glass substrate,, 'the semiconductor element comprisingthe method comprising:arranging, on the silicon substrate, multiple semiconductor element portions so as to be adjacent to one another;bonding the silicon substrate and the glass substrate together using the resin; and half-cutting the silicon substrate by dicing;', 'cutting the glass substrate by scribing; and', 'dividing the silicon substrate, the glass substrate, and the resin after the dicing and the scribing are carried out,, 'the cutting the silicon substrate and the glass substrate comprising, 'cutting the silicon substrate and the glass substrate, respectively, in a region in which the ...

LAMINATED SHEET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE LAMINATED SHEET

The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape, wherein the tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa, and the T-peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and 300 mm/min. 1. A laminated sheet having a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base , and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape , whereina tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa, anda T-peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and 300 mm/min.2. The laminated sheet according to claim 1 , wherein the resin composition layer contains a thermosetting resin.3. The laminated sheet according to claim 1 , wherein the thermosetting resin is an epoxy resin.4. A method of manufacturing a semiconductor device using a laminated sheet having a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base claim 1 , and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape claim 1 , in which a tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa claim 1 , and a T peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and ...

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. 1. A chip package , comprising:a substrate having a first surface and a second surface;a device region formed in the substrate or disposed on the substrate;a dielectric layer disposed on the first surface of the substrate;at least one conducting pad disposed in the dielectric layer and electrically connected to the device region;a planar layer disposed on the dielectric layer, wherein a vertical distance between an upper surface of the planar layer and an upper surface of the conducting pad is larger than about 2 μm;a transparent substrate disposed on the first surface of the substrate;a first spacer layer disposed between the transparent substrate and the planar layer; anda second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.2. The chip package as claimed in claim 1 , wherein the first spacer layer directly contacts with the planar layer and does not contact with the dielectric layer or the substrate. ...

Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication

Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

There is provided a method for producing a semiconductor device, capable of suppressing generation of voids at an interface between a semiconductor element and an under-fill sheet to produce a semiconductor device with high reliability. The method includes providing a sealing sheet having a support and an under-fill material laminated on the support; thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material. 1. A method for producing a semiconductor device having an adherend , a semiconductor element electrically connected to the adherend , and an under-fill material for filling a space between the adherend and the semiconductor element , wherein the method comprises:a providing step of providing a sealing sheet having a support and an under-fill material laminated on the support;a heat pressure-bonding step of thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher;a dicing step of dicing the semiconductor wafer to form a semiconductor element with the under-fill material; anda connection step of electrically connecting the semiconductor element and the adherend through the connection member while filling the space between the adherend and ...

Method for manufacturing a silicon carbide wafer and respective equipment

An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF

A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. 19-. (canceled)10. A fabrication method of a semiconductor package having electrical connecting structures , comprising the steps of:providing a metal board with a plurality of substrate units;forming a patterned metal layer on the substrate units;forming a conductive layer on the metal layer, wherein the conductive layer has a die pad and a plurality of traces disposed at a periphery of the die pad, the traces each comprising a trace body, a finger pad formed at an end of the trace body and positioned proximate to the die pad, and a trace end formed at another end of the trace body and positioned distal to the die pad;mounting a chip on the die pad and electrically connecting the chip to the finger pads through bonding wires;forming an encapsulant to cover the chip, the bonding wires and the conductive layer;removing the metal board and the metal layer so as to expose the conductive layer;forming a solder mask layer on bottom surfaces of the conductive layer and the encapsulant to cover the conductive layer and the encapsulant, followed by forming a plurality of openings in the solder mask layer to expose the trace ends, respectively;forming a plurality of solder balls in the openings of ...

Semiconductor device manufacturing method

In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper.

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Provided is a method for manufacturing electronic component improved in chip-holding efficiency, pickup efficiency and contamination resistance in a well-balanced manner, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer on the rear face of a wafer, a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame with a cohesive sheet, a dicing step of dicing the wafer into semiconductor chips, a UV-irradiating step of irradiating ultraviolet ray, and a pick-up step of picking up the chips and semi-cured adhesive layers from the cohesive layer, wherein the cohesive sheet has a cohesive layer of a cohesive agent having a particular composition formed on one face of its base film. 1. A method for manufacturing an electronic component , comprising:(1) a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer by coating a pasty adhesive on the rear face of a wafer and curing the pasty adhesive partially by UV irradiation or heating into the sheet shape;(2) a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame by bonding them to a cohesive sheet;(3) a dicing step of dicing the wafer into semiconductor chips with a dicing blade;(4) a UV-irradiating step of irradiating ultraviolet ray; and(5) a pick-up step of picking up the chips and semi-cured adhesive layers from the cohesive layer, wherein:the cohesive sheet has a base film and a cohesive layer formed on one face of the base film;the cohesive constituting the cohesive layer contains 100 parts by mass of a (meth)acrylate ester copolymer (A), 5 to 200 parts by mass of a ultraviolet polymerizable compound (B), 0.5 to 20 parts by mass of a multifunctional isocyanate curing agent (C), 0.1 to 20 parts by mass of a photopolymerization initiator (D), and 0.1 to 20 parts by mass of a silicone polymer (E);the (meth)acrylate ester copolymer (A) is a copolymer of (meth)acrylate ester monomers or a copolymer of a ...

Methods for processing a semiconductor wafer, a semiconductor wafer and a semiconductor device

A semiconductor wafer, comprising multiple active areas suitable for providing semiconductor devices or circuits. Inactive areas separate the active areas from each other. The wafer has a stressed layer with a first surface, and another layer which is in contact with the stressed layer along a second surface of the stressed layer, opposite to the first surface. Multiple trench lines, extend in parallel to the first surface of the stressed layer in an inactive area and have a depth less than the thickness of the semiconductor wafer.

WAFER DICING METHOD AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE CHIPS EMPLOYING THE SAME

A wafer dicing method includes forming a semiconductor device on a first surface of a wafer; first-dicing a portion of the wafer and the semiconductor device; and splitting the wafer and the semiconductor device into a plurality of semiconductor device chips by second-dicing the wafer that has been first-diced. 1. A wafer dicing method comprising:forming a semiconductor device on a first surface of a wafer;first-dicing a first portion of the wafer and the semiconductor device to produce a plurality of semiconductor devices; andsplitting the wafer and the plurality of semiconductor devices into a plurality of semiconductor device chips by second-dicing a second portion of the wafer that has been first-diced.2. The wafer dicing method of claim 1 , wherein the first-dicing comprises forming claim 1 , in the wafer claim 1 , grooves having a depth corresponding to from 30% to 70% of a thickness of the wafer.3. The wafer dicing method of claim 2 , wherein the grooves comprise:a plurality of first grooves formed on the wafer in parallel to a first direction; anda plurality of second grooves formed on the wafer in parallel to a second direction that is perpendicular to the first direction.4. The wafer dicing method of claim 1 , wherein the first-dicing is performed by using a blade claim 1 , a laser claim 1 , or plasma etching.5. The wafer dicing method of claim 1 , wherein the second-dicing comprises breaking the second portion of the wafer that has been first-diced by applying a physical force to a second surface of the wafer which is a surface opposite to the first surface.6. The wafer dicing method of claim 5 , wherein the physical force is applied to the wafer via a cutter having an unsharpened edge.7. The wafer dicing method of claim 1 , further comprising attaching a dicing tape onto a second surface of the wafer which is a surface opposite to the first surface.8. The wafer dicing method of claim 1 , further comprising performing additional processes to the plurality ...

METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS FROM A SEMICONDUCTOR WAFER

A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame. 1. A method for processing a semiconductor wafer , comprising:fastening a first frame to a second frame;disposing a wafer on a film affixed to the second frame;processing the wafer in first processing equipment configured to receive the first frame;removing the first frame from the second frame; andprocessing the wafer in second processing equipment configured to receive the second frame.2. A method for processing a semiconductor wafer as defined in claim 1 , wherein the second frame has outer dimensions less than outer dimensions of the first frame and greater than inner dimensions of the first frame.3. A method for processing a semiconductor wafer as defined in claim 1 , wherein the first frame includes at least one fastener element configured to fasten the second frame to the first frame.4. A method for processing a semiconductor wafer as defined in claim 3 , wherein the at least one fastener element comprises fastener elements on four sides of the first frame.5. A method for processing a semiconductor wafer as defined in claim 3 , wherein the at least one fastener element comprises guide rails on three sides of the first frame and a removable lug on a fourth side of the first frame.6. A method for processing a semiconductor wafer as defined in claim 5 , wherein fastening the first frame to the second frame comprises removing ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin. 1. A semiconductor device , comprising:a substrate including a metal base plate, an insulating sheet located on said metal base plate, and a wiring pattern located on said insulating sheet;a semiconductor element located on said substrate; anda molding resin forming a housing for sealing said semiconductor element, whereinsaid molding resin extends to side surfaces of said substrate,said insulating sheet and said wiring pattern are not exposed from said molding resin on the side surfaces of said substrate, andsaid metal base plate includes a projecting portion exposed from said molding resin on the side surfaces of said substrate.2. The semiconductor device according to claim 1 , further comprising:a conductive member passing through said molding resin and providing electrical conduction between said wiring pattern and the outside; anda sleeve board located on said molding resin, including an opening for exposing said conductive member, and formed of a thermoplastic resin.3. The semiconductor device according to claim 1 , wherein said metal base plate is formed of a material containing copper or aluminum.4. The semiconductor device according to claim 1 , wherein said semiconductor element includes a wide bandgap semiconductor.5. A method of manufacturing a semiconductor device claim 1 , comprising the steps of:(a) preparing a substrate including a metal base plate, an insulating sheet ...

WAFER PROCESSING METHOD

A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices. 1. A wafer processing method of dividing a wafer along a plurality of crossing streets formed on a front side of said wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed , said wafer processing method comprising:a protective tape attaching step of attaching a protective tape to the front side of said wafer;a laser processing apparatus preparing step of preparing a laser processing apparatus including a chuck table having a holding surface for holding said wafer, said holding surface being adapted to selectively receive a vacuum and an air pressure;a modified layer forming step of placing said protective tape attached to said wafer on said holding surface of said chuck table of said laser processing apparatus, next applying the vacuum to said holding surface to thereby hold said wafer through said protective tape on said holding surface under suction, and next applying a laser beam having a transmission wavelength to said wafer from a back side of said wafer along said streets, thereby forming a modified layer inside said wafer along each street at ...

METHOD FOR MANUFACTURING ELECTRONIC PARTS

A method for manufacturing electronic parts, which is characteristic in that it permits reduction of contamination to the semi-cured adhesive layer formed on semiconductor wafer and the cohesive sheet used therein is superior in adhesiveness for example to the lead frame, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer by coating a pasty adhesive entirely over the rear face of a wafer and curing the pasty adhesive partially by radiation-ray irradiation or heating into the sheet shape, a fixing step of fixing the semi-cured adhesive layer formed on a wafer and a ring frame by bonding them to the cohesive layer of a cohesive sheet, a dicing step of dicing the wafer together with the semi-cured adhesive layer with a dicing blade into semiconductor chips, and a pick-up step of picking up the chips carrying the semi-cured adhesive layer from the cohesive layer of the cohesive sheet after radiation-ray irradiation, wherein the photopolymerization initiator in the cohesive layer of the cohesive sheet has a particular property. 2. The method for manufacturing electronic parts according to claim 1 , wherein the photopolymerization initiator is ethanone claim 1 , 1-[9-ethyl-6-(2-methylbenzoyl)-9H-carbazol-3-yl]- claim 1 , 1-(O-acetyloxime) claim 1 , 2 claim 1 ,4 claim 1 ,6-trimethylbenzoyl-diphenyl-phosphine oxide claim 1 , or 2-hydroxy-1-{4-[4-(2-hydroxy-2-methyl-propionyl)-benzyl]-phenyl}-2-methyl-propan-1-one.3. The method for manufacturing electronic parts according to claim 1 , wherein the cohesive contains a (meth)acrylate ester polymer in an amount of 100 parts by mass claim 1 , an ultraviolet polymerizable compound in an amount of 5 parts or more by mass and 200 parts or less by mass claim 1 , a multifunctional isocyanate curing agent in an amount of 0.5 part or more by mass and 20 parts or less by mass and a photopolymerization initiator in an amount of 0.1 part or more by mass and 20 parts or less by mass.4. The ...

Methods and systems for laser processing of coated substrates

Examples of methods and systems for laser processing of materials are disclosed. Methods and systems for singulation of a wafer comprising a coated substrate can utilize a laser outputting light that has a wavelength that is transparent to the wafer substrate but which may not be transparent to the coating layer(s). Using techniques for managing fluence and focal condition of the laser beam, the coating layer(s) and the substrate material can be processed through ablation and internal modification, respectively. The internal modification can result in die separation.

SEMICONDUCTOR STACKED PACKAGE AND METHOD OF FABRICATING THE SAME

A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided. 1. A semiconductor stacked package package , comprising:a substrate; anda chip having a first surface attached onto the substrate, a second surface opposing the first surface, and a trace structure formed on the first surface, wherein the trace structure is formed with a warpage portion at a position that extends beyond an edge of the chip.2. The semiconductor stacked package package of claim 1 , wherein a stress applied onto the chip is subject to being concentrated on the warpage portion.3. The semiconductor stacked package package of claim 1 , further comprising a block layer formed between the substrate and the chip.4. The semiconductor stacked package structure of claim 1 , wherein the substrate is made of glass or silicon.5. A method of fabricating a semiconductor stacked package package claim 1 , comprising the steps of:mounting on a substrate a wafer having a first surface mounted on the substrate, a second surface opposing the first surface, a trace structure formed on the first surface and at least a cutting region on the first surface;removing a portion of the wafer to form a cutting groove corresponding to the cutting region for exposing the cutting region from the cutting groove; andcutting the substrate and the wafer along the cutting groove to form on the cutting region a stress concentrated region , so as for the trace structure to be formed with a warpage portion at a ...

Method for Fabricating Array-Molded Package-on-Package

a An improved semiconductor device package is manufactured by attaching semiconductor chips () on an insulating substrate () having contact pads (). A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations. 1. A method for fabricating a semiconductor device , said method comprising:providing a mold having a top portion and a bottom portion, the top portion including recesses suitable for a cavity and a plurality of protrusions shaped as truncated cones;placing a thin sheet of compliant inert polymer over the surface of the top portion;introducing a molding compound into the cavity to form a encapsulation body covering a semiconductor chip and linear arrays of contact pads adjacent to the chip, each conical protrusion matching a contact pad location, leaving a conical aperture in the encapsulation body over each contact pad corresponding to a conical protrusion in the cavity; andafter partial polymerizing of the molding compound, the mold is opened and the encapsulated semiconductor chip is removed.2. The method of claim 1 , wherein the thin sheet of compliant inert polymer is dissolved into the molding compound.3. The method of claim 1 , further comprising peeling off of the top portion the thin sheet of compliant inert polymer.4. The method of claim 3 , in which the semiconductor chip is disposed on a substrate.54. The method of claim 3 , in which the molding compound covers a first surface of the substrate on which the semiconductor chip is disposed and does not cover a second surface opposite the first surface.6. The ...

DEVICES WITH CRACK STOPS

An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device. 1. A method of making an apparatus comprising:providing at least two devices on a substrate wherein the substrate has a first thickness;reducing the thickness of the substrate to a second thickness; andproviding at least one crack stop in the substrate.2. The method of claim 1 , wherein the crack stop is located separate from the at least two devices.3. The method of claim 1 , further comprising singulating the at least two devices.4. The method of claim 1 , further comprising mounting a carrier to the at least two devices on a side opposite the substrate.5. The method of claim 1 , wherein reducing the thickness of the substrate comprises etching claim 1 , polishing claim 1 , or grinding the substrate.6. The method of claim 1 , wherein providing at least one crack stop comprises dry etching or wet etching.7. The method of claim 6 , wherein providing a crack stop in the substrate comprises dry etching or wet etching through a patterned mask.8. The method of claim 3 , wherein singulating the at least two devices comprises removing the carrier substrate and sawing or breaking the substrate.9. The method of claim 1 , wherein providing a crack stop in the substrate is performed at the same time as providing one or more via holes through the substrate and at least one of the devices.10. The method of claim 9 , further comprising forming an ohmic contact to the substrate.11. A method of making an apparatus ...

CHIP PACKAGE AND FABRICATION METHOD THEREOF

A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad. 113-. (canceled)14. A method for forming a chip package , comprising:providing a semiconductor substrate having a plurality of die regions and predetermined scribe regions, wherein each of the die regions comprise at least a contact pad region and at least a device region, and the predetermined scribe regions surround the die regions, wherein the predetermined scribe region comprises an actual scribe region, and a remained scribe region is between the predetermined scribe region and the actual scribe region;forming a signal contact pad structure and an EMI ground pad structure on the contact pad region;forming a first opening and a second opening in the die region to expose the signal contact pad structure and the EMI ground pad structure;forming a first conducting layer and a second conducting layer in the first opening and the second opening to electrically contact with the signal contact pad structure and the EMI ground pad structure, respectively, wherein the first conducting layer and the signal contact pad structure are separated from a periphery of the predetermined scribe ...

EPITAXY LEVEL PACKAGING

A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate. 1. A method of processing an epitaxial wafer comprising: wherein said plurality of compound semiconductor crystalline wafers and/or portions thereof are derived from wafers having at least one first nominal size including a first diameter;', 'mounting a separate assembly substrate over said assembly pattern, said separate assembly substrate having a second size, including a second diameter which exceeds said first diameter;', 'wherein said separate assembly substrate includes a plurality of through substrate vias extending from a top surface to a bottom surface which contacts said assembly pattern;', 'forming an epitaxial layer in said separate assembly substrate within said plurality of through substrate vias with an epitaxial process., 'arranging a plurality of compound semiconductor crystalline wafers and/or portions thereof into an assembly pattern;'}2. The method of wherein said separate assembly substrate is a solid rigid disc.3. The method of wherein said epitaxial process comprises liquid phase epitaxy (LPE) claim 1 , hydride vapor phase epitaxy (HVPE) claim 1 , metal organic chemical vapor deposition (MOCVD) claim 1 , molecular beam epitaxy (MBE) claim 1 , or other epitaxial growth methods.4. The method of wherein said plurality of compound semiconductor crystalline wafers include at least two separate wafers comprised of two different materials.5. The method of wherein a reactor used for said epitaxial process forms an epitaxial layer on N separate compound semiconductor ...

SEALANT LAMINATED COMPOSITE, SEALED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, SEALED SEMICONDUCTOR DEVICES FORMING WAFER, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed. In certain aspects, this can prevent the substrate or wafer from warping and the semiconductor devices from peeling; can collectively seal a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed on a wafer level; and can provide a sealant laminated composite that is excellent in the heat resistance and humidity resistance after sealing. 1. A sealant laminated composite for collectively sealing a semiconductor devices mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor devices forming surface of a wafer on which semiconductor devices are formed , comprising:a support wafer; andan uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer.2. The sealant laminated composite according to claim 1 , wherein difference between an expansion coefficient of the support wafer and that of the substrate on which the semiconductor devices are mounted or the wafer on which the semiconductor devices are formed is 3 ppm or less.3. The sealant laminated composite according to claim 1 , wherein a thickness of the uncured resin layer is 20 μm or more and 2000 μm or less.4. The sealant laminated composite according to claim 2 , wherein a thickness of the uncured resin layer is 20 μm or more and 2000 μm or ...

CUTTING METHOD FOR DEVICE WAFER

A cutting method for cutting a device wafer along a plurality of crossing division lines by using a cutting blade, the division lines being formed on the front side of the device wafer to partition a plurality of regions where a plurality of devices are respectively formed. The cutting method includes a hydrophilic property providing step of applying a plasma to the front side of the device wafer to thereby make hydrophilic the front side of the device wafer, and a cutting step of cutting the device wafer along the division lines by using the cutting blade as supplying a cutting fluid to the device wafer after performing the hydrophilic property providing step. 1a hydrophilic property providing step of applying a plasma to the front side of said device wafer to thereby make hydrophilic the front side of said device wafer; anda cutting step of cutting said device wafer along said division lines by using said cutting blade as supplying a cutting fluid to said device wafer after performing said hydrophilic property providing step.. A cutting method for cutting a device wafer along a plurality of crossing division lines by using a cutting blade, said division lines being formed on the front side of said device wafer to partition a plurality of regions where a plurality of devices are respectively formed, said cutting method comprising: 1. Field of the InventionThe present invention relates to a cutting method for cutting a device wafer having a plurality of devices on the front side thereof by using a cutting blade.2. Description of the Related ArtIn a semiconductor device fabrication process, a plurality of crossing division lines are formed on the front side of a semiconductor wafer to thereby partition a plurality of regions where a plurality of semiconductor devices are respectively formed. The back side of the semiconductor wafer is ground by a grinding apparatus to reduce the thickness of the wafer to a predetermined thickness. Thereafter, the semiconductor wafer ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Ineffective chips are formed in the circumference of a semiconductor wafer and effective chips are formed in a region surrounded by the ineffective chips. Dicing lines partition the effective chips and the ineffective chips. Polyimide is formed on an outer circumferential portion of the semiconductor wafer with a predetermined width from an outer circumferential end of the semiconductor wafer such that the polyimide continuously covers the ineffective chips from the outer circumferential end of the semiconductor wafer to the inside and continuously covers a portion which is a predetermined distance away from the outer circumferential end of the semiconductor wafer to the effective chip in the dicing line interposed between the ineffective chips. A metal film is formed on the front electrode formed on the effective chips by plating. The semiconductor wafer is cut into semiconductor chips along the dicing lines by a blade. 1. A method of manufacturing a semiconductor device comprising:forming ineffective chips in a circumference of a first main surface of a semiconductor wafer;forming effective chips in a region surrounded by the ineffective chips;forming a front electrode on the effective chips and the ineffective chips;providing an insulating film on dicing lines which partition the effective chips and the ineffective chips;forming a rear electrode on a second main surface of the semiconductor wafer;forming polyimide on an outer circumferential portion of the first main surface of the semiconductor wafer with a predetermined width from an outer circumferential end of the semiconductor wafer such that the polyimide continuously covers the ineffective chips from the outer circumferential end of the semiconductor wafer to the inside and continuously covers a portion which is a predetermined distance away from the outer circumferential end of the semiconductor wafer to the effective chip in the dicing line interposed between the ineffective chips;forming a metal film on ...

Methods for scribing of semiconductor devices with improved sidewall passivation

A method of singulating semi-conductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semi-conductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semi-conductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.

Method for the reuse of gallium nitride epitaxial substrates

A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING ELECTRONIC ASSEMBLY

A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed. 1. A method of manufacturing a semiconductor device , the method comprising:providing an adhesive layer on a support body;providing a semiconductor element on the adhesive layer;providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; andremoving the substrate from the adhesive layer,wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed.2. The method according to claim 1 ,wherein the adhesive layer has an irregularity on a surface thereof, the substrate being formed on the surface.3. The method according to claim 2 ,wherein an example of the irregularity is a crater-shaped irregularity.4. The method according to claim 2 , providing a layer that includes a first resin that exhibits an adhesive property on the support body and a particle of a second resin, the particle of the second resin being contained in the first resin, an etching rate of the second resin being higher than the first resin, and', 'etching a surface portion of the layer and removing the particle of the second resin existing in the surface ...

Film for forming protective layer

The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×10 2 Pa·S or more and 2×10 4 Pa·S or less, and the shear modulus of the adhesive layer is 1×10 3 Pa or more and 2×10 6 Pa or less, when the thermosetting resin layer has a temperature in a range of 50 to 120° C.

LAMINATE AND METHOD FOR SEPARATING THE SAME

A laminate including a supporting member which is light transmissive; a supported substrate supported by the supporting member; an adhesive layer provided on a surface of the supported substrate which surface faces toward the supporting member; and a release layer which is made of a fluorocarbon and is provided between the supporting member and the supported substrate, the release layer having a property that changes when it absorbs light coming through the supporting member. 1. A laminate comprising:a supporting member which is light transmissive;a supported substrate supported by the supporting member;an adhesive layer provided on a surface of the supported substrate, wherein said surface faces toward the supporting member; anda release layer which is made of a fluorocarbon and is provided between the supporting member and the supported substrate,the release layer has a property that changes when it absorbs light coming through the supporting member.2. The laminate as set forth in claim 1 , wherein the release layer is formed by plasma CVD.3. The laminate as set forth in claim 1 , wherein the supporting member is made of glass or silicon.4. The laminate as set forth in claim 1 , further comprising at least one layer provided between the supporting member and the release layer.5. A method for separating the supported substrate and the supporting member from each other which are included in a laminate as set forth in claim 1 ,said method comprising changing a property of the release layer by irradiating the release layer with light through the supporting member. The present invention relates to (i) a laminate produced by adhering together a supporting member and a supported substrate supported by the supporting member and (ii) a method for separating the laminate.As mobile phones, digital AV devices, IC cards and the like are highly functionalized, it is more demanded that a semiconductor silicon chip (hereafter referred to as “chip”) be highly integrated in a ...

METHOD FOR CHIP PACKAGE

Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. 1. A method for chip package , comprising:providing a semi-packaged wafer, the semi-packaged wafer having a dicing street and a metal pad;selectively forming a metal electrode on the metal pad; forming a protective layer in area outside the metal electrode on the wafer, the protective layer covering the dicing street;forming a solder ball on the metal electrode; anddicing the wafer along the dicing street.2. The method according to claim 1 , where the selective forming process is a selective electroplating process.3. The method according to claim 2 , where the selective electroplating process comprises: forming a first mask layer on the wafer claim 2 , exposing an area the metal electrode to be formed; cleaning the wafer using zincate; with the first mask layer protection claim 2 , electroplating nickel and gold successively on the wafer using a non-electrolytic electroplating process; and removing the first mask layer.4. The method according to claim 3 , where the nickel is electroplated to a thickness of 3 μm claim 3 , and the gold is electroplated to a thickness of 0.05 μm.5. The method according to claim 3 , where the first mask layer is a photoresist mask.6. The method ...

Method and Apparatus for Plasma Dicing a Semi-conductor Wafer

The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. (canceled)13. (canceled)14. (canceled)15. (canceled)16. (canceled)17. (canceled)18. (canceled)19. (canceled)20. (canceled)21. (canceled)22. (canceled)23. (canceled)24. (canceled)25. (canceled)26. (canceled)27. (canceled)28. (canceled)29. (canceled)30. (canceled)31. (canceled)32. (canceled)33. A method for plasma dicing a substrate , the method comprising:providing a process chamber having a wall;providing a plasma source adjacent to the wall of the process chamber;providing a work piece support within the process chamber;providing a lifting mechanism within the work piece support;placing the substrate onto a support film on a frame to form the work piece;loading the work piece onto the lifting mechanism;generating a plasma through the plasma source; andetching the work piece through the generated plasma.34. The method according to wherein the lifting mechanism touches only the frame area.35. The method according to wherein the lifting mechanism does not make point contact with the substrate.36. The method according to further comprising a transfer arm.37. The method according to wherein the transfer arm supports the frame and the substrate.38. The method according to wherein the transfer arm supports the tape and the frame.39. The method according to wherein the ...

Method and Apparatus for Plasma Dicing a Semi-conductor Wafer

The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.