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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2869. Отображено 100.
16-02-2012 дата публикации

High-frequency switch

Номер: US20120038411A1
Принадлежит: Toshiba Corp

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

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22-03-2012 дата публикации

Multi-function and shielded 3d interconnects

Номер: US20120068327A1
Принадлежит: TESSERA RESEARCH LLC

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

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19-04-2012 дата публикации

Rf bus controller

Номер: US20120093132A1
Принадлежит: Broadcom Corp

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

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31-05-2012 дата публикации

Radiofrequency amplifier

Номер: US20120133442A1
Автор: Igor Blednov
Принадлежит: NXP BV

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

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23-08-2012 дата публикации

Microwave unit and method therefore

Номер: US20120211487A1
Принадлежит: Huawei Technologies Co Ltd

A microwave unit comprising a motherboard and a package adapted to be assembled automatically in, e.g., a Surface Mounted Device, SMD, machine is disclosed. The microwave unit preferably comprises a connecting component interconnecting the motherboard and the package, and operable to make the signal ways on a same level at both the motherboard and at the package. Furthermore, the microwave unit preferably comprises a micro-strip adapted soldering tag for soldering on two sides.

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08-11-2012 дата публикации

Processing Signals by Couplers Embedded in an Integrated Circuit Package

Номер: US20120280763A1
Автор: Ahmadreza Rofougaran
Принадлежит: Broadcom Corp

Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

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04-04-2013 дата публикации

Semiconductor package including an integrated waveguide

Номер: US20130082379A1
Принадлежит: Broadcom Corp

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

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25-04-2013 дата публикации

Antenna-printed circuit board package

Номер: US20130099006A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An antenna-printed circuit board (PCB) package is provided. The antenna-PCB package includes a PCB; an antenna portion formed on an upper surface of the PCB and inside the PCB; and a radio frequency integrated circuit (RFIC) chip bonded to a lower surface of the PCB.

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01-08-2013 дата публикации

Transmission line transition having vertical structure and single chip package using land grip array coupling

Номер: US20130194754A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

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29-08-2013 дата публикации

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

Номер: US20130222401A1
Принадлежит: Toshiba Corp

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

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03-10-2013 дата публикации

Power recovery circuit based on partial standing waves

Номер: US20130260708A1
Автор: Ahmadreza Rofougaran
Принадлежит: Broadcom Corp

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

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10-10-2013 дата публикации

Interchip communication using a dielectric waveguide

Номер: US20130265732A1
Принадлежит: Texas Instruments Inc

An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

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10-10-2013 дата публикации

Interchip communication using an embedded dielectric waveguide

Номер: US20130265733A1
Принадлежит: Texas Instruments Inc

An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

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07-11-2013 дата публикации

Interlayer communications for 3d integrated circuit stack

Номер: US20130293292A1
Принадлежит: Intel Corp

Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

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27-03-2014 дата публикации

Noise attenuation wall

Номер: US20140084477A1
Принадлежит: Xilinx Inc

An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

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06-01-2022 дата публикации

INTERPOSER

Номер: US20220005757A1
Принадлежит: AMOSENSE CO., LTD

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device. 1. An interposer comprising:a support body including a top surface and a bottom surface, at least a part of the support body disposed along the edge of a substrate;a connection electrode configured to connect the top surface and bottom surface of the support body; anda shielding member disposed at an outer surface of the support body.2. The interposer of claim 1 , wherein the support body is disposed along the edge of the substrate claim 1 , as one part or a combination of two or more parts claim 1 , selected from a group including:a straight part disposed in a straight line shape along a part of the edge of the substrate;a inclined part disposed in an inclined shape so as to be adjacent to a part of the edge of the substrate or a corner of the substrate; anda curved part disposed in a round shape.3. The interposer of claim 1 , wherein the support body is formed of a ceramic material.4. The interposer of claim 1 , wherein the connection electrode is formed as a conductive material filled in a via hole formed through the support body in a thickness direction thereof to connect the top and bottom surfaces of the support body.5. The interposer of claim 4 , wherein ...

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05-01-2017 дата публикации

Electronic apparatus operable in high frequencies

Номер: US20170005047A1
Принадлежит: Sumitomo Electric Industries Ltd

An electronic apparatus that includes a semiconductor device mounted on an assembly base is disclosed. The semiconductor device includes a transmission line, whose impedance is matched to characteristic impedance, and a pad connected to the transmission line, through which a high frequency signal is supplied to or extracted from the semiconductor device. The pad accompanies a stub line that is concurrently formed with the transmission line and grounded within the semiconductor device. The stub line operates as a short stub that may compensate parasitic capacitance attributed to the pad.

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02-01-2020 дата публикации

MICROELECTRONIC ASSEMBLIES HAVING INTERPOSERS

Номер: US20200006235A1
Принадлежит: Intel Corporation

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect. 1. A microelectronic assembly , comprising:a package substrate having a high bandwidth interconnect;a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect; anda second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.2. The microelectronic assembly of claim 1 , wherein the high bandwidth interconnect is a waveguide.3. The microelectronic assembly of claim 1 , wherein the high bandwidth circuitry of the first interposer is radio frequency (RF) circuitry.4. The microelectronic assembly of claim 1 , further comprising:a first die having a first surface and an opposing second surface, wherein the first surface of the first die is electrically coupled to a surface of the package substrate and the second surface of the first die is electrically coupled to the first interposer; anda second die having a first surface and an ...

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02-01-2020 дата публикации

INDUCTOR AND TRANSMISSION LINE WITH AIR GAP

Номер: US20200006261A1
Автор: LIN Kevin
Принадлежит:

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines. 1. An integrated circuit structure , comprising:one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm; andan air gap in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.2. The integrated circuit structure of claim 1 , wherein the width of the air gap and a distance between the first and second conductive lines is approximately 1 to 10 μm.3. The integrated circuit structure of claim 1 , wherein the air gap includes one or more spacers along at least one top corner of the air gap and at least one sidewall of the first and second conductive lines.4. The integrated circuit structure of claim 3 , wherein the one or more spacers leave an opening in the air gap of approximately 100-300 nm.5. The integrated circuit structure of claim 3 , wherein the air gap includes left and right spacers formed along the sidewalls of the first and second conductive lines claim 3 , respectively claim 3 , where the left and right spacers are coplanar with a top surface of the first and second conductive lines.6. The integrated circuit structure of claim 1 , wherein the air gap is formed as a continuous recess between the first and second conductive lines.7. The integrated circuit structure of claim 1 , wherein the air gap is formed as non-contiguous air gap segments that are spaced apart by the ILD to provide structural support to the sidewalls of the first and second conductive lines.8. ...

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03-01-2019 дата публикации

Platform with thermally stable wireless interconnects

Номер: US20190006298A1
Принадлежит: Intel Corp

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

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03-01-2019 дата публикации

SHIELDED INTERCONNECTS

Номер: US20190006572A1
Принадлежит: Intel Corporation

Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines. 1. A quantum computing (QC) assembly , comprising:a quantum processing die;a control die; anda flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines, and the shield structure includes a plurality of air gaps.2. The QC assembly of claim 1 , wherein the flexible interconnect includes a flexible portion having a first end and an opposing second end claim 1 , a first rigid connection portion at the first end claim 1 , and a second rigid connection portion at the second end.3. The QC assembly of claim 2 , further comprising:a circuit component;wherein the quantum processing die and the first rigid connection portion are coupled to the circuit component, and the circuit component includes electrical pathways to electrically couple the quantum processing die and the first rigid connection portion.4. The QC assembly of claim 1 , wherein the plurality of transmission lines have a longitudinal portion and at least one transverse portion.5. The QC assembly of claim 4 , wherein a pitch of the plurality of transmission lines in the longitudinal portion is less than a pitch of the plurality of transmission lines in the transverse portion.6. The QC assembly of claim 4 , wherein the shield structure includes a plurality of rectangular sleeves in the longitudinal portion ...

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02-01-2020 дата публикации

Method and Apparatus for Integrated Shielded Circulator

Номер: US20200006833A1
Принадлежит: HRL LABORATORIES LLC

An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.

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12-01-2017 дата публикации

HIGH-FREQUENCY PACKAGE

Номер: US20170012008A1
Автор: Yasooka Kosuke
Принадлежит: Mitsubishi Electric Corporation

A high-frequency package has: a resin substrate; a high-frequency device mounted on a side of a first surface of the resin substrate; a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; and a ground via of a ground potential formed within the resin substrate. A through hole is formed in the ground surface conductor. The ground via is placed between the transmission line and the through hole. 1. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface;a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; anda ground via of a ground potential formed within the resin substrate, whereina through hole is formed in the ground surface conductor, andthe ground via is placed between the transmission line and the through hole.2. The high-frequency package according to claim 1 , whereina number of the ground via is plural, andthe plural ground vias are placed along the transmission line.3. The high-frequency package according to claim 1 , wherein a diameter of the through hole is less than half of a wavelength of the high-frequency signal.4. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; anda transmission line for a high-frequency signal formed in an inner layer of the resin substrate, whereina through hole is formed in the ground surface conductor, anda diameter of the through hole is less than half of a ...

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14-01-2016 дата публикации

RF Switch on High Resistive Substrate

Номер: US20160013141A1
Принадлежит:

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. 1. A method comprising:performing a first implantation to implant a semiconductor substrate and to form a deep well region, wherein the semiconductor substrate is of a first conductivity type, and has a resistivity higher than about 5,000 ohm-cm, and wherein in the first implantation, an impurity of a second conductivity type opposite to the first conductivity type is implanted; a top portion overlying the well region; and', 'a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are substantially un-implanted in the first and the second implantations;, 'performing a second implantation to implant the semiconductor substrate, wherein a well region of the first conductivity type is formed over the deep well region, and wherein after the first and the second implantations, the semiconductor substrate comprisesforming a gate dielectric over the top portion of the semiconductor substrate;forming a gate electrode over the gate dielectric; andperforming a third implantation to implant the top portion of the semiconductor substrate and to form a source region and a ...

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11-01-2018 дата публикации

EMBEDDED MILLIMETER-WAVE PHASED ARRAY MODULE

Номер: US20180012852A1
Принадлежит:

Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit. 1. A method for fabricating a phased array module , the method comprising:embedding a radio integrated circuit into a first set of substrates comprising a first material; andcoupling a second set of substrates to the first set of substrates wherein the second set of substrates comprises a second material having a lower electrical loss than the first material, the second set of substrates comprising a plurality of antenna elements coupled to the radio integrated circuit through one or more vias.2. The method of wherein coupling the second set of substrates to the first set of substrates comprises coupling with a row of solder balls and further comprising embedding the radio integrated circuit into the first set of substrates in a substrate layer adjacent to the second set of substrates.3. The method of and further comprising:coupling the second set of substrates to the first set of substrates with a first row of solder balls;coupling a second row of solder balls to the first set of substrates; andcoupling the radio integrated circuit to the second row of substrates with a first set of vias.4. The method of and further comprising coupling the plurality of antenna elements to the radio integrated circuit through the one or more vias that are coupled to the first row of solder balls.5. The method of wherein ...

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11-01-2018 дата публикации

MULTIPLE-PATH RF AMPLIFIERS WITH ANGULARLY OFFSET SIGNAL PATH DIRECTIONS, AND METHODS OF MANUFACTURE THEREOF

Номер: US20180013391A1
Принадлежит:

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions. 1. An amplifier module comprising:a substrate with a mounting surface, wherein a plurality of non-overlapping zones is defined at the mounting surface, including a first-die mounting zone and a second-die mounting zone;a first amplifier die in the first-die mounting zone, wherein the first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal; anda second amplifier die in the second-die mounting zone, wherein the second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal, wherein the first amplifier die and the second amplifier die are coupled to the substrate so that the first and second signal paths through the first amplifier die and the second amplifier die extend in substantially different directions.2. The module of claim 1 , further comprising:a first wirebond array coupled between an RF output terminal of the first ...

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09-01-2020 дата публикации

METHOD FOR FABRICATING ELECTRONIC PACKAGE

Номер: US20200013728A1
Принадлежит:

An electronic package and a method for fabricating the same are provided. The method includes disposing an electronic component on a lower side of a first carrier and forming an encapsulant on an upper side of the first carrier. A first conductor is disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation. As such, the electronic package has a reduced thickness and improved antenna efficiency. 110-. (canceled)11. A method for fabricating an electronic package , comprising:providing a first carrier having a first side and a second side opposite to the first side;disposing at least one electronic component on at least one of the first side and the second side of the first carrier;forming an encapsulant on the second side of the first carrier; anddisposing on the encapsulant a first conductor configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation.12. The method of claim 11 , further comprising disposing on the second side of the first carrier a second conductor corresponding in function to the first conductor.13. The method of claim 12 , further comprising forming a first shielding layer in the first carrier.14. The method of claim 13 , wherein the first shielding layer is greater than the second conductor in a layout area in the first carrier.15. The method of claim 11 , wherein the encapsulant is further formed on the first side of the first carrier.16. The method of claim 11 , further comprising bonding a plurality of supporting members to the first side of the first carrier.17. The method of claim 11 , further comprising stacking a second carrier on the first side of the first carrier.18. The method of claim 17 , wherein the second carrier has a third conductor corresponding in function to the first conductor.19. The method of claim 17 , wherein the second carrier further has a second shielding layer.20. The method ...

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18-01-2018 дата публикации

Calibration Kits for RF Passive Devices

Номер: US20180019217A1
Принадлежит:

A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices. 1. A device comprising: a substrate; and', 'a plurality of low-k dielectric layers over the substrate, wherein the plurality of low-k dielectric layer comprises a first region and a second region;, 'a chip comprising 'a first passive device, wherein the first region extends into all low-k dielectric layers in the chip, and is overlapped by the first passive device, and the first region is free from dummy metal lines and dummy vias; and', 'a first calibration kit in the chip, wherein the first calibration kit comprises a second passive device, wherein the second passive device is identical to the first passive device, wherein the second region extends into the all low-k dielectric layers in the chip, and is overlapped by the second passive device, and each of the first and the second calibration kits comprises a probe pad connected to a respective one of the first passive device and the second passive device; and', 'second dummy patterns in the second region of the plurality of low-k dielectric layers, wherein the second dummy ...

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22-01-2015 дата публикации

Multi-Function and Shielded 3D Interconnects

Номер: US20150021788A1
Принадлежит:

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. 115-. (canceled)16. A microelectronic unit , comprising:a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element, wherein a first one of the conductive pads at least partially overlies the opening;a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the first conductive pad; anda second conductive element extending through the opening and directly contacting a surface of the semiconductor material within the opening, the second conductive element being insulated from the first conductive element, the second conductive element exposed at the rear surface for connection with the external component, the second conductive ...

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17-01-2019 дата публикации

ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE

Номер: US20190019767A1
Автор: Ishibashi Daijiro
Принадлежит: FUJITSU LIMITED

An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer. 1. An electronic device comprising:a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, and a first wiring layer that constitutes a first transmission line that has a predetermined characteristic impedance with the first grounded layer;a mold resin arranged on a side of the semiconductor device;an insulating layer arranged over the semiconductor device and the mold resin;a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer;a second wiring layer formed over the insulating layer and includesa first area disposed at a part overlapping with the second grounded layer anda second area disposed on a side of an end part of the second grounded layer, the first area including a first line width and constituting a second transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the second grounded layer, the second area including a second line width smaller than the first line ...

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17-01-2019 дата публикации

PHOTODIODE STRUCTURES

Номер: US20190019914A1
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A method comprising forming an amorphous Ge material over a waveguide structure in a back end of line (BEOL) metal layer comprising depositing a metal layer on the amorphous Ge material through an opening of a via and crystallizing the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.2. The method of claim 1 , wherein the amorphous Ge material is formed over an upper surface the waveguide structure in the BEOL metal layer.3. The method of claim 1 , wherein the annealing process is at about 350° C. to 420° C.4. The method of claim 1 , wherein the crystallizing the amorphous Ge material into the crystalline Ge structure is performed by the annealing process with a metal layer in contact with the Ge material.5. The method of claim 1 , wherein the forming of the amorphous Ge material is adjacent to the waveguide structure in the BEOL metal layer and comprises:depositing a barrier layer of nitride directly on the upper surface of the waveguide structure, followed by a patterning of the barrier layer;depositing the amorphous Ge material directly on the barrier layer, followed by a patterning of the amorphous Ge material;depositing the metal layer on the amorphous Ge material through the opening of the via; andcrystallizing of the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.6. The method claim 5 , wherein the metal layer is a metal seed layer formed in direct contact with the amorphous Ge material ...

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16-01-2020 дата публикации

Radio-frequency module

Номер: US20200020651A1
Принадлежит: Fujitsu Component Ltd

A radio-frequency module includes a semiconductor device, a first signal line configured to transmit an electrical signal to the semiconductor device, a ground electrode, and a first discharge unit situated between the first signal line and the ground electrode, wherein the first discharge unit includes a first projection formed on the ground electrode and a second projection formed on the first signal line, and the first projection and the second projection are situated opposite each other, with a predetermined distance therebetween, and wherein when an effective wavelength of the transmitted electrical signal is denoted as λg, and a length of the first projection is denoted as L, λg and L are related as: 0<( L/λg )≤0.1.

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16-01-2020 дата публикации

REFLECTION-CANCELING PACKAGE TRACE DESIGN

Номер: US20200020673A1
Автор: LIU Xike, MA Mengying
Принадлежит: CREDO TECHNOLOGY GROUP LIMITED

A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval. 1. A method of providing a high-bandwidth chip-to-chip link having a first die coupled to a second die via a first substrate trace , an intermediate trace , and a second substrate trace , the method comprising:determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval;determining a second propagation delay for the electrical signal to traverse the second substrate trace; andsetting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.2. The method of claim 1 , further comprising:manufacturing a substrate for packaging at least one of the first and second dies, the substrate having at least one of the first and second traces with said length.3. The method of claim 2 , further comprising:assembling the link, wherein said assembling includes electrically connecting said at least one of the first and second traces to the intermediate trace.4. The method of claim 1 , wherein ...

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21-01-2021 дата публикации

COUPLED LINE STRUCTURES FOR WIDEBAND APPLICATIONS

Номер: US20210020589A1
Принадлежит:

Coupled line structures for wideband applications are provided herein. In certain embodiments, a coupled line structure includes one transmission line that is segmented in a metal layer and another that is substantially continuous in the metal layer, thereby allowing tighter spacing and higher coupling between the transmission lines relative to what is achievable if both transmission lines were continuous. The high coupling in turn aids in achieving wide bandwidth. 1. A semiconductor die with an integrated wideband coupled line structure , the semiconductor die comprising:two or more metallization layers including a first metallization layer and a second metallization layer;a first transmission line formed in the two or more metallization layers; anda second transmission formed in the two or more metallization layers and coupled to the first transmission line,wherein the first transmission line is substantially continuous in the second metallization layer, and the second transmission line is segmented in the second metallization layer.2. The semiconductor die of claim 1 , wherein the first transmission line and the second transmission line are edge coupled in the second metallization layer.3. The semiconductor die of claim 1 , wherein the first transmission line and the second transmission line are separated by a minimum design rule spacing of the second metallization layer.4. The semiconductor die of claim 1 , wherein the second transmission line is substantially continuous in the first metallization layer and connected to a plurality of metal segments in the second metallization layer by way of a plurality of vias.5. The semiconductor die of claim 1 , wherein the two or more metallization layers include exactly two metallization layers.6. The semiconductor die of claim 1 , further comprising a compound semiconductor substrate over which the two or more metallization layers are formed claim 1 , wherein the compound semiconductor substrate includes gallium arsenide ...

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16-01-2020 дата публикации

Semiconductor package with plastic waveguide

Номер: US20200021002A1
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.

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26-01-2017 дата публикации

RADIO FREQUENCY PROBE APPARATUS

Номер: US20170023635A1

Provided herein is a radio frequency probe apparatus including a RF waveguide including a ground electrode and a signal electrode, a register connected to the signal electrode, a RF connector including an outer conductor connected to the ground electrode, an inner conductor connected to the signal electrode, and a dielectric body filling a portion between the outer conductor and the inner conductor, and a single tip probe connected to the signal electrode of the RF waveguide, or the register. 1. A radio frequency probe apparatus , comprising:a RF waveguide including a ground electrode and a signal electrode;a register connected to the signal electrode;a RF connector including an outer conductor connected to the ground electrode, an inner conductor connected to the signal electrode, and a dielectric body filling a portion between the outer conductor and the inner conductor; anda single tip probe connected to the signal electrode of the RF waveguide, or the register.2. The radio frequency probe apparatus according to claim 1 , wherein the RF waveguide comprises:a metal substrate;the ground electrode contacted to and formed on the metal substrate;a dielectric layer formed on the ground electrode;the signal electrode formed on the dielectric layer; anda protective layer covering a portion of the signal electrode and including openings exposing both ends of the signal electrode.3. The radio frequency probe apparatus according to claim 2 , wherein the register is formed in a surface mountable apparatus (SMD) type including a first terminal connected to the signal electrode and a second terminal connected to the signal tip probe claim 2 , and mounted on the metal substrate.4. The radio frequency probe apparatus according to claim 3 , further comprising a bonding wire connecting the first terminal to the signal electrode and fixed to the first terminal and the signal electrode by a solder.5. The radio frequency probe apparatus according to claim 3 , wherein the single tip ...

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24-04-2014 дата публикации

Embedded chip packages and methods for manufacturing an embedded chip package

Номер: US20140110858A1
Принадлежит: INFINEON TECHNOLOGIES AG

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

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25-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180025998A1
Автор: KARIYAZAKI Shuuichi
Принадлежит:

A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer. 1. A semiconductor device comprising:a first substrate having a first front surface and a first back surface opposite to the first front surface;a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; anda first semiconductor component mounted over the second front surface of the second substrate and coupled with a first signal transmission path,the first signal transmission path comprising:a first coupling part to couple the first semiconductor component and the second substrate electrically;a second coupling part to couple the second substrate and the first substrate;a first external terminal formed on the first back surface of the first substrate;a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; anda second transmission part located in the first substrate to couple the second ...

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28-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210028132A1
Автор: HIRAYAMA Masahiro

A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part. 1. A semiconductor device comprising:an insulation substrate provided with a ground pattern having a reference potential;a semiconductor element provided on the insulation substrate;an input terminal provided on the insulation substrate and to which an electric signal to be supplied to the semiconductor element is input;a 1st signal line electrically connected between the semiconductor element and the input terminal, and provided on the insulation substrate;a 2nd signal line electrically connected between the 1st signal line and the input terminal, and provided on the insulation substrate; anda capacitor connected to the 2nd signal line and provided on the insulation substrate,wherein the 2nd signal line has impedance lower than impedance of the 1st signal line, a 1st metal pattern provided on the insulation substrate so as to connect to the 2nd signal line and extend along a longitudinal direction of the 2nd signal line, and', 'a 2nd metal pattern which is at least a part of the ground pattern, and is provided between the 1st metal pattern and the 2nd signal line and between the 1st metal pattern and an end part of the insulation substrate, to be electrically coupled with the 1st metal pattern., 'wherein the capacitor includes'}2. The ...

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05-02-2015 дата публикации

Interconnection structure of semiconductor device

Номер: US20150035165A1
Принадлежит: National Chiao Tung University NCTU

An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second through silicon via by a distance ranged from 2 μm to 40 μm.

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02-02-2017 дата публикации

PRINTED INTERCONNECTS FOR SEMICONDUCTOR PACKAGES

Номер: US20170033072A1
Принадлежит:

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads. 1. A method of forming packaged semiconductor devices , comprising:providing a first semiconductor die (first die) having bond pads thereon mounted face up on a package substrate or on a die pad of a lead frame (substrate), wherein said substrate includes terminals or contact pads (substrate pads);forming a first dielectric layer comprising printing a first dielectric precursor layer comprising a first ink including a first liquid carrier extending from said substrate pads to said bond pads;printing a first interconnect precursor layer comprising a second ink including a second liquid carrier over said first dielectric layer or said first dielectric precursor layer extending from said substrate pads to said bond pads, andsintering or curing said first interconnect precursor layer to remove at least said second liquid carrier to form a first electrically conductive interconnect comprising an ink residue which connects respective ones of said substrate pads to respective ones of said bond pads.2. The method of claim 1 , further comprising:forming a second dielectric ...

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01-02-2018 дата публикации

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Номер: US20180033754A1
Автор: Dugas Roger, Trezza John
Принадлежит:

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

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17-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND ANTENNA DEVICE

Номер: US20220051997A1
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device according to the present invention includes: a semiconductor element; a first metal body having a die pad to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad; a second metal body which has a wire bond pad connected to a signal electrode of the semiconductor element via a wire, and is provided on the same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; and a molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed. 1. A semiconductor device comprising:a semiconductor element;a first metal body having a die pad portion to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad portion;a second metal body which has a wire bond pad portion connected to a signal electrode of the semiconductor element via a wire, and is provided on a same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; anda molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed, whereinthe exposed surface of the first metal body protrudes by a predetermined amount from an outer shape of the molding resin.2. The semiconductor device according to claim 1 , whereinthe molding resin holds the first metal body and the second metal body such that the die bond surface and the wire bond pad portion are exposed.3. The semiconductor device according to claim 1 , whereinthe transmission line is a microstrip line.4. ...

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31-01-2019 дата публикации

POWER FET WITH A RESONANT TRANSISTOR GATE

Номер: US20190035781A1
Принадлежит:

A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. 1. A semiconductor FET , comprising a resonant gate and source and drain electrodes , wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.2. The FET of claim 1 , wherein the resonant gate includes integrally constructed reactive components connected in series or parallel with resonant gate segments.3. The FET of claim 2 , wherein the reactive components include ceramic dielectric material.4. The FET of claim 3 , wherein the dielectric material has dielectric properties that vary ≤±1% over temperatures in the range of −40° C. to +120° C.5. The FET of claim 1 , further comprising a plurality of embedded capacitive circuit elements electrically connected in series with one or more resonant gate segments to form a lumped capacitance that reduces overall input capacitance of the resonant gate.6. The FET of claim 1 , wherein the resonant gate has adjacently located segments which reactively couple to each other.7. The FET of claim 6 , further comprising dielectric material integrally constructed to affect the reactive coupling between adjacently located segments of the resonant gate.8. The FET of claim 1 , wherein the resonant gate forms an elongated resonant transmission line.9. The FET of claim 8 , further comprising reactive and resistive components integrally constructed within the resonant gate to form the elongated resonant transmission line in combination with segments of the resonant gate claim 8 , which elongated transmission line is resonant at one or more predetermined frequencies.10. The FET of claim 9 , wherein the resistive component is located to terminate the resonant transmission line.11. The FET of claim 9 , wherein one or more resistive components within the resonant gate are adapted to control bandwidth of the resonant gate.12. The ...

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04-02-2021 дата публикации

Method, System, and Apparatus for Forming Three-Dimensional Semiconductor Device Package with Waveguide

Номер: US20210035927A1
Принадлежит: NXP USA, Inc.

A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide. 1. An integrated circuit package comprising:a rigid-flex PCB structure;one or more antenna launchers coupled to the rigid-flex PCB structure; anda waveguide assembly comprising one or more metallized surfaces coupled to the rigid-flex PCB structure and configured to propagate electromagnetic waves emitted by the one or more antenna launchers.2. The integrated circuit package of wherein the rigid-flex PCB structure comprises:a first rigid PCB region; andone or more second rigid PCB regions coupled to corresponding edges of the first rigid PCB region at corresponding flexible PCB regions.3. The integrated circuit package of wherein the metallized surface coupled to the rigid-flex PCB comprises a metal layer applied to a top major surface of the one or more second rigid PCB regions.4. The integrated circuit package of wherein the metal layer comprises copper.5. The integrated circuit package of wherein the one or more antenna launchers are coupled to the top major surface of the first rigid PCB region.6. The integrated circuit package of wherein one of the second rigid PCB region is oriented in a plane at an angle to the first rigid PCB region wherein the corresponding flex PCB region maintains electrical and physical coupling at the corresponding edges.7. The integrated circuit package of wherein the angle is a 90 degree angle.8. The integrated circuit package of claim 5 , whereineach second rigid PCB region is oriented in a plane orthogonal to the first rigid PCB ...

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04-02-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210035931A1

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member. 1. A semiconductor device comprising:a semiconductor die;a base member having a conductive main surface including a region that mounts the semiconductor die thereon;a side wall provided on the conductive main surface of the base member and surrounding the region of the conductive main surface, the side wall being made of a dielectric, wherein the side wall includes a first portion and a second portion sandwiching the region therebetween;a first conductive film provided on the first portion of the side wall, the first conductive film being electrically connected to the semiconductor die;a second conductive film provided on the second portion of the side wall, the second conductive film being electrically connected to the semiconductor die;a first conductive lead conductively bonded to the first conductive film on the first portion of the side wall;a second conductive lead conductively bonded to the second conductive film on the second portion of the side wall;wherein at least one of the first portion and the second portion of the base member includes a recess on a back ...

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04-02-2021 дата публикации

FIELD-EFFECT TRANSISTOR

Номер: US20210036115A1
Автор: Watanabe Shinsuke
Принадлежит: Mitsubishi Electric Corporation

A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder. 1. A field-effect transistor comprising:a semiconductor substrate;a plurality of drain electrodes that are provided on a first surface of the semiconductor substrate and extend in a first direction;a plurality of source electrodes that are provided on the first surface of the semiconductor substrate, extend in the first direction, and are alternately arranged with each other with the plurality of drain electrodes;a plurality of gate electrodes that are provided on the first surface of the semiconductor substrate, extend in the first direction, and are provided between the plurality of source electrodes and the plurality of drain electrodes, respectively;an input terminal connected to the plurality of gate electrodes;an output terminal connected to the plurality of drain electrodes; anda plurality of metal layers that are provided in the semiconductor substrate apart from the first surface, extend in a second direction intersecting the first direction, and intersect the plurality of drain electrodes when viewed in a direction perpendicular to the first surface,wherein the plurality of metal layers ...

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07-02-2019 дата публикации

SINGLE CLOCK SOURCE FOR A MULTIPLE DIE PACKAGE

Номер: US20190041895A1
Принадлежит:

A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source. 1. A processing device comprising:a package;a plurality of dies disposed on the package, wherein each die comprises a clock receiver;a single common clock source to generate a common clock signal; and a first terminated transmission line; and', 'a second terminated transmission line, wherein the first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source., 'a first group of terminated transmission lines, comprising, 'a clock distribution circuitry coupled to the single common clock source, the clock distribution circuitry to distribute the common clock signal from the single common clock source to each of the plurality of dies individually, wherein the clock distribution circuitry comprises2. The processing device of claim 1 , wherein the clock distribution circuitry further comprises: a third terminated transmission line;', 'a fourth terminated transmission line, wherein the third terminated transmission line and the fourth ...

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24-02-2022 дата публикации

DEVICES INCLUDING COAX-LIKE ELECTRICAL CONNECTIONS AND METHODS FOR MANUFACTURING THEREOF

Номер: US20220059487A1
Принадлежит:

A device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip. The device includes an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection includes a section extending in a direction vertical to the main surface of the semiconductor chip. The device further includes an electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection includes a section extending in a direction parallel to the main surface of the semiconductor chip. 1. Device , comprising:a semiconductor chip comprising an electrical contact arranged on a main surface of the semiconductor chip;an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection comprises a section extending in a direction vertical to the main surface of the semiconductor chip; andan electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection comprises a section extending in a direction parallel to the main surface of the semiconductor chip.2. The device of claim 1 , wherein the external connection element is configured to provide a mechanical connection between the device and the printed circuit board.3. The device of claim 1 , further comprising:an encapsulation material, wherein the semiconductor chip is at least partly embedded in the ...

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07-02-2019 дата публикации

HIGH-DENSITY TRIPLE DIAMOND STRIPLINE INTERCONNECTS

Номер: US20190043816A1
Автор: Sutono Albert
Принадлежит:

In accordance with embodiments disclosed herein, there is provided a high density triple diamond stripline interconnect. An interconnect includes a first reference layer, a second reference layer disposed below the first reference layer, and a dielectric disposed between the first reference layer and the second reference layer. The interconnect further includes a first pair of conductors including a first conductor and a second conductor that are in a broadside-facing orientation within the dielectric below the first reference layer and above the second reference layer. The interconnect further includes a second pair of conductors including a third conductor and a fourth conductor that are in an edge-facing orientation within the dielectric below the first conductor and above the second conductor. 1. An interconnect comprising:a first reference layer;a second reference layer disposed below the first reference layer;a dielectric disposed between the first reference layer and the second reference layer;a first pair of conductors comprising a first conductor and a second conductor that are in a broadside-facing orientation within the dielectric below the first reference layer and above the second reference layer; anda second pair of conductors comprising a third conductor and a fourth conductor that are in an edge-facing orientation within the dielectric below the first conductor and above the second conductor.2. The interconnect of claim 1 , wherein:the first conductor and the second conductor are differential striplines;the third conductor and the fourth conductor are differential striplines;first dimensions of the first conductor are substantially equal to second dimensions of the second conductor; andthird dimensions of the third conductor are substantially equal to fourth dimensions of the fourth conductor.3. The interconnect of claim 1 , wherein:the first conductor and the second conductor are differential striplines;the third conductor and the fourth conductor ...

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07-02-2019 дата публикации

Transmission Line Bias Resistor

Номер: US20190044212A1
Автор: George Korony
Принадлежит: AVX Corp

Systems and methods for introducing DC bias in a radio frequency (RF) signal communicated over a transmission line are provided. In one example implementation, the RF system can include a transmission line having a first port and a second port. The transmission line can be configured to communicate an RF signal between a first port and a second port. One or more DC bias resistors can be coupled to the transmission line at a location between the first port and the second port. Each DC bias resistor can provide a path for injecting DC current to the transmission line to provide DC bias for the RF signal. Each DC bias resistor can be coupled to the transmission line via a point connection.

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18-02-2021 дата публикации

INTEGRATED STRUCTURES WITH ANTENNA ELEMENTS AND IC CHIPS EMPLOYING EDGE CONTACT CONNECTIONS

Номер: US20210050312A1
Принадлежит:

Disclosed is an antenna apparatus including a substrate having a cavity in a first outer surface thereof. The substrate has a sidewall defining a portion of the cavity, and a first edge contact is formed at the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact. An antenna element, disposed at a second outer surface of the substrate opposite the first outer surface, is electrically connected to RF circuitry within the IC chip through a conductive via extending within the substrate. 1. An antenna apparatus comprising:a substrate having a cavity in a first outer surface thereof, the substrate having a sidewall defining a portion of the cavity, wherein a first edge contact is formed at the sidewall;an integrated circuit (IC) chip disposed within the cavity, having a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact; andan antenna element disposed at a second outer surface of the substrate opposite the first outer surface, the antenna element being electrically connected to radio frequency (RF) circuitry within the IC chip through a conductive via extending within the substrate.2. The antenna apparatus of claim 1 , wherein the electrical connection of the antenna element to the RF circuitry within the IC chip is made through the first and second edge contacts.3. The antenna apparatus of claim 2 , further comprising a conductive trace on or within the first outer surface and connecting to the first edge contact claim 2 , wherein the electrical connection of the antenna element to the RF circuitry is made through the conductive via to the conductive trace.4. The antenna apparatus of claim 1 , wherein:the cavity has a bottom surface facing a bottom surface of the IC chip; andthe conductive via extends to the bottom surface of the cavity and ...

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18-02-2021 дата публикации

CRYPTOGRAPHIC DEVICE ARRANGED TO COMPUTE A TARGET BLOCK CIPHER

Номер: US20210050313A1
Принадлежит:

A cryptographic device () arranged to compute a target block cipher (B) on an input message (), the device comprising a first and second block cipher unit () arranged to compute the target block cipher (B) on the input message, and a first control unit () arranged to take the first block cipher result and the second block cipher result as input, and to produces the first block cipher result only if the block cipher results are equal. 1. A cryptographic device configured to encrypt an input message using a target block cipher (B) , the device comprising:{'sub': 'store', 'a memory circuit, wherein the memory circuit is configured to store a stored control value (Δ); and'} wherein the processor circuit comprises circuits configured to execute computer instructions stored in the memory circuit,', [{'sub': t', '1, 'a first circuit configured to compute the target block cipher (B) on the input message to obtain a first block cipher result (C);'}, {'sub': t', '2, 'a second circuit configured to compute the target block cipher (B) on the input message to obtain a second block cipher result (C); and'}, 'a control circuit configured to receive the first block cipher result as a first value and the second block cipher result as a second value,', 'wherein the control circuit produces the first value only when the first value and the second value are equal,', [{'sub': 1', '2', '1', '2', '1', '2, 'combine the first value and the second value by applying a first combination function to the first value and the second value to obtain a comparison value (C−C; C⊕C; comb (C, C)), wherein the combination function is equal to a predetermined value (0; δ) only when the first value and second value are equal, and'}, {'sub': 1', 'comp, 'compute an ancillary block cipher (B) on the comparison value to obtain a computed control value (Δ),'}, {'sub': comp', 'store, 'combine the first value, the computed control value (Δ), and the stored control value (Δ) by applying a second combination ...

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06-02-2020 дата публикации

MICROWAVE TRANSMITTER WITH IMPROVED INFORMATION THROUGHPUT

Номер: US20200044608A1
Принадлежит:

An RF amplifier module comprises a package having a package base, at least one RF amplifier chip attached to the package base, and an RF power combiner chip attached to the package base. The RF amplifier chip comprises a substrate and at least one transistor disposed on an epilayer overlying the substrate. The substrate comprises a first layer of synthetic diamond characterized by an average value of thermal conductivity. 123-. (canceled)24. A radiofrequency (RF) device , comprising:a housing; and an RF power combiner operatively coupled to a port,', 'at least one RF amplifier chip operatively coupled to said RF power combiner,, 'at least one RF amplifier module within said housing, wherein said RF amplifier module comprises 'a heat conductor in thermal communication with said at least one RF amplifier chip.', 'wherein said at least one RF amplifier chip comprises a transistor that comprises a material layer overlying a substrate, wherein said substrate comprises carbon, and'}25. The RF device of claim 24 , wherein said substrate has a thickness up to about 600 micrometers.26. The RF device of claim 24 , wherein said substrate has an average value of thermal conductivity greater than about 1000 W/mK.27. The RF device of claim 24 , wherein said material layer comprises a semiconductor material.28. The RF device of claim 27 , wherein said semiconductor material comprises a Group III-V material.29. The RF device of claim 24 , wherein said RF power combiner comprises an electromagnetic waveguide.30. The RF device of claim 24 , wherein said transistor is a high-electron mobility transistor.31. The RF device of claim 24 , wherein said RF amplifier module further comprises a plurality of transistor gates operatively coupled to said RF power combiner claim 24 , wherein said plurality of transistor gates has a pitch of up to 60 micrometers.32. The RF device of claim 24 , wherein said material layer comprises a two-dimensional electron gas layer.33. A radiofrequency (RF) ...

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07-02-2019 дата публикации

Dielectric coating for crosstalk reduction

Номер: US20190045623A1
Принадлежит: Intel Corp

Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

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18-02-2016 дата публикации

LEADFRAME PACKAGE WITH INTEGRATED PARTIAL WAVEGUIDE INTERFACE

Номер: US20160050793A1
Принадлежит: VIASAT, INC.

A MMIC package is disclosed comprising: a leadframe based overmolded package, a die positioned within the overmolded package; and a partial waveguide interface, wherein the partial waveguide interface is integral with the overmolded package facilitating low cost and reliable assembly. Also disclosed is an overmolded package where the die sits on a metal portion exposed on the bottom of the package and the package is configured for attachment to a chassis of a transceiver such that heat from the die is easily dissipated to the chassis with a direct thermal path. The disclosure facilitates parallel assembly of MMIC packages and use of pick and place/surface mounting technology for attaching the MMIC packages to the chassis of transceivers. This facilitates reliable and low cost transceivers. 1. (canceled)2. A semiconductor device comprising:a molded Monolithic Microwave Integrated Circuit (“MMIC”) package including a MMIC, wherein the molded MMIC package further comprises a heat sink interface in thermal contact with the MMIC for transferring heat away from the MMIC through the heat sink interface, wherein the heat sink interface is integrated in the molded MMIC package; anda waveguide launch molded into the molded MMIC package.3. The semiconductor device of claim 2 , wherein the heat sink interface is a bottom side heat sink interface claim 2 , and wherein either the heat sink interface is flush with a bottom surface of the molded MMIC package claim 2 , or the heat sink interface is recessed from the bottom surface within the molded MMIC package claim 2 , wherein the bottom surface is a surface closest to a surface mounting side of the molded MMIC package.4. The semiconductor device of claim 2 , wherein the heat sink interface is a portion of a leadframe.5. The semiconductor device of claim 2 , the molded MMIC package further comprising:a leadframe, wherein the leadframe is injection over-molded with an overmold material to form a package body portion, wherein the ...

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16-02-2017 дата публикации

Interconnect array pattern with a 3:1 signal-to-ground ratio

Номер: US20170048967A1
Принадлежит: International Business Machines Corp

An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

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22-02-2018 дата публикации

Systems and methods for improved chip device performance

Номер: US20180053982A1
Автор: Jayesh Nath, YING Shen
Принадлежит: Aviat US Inc

Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.

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23-02-2017 дата публикации

Field Effect Transistor Having Loop Distributed Field Effect Transistor Cells

Номер: US20170053910A1
Принадлежит: Raytheon Company

A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration. 1. A Field Effect Transistor (FET) , comprising:a plurality of FET cells disposed in a loop configuration, the plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes; each one of the plurality of gate electrodes extending along directions outwardly from an inner region of the loop configuration between a corresponding one of the source pads and a corresponding one of the drain pads;a gate contact connected to the gate electrode of each one of the FET cells;a drain contact connected to the drain pad of each one of the FET cells; anda source contact connected to source pad of each one of the FET cells;2. A Field Effect Transistor (FET) , comprising:a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads;a gate contact connected to the gate electrode of each one of the FET cells;a drain contact connected to the drain pad of each one of the FET cells;a source contact connected to source pad of each one of the FET cells;wherein the ...

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10-03-2022 дата публикации

RECONSTITUTED WAFER INCLUDING MOLD MATERIAL WITH RECESSED CONDUCTIVE FEATURE

Номер: US20220077015A1
Принадлежит:

A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A a surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die. 1. A system , comprising:{'claim-text': ['an integrated circuit (IC) die having two faces and sides;', 'mold material surrounding at least the sides of the IC die;', 'a redistribution layer; and', 'signal pads;', 'wherein the redistribution layer is positioned between (a) the signal pads and (b) the mold material and the IC die, wherein the redistribution layer has conductive paths at least connecting the IC die and at least some of the signal pads;', 'wherein a surface of the mold material and one of the two faces of the IC die abut the redistribution layer, wherein the surface of the mold material includes at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.'], '#text': 'a reconstituted wafer, comprising:'}2. The system of claim 1 , wherein the reconstituted wafer further comprises a plurality of IC dies claim 1 , the mold material claim 1 , the redistribution layer claim 1 , and the signal pads claim 1 , wherein the plurality of IC dies comprises the IC die.3. The system of claim 2 , wherein the plurality of IC dies further comprises a second IC die claim 2 , wherein the surface of the mold material and one of two faces of the second IC die abuts the ...

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20-02-2020 дата публикации

Semiconductor Devices Having Phase-Change Material (PCM) Radio Frequency (RF) Switches and Integrated Passive Devices

Номер: US20200058851A1
Принадлежит:

A semiconductor device includes a substrate and a phase-change material (PCM) radio frequency (RF) switch, having a heating element, a PCM situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM and underlies an active segment of the PCM. In one approach, the PCM RF switch is situated over the substrate, and the substrate is a heat spreader for the PCM RF switch. An integrated passive device (IPD) is disposed in an interlayer dielectric above the PCM RF switch, and is a metal resistor, a metal-oxide-metal (MOM) capacitor, and/or and inductor. In another approach, the PCM RF switch is disposed in an interlayer dielectric above the IPD, and the IPD is a poly resistor and/or a capacitor. 1. A semiconductor device including a substrate , said semiconductor device further comprising: a heating element;', 'a PCM situated over said heating element;', 'PCM contacts situated over passive segments of said PCM;', 'said heating element extending transverse to said PCM and underlying an active segment of said PCM;, 'a phase-change material (PCM) radio frequency (RF) switch comprisingsaid PCM RF switch being situated over said substrate and wherein said substrate is a heat spreader for said PCM RF switch;an integrated passive device (IPD) disposed in or over an interlayer dielectric, said interlayer dielectric being situated above said PCM RF switch in said semiconductor device;said IPD being selected from the group consisting of a metal resistor, a MOM capacitor, and an inductor.2. The semiconductor device of claim 1 , further comprising through-substrate-vias (TSVs).3. The semiconductor device of claim 1 , further comprising micro bumps.4. The semiconductor device of claim 1 , wherein said inductor is situated in a top metal level of said semiconductor device and wherein said inductor comprises a subtractively etched aluminum spiral inductor.5. The semiconductor device of claim 1 , wherein ...

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04-03-2021 дата публикации

Method and Apparatus for improved Circuit Structure Thermal Reliability on Printed Circuit Board Materials

Номер: US20210066209A1
Принадлежит: NXP B.V.

A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point. 1. A method for routing a conductive trace on a printed circuit board (PCB) , the method comprising:locating an expansion neutral point on a PCB subject to expansion and contraction;determining a first line from the expansion neutral point to a first point on the PCB, wherein the first point is an end point of the conductive trace;determining a second line perpendicular to the first line through the first point;locating a second point on the PCB at a point on the second line; andaligning the conductive trace from the first point to the second point along the second line, wherein the second point is an end point of the conductive trace.2. The method of claim 1 , whereinthe first point is a solder land on the PCB; andthe second point is on a portion of a metal structure formed on the PCB having greater than a threshold surface area.3. The method of wherein the solder land is one of a plurality of solder lands coupled to the metal structure.4. The method of further comprising for each one of the plurality of solder lands:determining a line from the neutral point to the one of the plurality of solder lands;determining a line perpendicular to the line ...

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04-03-2021 дата публикации

SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOF

Номер: US20210066219A1
Принадлежит:

A semiconductor structure and a method of forming the same are provided. A method of manufacturing the semiconductor structure includes: providing a substrate; depositing a first dielectric layer over the substrate; attaching a waveguide to the first dielectric layer; depositing a second dielectric layer to laterally surround the waveguide; and forming a first conductive member and a second conductive member over the second dielectric layer and the waveguide, wherein the first conductive member and the second conductive member are in contact with the waveguide. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member. 1. A method of manufacturing a semiconductor structure , comprising:providing a substrate;depositing a first dielectric layer over the substrate;attaching a waveguide to the first dielectric layer;depositing a second dielectric layer to laterally surround the waveguide; andforming a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide,wherein the waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.2. The method of claim 1 , further comprising claim 1 , prior to the attaching of the waveguide to the first dielectric layer claim 1 , attaching the waveguide to a carrier and aligning the waveguide to a location between the first conductive member and the second conductive member.3. The method of claim 2 , further comprising detaching the carrier from the waveguide and performing a thermal operation on the semiconductor structure subsequent to the detachment.4. The method of claim 1 , further comprising annealing the semiconductor structure subsequent to the attaching of the waveguide to the first dielectric layer.5. The method of claim 1 , further ...

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17-03-2022 дата публикации

RADIO FREQUENCY ANTENNAS AND WAVEGUIDES FOR COMMUNICATION BETWEEN INTEGRATED CIRCUIT DEVICES

Номер: US20220084962A1
Принадлежит: Intel Corporation

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device. 1. An integrated circuit package , comprising:a package substrate;a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices include radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto; anda radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.2. The integrated circuit package of claim 1 , wherein the radio frequency waveguide comprises a plate structure having a recess therein.3. The integrated circuit package of claim 2 , wherein the plate structure extends over each integrated circuit device of the plurality of integrated circuit devices.4. The integrated circuit package of claim 1 , wherein the radio frequency waveguide comprises a pipe structure extending between the first integrated circuit device and the second integrated circuit device.5. The integrated circuit package of claim 1 , wherein the radio ...

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17-03-2022 дата публикации

IN-PACKAGE RF WAVEGUIDES AS HIGH BANDWIDTH CHIP-TO-CHIP INTERCONNECTS AND METHODS FOR USING THE SAME

Номер: US20220084965A1
Принадлежит:

In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile. 1. An electronic package comprising:a package substrate;a first silicon die or tile and a second silicon die or tile attached to the package substrate;a first waveguide formed in the package substrate, the first waveguide interconnecting the first silicon die or tile with the second silicon die or tile;a second waveguide formed in the package substrate, the second waveguide interconnecting the first silicon die or tile with the second silicon die or tile, wherein the second waveguide is vertically beneath the first waveguide; anda conductive interconnect in the package substrate, the conductive interconnect interconnecting the first silicon die or tile with the second silicon die or tile.2. The electronic package of claim 1 , wherein the first waveguide is a radio frequency (RF) waveguide.3. The electronic package of claim 1 , wherein the second waveguide is a radio frequency (RF) waveguide.4. The electronic package of claim 1 , wherein the first waveguide is to communicate ultra-high bandwidth RF signals between the first silicon die or tile and the second silicon die or tile.5. The electronic package of claim 4 , wherein the first silicon die or tile includes an input/output (I/O) block and the second silicon die or tile includes an I/O block claim 4 , each I/O block is a broadband transceiver for RF signals and to up and down convert frequencies of the RF signals.6. The electronic package of claim 5 , wherein the first waveguide is coupled to the I/O block of the first silicon die or tile ...

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17-03-2022 дата публикации

Electronic device package and method for manufacturing the same

Номер: US20220084972A1
Принадлежит: Advanced Semiconductor Engineering Inc

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

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27-02-2020 дата публикации

ON-CHIP INTEGRATED CAVITY RESONATOR

Номер: US20200066661A1
Принадлежит:

A semiconductor chip may include high frequency electrical circuitry. The semiconductor chip may include a cavity resonator integrated with the high frequency electrical circuitry in a semiconductor substrate of the semiconductor chip. The cavity resonator may include a resonator body in a cavity in the semiconductor substrate of the semiconductor chip. The resonator body may comprise a metal layer. The cavity resonator may include a feeding structure electrically connected to the high frequency electrical circuitry. 1. A semiconductor chip , comprising:high frequency electrical circuitry; and [ 'wherein the resonator body comprises a metal layer, and', 'a resonator body in a cavity in the semiconductor substrate of the semiconductor chip,'}, 'a feeding structure electrically connected to the high frequency electrical circuitry., 'the cavity resonator comprising, 'a cavity resonator integrated with the high frequency electrical circuitry in a semiconductor substrate of the semiconductor chip,'}2. The semiconductor chip of claim 1 , further comprising an insulation layer between the resonator body and the semiconductor substrate within the cavity.3. The semiconductor chip of claim 1 , wherein an interior portion of the cavity is at least partially filled with a dielectric material.4. The semiconductor chip of claim 1 , wherein the feeding structure comprises at least one of:an electrode that extends into an interior portion of the resonator body, ora slot antenna.5. The semiconductor chip of claim 1 , wherein an interior portion of the resonator body includes at least one region in which a dielectric material is not present.6. The semiconductor chip of claim 1 , wherein the cavity resonator is arranged on an opposite side of the semiconductor substrate from the high frequency electrical circuitry.7. The semiconductor chip of claim 1 , wherein an operable frequency range of a circuit formed by the high frequency electrical circuitry and the cavity resonator is between ...

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27-02-2020 дата публикации

AMPLIFIER WITH INTEGRATED DIRECTIONAL COUPLER

Номер: US20200067459A1
Принадлежит:

An embodiment of an amplifier includes a first amplifier with a first output terminal, a second amplifier with a second output terminal, and a plurality of microstrip transmission lines electrically connected to the amplifiers. The transmission lines include an impedance inverter line electrically connected between the first and second output terminals, and an output line electrically connected between the second output terminal and an output of the amplifier, where the output line forms a portion of an output impedance transformer. The amplifier also includes a directional coupler formed from a main line and a coupled line positioned in proximity to the main line, where the main line is formed from a portion of one of the transmission lines. The amplifier may also include a module substrate with a plurality of metal layers, where the main line and the coupled line are formed from different portions of the metal layers. 1. An amplifier comprising:a first amplifier with a first output terminal;a second amplifier with a second output terminal; an impedance inverter line electrically connected between the first and second output terminals, and', 'an output line electrically connected between the second output terminal and an output of the amplifier, wherein the output line forms a portion of an output impedance transformer; and, 'a plurality of microstrip transmission lines electrically connected to the first and second amplifiers, wherein the plurality of microstrip transmission lines include'}a directional coupler formed from a main line and a coupled line that is positioned in proximity to the main line, wherein the main line is formed from a portion of one of the plurality of microstrip transmission lines, and the coupled line is electrically isolated from the main line.2. The amplifier of claim 1 , wherein the amplifier is a Doherty amplifier claim 1 , the first amplifier is a carrier amplifier claim 1 , and the second amplifier is a peaking amplifier.3. The ...

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28-02-2019 дата публикации

STACKED TRANSMISSION LINE

Номер: US20190069392A1
Принадлежит: INVENSAS CORPORATION

A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces. 1. A multi-layer microelectronic structure , comprising:a first conductive trace disposed at a first spatial layer of a carrier or a package, the first conductive trace being coplanar to a plane of the first spatial layer;a second conductive trace disposed at a second spatial layer, a plane of the second spatial layer coplanar to or parallel to the plane of the first spatial layer, at least a portion of the second conductive trace parallel to the first conductive trace, the first and second conductive traces comprising a transmission line;a first plurality of conductive stubs disposed at a third spatial layer of the carrier or the package and electrically coupled to the first conductive trace, one or more stubs of the first plurality of conductive stubs at least partly overlaps one or more sections of the second conductive trace in a plan view without being mechanically coupled to the second conductive trace, a plane of the third spatial layer coplanar to or parallel to the plane of the first spatial layer; anda second plurality of conductive stubs disposed at a fourth spatial layer of the carrier or the package and electrically coupled to the second conductive trace, one or more stubs of the second plurality of conductive stubs at least partly overlaps one or more sections of the first conductive trace in a plan view without being mechanically coupled to the first conductive trace, a plane of the fourth spatial layer coplanar to or parallel to the plane of the first spatial layer, the first and second pluralities of conductive stubs adapted to increase a capacitive coupling between the first and second conductive traces based on an arrangement and an ...

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17-03-2016 дата публикации

Photodiode structures

Номер: US20160079451A1
Принадлежит: International Business Machines Corp

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

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16-03-2017 дата публикации

FLIP-CHIP EMPLOYING INTEGRATED CAVITY FILTER, AND RELATED COMPONENTS, SYSTEMS, AND METHODS

Номер: US20170077574A1
Принадлежит:

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer. 1. An integrated circuit (IC) comprising: at least one semiconductor layer;', a first transmission line configured to transmit a first electromagnetic (EM) signal through a first signal transmission aperture; and', 'a second transmission line configured to receive a second EM signal through a second signal transmission aperture; and, 'a plurality of interconnect layers for providing interconnections to the at least one semiconductor layer, at least one of the plurality of interconnect layers comprising], 'a semiconductor die comprising a plurality of die layers, the plurality of die layers comprisinga plurality of conductive elements interconnected to at least one of the plurality of interconnect layers, the plurality of conductive elements and at least one of the plurality of die layers defining an interior resonator cavity;the interior resonator cavity configured to receive the first EM signal from the first transmission line through the first signal transmission aperture, resonate the first EM signal to generate the second EM signal comprising a ...

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05-03-2020 дата публикации

RADIO FREQUENCY INTERCONNECTIONS FOR OSCILLATORY NEURAL NETWORKS

Номер: US20200074268A1
Принадлежит: Intel Corporation

Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency. 1. An oscillatory neural network (ONN) gate comprising:a transmission line;a first oscillator circuit tuned to a first frequency based on a first tuning voltage, the first tuning voltage associated with a first synapse weight;a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line;a second oscillator circuit tuned to a second frequency based on a second tuning voltage, the second tuning voltage associated with a second synapse weight; anda second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line, wherein an amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.2. The ONN gate of claim 1 , wherein the first oscillator circuit and the second oscillator circuit are ring oscillators.3. The ONN gate of claim 2 , wherein the ring oscillators ...

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05-03-2020 дата публикации

Compact Transceiver on a Multi-Level Integrated Circuit

Номер: US20200075233A1
Принадлежит:

Power and/or data are transmitted through variable magnetic fields between a first transceiver coil on a transceiver apparatus and a second transceiver coil in an inductor integrated into a multilevel wiring structure on a semiconductor integrated circuit chip. The first transceiver apparatus generates magnetic fields and can transmit data by varying a characteristic of the magnetic fields. The second transceiver coil receives the power from and/or detects data in the magnetic fields from the first transceiver apparatus. The inductor can include a ferromagnetic core that concentrates magnetic flux to improve data or power transmission efficiency to miniaturize the second transceiver coil while maintaining adequate inductive coupling between the coils. The second transceiver coil can transmit data by varying the impedance of the inductor and/or the integrated circuit. The semiconductor integrated circuit chip can be coupled to an object and the second transceiver coil can transmit data relating to the object. 1. A system for transmitting power or data through variable magnetic fields , comprising:a first transceiver apparatus comprising a first transceiver coil that generates first variable magnetic fields;a semiconductor integrated circuit comprising a multilevel wiring network fabricated on a semiconductor die; and a magnetic core; and', 'a second transceiver coil that is wound in a generally spiral manner on the outside of the magnetic core, the second transceiver coil including, 'an inductor integrated into the multilevel wiring network, wherein the inductor comprisesat least one level from the multilevel wiring network, whereinthe second transceiver coil is electrically coupled to active circuit elements on the semiconductor die, andthe first and second transceiver coils are inductively coupled to each other.2. The system of claim 1 , wherein the magnetic core includes a ferromagnetic material that concentrates a magnetic flux at the second transceiver coil to ...

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05-03-2020 дата публикации

WAVEGUIDE DEVICE, AND ANTENNA DEVICE INCLUDING THE WAVEGUIDE DEVICE

Номер: US20200076038A1
Принадлежит:

A waveguide device includes a first electrical conductor including an electrically conductive surface and a first throughhole, a second electrical conductor including electrically conductive rods and a second throughhole overlapping the first throughhole as viewed along an axial direction of the first throughhole, and a pair of electrically-conductive waveguiding walls positioned so that at least a portion of a space between the first throughhole and the second throughhole is interposed therebetween. The pair of waveguiding walls are surrounded by the electrically conductive rods, and allow an electromagnetic wave to propagate between the first throughhole and the second throughhole. 1. A waveguide device comprising:a first electrical conductor including an electrically conductive surface and a first throughhole;a second electrical conductor including a plurality of electrically conductive rods each including a leading end opposing the electrically conductive surface, the second electrical conductor including a second throughhole which overlaps the first throughhole as viewed along an axial direction of the first throughhole; anda pair of electrically-conductive waveguiding walls positioned so that at least a portion of a space between the first throughhole and the second throughhole is interposed therebetween, the pair of waveguiding walls being surrounded by the plurality of electrically conductive rods and allowing an electromagnetic wave to propagate between the first throughhole and the second throughhole; whereina cross section of at least one of the pair of electrically-conductive waveguiding walls taken perpendicular or substantially perpendicular to the axial direction includes a lateral portion extending along a first direction;as viewed along the axial direction, the pair of waveguiding walls extend along a second direction which intersects the first direction, and are on opposite sides of a central portion of the lateral portion;at least one end along ...

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22-03-2018 дата публикации

INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF

Номер: US20180082923A1
Принадлежит:

Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals. 18-. (canceled)9. A method of forming an integrated electronic component , comprising:providing an electronic device;disposing a plurality of layers over a substrate, wherein the layers comprise one or more of dielectric, conductive and sacrificial materials; andforming from the layers a microstructure comprising: a waveguide section comprising a plurality of waveguides, the waveguides each having a non-solid core volume within an outer conductor surrounding the core volume; and a transition structure coupling the waveguides to the electronic device.10. The method according to claim 9 , wherein the transition structure comprises a thermally conductive and electrically isolative material.11. The method according to claim 9 , wherein the waveguides each comprise a center conductor disposed in and surrounded by the outer conductor with the non-solid volume disposed between the center conductor and the outer conductor claim 9 , and wherein the transition structure comprises a post mechanically coupling the substrate to the center conductor.12. The method according to claim 11 , wherein the transition structure is disposed at an end of the center conductor.13. The method according to claim 11 , wherein the center conductor primarily comprises copper.14. The method according to claim 9 , wherein the transition structure comprises a dielectric.15. The method according to claim 9 , wherein the transition structure comprises silicon carbide.16. The method according to claim 9 , wherein the core volume comprises air.17. The method according to claim 9 , wherein the core volume comprises a vaporizing and condensing vapor.18. The method ...

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22-03-2018 дата публикации

MICROWAVE SEMICONDUCTOR DEVICE

Номер: US20180083582A1
Автор: TAKAGI Kazutaka
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A microwave semiconductor device of an embodiment includes a package, a semiconductor amplifying element, an output matching circuit, and a smoothing circuit. The package includes a metal base plate, a frame body bonded to a surface of the metal base plate, an input feedthrough part, and an output feedthrough part. The semiconductor amplifying element has an output electrode. The output matching circuit includes an output matching capacitor, and a first bonding wire connected to the output matching capacitor and the output electrode. The smoothing circuit includes a smoothing capacitor, and a second bonding wire. The smoothing capacitor is connected by the second bonding wire to a position in the output matching circuit at which capacitive reactance component of a load impedance seen from the output matching capacitor is smaller than inductive reactance component of the load impedance seen from the output electrode of the semiconductor amplifying element. 1. A microwave semiconductor device comprising:a package including a metal base plate, a frame body bonded to a surface of the metal base plate, an input feedthrough part bonded to the surface of the metal base plate and fitted in the frame body, and an output feedthrough part bonded to the surface of the metal base plate and fitted in the frame body at a position opposite to the input feedthrough part;a semiconductor amplifying element bonded to a region of the surface of the metal base plate surrounded with the frame body, having an output electrode, and having a rectangular planar shape;an output matching circuit including an output matching capacitor provided on a region of the surface of the metal base plate between the semiconductor amplifying element and the output feedthrough part and disposed along a long side direction of the semiconductor amplifying element, and a first bonding wire connected to the output matching capacitor and the output electrode; anda smoothing circuit including a smoothing capacitor ...

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31-03-2022 дата публикации

Photonic package and method of manufacture

Номер: US20220099887A1

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

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23-03-2017 дата публикации

TRANMISSION LINE BRIDGE INTERCONNECTS

Номер: US20170084553A1
Принадлежит:

In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits. 1. An integrated circuit package , comprising:a package substrate;an interposer structure formed at a top surface of the package substrate, wherein the interposer structure comprises a plurality of interposer layers; anda transmission line formed on at least one of the plurality of interposer layers, wherein the transmission line conveys signals between the package substrate and an external circuit.2. The integrated circuit package defined in claim 1 , wherein the transmission line comprises a transmission line selected from the group consisting of:a micro-strip transmission line and a stripline transmission line.3. The integrated circuit package defined in claim 1 , further comprising:an additional transmission line formed on the at least one of the plurality of interposer layers, wherein the transmission line transmits a first signal from the package substrate to a printed circuit board and wherein the additional transmission line transmits a second signal from the printed ...

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23-03-2017 дата публикации

PLATFORM WITH THERMALLY STABLE WIRELESS INTERCONNECTS

Номер: US20170084554A1
Принадлежит:

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC. 1. A packaged device comprising:an integrated circuit chip;a package substrate to carry the integrated circuit chip, the package substrate having conductive lines to communicatively couple the integrated circuit chip to one or more external components; and a radio frequency integrated circuit (RFIC) coupled to the RFIC module; and', 'a millimeter wave antenna communicatively coupled to the RFIC to send data to an external device., 'a radio frequency integrated circuit (RFIC) module communicatively coupled to the integrated circuit chip by traces for transmitting baseband signals, wherein the RFIC module comprises2. The packaged device of claim 1 , wherein the RFIC is flip-chip mounted to the RFIC module.3. The packaged device of claim 2 , wherein the RFIC is mounted to a first surface of the RFIC module that faces towards the package substrate and is between the RFIC module and a surface of the package substrate.4. The packaged device of claim 3 , wherein the antenna is embedded in the RFIC module and is located above the RFIC.5. The packaged device of claim 2 , wherein the RFIC is mounted to a second surface of the RFIC module that faces away from the package substrate.6. The ...

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22-03-2018 дата публикации

HIGH FREQUENCY MODULE, BOARD EQUIPPED WITH ANTENNA, AND HIGH FREQUENCY CIRCUIT BOARD

Номер: US20180084637A1
Автор: UEDA Hideki
Принадлежит:

A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor. 1. A high frequency module comprising:a first board having a first ground plane, a first ground land connected to the first ground plane, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are located on a same surface;a second board having a second ground plane, a second ground land connected to the second ground plane, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are located on a surface opposing to the first board and are respectively opposed to the first ground land and the first signal land; anda conduction member for connecting the first ground land to the second ground land,wherein the first signal land and the second signal land are connected by capacitance coupling without using any conductor.2. The high frequency module according to claim 1 ,wherein the first board further includes a radiation element connected to the first signal land with the first transmission line interposed between the radiation element and the first signal land, ...

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12-03-2020 дата публикации

Impedance Controlled Electrical Interconnection Employing Meta-Materials

Номер: US20200083171A1
Автор: Wyland Christopher
Принадлежит:

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation. 120.-. (canceled)21. A device comprising: the first set of layers includes a second conductor layer and a third conductor layer, wherein the second conductor layer is disposed between the first surface of the first conductor layer and the third conductor layer;', 'the second set of layers includes a fourth conductor layer and a fifth conductor layer, wherein the fourth conductor layer is disposed between the second surface of the first conductor layer and the fifth conductor layer;', 'the second conductor layer includes a first plurality of electrically independent conductors arranged to span the width of the plurality of layers and the third conductor layer extends continuously along the width of the plurality of layers; and', 'the fourth conductor layer includes a second plurality of electrically independent conductors arranged to span the width of the plurality of layers and the ...

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12-03-2020 дата публикации

WAFER LEVEL CHIP SCALE FILTER PACKAGING USING SEMICONDUCTOR WAFERS WITH THROUGH WAFER VIAS

Номер: US20200083202A1
Принадлежит:

A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity. 1. A method of fabricating an electronics package , the method comprising:forming a cavity in a first surface of a semiconductor substrate;forming one or more passive devices on the semiconductor substrate;forming a microelectromechanical device on a piezoelectric substrate; andbonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.2. The method of wherein the one or more passive devices are formed within the cavity.3. The method of wherein the one or more passive devices are formed on a second surface of the semiconductor wafer opposite the first surface.4. The method of further comprising forming bond pads for connection to a mounting substrate on the second surface of the semiconductor wafer.5. The method of further comprising electrically connecting the bond pads on the second surface of the semiconductor wafer and bond pads formed on the piezoelectric substrate.6. The method of further comprising forming one or more through wafer vias passing through the semiconductor substrate claim 5 , the one or more through wafer vias providing electrical communication between the bond pads on the second surface of the semiconductor wafer and the bond pads formed on the piezoelectric substrate.7. The method of further comprising hermetically sealing the cavity with a metallic seal ring.8. The method of comprising bonding the semiconductor substrate to the piezoelectric substrate with a transient liquid phase bond.9. The method of wherein forming the microelectromechanical device includes forming one of a ...

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31-03-2022 дата публикации

Microstructure enhanced absorption photosensitive devices

Номер: US20220102563A1
Принадлежит: W&w Sens Devices Inc, W&wsens Devices Inc

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

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12-03-2020 дата публикации

HIGH FREQUENCY CIRCUIT WITH RADAR ABSORBING MATERIAL TERMINATION COMPONENT AND RELATED METHODS

Номер: US20200083582A1
Принадлежит: XCERRA CORPORATION

A high speed circuit assembly includes a high speed circuit including at least one transmission line extending to a transmission line end, and radar absorbing material disposed adjacent the transmission line. 1. A high speed circuit assembly comprising:a high speed circuit including at least one transmission line extending to a transmission line end; andradar absorbing material in contact with or in close proximity with the at least one transmission line, the radar absorbing material terminates the at least one transmission line.2. The high speed circuit assembly as recited in claim 1 , wherein the high speed circuit is a lead frame.3. The high speed circuit assembly as recited in claim 2 , further comprising a frame assembly disposed near the lead frame claim 2 , and the frame assembly is a ground reference for the lead frame.4. The high speed circuit assembly as recited in claim 2 , further comprising a frame assembly disposed near the lead frame claim 2 , and the frame assembly is a power supply.5. The high speed circuit assembly as recited in claim 4 , wherein the radar absorbing material is disposed between the frame assembly and the transmission line end.6. The high speed circuit assembly as recited claim 5 , wherein the frame assembly includes a recess claim 5 , and the radar absorbing material is disposed at least partially within the recess.7. The high speed circuit assembly as recited in claim 1 , wherein the radar absorbing material is an attenuator for the high speed circuit.8. The high speed circuit assembly as recited in claim 1 , wherein the high speed circuit includes at least one ring coupler.9. The high speed circuit assembly as recited in claim 1 , wherein the high speed circuit has an operating frequency and an operating frequency wavelength claim 1 , and the at least one transmission line is defined by a length claim 1 , and the length of the at least one transmission line is greater than 0.1*operating frequency wavelength.10. A method ...

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12-03-2020 дата публикации

WELL THERMALIZED MICROSTRIP FORMATION FOR FLEXIBLE CRYOGENIC MICROWAVE LINES IN QUANTUM APPLICATIONS

Номер: US20200083585A1

A microstrip that is usable in a quantum application (q-microstrip) includes a ground plane, a polyimide film disposed over the ground plane at a first surface of the polyimide film, and a conductor formed on a second side of the polyimide film such that the first surface is substantially opposite to the second surface. A material of the conductor provides greater than a threshold thermal conductivity (Tx) with a structure of a dilution fridge stage (stage). The stage is maintained at a cryogenic temperature, and the material of the conductor bonds at the cryogenic temperature with a second material of a part of a connector of a microwave line. 1. A microstrip that is usable in a quantum application (q-microstrip) comprising:a ground plane;a polyimide film disposed over the ground plane at a first surface of the polyimide film; anda conductor formed on a second side of the polyimide film such that the first surface is substantially opposite to the second surface, wherein a material of the conductor provides greater than a threshold thermal conductivity (Tx) with a structure of a dilution fridge stage (stage), wherein the stage is maintained at a cryogenic temperature, and wherein the material of the conductor bonds at the cryogenic temperature with a second material of a part of a connector of a microwave line.2. The q-microstrip of claim 1 , wherein the material of the conductor provides greater than a threshold electrical conductivity (Td with an electrical component in the stage.3. The q-microstrip of claim 2 , wherein Tc represents Residual Resistance Ratio (RRR) of at least 100.4. The q-microstrip of claim 2 , further comprising:a disposition of the conductor relative to a second conductor in the q-microstrip, wherein the disposition prevents a microwave crosstalk between the conductor and the second conductor from exceeding −50 decibels.5. The q-microstrip of claim 1 , further comprising:a height (H) of the polyimide film, wherein H is selected as a function ...

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29-03-2018 дата публикации

INTERCONNECTS FOR WEARABLE DEVICE

Номер: US20180088627A1
Принадлежит:

Various embodiments disclosed relate to a wearable electronic device. One embodiment includes of a wearable electronic device includes a first flexible layer. The first flexible layer includes a first surface and a second surface that is substantially parallel to the first surface. A first electrical component and a second electrical component is attached to the second surface. A transmission line connects the first electrical component and the second electrical component. A voltage reference trace connected to a voltage reference source attached to at least one of the first electrical component or the second electrical component. The device further includes a second flexible layer. The second flexible layer includes a third surface that is substantially parallel to the second surface and facing the second surface. The second flexible layer also includes a fourth surface. The device further includes a voltage reference plane attached to the third surface. An interconnection is formed between the voltage reference trace and the voltage reference plane. 1. A wearable electronic device comprising:a first flexible layer comprising:a first surface;a second surface substantially parallel to the first surface;a first electrical component attached to the second surface;a second electrical component attached to the second surface;a transmission line connecting the first electrical component and the second electrical component; anda voltage reference trace connected to a voltage reference source attached to at least one of the first electrical component or the second electrical component;a second flexible layer attached to the first flexible layer to form a laminate, the second flexible layer comprising:a third surface substantially parallel to the second surface and facing the second surface;a fourth surface;a voltage reference plane attached to the third surface; andan interconnection formed between the voltage reference trace and the voltage reference plane.2. The wearable ...

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21-03-2019 дата публикации

SPINTRONIC DEVICES

Номер: US20190086487A1
Принадлежит:

A monolithic reusable microwire assembly can include a substrate and an electrically conductive thin-film wire formed on the substrate. The conductive thin-film wire can include a narrow segment forming an active area. A thermally and electrically insulating barrier can be formed on the electrically conductive thin-film wire. A roughness-reducing layer can be formed on the thermally and electrically insulating barrier and can have minimal surface roughness. 1. A monolithic reusable microwire assembly , comprising:a substrate;an electrically conductive thin-film wire formed on the substrate, said thin film wire having a narrow segment forming an active area;a thermally and electrically insulating barrier formed on the electrically conductive thin-film wire; anda roughness-reducing layer formed on the thermally and electrically insulating barrier, said roughness-reducing layer having a surface roughness of less than or equal to 20 nm.2. The monolithic reusable microwire assembly of claim 1 , wherein the substrate comprises silicon claim 1 , quartz claim 1 , glass claim 1 , plastic claim 1 , or a combination thereof.3. The monolithic reusable microwire assembly of claim 1 , further comprising a substrate adhesion layer claim 1 , a thin film wire adhesion layer claim 1 , a diffusion barrier layer claim 1 , or a combination thereof formed between the substrate and the thin film wire.4. The monolithic reusable microwire assembly of claim 3 , wherein the substrate is not thermally isolated from the thin film wire and functions as a heat drain for the thin film wire.5. The monolithic reusable microwire assembly of claim 3 , wherein the substrate adhesion layer comprises SiO.6. The monolithic reusable microwire assembly of claim 3 , wherein the thin film wire adhesion layer comprises titanium or chromium.7. The monolithic reusable microwire assembly of claim 3 , wherein the diffusion barrier layer comprises SiN.8. The monolithic reusable microwire assembly of claim 1 , ...

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25-03-2021 дата публикации

Semiconductor package and method of manufacturing the same

Номер: US20210091006A1
Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

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31-03-2016 дата публикации

Printed interconnects for semiconductor packages

Номер: US20160093525A1
Принадлежит: Texas Instruments Inc

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

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29-03-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180090456A1
Автор: Kato Katsuya
Принадлежит: Mitsubishi Electric Corporation

In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines. 1. A semiconductor device comprising:an input terminal;a circuit substrate including a plurality of circuit patterns containing a parallel capacitor, a plurality of first input pads connected to inputs of the circuit patterns respectively; a plurality of first output pads, and a plurality of first microstrip lines connecting outputs of the circuit patterns to the first output pads respectively;a semiconductor substrate including a plurality of transistor cells, a plurality of second input pads connected to inputs of the transistor cells, and a plurality of second output pads connected to outputs of the transistor cells;an output terminal;a plurality of first wires connecting the input terminal to the first input pads respectively;a plurality of second wires connecting the first output pads to the second input pads respectively; anda plurality of third wires connecting the second output pads to the output terminal respectively,wherein each of the transistor cells has a plurality of fingers connected in parallel and a source electrode connected to a rear electrode through a via hole,the numbers of the fingers of the transistor cells are the same, andthe first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.2. The semiconductor device according to claim 1 , wherein the ...

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21-03-2019 дата публикации

ON-CHIP WAVEGUIDE NETWORKS

Номер: US20190089036A1
Принадлежит: Intel Corporation

Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed. 1. A dielectric waveguide comprising:a substrate;a waveguide material disposed within the substrate; anda waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the substrate.2. The dielectric waveguide of claim 1 , wherein the waveguide material includes polymer or silicon dioxide (SiO2).3. The dielectric waveguide of claim 1 , wherein the substrate is glass or silicon.4. The dielectric waveguide of claim 1 , wherein the waveguide launcher is a first waveguide launcher claim 1 , and further comprising a second waveguide launcher electromagnetically and physically coupled with the waveguide material claim 1 , wherein the second waveguide launcher is exposed at the side of the substrate.5. The dielectric waveguide of claim 4 , wherein the waveguide material is to allow electromagnetic waves to propagate from the first waveguide launcher to the second waveguide launcher.6. A semiconductor package that includes a dielectric waveguide claim 4 , wherein the semiconductor package includes:a rigid substrate;a waveguide material disposed within the rigid substrate; anda chiplet coupled with the rigid substrate, wherein the chiplet is to cause a radio frequency (RF) signal to propagate throughout the waveguide material within the rigid substrate.7. The semiconductor package of claim 6 , wherein the RF signal has a frequency of at least one terahertz (THz).8. The semiconductor package of claim 6 , further comprising a package substrate that is coupled with the rigid substrate by one or more ...

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09-04-2015 дата публикации

60 ghz integrated circuit to printed circuit board transitions

Номер: US20150097633A1
Принадлежит: BlackBerry Ltd

Embodiments are directed to a transition structure for interfacing an integrated circuit chip and a substrate, comprising: a co-planar waveguide (CPW) structure formed based on ground-signal-ground (GSG) pads on the integrated circuit chip, a grounded co-planar waveguide (CPWG) structure coupled to the GSG pads, and a microstrip coupled to the CPWG structure.

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26-06-2014 дата публикации

Stripline and reference plane implementation for interposers using an implant layer

Номер: US20140175619A1
Автор: Abraham F. Yee, Mayan Riat
Принадлежит: Nvidia Corp

An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer.

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19-03-2020 дата публикации

MICROELECTRONIC ASSEMBLIES

Номер: US20200091128A1
Принадлежит: Intel Corporation

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar. 1. A microelectronic assembly , comprising:a package substrate having a first surface and an opposing second surface;a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate;a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; anda shield structure, wherein the shield structure at least partially surrounds the conductive pillar.2. The microelectronic assembly of claim 1 , wherein the shield structure is coupled to a ground connection on the package substrate.3. The microelectronic assembly of claim 1 , wherein the shield structure is coupled to a ground connection on the ...

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19-03-2020 дата публикации

MODULE WITH HIGH PEAK BANDWIDTH I/O CHANNELS

Номер: US20200092014A1
Принадлежит:

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die. 2. The hybrid computing module of claim 1 , wherein active switching elements embedded within an active semiconductor surface of a semiconductor chip earner claim 1 , a semiconductor die mounted on the semiconductor chip carrier claim 1 , or semiconductor embedded within the stacked assembly of semiconductor chips claim 1 , form an electrical interface with a signal control plane in the multilayer surface interface and the passive network filtering circuit functions as a clock or data recovery circuit.4. The resonant gate transistor of claim 3 , wherein inductors claim 3 , capacitors claim 3 , and resistors embedded within the resonant gate transistor's gate electrode function as band tuning elements to tailor maximal amplification of the attenuated signal at a resonant frequency or over desired spectral frequency bands.5. The high-peak bandwidth I/O channel of claim 3 , wherein the high-peak bandwidth I/O channel additionally comprises conductive means configured as a differential pair and active switching elements that configure the resonant gate transistor to operate as a bi-directional amplification stage.6. The hybrid computing module of claim 1 , wherein the high peak bandwidth I/O channels are distributed across several data signal planes of the multilayer surface interface and comprise ground walls and ground planes claim 1 , and have interconnection density exceeding 200 IO/mm/layer.8. The high peak bandwidth I/O channel of claim 7 , wherein the multilayer surface interface is formed on a dielectric substrate or semiconducting die claim 7 , a semiconductor carrier claim 7 , or an interposer circuit embedded within a stacked assembly of semiconductor chips.9. The high-peak bandwidth I/O channel of claim 8 , ...

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26-03-2020 дата публикации

TRANSMISSION CIRCUIT AND ELECTRONIC DEVICE

Номер: US20200098816A1
Автор: Matsumoto Shoji
Принадлежит:

A transmission circuit includes a first semiconductor device, a second semiconductor device, a first signal line, a second signal line, a third signal line, and a ground line. A differential signal is composed of a first signal and a second signal. The first signal line is configured to connect the first semiconductor device and the second semiconductor device and used to transmit the first signal. The second signal line is configured to connect the first semiconductor device and the second semiconductor device and used to transmit the second signal. The second signal line, the first signal line, the ground line, and the third signal line are disposed in this order. A distance between the first signal line and the ground line is larger than a distance between the first signal line and the second signal line. 1. A transmission circuit comprising:a first semiconductor device configured to receive and/or send a differential signal and a single-ended signal, the differential signal being composed of a first signal and a second signal;a second semiconductor device configured to receive and/or send the differential signal and the single-ended signal;a first signal line configured to connect the first semiconductor device and the second semiconductor device and used to transmit the first signal;a second signal line configured to connect the first semiconductor device and the second semiconductor device and used to transmit the second signal;a third signal line configured to connect the first semiconductor device and the second semiconductor device and used to transmit the single-ended signal; anda ground line,wherein the first signal line, the second signal line, the third signal line, and the ground line are disposed in order of the second signal line, the first signal line, the ground line, and the third signal line, andwherein a distance between the first signal line and the ground line is larger than a distance between the first signal line and the second signal line.2 ...

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02-06-2022 дата публикации

GLASS BASED EMPTY SUBSTRATE INTEGRATED WAVEGUIDE DEVICES

Номер: US20220173488A1
Принадлежит:

The present invention includes a method of creating high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in photodefinable glass ceramic substrate. The photodefinable glass ceramic process enables high performance, high quality, and/or low-cost structures. Compact low loss RF empty substrate integrated waveguide devices are a cornerstone technological requirement for RF systems, in particular, for portable systems. 1. A method of making an empty substrate integrated waveguide (ESIW) device including antenna and RF signal launch elements comprising the steps of:forming an ESIW pattern, an ESIW supports RF signal launch, a perimeter ground patterns and one or more edges of a waveguide on a wafer comprising lithium ions;annealing the exposed pattern in the presence of silver ions at a temperature that enables silver ions to coalesce into silver nanoparticles, and increasing the temperature to between 520° C.-620° C. to allow lithium oxide to form around the silver nanoparticles;coating a topside of the wafer with a photoresist; exposing and developing a pattern to protect the waveguide pattern while leaving the ground pattern exposed;spinning on a blanket photoresist on a backside of the wafer and etching exposed ground ceramic portions in an HF bath;removing the photoresist leaving one or more ground pattern openings and a ceramic waveguide;electroplating copper on the open ground pattern until all ground openings are filled;coating a backside of the wafer with photoresist; exposing and developing a rectangular element with one or more small etch release features;depositing 200 Å to 2,000 Å of titanium metal to form a first titanium layer, followed by a 1 μm deposition of copper onto the backside of the wafer;removing the photoresist leaving a rectangular copper element to form a bottom of the ESIW structure that is electrically connected to the ground pattern copper and waveguide launching element; ...

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02-06-2022 дата публикации

Dielectric waveguide including a dielectric material with cavities therein surrounded by a conductive coating forming a wall for the cavities

Номер: US20220173489A1
Принадлежит: Intel Corp

Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

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02-06-2022 дата публикации

SEMICONDUCTOR DEVICE WITH SUBSTRATE INTEGRATED HOLLOW WAVEGUIDE AND METHOD THEREFOR

Номер: US20220173490A1
Принадлежит:

A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device. 1. A method comprising:forming a first cavity in a first substrate, the first cavity having a first depth;forming a second cavity in a second substrate, the second cavity having a second depth;aligning the first cavity and the second cavity with each other;affixing the first substrate to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth;forming a conductive layer on the sidewalls of the hollow waveguide; andplacing the waveguide substrate over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.2. The method of claim 1 , wherein the conductive layer formed on the sidewalls of the hollow waveguide comprises a copper material.3. The method of claim 1 , further comprising placing a waveguide antenna structure over the waveguide substrate claim 1 , the hollow waveguide providing a continuous channel between the launcher of the packaged semiconductor device and the waveguide antenna structure.4. The method of claim 1 , wherein the second cavity formed in the second substrate is a mirrored copy of the first cavity formed in the first substrate.5. The method of claim 1 , ...

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02-06-2022 дата публикации

ANTENNA-ON-PACKAGE INTEGRATED CIRCUIT DEVICE

Номер: US20220173496A1
Принадлежит:

An integrated circuit package is provided. In some examples, the integrated circuit package is an antenna-on-package package that includes a plurality of dielectric layers, a plurality of conductor layers interspersed with the plurality of dielectric layers, and an integrated circuit die disposed on a first side of the plurality of dielectric layers. The plurality of conductor layers includes a first layer disposed on a second side of the plurality of dielectric layers that includes a set of antennas. In some such examples, the integrated circuit die includes radar processing circuitry, and the AOP integrated circuit package is configured for radar applications. 1. An integrated circuit package comprising:at least one dielectric layer;an integrated circuit die disposed on a first side of the at least one dielectric layer; anda plurality of conductor layers interspersed with the at least one dielectric layer,wherein the plurality of conductor layers includes a first conductor layer disposed on a second side of the at least one dielectric layer opposite the first side,wherein the first conductor layer includes at least one transmitter antenna electrically coupled to the integrated circuit die and aligned in a first direction, andwherein the first conductor layer includes at least one receiver antenna electrically coupled to the integrated circuit die and aligned in a second direction that is approximately perpendicular to the first direction.2. The integrated circuit package of claim 1 ,wherein the first direction is at a first angle of about 45° relative to side surfaces of the at least one transmitter antenna, andwherein the second direction is at a second angle of about 45° relative to side surfaces of the at least one receiver antenna.3. The integrated circuit package of claim 1 , wherein each antenna of the at least one transmitter antenna and the at least one receiver antenna comprises:a center portion;a first side portion partially separated from the center ...

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