Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer. 1. A hetero-integrated structure , comprising:a substrate;a die attached on the substrate, wherein the die has an active surface and a non-active surface, and the active surface has pads;a passivation layer covering sidewalls and a surface of the die to expose a surface of the pads;a first redistribution layer located on the passivation layer and electrically connected to the pads;a second redistribution layer located on the substrate and adjacent to the die; andconnecting portions connected to the first redistribution layer and the second redistribution layer.2. The hetero-integrated structure of claim 1 , wherein a width of the connecting portions is greater than a width of the first redistribution layer and greater than a width of the second redistribution layer.3. The hetero-integrated structure of claim 1 , further comprising an adhesive layer located between the die and the substrate.4. The hetero-integrated structure of claim 3 , wherein the non-active surface of the die is in contact with the adhesive layer.5. The hetero-integrated structure of claim 3 , wherein the sidewalls of the die are in contact with the adhesive layer.6. The hetero-integrated structure of claim 4 , wherein the active surface of the die is closer to the adhesive layer than the non-active surface thereof.7. The ...

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

HALBLEITERPAKETE UND -VERFAHREN ZUR BILDUNG DERSELBEN

Eine Ausführungsform ist eine Vorrichtung, die einen integrierten Schaltkreisdie enthält, der eine aktive Seite und eine Rückseite aufweist, wobei die Rückseite der aktiven Seite gegenüberliegt, eine Formmasse, die den integrierten Schaltkreisdie verkapselt, und eine erste Umverteilungsstruktur, die über dem integrierten Schaltkreisdie und der Formmasse liegt, wobei die erste Umverteilungsstruktur eine erste Metallisierungsstruktur und eine erste dielektrische Lage aufweist, wobei die erste Metallisierungsstruktur elektrisch mit der aktiven Seite des integrierten Schaltkreisdies gekoppelt ist, und mindestens ein Abschnitt der ersten Metallisierungsstruktur einen Induktor bildet.

Heterogeneous integrated assembly structure and manufacturing method thereof

MANUFACTURING OF FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

SEMICONDUCTOR PACKAGE

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Verfahren zur Reduzierung von thermomechanischer Belastung in Halbleitervorrichtungen und entsprechende Vorrichtung

In einer Ausführungsform weist eine Halbleitervorrichtung eine oder mehrere Metallisierungen (10), beispielsweise Cu-RDL-Metallisierungen, auf, die auf einer Passivierungsschicht (12) über einer dielektrischen Schicht (22) vorgesehen sind. Ein Durchgangsloch (16) durch die Passivierungsschicht (12) und die elektrische Schicht (22) ist in der Nachbarschaft der Ecken (10a, 10b) der Metallisierung vorgesehen. Dieses Durchgangsloch kann ein „Dummy”-Durchgangsloch ohne elektrische Verbindungen zu einer aktiven Vorrichtung sein und kann mit einem Abstand zwischen circa 1 Mikrometer (10–6 m.) und circa 10 Mikrometer (10–5 m.) von jeder der zusammenlaufenden Seiten (10b) vorgesehen sein und auf eine unterliegende Mittelschicht (24) auftreffen.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s ...

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

An electronic device 200 of flip-chip type comprises at least one chip carrier 110 having a carrier surface 135, the carrier comprising one or more contact elements 140s,140p of electrically conductive material on the carrier surface, at least one integrated circuit chip 105 having a chip surface 120, the chip comprising one or more terminals 125s,125p of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material 150 soldering each terminal to the corresponding contact element, and restrain means 210s,210p around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements 205s,205p of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. The restrain means 210s,210p may have a surface phobic to solder ...

몰딩 화합물 내에 리세스들을 가진 집적 팬아웃 패키지 구조

... 패키지는 제1 다이와 제2 다이를 포함한다. 제1 다이는 제1 기판과 이 제1 기판 위에 가로 놓이는 제1 금속 패드를 포함한다. 제2 다이는 제2 기판과 이 제2 기판 위에 가로 놓이는 제2 금속 패드를 포함한다. 몰딩 화합물은 그 안에 제1 다이 및 제2 다이를 몰딩한다. 몰딩 화합물은 제1 다이 및 제2 다이 사이의 제1 부분과, 상기 제1 부분을 둘러싸는 링을 형성할 수 있는 제2 부분을 갖는다. 제1 부분과 제2 부분은 제1 다이의 반대 측에 있다. 제1 부분은 제1 상면을 가진다. 제2 부분은 제1 상면보다 더 높은 제2 상면을 갖는다.

Temporary Post-Assisted Embedding of Semiconductor Dies

A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

Semiconductor packages and methods of forming same

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Semiconductor copper metallization structure and related methods

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

Semiconductor package

A semiconductor package includes a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 DEG C). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board or the ...

Three-dimensional integrated circuit used for the through hole of the structure and method of forming the same

本发明的实施例涉及用于三维电路集成的过孔结构及其形成方法。公开并入三维集成的电路及其制作方法。一种电路包括底层和多个上层。底层包括连接到底层中的功能部件的底部着陆焊盘。此外，在底层以上堆叠上层。每个上层包括连接到相应上层中的相应功能部件的相应上着陆焊盘。着陆焊盘由单个传导过孔耦合并且在底层和上层的堆叠中被对准，从而每个着陆焊盘从堆叠中的相邻层中的任何着陆焊盘被偏移至少一个预定数量。

Via structure for three-dimensional circuit integration

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Substrate structure

Heterogeneous integrated assembly structure and method of fabricating the same

A heterogeneous integrated assembly structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and a connection. A die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads formed thereon. A passivation layer covers the sidewalls and surfaces of the die and exposes a surface of the pad. The first redistribution layer is disposed on the passivation layer and electrically connected to the pads. The second redistribution layer is disposed on the substrate adjacent to the die. The connection portion connects the first redistribution layer and the second redistribution layer.

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Halbleiterbauelemente und Verfahren zu deren Ausbildung

Gemäß einer Ausführungsform der vorliegenden Erfindung beinhaltet ein Verfahren zum Ausbilden eines Halbleiterelements (1) ein Ausbilden einer Kontaktschicht (55) über einer ersten Hauptoberfläche (12) eines Substrats (10). Das Substrat (10) weist durch Kerf-Bereiche (121) getrennte Bauelementbereiche (23) auf. Die Kontaktschicht (55) ist in dem Kerf-Bereich (121) und den Bauelementbereichen (23) angeordnet. Eine strukturierte Lötschicht (70) ist über den Bauelementbereichen (23) ausgebildet. Die Kontaktschicht (55) liegt nach dem Ausbilden der strukturierten Lötschicht (70) in dem Kerf-Bereich (121) frei. Die Kontaktschicht (55) und das Substrat (10) in dem Kerf-Bereich (121) werden geschnitten.

Semiconductor integrated circuit device

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor. 1. A device comprising:an integrated circuit die having an active side and a back side, the back side being opposite the active side;a molding compound encapsulating the integrated circuit die; anda first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure comprising a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.2. The device of further comprising:a conductive connector over the first redistribution structure, the conductive connector being electrically coupled to the first metallization pattern; anda protection layer over the first redistribution structure and adjacent the conductive connector, the protection layer over and contacting the inductor.3. The device of claim 2 , wherein the protection layer contacts and surrounds the conductive connector.4. The device of claim 2 , wherein the protection layer extends across an entirety of the first redistribution structure.5. The device of claim 2 , wherein the protection layer has a different material composition than the first dielectric layer.6. The device of claim 1 , wherein at least a portion of the first metallization pattern of the first redistribution structure ...

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin.

Substrate structure

Provided is a substrate structure, comprising a substrate body having electrical contact points, an insulating layer formed on the substrate body while exposing the electrical contact points therefrom, and an insulating protection layer formed on partial surfaces of the insulating layer, wherein the insulating protection layer has a plurality of openings corresponding in positions with each of the electrical contact points, wherein at least one opening is posited at an outer periphery of the electrical contact point, thereby allowing the insulating protection layer to use these openings to dissipate and disperse residual stresses in manufacturing processes of high operating temperatures.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

TEMPORÄRE-SÄULEN-UNTERSTÜTZTE EINBETTUNG VON HALBLEITERCHIPS

Ein Verfahren umfasst: Bereitstellen eines Halbleiterchips mit einer ersten Hauptoberfläche, einer zweiten Hauptoberfläche gegenüber der ersten Hauptoberfläche und einem Rand zwischen der ersten Hauptoberfläche und der zweiten Hauptoberfläche; Aufbringen eines temporären Abstandshalters auf einen ersten Teil der ersten Hauptoberfläche des Halbleiterchips, wobei der erste Teil einwärts von einem peripheren Teil der ersten Hauptoberfläche positioniert ist; nach dem Aufbringen des temporären Abstandshalters, Einbetten des Halbleiterchips zumindest teilweise in ein Einbettungsmaterial, wobei das Einbettungsmaterial den Rand und den peripheren Teil der ersten Hauptoberfläche des Halbleiterchips bedeckt und eine Seitenwand des temporären Abstandshalters kontaktiert; und nach dem Einbetten, Entfernen des temporären Abstandshalters von der ersten Hauptoberfläche des Halbleiterchips, um den ersten Teil der ersten Hauptoberfläche des Halbleiterchips freizulegen. Eine durch das Verfahren hergestellte Halbleitervorrichtung wird ebenfalls bereitgestellt.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

Semiconductor Package

A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening. 1. A semiconductor package , comprising:a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, and including a passivation film disposed on the active surface and having a first opening exposing at least a portion of the connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening;an encapsulant covering at least a portion of the semiconductor chip; anda connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via,wherein the second opening has a width narrower than a width of the first opening.2. The semiconductor package of claim 1 , wherein a region claim 1 , excluding a region exposed by the second opening claim 1 , of a region exposed by the first opening of ...

Methods of forming semiconductor packages having a die with an encapsulant

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

Method for preparing a semiconductor device with spacer over sidewall of bonding pad

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board ...

Halbleiterbauelemente und Verfahren zu deren Ausbildung

Verfahren zum Ausbilden eines Halbleiterbauelements (1), wobei das Verfahren aufweist:Ausbilden einer Kontaktschicht (55), die eine oder mehrere Metallschichten aufweist, über einer ersten Hauptoberfläche (12) eines Substrats (10), wobei das Substrat (10) durch Schneidbereiche (121), in denen freiliegende Oberflächen ausgebildet sind, getrennte Bauelementbereiche (23) aufweist, wobei die Kontaktschicht (55) in dem Schneidbereich (121) und den Bauelementbereichen (23) angeordnet ist;Ausbilden einer strukturierten Lötschicht (70) über den Bauelementbereichen (23), wobei die Kontaktschicht (55) nach dem Ausbilden der strukturierten Lötschicht (70) in dem Schneidbereich (121) frei liegt, wobei die strukturierte Lötschicht (70) dicker ist als das Substrat (10); undSchneiden durch die Kontaktschicht (55) und das Substrat (10) in den Schneidbereichen (121). A method for forming a semiconductor component (1), the method comprising: forming a contact layer (55), which has one or more metal layers, over a first main surface (12) of a substrate (10), the substrate (10) being formed by cutting regions ( 121), in which exposed surfaces are formed, has separate component areas (23), the contact layer (55) being arranged in the cutting area (121) and the component areas (23); forming a structured soldering layer (70) over the component areas (23) ), wherein the contact layer (55) is exposed after the formation of the structured soldering layer (70) in the cutting area (121), the structured soldering layer (70) being thicker than the substrate (10); and cutting through the contact layer (55) and the substrate (10) in the cutting areas (121).

Semiconductor device having conductive film

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

METHOD FOR PREPARING A SEMICONDUCTOR DEVICE WITH SPACER OVER SIDEWALL OF BONDING PAD

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

METHOD FOR THERMO-MECHANICAL STRESS REDUCTION IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10m.) and approximately 10 micron (10m.) from each one of said converging sides landing on an underlying metal layer. 1. A method , comprising:manufacturing a semiconductor device, the manufacturing including:providing a passivation layer over a dielectric layer;providing a metallization on the passivation layer, the metallization having a corner; andproviding a via through said passivation layer and said dielectric layer near said corner.2. The method of claim 1 , wherein providing said via includes providing the via without electrical connections to an active device.3. The method of claim 1 , wherein:said corner includes converging sides; andproviding said via includes providing said via at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.4. The method of claim 1 , wherein providing said metallization as a Cu metallization.5. The method of claim 1 , wherein providing said via includes providing the via as a via landing on an underlying metal layer.6. The method of claim 1 , further comprising forming a barrier layer lining the via and underlying the metallization.7. A semiconductor device claim 1 , comprising:a dielectric layer;a passivation layer over the dielectric layer;a metallization having a corner; anda via through said passivation layer and said dielectric layer near said corner.8. The semiconductor device of claim 7 , wherein said via is without electrical connections to an active device.9. The semiconductor device of claim 7 , wherein said corner includes ...

SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

Semiconductor device

本公开的实施例涉及一种半导体器件。该半导体器件包括一个或多个金属化层，诸如例如Cu‑RDL金属化层，设置在电介质层之上的钝化层上。在金属化层的角部附近穿过钝化层和电介质层提供过孔。过孔可以是不具有去往有源器件的电连接的“虚设”过孔，并且可以设置在距位于下方金属层上的所述汇聚侧边的每一个近似1微米(10 ‑6 m)和近似10微米(10 ‑5 m)之间的距离处。

Substrate structure

Semiconductor copper metallization structure and related methods

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;a first copper layer coupled directly over and to the pad;a second copper layer coupled over the first copper layer; anda metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers claim 1 , the metal coating applied through one of electroless plating or electrolytic plating.4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel claim 3 , palladium claim 3 , and gold (Ni/Pd/Au); ...

Chip package and method for forming the same

A chip package including a substrate is provided. The substrate includes a front surface, a back surface, and a side surface. A redistribution layer is on the back surface and is electrically connected to a sensing region or device region in the substrate. A protection layer covers the redistribution layer and extends onto the side surface. A cover plate is on the front surface and laterally protrudes from the protection layer on the side surface. The cover plate includes a first surface facing the front surface and a second surface facing away from the front surface. A bottom portion of the cover plate broadens from the first surface towards the second surface. A method of forming the chip package is also provided.

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410s1,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s ...

Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

A chip package including a substrate is provided. The substrate includes a front surface, a back surface, and a side surface. A redistribution layer is disposed on the back surface and is electrically connected to a sensing or device region in the substrate. A protection layer covers the redistribution layer and extends onto the side surface. A cover plate is disposed on the front surface and laterally protrudes from the protection layer on the side surface. The cover plate includes a first surface facing the front surface and a second surface facing away from the front surface. A bottom portion of the cover plate broadens from the first surface towards the second surface. A method of forming the chip package is also provided.

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin.

Semiconductor component and manufacturing method thereof

本發明提供了一種半導體元件及其製造方法。半導體元件包括基板和焊盤。焊盤位於基板上並且具有上表面和狹槽，其中，狹槽相對于上表面向內凹進。本發明中在焊盤上包括狹槽，可以使得在焊接過程中容納焊盤部分的變形和/或減小或釋放焊盤的應力，可以縮小相鄰兩個焊盤之間的間距。

VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

Semiconductor device

分散接合有导线的导电膜的应力，而防止导电膜剥离。提供一种半导体装置，该半导体装置具备：半导体基板；第一导电膜，在半导体基板的上方，以隔着未设置有第一导电膜的非形成区的方式至少设置于非形成区的两侧；层间绝缘膜，包括设置于非形成区的第一部分、在隔着非形成区的两侧设置于第一导电膜的上方的第二部分、以及将第一部分与第二部分连结的阶梯部；第二导电膜，设置于层间绝缘膜的上方；多个贯通端子部，贯通层间绝缘膜的第二部分而将第一导电膜与第二导电膜电连结；以及导线，在层间绝缘膜的第一部分的上方，与第二导电膜接合，多个贯通端子部至少包括一个以上的第一贯通端子部和一个以上的第二贯通端子部，一个以上的第一贯通端子部与一个以上的第二贯通端子部设置于隔着导线的接合部而彼此对置的位置。

Semiconductor devices with solder-based connection terminals and method of forming the same

An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

Semiconductor devices and methods of forming thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Semiconductor copper metallization structure and related methods

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

Semiconductor packages having a die, an encapsulant, and a redistribution structure

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board or the like (wiring substrate).

SUBSTRATE STRUCTURE

Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures. 1: A substrate structure , comprising:a substrate body having at least one conductive contact;an insulating layer formed on the substrate body with the at least one conductive contact exposed from the insulating layer; andan insulating protection layer formed only on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the at least one conductive contact, wherein at least one of the openings is disposed at an outer periphery of the at least one conductive contact.2: The substrate structure of claim 1 , wherein the at least one conductive contact is a conductive pillar or a conductive pad.3: The substrate structure of claim 1 , further comprising a circuit layer formed on the substrate body.4: The substrate structure of claim 3 , wherein the insulating layer is formed on the circuit layer.5: The substrate structure of claim 3 , wherein the conductive contact forms a portion of the circuit layer.6: The substrate structure of claim 1 , wherein at least one of the openings has a top view in a shape of a closed curve or a polygon.7: The substrate structure of claim 1 , further comprising a metal layer formed in at least one of the openings.8: The substrate structure of claim 7 , wherein the metal layer is in contact with the conductive contact.9: The substrate structure of claim 1 , further comprising a conductive ...

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

Semiconductor device and electronic device

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

半導体装置の作製方法

Manufacturing of flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

SEMICONDUCTOR DEVICE WITH SPACER OVER SIDEWALL OF BONDING PAD AND METHOD FOR PREPARING THE SAME

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

Semiconductor package

A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

INTEGRATED CIRCUIT PACKAGE

An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces. 1. An integrated circuit (IC) package comprising:an IC die having a first side and a second side opposite the first side;a bump pad on the first side;a first substrate having a first side with a plurality of electrical contact surfaces;a plurality of metal pillars, each having a first end attached to the bump pad via a passivation layer, and a second end attached to one of a plurality of electrical contact surfaces of a first substrate;an intermetallic compound surrounding portions of the plurality of metal pillars; anda mold compound encapsulating the intermetallic compound.2. The IC package of claim 1 , wherein the plurality of metal pillars include copper.3. The IC package of claim 1 , wherein the intermetallic compound comprises a copper and lead compound.4. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.5. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.6. The IC package of further comprising a second substrate attached to the second side of the IC die.7. The IC package of claim 6 , wherein the mold compound encapsulates at least a portion of the IC die claim 6 , and the first and second substrates.8. The IC package of claim 6 , wherein said first substrate comprises a first leadframe and wherein said second substrate comprises a second leadframe.9. The IC package of claim 1 , wherein the intermetallic compound has higher melting temperatures than solder and lower coefficients of expansion than solder.10. An integrated circuit (“IC”) package comprising:an IC die ...

Semiconductor devices and methods of forming thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Semiconductor package

Heterogeneous integrated assembly structure and mehod of fabricating the same

Semiconductor packages and methods of forming same

Molding material has a groove integrated fan-out packaging structure

模塑料中具有凹槽的集成扇出封装结构。一种封装件包括第一管芯和第二管芯。第一管芯包括第一衬底和第一衬底上方的第一金属焊盘。第二管芯包括第二衬底和第二衬底上方的第二金属焊盘。在模塑料中模制第一管芯和第二管芯。模塑料具有介于第一管芯和第二管芯之间的第一部分、以及可形成围绕第一部分的环的第二部分。第一部分和第二部分位于第一管芯的相对侧。第一部分具有第一顶面。第二部分具有高于第一顶面的第二顶面。

SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR DIE EMBEDDED IN A MOLDING COMPOUND

A semiconductor device includes: a first semiconductor die having opposing first and second main surfaces and an edge between the first and second main surfaces; a molding compound covering the edge and a peripheral part of the first main surface of the first semiconductor die, the molding compound including a resin and filler particles embedded within the resin; and a first opening in the molding compound which exposes a first part of the first main surface of the first semiconductor die from the molding compound, the first part being positioned inward from the peripheral part, wherein the first opening in the molding compound has a sidewall, wherein predominantly all of the filler particles disposed along the sidewall of the first opening are fully embedded within the resin and not exposed at all along the sidewall. A semiconductor structure including a semiconductor wafer or panel is also described.

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Chip package and method for forming the same

Semiconductor copper metallization structure

本发明涉及半导体铜金属化结构。半导体封装的实现方式可以包括：包括焊盘的硅管芯，焊盘包括铝和铜；硅管芯的至少一部分上的钝化层，以及耦合到钝化层的聚酰亚胺(PI)、聚苯并恶唑(PBO)或者聚合树脂中的一种的层。封装可以包括耦合在焊盘上的第一铜层，第一铜层为1微米至20微米厚；耦合在第一铜层上的第二铜层，第二铜层可以为5微米至40微米厚；其中焊盘上第一铜层的宽度可以比焊盘上第二铜层的宽度宽。第一铜层和第二铜层可以被配置为与粗铜丝线键合或者与铜夹焊料接合。

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin.

Temporary post-assisted embedding of semiconductor dies

A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

Methods of Forming Semiconductor Packages Having a Die with an Encapsulant

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Hetero-integrated structure

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Method for thermo-mechanical stress reduction in semiconductor devices and corresponding device

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10 −6 m.) and approximately 10 micron (10 −5 m.) from each one of said converging sides landing on an underlying metal layer.

METHOD FOR THERMO-MECHANICAL STRESS REDUCTION IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

在一个实施例中，一种半导体器件包括一个或多个金属化层，诸如例如Cu‑RDL金属化层，设置在电介质层之上的钝化层上。在金属化层的角部附近穿过钝化层和电介质层提供过孔。过孔可以是不具有去往有源器件的电连接的“虚设”过孔，并且可以设置在距位于下方金属层上的所述汇聚侧边的每一个近似1微米(10 ‑6 m)和近似10微米(10 ‑5 m)之间的距离处。

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

PROBLEM TO BE SOLVED: To provide a means for thinning a highly integrated semiconductor integrated circuit. SOLUTION: The semiconductor device and the method for producing the same include the steps of: forming a first semiconductor element layer 51 connecting to a first bump and a first through electrode 104 on a substrate 11; forming a second semiconductor element layer 59 connecting to a second bump and a second structure 120 having a second sheet-like fiber body and a second organic resin; forming a third through electrode 201 penetrating a third structure by disposing a conductive resin having metal particles on a uncured third organic resin 114 of a third structure 121 having a third sheet-like fiber body and a third organic resin, wherein the uncured third organic resin is molten and metal particles move between the third fiber sheet; disposing the first through electrode, the third through electrode and the second bump on the substrate in an overlapped manner; and curing the third ...

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. 1. A circuit incorporating three-dimensional integration (3Di) comprising:a bottom layer including a bottom landing pad connected to functional components in the bottom layer; anda plurality of upper layers, stacked above the bottom layer, wherein each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer,wherein the upper and bottom landing pads are coupled by a single conductive via and wherein the upper and bottom landing pads are aligned in a stack of the bottom layer and the upper layers such that each of the upper and bottom landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.2. The circuit of claim 1 , wherein the landing pads are aligned such that the landing pads are successively offset in one direction.3. The circuit of claim 1 , wherein the landing pads are aligned in a spiral configuration.4. The circuit of claim 1 , wherein at least one of the upper and bottom landing pads includes a conductive liner.5. The circuit of claim 1 , wherein cross-sectional areas of the landing pads that are in contact with the via are equal.6. The circuit of claim 1 , ...

SEMICONDUCTOR DEVICES WITH SOLDER-BASED CONNECTION TERMINALS AND METHOD OF FORMING THE SAME

An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section. 1. An electronic device , comprising:a substrate having an electrically conductive contact pad thereon; andan electrically conductive connection terminal on the contact pad, said connection terminal comprising an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure, said pillar structure comprising a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer.2. The device of claim 1 , wherein the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer.3. The device of claim 1 , wherein a width of the diffusion barrier layer is greater than a width of the upper pillar layer when viewed in transverse cross-section.4. The device of claim 3 , wherein an upper surface of the diffusion barrier layer directly contacts a bottom surface of the upper pillar layer.5. The device of claim 3 , wherein the width of the ...

Semiconductor device

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Semiconductor device

The purpose of the present invention is to disperse stress in an electroconductive film to which a wire is bonded and to prevent the electroconductive film from separating. Provided is a semiconductor device equipped with: a semiconductor substrate; a first electroconductive film provided above the semiconductor substrate so as to flank a non-formation region in which the first electroconductive film is not provided, the first electroconductive film being provided at least on both sides of the non-formation region; an interlayer insulation film including a first portion provided in the non-formation region, a second portion provided above the first electroconductive film on two sides flanking the non-formation region, and a step part linking the first portion and the second portion; a second electroconductive film provided above the interlayer insulation film; a plurality of penetrating terminal parts, which penetrate the second portion of the interlayer insulation film and electrically connect the first electroconductive film and the second electroconductive film to each other; and a wire bonded to the second electroconductive film above the first portion of the interlayer insulation film. The plurality of penetrating terminal parts include at least one or more first penetrating terminal parts and one or more second penetrating terminal parts provided at positions that face each other across the part at which the wire is bonded.

Semiconductor package

본 개시는 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 가지며, 상기 활성면 상에 배치되며 상기 접속패드의 적어도 일부를 오픈시키는 제1개구부를 갖는 패시베이션막 및 상기 패시베이션막 상에 배치되어 상기 제1개구부 내의 적어도 일부를 채우며 상기 제1개구부 내에서 상기 접속패드의 적어도 일부를 오픈시키는 제2개구부를 갖는 보호막을 포함하는 반도체칩; 상기 반도체칩의 적어도 일부를 덮는 봉합재; 및 상기 반도체칩의 활성면 상에 배치되며, 상기 제1 및 제2개구부 내에서 상기 접속패드와 연결된 접속비아 및 상기 접속비아를 통하여 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결구조체; 를 포함하며, 상기 제2개구부는 상기 제1개구부 보다 폭이 좁은, 반도체 패키지에 관한 것이다. The present disclosure discloses a passivation film having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, and having a first opening disposed on the active surface and opening at least a portion of the connection pad, and on the passivation film a semiconductor chip including a protective film disposed on the first opening and having a second opening that fills at least a portion of the first opening and opens at least a portion of the connection pad within the first opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on an active surface of the semiconductor chip and including a connection via connected to the connection pad within the first and second openings and a redistribution layer electrically connected to the connection pad through the connection via; It relates to a semiconductor package, wherein the second opening has a narrower width than the first opening.

Heterogeneous integrated assembly structure and manufacturing method thereof

本发明公开一种异质整合组装结构及其制造方法，其中该异质整合组装结构包括基底、管芯、钝化层、第一重布线层、第二重布线层以及连接部。管芯安装于所述基底上。管芯具有有源面与无源面。有源面具有接垫。钝化层覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面。第一重布线层位于钝化层上，电连接接垫。第二重布线层位于基底上，与管芯相邻。连接部连接第一重布线层与第二重布线层。

Flip-chip type electronic device and method for manufacturing flip-chip type electronic device

Semiconductor device and method of manufacturing the same

반도체 장치는, 기판 상에 배치되는 도전 패드 및 상기 도전 패드에 전기적으로 연결되는 연결 단자(connection terminal)를 포함하며, 상기 연결 단자는, 순차적으로 적층된 하부 필라층, 확산 방지층 및 상부 필라층을 포함하며, 측벽에 돌출부를 구비하는 도전성 필라 구조물(conductive pillar structure), 및 상기 상부 필라층 상에 배치되며, 상기 돌출부의 적어도 일부분과 접촉하는 솔더층(solder layer)을 구비한다. The semiconductor device includes a conductive pad disposed on a substrate and a connection terminal electrically connected to the conductive pad, wherein the connection terminal includes a lower pillar layer, a diffusion barrier layer, and an upper pillar layer sequentially stacked. a conductive pillar structure having a protrusion on a sidewall thereof, and a solder layer disposed on the upper pillar layer and in contact with at least a portion of the protrusion.

半导体组件及其制造方法

本发明提供了一种半导体组件及其制造方法。半导体组件包括基板和焊盘。焊盘位于基板上并且具有上表面和狭槽，其中，狭槽相对于上表面向内凹进。本发明中在焊盘上包括狭槽，可以使得在焊接过程中容纳焊盘部分的变形和/或减小或释放焊盘的应力，可以缩小相邻两个焊盘之间的间距。

半導體封裝

一種半導體封裝包括：半導體晶片，包括鈍化膜以及保 護膜，所述鈍化膜配置於主動面上且具有暴露出半導體晶片的連接墊的至少一部分的第一開口，所述保護膜配置於鈍化膜上、填充第一開口中的至少一部分、且具有暴露出第一開口中的連接墊的至少一部分的第二開口；包封體，覆蓋半導體晶片的至少一部分；以及連接結構，配置於所述半導體晶片的所述主動面上，且包括連接至所述第一開口及所述第二開口中的所述連接墊的連接通孔以及經由所述連接通孔電性連接至所述連接墊的重佈線層。所述第二開口具有較所述第一開口的寬度窄的寬度。

焊盘结构及其形成方法、半导体器件及其形成方法

本发明涉及半导体制造技术领域，尤其涉及一种焊盘结构及其形成方法、半导体器件及其形成方法。所述焊盘结构包括：焊盘本体，包括相对分布的上表面和下表面，所述下表面用于与芯片的内部电路电连接；沟槽，自所述上表面向所述焊盘本体的内部延伸，将所述焊盘本体分隔为测试区域和焊接区域；保护层，至少覆盖于所述沟槽的底壁。本发明分隔了测试区域与焊接区域，避免了因探针测试而导致的封装连线易失败的问题，同时避免了外界环境对所述测试区域与所述焊接区域之间的芯片的损伤，提高了半导体器件的良率和性能稳定性。

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

반도체 장치 및 이의 제조 방법

반도체 장치는, 기판 상에 배치되는 도전 패드 및 상기 도전 패드에 전기적으로 연결되는 연결 단자(connection terminal)를 포함하며, 상기 연결 단자는, 순차적으로 적층된 하부 필라층, 확산 방지층 및 상부 필라층을 포함하며, 측벽에 돌출부를 구비하는 도전성 필라 구조물(conductive pillar structure), 및 상기 상부 필라층 상에 배치되며, 상기 돌출부의 적어도 일부분과 접촉하는 솔더층(solder layer)을 구비한다.

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

半导体裸片的临时后辅助嵌入

一种方法，其包括：提供具有第一主表面、与第一主表面相反的第二主表面和第一主表面与第二主表面之间的边缘的半导体裸片；将临时间隔件施加到所述半导体裸片的第一主表面的第一部分，所述第一部分相对于所述第一主表面的外周部分向内定位；在施加所述临时间隔件之后，将所述半导体裸片至少部分地嵌入到嵌入材料中，所述嵌入材料覆盖所述边缘和所述半导体裸片的第一主表面的外周部分，并接触所述临时间隔件的侧壁；以及在所述嵌入之后，将所述临时间隔件从所述半导体裸片的第一主表面移除，以暴露所述半导体裸片的第一主表面的第一部分。还提供了通过所述方法生产的半导体装置。

반도체 장치 및 그의 제조 방법

기판 상의 패드, 상기 기판 상에서 상기 패드를 덮는 보호막, 상기 보호막은 상기 패드의 상부면의 일부를 노출시키는 오프닝을 갖고, 및 상기 패드에 전기적으로 연결되는 범프 구조체를 포함하는 반도체 장치를 제공하되, 상기 범프 구조체는 상기 패드 상의 금속 층, 및 상기 금속 층 상의 솔더 볼을 포함하고, 상기 금속 층의 제 1 폭은 상기 오프닝의 제 2 폭의 0.85배 내지 0.95배일 수 있다.

Semiconductor component and manufacturing method thereof

A semiconductor component is provided. The semiconductor component includes a substrate (110) and a pad (120). The pad (120) has an upper surface and a slot (120r), wherein the slot (120r) is recessed with respect to the upper surface of the pad (120). The slot (120r) can receive deformed pad material resulting from the wire connecting process. The slot (120r) can thereby prevent the pad (120) from cracking or touching adjacent pads due to over-deformation or cause damage to the passivation layer (130).

半導体装置の作製方法

【課題】高集積化された半導体集積回路の厚さを薄くすることができる。 【解決手段】基板上に、第１のバンプと接続する第１の半導体素子層と、第１のシート状繊維体と第１の有機樹脂を有する第１の構造体と、第１の構造体を貫通する第１の貫通電極を作製し、第２のバンプに接続する第２の半導体素子層と、第２のシート状繊維体と第２の有機樹脂を有する第２の構造体を作製し、第３のシート状繊維体と第３の有機樹脂を有する第３の構造体の、未硬化の第３の有機樹脂上に金属粒子を有する導電性樹脂を配置することより未硬化の第３の有機樹脂が溶解し、金属粒子が第３のシート状繊維体の間を移動し、第３の構造体を貫通する第３の貫通電極が形成され、基板上で第１の貫通電極、第３の貫通電極、第２のバンプが重なり合うように配置し、第３の有機樹脂を硬化させる半導体装置及びその作製方法に関する。 【選択図】図９

Vorrichtung umfassend einen Induktor und Verfahren zur Bildung derselben

Vorrichtung, umfassend:einen integrierten Schaltkreisdie (114), der eine aktive Seite und eine Rückseite aufweist, wobei die Rückseite der aktiven Seite gegenüber liegt;eine Formmasse (130), die den integrierten Schaltkreisdie (114) verkapselt; undeine erste Umverteilungsstruktur (132) über dem integrierten Schaltkreisdie (114) und der Formmasse (130), wobei die erste Umverteilungsstruktur (132) eine erste Metallisierungsstruktur (138) und eine erste dielektrische Lage (136) umfasst, wobei die erste Metallisierungsstruktur (138) elektrisch mit der aktiven Seite des integrierten Schaltkreisdies (114) gekoppelt ist, und mindestens ein Abschnitt der ersten Metallisierungsstruktur (138) einen Induktor (150) bildet;eine erste Öffnung, (158), die sich durch die erste dielektrische Lage (136) erstreckt, wobei die erste Öffnung (158) an den Induktor (150) in der ersten Umverteilungsstruktur (132) angrenzt.

具有不含焊接掩模的热消散元件的载体的倒装芯片电子装置

提出了一种涉及倒装芯片类型的电子装置的技术方案。特别是，一种倒装芯片类型的电子装置(200,300；400；700；800)，包括：具有载体表面(135；835)的至少一个芯片载体(110；805)，该载体包括在该载体表面上的导电材料的一个或多个接触元件(140s,140p；740s,740p；840s,840p)，具有芯片表面(120；720)的至少一个集成电路芯片(105；705)，该芯片包括在该芯片表面上的导电材料的一个或多个端子(125s,125p；725s,725p)，每个芯片端子面对对应的接触元件，将每个端子焊接到该对应的接触元件的焊料材料(150；750)，以及围绕该接触元件的限制装置(210s,210p,310；410sl,410sd,410p；790s,790p；890s,890p)，用于在将该端子焊接到该接触元件期间限制该焊料材料，其中，该载体包括在该载体表面上的导热材料的一个或多个热消散元件(205s,205p；785s,785p；885s,885p)，一个或多个热消散元件从该端子移位，该载体表面面对该芯片表面，该消散元件不含任何焊接掩模。

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s,885p) of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

フリップチップ・タイプの電子デバイス、およびフリップチップ・タイプの電子デバイスを製造するための方法

【課題】フリップチップ・タイプの電子デバイスに関する解決策を提供する。【解決手段】詳細には、フリップチップ・タイプの電子デバイス（２００、３００、４００、７００、８００）が、キャリア面（１３５、８３５）を有する少なくとも１つのチップ・キャリア（１１０、８０５）であって、キャリア面上に導電性材料の１つまたは複数の接点要素（１４０ｓ、１４０ｐ、７４０ｓ、７４０ｐ、８４０ｓ、８４０ｐ）を備えるチップ・キャリア（１１０、８０５）と、チップ面（１２０、７２０）を有する少なくとも１つの集積回路チップ（１０５、７０５）であって、対応する接点要素に各々が向く、チップ面上の導電性材料の１つまたは複数の端子（１２５ｓ、１２５ｐ、７２５ｓ、７２５ｐ）を備える集積回路チップ（１０５、７０５）と、各端子を対応する接点要素にはんだ付けするはんだ材料（１５０、７５０）と、接点要素への端子のはんだ付けの期間にはんだ材料を制限するための接点要素の周りの制限手段（２１０ｓ、２１０ｐ、３１０、４１０ｓｌ、４１０ｓｄ、４１０ｐ、７９０ｓ、７９０ｐ、８９０ｓ、８９０ｐ）とを備え、キャリアが、端子からずれたチップ面に向くキャリア面上の熱的に伝導性の材料の１つまたは複数の熱放散要素（２０５ｓ、２０５ｐ、７８５ｓ、７８５ｐ、８８５ｓ、８８５ｐ）を備え、放散要素には何らはんだマスクがない。【選択図】図２

半导体铜金属化结构

本发明涉及半导体铜金属化结构。半导体封装的实现方式可以包括：包括焊盘的硅管芯，焊盘包括铝和铜；硅管芯的至少一部分上的钝化层，以及耦合到钝化层的聚酰亚胺(PI)、聚苯并恶唑(PBO)或者聚合树脂中的一种的层。封装可以包括耦合在焊盘上的第一铜层，第一铜层为1微米至20微米厚；耦合在第一铜层上的第二铜层，第二铜层可以为5微米至40微米厚；其中焊盘上第一铜层的宽度可以比焊盘上第二铜层的宽度宽。第一铜层和第二铜层可以被配置为与粗铜丝线键合或者与铜夹焊料接合。

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

用于减小半导体器件中的热机械应力的方法以及对应器件

在一个实施例中，一种半导体器件包括一个或多个金属化层，诸如例如Cu‑RDL金属化层，设置在电介质层之上的钝化层上。在金属化层的角部附近穿过钝化层和电介质层提供过孔。过孔可以是不具有去往有源器件的电连接的“虚设”过孔，并且可以设置在距位于下方金属层上的所述汇聚侧边的每一个近似1微米(10 ‑6 m)和近似10微米(10 ‑5 m)之间的距离处。

半导体封装件

本发明提供一种半导体封装件，所述半导体封装件包括：半导体芯片，并且包括设置在有效表面上并且具有使所述半导体芯片的连接焊盘的至少一部分暴露的第一开口的钝化膜以及设置在所述钝化膜上的保护膜，所述保护膜填充所述第一开口的至少一部分，并且具有使所述连接焊盘的位于所述第一开口中的至少一部分暴露的第二开口；包封剂，覆盖所述半导体芯片的至少一部分；以及连接结构，设置在所述半导体芯片的所述有效表面上，并包括连接到位于所述第一开口中且位于所述第二开口中的所述连接焊盘的连接过孔，以及通过所述连接过孔电连接到所述连接焊盘的重新分布层。所述第二开口的宽度窄于所述第一开口的宽度。

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

焊盘结构及其形成方法、半导体器件及其形成方法

本发明涉及半导体制造技术领域，尤其涉及一种焊盘结构及其形成方法、半导体器件及其形成方法。所述焊盘结构包括：焊盘本体，包括相对分布的上表面和下表面，所述下表面用于与芯片的内部电路电连接；沟槽，自所述上表面向所述焊盘本体的内部延伸，将所述焊盘本体分隔为测试区域和焊接区域；保护层，至少覆盖于所述沟槽的底壁。本发明分隔了测试区域与焊接区域，避免了因探针测试而导致的封装连线易失败的问题，同时避免了外界环境对所述测试区域与所述焊接区域之间的芯片的损伤，提高了半导体器件的良率和性能稳定性。

半导体裸片的临时后辅助嵌入

一种方法，其包括：提供具有第一主表面、与第一主表面相反的第二主表面和第一主表面与第二主表面之间的边缘的半导体裸片；将临时间隔件施加到所述半导体裸片的第一主表面的第一部分，所述第一部分相对于所述第一主表面的外周部分向内定位；在施加所述临时间隔件之后，将所述半导体裸片至少部分地嵌入到嵌入材料中，所述嵌入材料覆盖所述边缘和所述半导体裸片的第一主表面的外周部分，并接触所述临时间隔件的侧壁；以及在所述嵌入之后，将所述临时间隔件从所述半导体裸片的第一主表面移除，以暴露所述半导体裸片的第一主表面的第一部分。还提供了通过所述方法生产的半导体装置。

半导体组件及其制造方法

本发明提供了一种半导体组件及其制造方法。半导体组件包括基板和焊盘。焊盘位于基板上并且具有上表面和狭槽，其中，狭槽相对于上表面向内凹进。本发明中在焊盘上包括狭槽，可以使得在焊接过程中容纳焊盘部分的变形和/或减小或释放焊盘的应力，可以缩小相邻两个焊盘之间的间距。

半导体封装件

本发明提供一种半导体封装件，所述半导体封装件包括：半导体芯片，并且包括设置在有效表面上并且具有使所述半导体芯片的连接焊盘的至少一部分暴露的第一开口的钝化膜以及设置在所述钝化膜上的保护膜，所述保护膜填充所述第一开口的至少一部分，并且具有使所述连接焊盘的位于所述第一开口中的至少一部分暴露的第二开口；包封剂，覆盖所述半导体芯片的至少一部分；以及连接结构，设置在所述半导体芯片的所述有效表面上，并包括连接到位于所述第一开口中且位于所述第二开口中的所述连接焊盘的连接过孔，以及通过所述连接过孔电连接到所述连接焊盘的重新分布层。所述第二开口的宽度窄于所述第一开口的宽度。

异质整合组装结构及其制造方法

本发明公开一种异质整合组装结构及其制造方法，其中该异质整合组装结构包括基底、管芯、钝化层、第一重布线层、第二重布线层以及连接部。管芯安装于所述基底上。管芯具有有源面与无源面。有源面具有接垫。钝化层覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面。第一重布线层位于钝化层上，电连接接垫。第二重布线层位于基底上，与管芯相邻。连接部连接第一重布线层与第二重布线层。

Semiconductor device having a wire bonding pad structure connected through vias to lower wiring

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

半导体封装件及其形成方法

本发明的实施例是半导体器件及其形成方法，半导体器件包括具有有源侧和背侧的集成电路管芯，背侧与有源侧相对；密封集成电路管芯的模塑料以及位于集成电路管芯和模塑料上面的第一再分布结构，第一再分布结构包括第一金属化图案和第一介电层，第一金属化图案电连接至集成电路管芯的有源侧，第一金属化图案的至少部分形成电感器。

半导体装置

分散接合有导线的导电膜的应力，而防止导电膜剥离。提供一种半导体装置，该半导体装置具备：半导体基板；第一导电膜，在半导体基板的上方，以隔着未设置有第一导电膜的非形成区的方式至少设置于非形成区的两侧；层间绝缘膜，包括设置于非形成区的第一部分、在隔着非形成区的两侧设置于第一导电膜的上方的第二部分、以及将第一部分与第二部分连结的阶梯部；第二导电膜，设置于层间绝缘膜的上方；多个贯通端子部，贯通层间绝缘膜的第二部分而将第一导电膜与第二导电膜电连结；以及导线，在层间绝缘膜的第一部分的上方，与第二导电膜接合，多个贯通端子部至少包括一个以上的第一贯通端子部和一个以上的第二贯通端子部，一个以上的第一贯通端子部与一个以上的第二贯通端子部设置于隔着导线的接合部而彼此对置的位置。

半导体组件及其制造方法

本发明提供了一种半导体组件及其制造方法。半导体组件包括基板和焊盘。焊盘位于基板上并且具有上表面和狭槽，其中，狭槽相对于上表面向内凹进。本发明中在焊盘上包括狭槽，可以使得在焊接过程中容纳焊盘部分的变形和/或减小或释放焊盘的应力，可以缩小相邻两个焊盘之间的间距。