In-street integrated circuit wafer via

Method of and apparatus for sealing a hermetic lid to a semicond uctor die

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to each other. The package structure is over the first surface, and includes a die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the exposed first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant encapsulates the package structure, and exposes at least part of the second conductive terminals ...

Method for establishing and closing a trench of a semiconductor component

A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor device and production thereof, with which a package can be miniaturized and handling or performance test and the like can be simplified by using no rewiring board while attaining cost reduction. SOLUTION: For the production of this semiconductor device, the semiconductor device provided with a semiconductor chip 11 to connect electrodes corresponding to the plural electrodes of a wiring board to the respective electrodes is produced. In this production, plural metal bumps 12 corresponding to the electrode patterns of the semiconductor chip 11 are formed at least on one of the semiconductor chip 11 and a temporary board 13 having a size corresponding to this semiconductor chip 11, the semiconductor chip 11 and the temporary board 13 are mutually fixed via the metal bumps 12, a protective layer 14 is formed by filling the gaps between the semiconductor chip 11 and the temporary board 13 and mutually between the metal bumps 12 with underfill ...

Halbleiterstruktur mit nachgiebigem Zwischenverbindungselement und Verfahren zu deren Herstellung

Halbleiterstruktur, die umfaßt: ein Halbleitersubstrat; ein erstes leitendes Pad auf dem Substrat; ein nachgiebiges Zwischenverbindungselement, das eine nachgiebige dielektrische Schicht umfasst; eine auf dem nachgiebigen Zwischenverbindungselement in Kontakt mit dem ersten leitenden Pad angeordnete leitende Schicht; wobei das nachgiebige Zwischenverbindungselement auf einer ersten Oberfläche des Substrats derart angeordnet ist, daß eine dielektrische Oberfläche der nachgiebigen Schicht eine Substratoberfläche des Halbleitersubstrats kontaktiert; wobei das nachgiebige Zwischenverbindungselement eine Kammer zwischen der ersten Oberfläche des Substrats und einer Oberfläche des Zwischenverbindungselements definiert. Semiconductor structure comprising: a semiconductor substrate; a first conductive pad on the substrate; a compliant interconnect element comprising a compliant dielectric layer; a conductive layer disposed on the compliant interconnect member in contact with the first conductive pad; wherein the compliant interconnect element is disposed on a first surface of the substrate such that a dielectric surface of the compliant layer contacts a substrate surface of the semiconductor substrate; wherein the compliant interconnect member defines a chamber between the first surface of the substrate and a surface of the interconnect member.

Method of making a structure with improved material properties by moderate heat treatment of a metal deposit

MODULATE POWER FOR MOTOR VEHICLE

L'invention concerne un module de puissance (10), de préférence pour un véhicule, notamment électrique, caractérisé en ce qu'il comprend deux pastilles semiconductrices (12, 14) superposées, chaque pastille comportant une première face (20, 22), destinée à être connectée à un substrat de dissipation de chaleur (24, 26) et une deuxième face (28, 30), distincte de la première, sur laquelle est agencée au moins un composant électronique (38a-44b), le module étant agencé de sorte que les deuxièmes faces des pastilles sont disposées en vis-à-vis.

Microelectronic contact structures

Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a post component, a beam component, and a tip component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.

Chip package and method for forming the same

A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

Semiconductor Package and Method of Forming the Same

A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

VERFAHREN ZUM HERSTELLEN EINES HALBLEITERBAUELEMENTES FÜR VERTIKALE INTEGRATION UND VERWENDUNG FÜR TEST-ZWECKE

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

本发明提供半导体封装结构及其制造方法。半导体封装结构包括重布线结构、封装结构以及第二封装层。重布线结构具有彼此相对的第一与第二表面。封装结构位于第一表面上。封装结构包括管芯、第一封装层、重布线层以及多个第二导电端子。管芯具有位于其上的多个第一导电端子。第一封装层包覆管芯。第一封装层暴露出至少一部分的第一导电端子。重布线层位于第一封装层上。重布线层电性连接至暴露出的第一导电端子。多个第二导电端子电性连接于重布线层与重布线结构之间。第二封装层包覆封装结构。第二封装层暴露出至少一部分的第二导电端子。

MODULATE POWER FOR MOTOR VEHICLE

POWER MODULE FOR AN AUTOMOBILE

The invention relates to a power module (10), preferably for a vehicle, in particular an electric vehicle, characterised in that said module includes two vertically adjacent semiconducting chips (12, 14), each chip having a first surface (20, 22) to be connected to a heat sink substrate (24, 26), and a second surface (28, 30) separate from the first and on which at least one electronic component (38a-44b) is arranged, the module being arranged such that the second surfaces of the chips are arranged opposite one another.

Methods and systems for fabricating semiconductor components with through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding ...

Vertical integration semiconductor element

The upper surface of the component proposed has a layer structure including an insulating layer (7) with a hole in it, a contact metallization (8) being applied to the upper surface of the insulating layer and to an area of metallization intended for electrical contacting, and subsequently being featured. A metal contact post (12) fills the hole in the covering dielectric, the post resting on the contact metallization (8) in such a way that it can elastically move on the free end of the contact metallization in the hole (14) of the component, the other end of the contact metallization being anchored in the layer structure. This permits reversible contacting of the component with another component disposed vertically above it. It is possible to bring the planar upper surfaces of the two components into intimate contact with each other since the post (12) which is pressed against a contact (15) on the other component is pushed back into the hole (14), the springiness of the contact metallization ...

CASE OF SEMICONDUCTOR HAVING an ELEMENT SEMICONDUCTOR, a STRUCTURE DEFIXATION OF CASE OF SEMICONDUCTOR ASSEMBLED ON a PLATE OF CIRCUITSIMPRIMES, AND PROCEEDED Of ASSEMBLY OF CASE OF SEMICONDUCTOR

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

An interposer film for IC packaging is disclosed. The interposer film comprises a substrate that supports a plurality of electrically conductive domains. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

THERMALLY AND DIMENSIONALLY STABLE POLYIMIDE FILMS AND METHODS RELATING THERETO

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN

A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process ...

Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)

A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Metallfolie mit Hockerkontakten, Schaltungssubstrat mit der Metallfolie, und Halbleitervorrichtung mit dem Schaltungssubstrat

Verfahren zum Herstellen einer für die Anbindung eines elektrischen Leiters geeigneten metallischen Kontaktfläche zur Kontaktierung eines Leistungshalbleiters, Leistungshalbleiter, Bond Buffer und Verfahren zur Herstellung eines Leistungshalbleiters

Verfahren zum Herstellen einer für die Anbindung eines elektrischen Leiters geeigneten metallischen Kontaktfläche zur Kontaktierung eines Leistungshalbleiters (10), mit den Schritten: Aufbringen einer Trägerfolie (20) auf den Leistungshalbleiter (10) unter Aussparen eines Steuer- oder Leistungskontakts des Leistungshalbleiters (10), Anordnen eines Metallformkörpers (30´) auf der Trägerfolie (20) unter Ausbilden eines auf der Trägerfolie (20) angeordneten ersten Metallformkörperabschnitts und eines oberhalb des Steuer- oder Leistungskontakts über die Fläche der Trägerfolie (20) hinausragenden zweiten Metallformkörperabschnitts, wobei die Trägerfolie (20) für den über die Fläche der Trägerfolie (20) hinausragenden Abschnitt des Metallformkörpers (30´) ein einseitiges Auflager bildet, Verbinden des über die Fläche der Trägerfolie (20) hinausragenden Abschnitts des Metallformkörpers (30´) mit dem Steuer- oder Leistungskontakt unter Verformen des Metallformkörpers (30´).

Contacts for semiconductor packages

A chip size package is disclosed herein, as well as a method for fabricating the same. A recess is formed in a surface of semiconductor chip. Bonding pads are formed on a bottom center of the recess and insulating pads 30 are formed on both lateral sides of the recess. The respective pads are connected to each other with metal wires. An epoxy compound is filled in the recess. Herein, midway portions of the metal wires are exposed from the epoxy compound. Bumps are formed on the midway portions of the metal wires being exposed from the epoxy compound and solder balls are mounted on the bumps. Therefore, the epoxy compound is not protruded from the semiconductor chip, thickness of the package is equal to that of the semiconductor chip. The thickness of package is minimized.

Method of making a structure with improved material properties by moderate heat treatment of a metal deposit

以优选的型材沉积金属,包括在部件(204)或孤立的材料(300)上涂层(206)、和后续的热处理(106),可以提供改善了的力学性能。该方法尤能提供屈服强度较高的制品。这些制品常常具有较高的弹性模量、热稳定性,并可在远高于25℃的温度下保持高屈服强度。该技术包括在所选定的添加剂存在条件下沉积材料(206),接着对沉积材料进行适度的热处理(106)。这种适度热处理与其他经常使用的“消除应力”热处理不同,它使用较低温度和/或较短时间,只要足以使材料重组成所要求的新形式就可以。例如涂覆并热处理弹簧状的细长元件,能提供适于电子学应用的弹性导电触点(212,920,1060)。

Semi-conductor chip with compressible contact structure and electronic package utilizing same

A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Verfahren zum Erzeugen einer freistehenden, abgeschirmten Metallelektrode durch einen Einzelmaskenprozess und ein Verfahren zum Freilegen einer Elektrodenspitze

Verfahren zum Herstellen einer freistehenden, abgeschirmten Metallelektrode, insbesondere Goldelektrode, durch einen Einzelmaskenprozess, umfassend die folgenden Verfahrensschritte: – Bereitstellen eines Siliziumwafers (1), – Aufbringen einer ersten Isolationsschicht (3), insbesondere einer Siliziumnitridschicht (3), auf eine Vorderseite (V) des Siliziumwafers (1), – Aufbringen einer inneren Metallverbundschicht (4) auf die erste Isolationsschicht (3) auf der Vorderseite (V) des Siliziumwafers, – Durchführen eines ersten Lithographieverfahrens auf der Vorderseite (V) und anschließend Durchführen eines ersten Ätzverfahrens zum Wegätzen von Teilen der inneren Metallverbundschicht (4) zum Herstellen von separierten Bereichen (5), insbesondere eines auskragenden Arms oder einer Sternstruktur der inneren Metallverbundschicht (4), – Durchführen eines zweiten Lithographieverfahrens auf einer Rückseite (R) und anschließend Durchführen eines zweiten Ätzverfahrens zum Wegätzen von Teilen des Siliziumwafers (1) zur Freistellung der separierten Bereiche (5) der inneren Metallverbundschicht (4), – Ummanteln der inneren Metallverbundschicht (4) mit einer leitfähigen Abschirmungsschicht (11), insbesondere aus einem Titan-Gold Metallverbund, – Einbringen eines Schnitts (12) quer durch die innere Metallverbundschicht (4) und die leitfähige Abschirmungsschicht (11), insbesondere anhand eines fokussierten Ionenstrahls (13). A method for producing a freestanding, shielded metal electrode, in particular a gold electrode, by a single mask process, comprising the following method steps: - providing a silicon wafer (1), - applying a first insulation layer (3), in particular a silicon nitride layer (3), to a front side (V ) of the silicon wafer (1), - applying an inner metal composite layer (4) on the first insulating layer (3) on the front side (V) of the silicon wafer, - performing a first lithography process on the front side (V) and then performing a first etch process for etching away ...

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

Method for manufacturing i/o terminals and the structure thereof

A method for manufacturing I/O terminals and the structure thereof is provided. The present invention provides movable supporting elements instead of copper posts in the conventional package process. A conductive composite layer covering the supporting elements is patterned to form metal traces connecting between metal pads and the supporting elements on a semiconductor wafer, so as to provide I/O electrical connections of the metal pads with externals. When a stress applied to the supporting element, the supporting element deforms/or attachably moves, and thus providing a cushion effect to release the stress. By the way, the conductive composite layer covering the supporting element confines the space the supporting element can move, limiting the supporting element still in the attached position. The present invention can solve the issue of breakage between the copper post and a solder ball in the conventional wafer-level package. Hence, the quality reliability of package devices can be ...

Semiconductor device with strain relieving bump de

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

Casing for PCB-mounted semiconductor device

Boîtier de semi-conducteur incluant un élément semi-conducteur (11) ayant une première face (21a) et une seconde face (21b) qui est opposée à la première face (21a), une électrode (22) prévue sur la première face (21a), et un conducteur (23) connecté à l'électrode (22), comprenant un élément de film isolant (24) prévu sur la seconde face (21b) pour connecter l'autre extrémité du conducteur. Une partie repliée du conducteur entre l'électrode (22) et l'élément de film (24) forme une partie terminale (23a) (borne). Une plaquette de circuits imprimés possède un moyen de connexion, se connectant à la partie terminale (23a), et ayant une taille adéquate pour placer le boîtier (11). Le moyen de connexion comporte une partie à rainure de logement, et une pluralité d'électrode, et la partie terminale (23a) est connectée entre les électrodes.

COVERLAY COMPOSITIONS AND METHODS RELATING THERETO

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydhde, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Nachgiebige Entlastungsverkapselung auf Waferebene

Eine Halbleiterstruktur enthält ein Halbleitersubstrat und ein auf einer ersten Oberfläche des Substrats angeordnetes nachgiebiges Zwischenverbindungselement. Das nachgiebige Zwischenverbindungselement definiert eine Kammer zwischen der ersten Oberfläche des Substrats und einer Oberfläche des nachgiebigen Zwischenverbindungselements. Beim nachgiebigen Zwischenverbindungselement kann es sich um eine nachgiebige Schicht handeln. Die nachgiebige Schicht kann aus einem Polymer wie etwa Silikon ausgebildet werden. Eine leitende Schicht kann auf der nachgiebigen Schicht in Kontkat mit einem Kontaktpad auf dem Halbleitersubstrat angeordnet werden. Ein Verfahren zum Ausbilden einer Halbleiterstruktur beinhaltet das Bereitstellen eines Halbleitersubstrats und das Bereitstellen eines nachgiebigen Zwischenverbindungselements auf einer ersten Oberfläche des Substrats, so daß das nachgiebige Zwischenverbindungselement eine Kammer zwischen dem nachgiebigen Zwischenverbindungselement und der ersten Oberfläche ...

Chip size package and method of fabricating the same

Substrate-less package structure

SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN

COMPLIANT PRINTED CIRCUIT WAFER LEVEL SEMICONDUCTOR PACKAGE

A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

An interposer film (30) for IC packaging is disclosed. The interposer film comprises a substrate that supports a plurality of electrically conductive domains. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Ball Amount Process in the Manufacturing of Integrated Circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Chip size package and method of fabricating the same

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

Microelectronic contact structures, and methods of making same

Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a "post" component, a "beam" component, and a "tip" component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.

Microelectronic unit forming methods and materials

Releasable leads having an elongated fixed portion extend over a surface defined by a dielectric material of a component or by a semiconductor body. A semiconductor element having a conductive structure connected to a set of contacts is also disclosed. A method of making the conductive structure is disclosed.

HYBRID CIRCUIT FORMED OF TWO CIRCUITS WHOSE TRACKS ARE CONNECTED BY ELECTRIC CONNECTION BALLS

Hybrid circuit formed of two circuits (1, 2) combined by spherical balls (10) with electric connection. The conductive tracks (6) the balls (10) connect do not adhere to the circuits (1, 2) at portions (11) situated around the balls (10). As a result, these portions (11) may be safely removed and the balls (10) are able to roll onto the circuits (1, 2) if the latter are subjected to a relative movement due, for example, to differential thermic cubical expansions. Thus, the balls (10) are not stressed.

Resin seal semiconductor package

Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

제1 및 제2 플레이너 표면(26) 및 에지 표면(25)을 갖는 크리스탈 기판 및 제1 플레이너 표면상에 형성된 액티브 표면(24)을 포함하는 집적 회로 다이(22), 액티브 표면 위에 형성된 적어도 하나의 칩 스케일 패키징 레이어(20), 및 제1 플레이너 표면상에 형성된 적어도 하나의 패드(16)에 의해 액티브 표면상의 회로에 접속되는 적어도 하나의 전기적 콘택트를 포함하는 일체로 패키징된 집적 회로 디바이스(10)가 제공된다. 패키징, 집적 회로, 액티브 표면, 다이, 콘택트, 절연 레이어, 갭 Integrated circuit die 22 comprising a crystal substrate having first and second planar surfaces 26 and edge surfaces 25 and an active surface 24 formed on the first planar surface, at least formed on the active surface Integrally packaged integrated circuit device comprising one chip scale packaging layer 20 and at least one electrical contact connected to a circuit on an active surface by at least one pad 16 formed on a first planar surface 10 is provided. Packaging, Integrated Circuits, Active Surfaces, Dies, Contacts, Insulation Layers, Gap

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

Semiconductor with top-side wrap-around flange contact

A method and apparatus are described for an electronic component package. A standoff is formed on an active side of a substrate. The substrate has an electronic circuit. A conductive layer is deposited over at least a portion of the active side of the substrate. The conductive layer electrically couples a contact area on the active side of the substrate. The standoff is removed to create a flexible conductor.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.

ASSEMBLIES COMPRISING A POLYIMIDE FILM AND AN ELECTRODE, AND METHODS RELATING THERETO

Wafer level chip size package and method for fabricating the same

본 발명 웨이퍼 레벨 칩 사이즈 패키지는, 반도체 기판과 연결된 칩 패드 및 외부 칩 패드를 구비하되, 칩 패드는 보호막에 의해 표면에 노출되고, 외부 칩 패드 상기 보호막 위에서 노출된 구조를 갖는 웨이퍼 레벨 칩 사이즈 패키지에 관한 것으로서, 칩 패드 및 외부 칩 패드 위에 형성된 스터드 범프와, 스터드 범프를 상호 연결하는 와이어와, 외부 칩 패드 위에서 스터드 범프와 일정 간격 이격되도록 형성된 단자 스터드 범프와, 단자 스터드 범프 표면 위에 형성된 솔더 볼, 및 솔더 볼이 노출되도록 스터드 범프, 와이어 및 단자 스터드 범프를 덮는 몰딩재를 구비한다. The wafer level chip size package of the present invention includes a chip pad connected to a semiconductor substrate and an external chip pad, wherein the chip pad is exposed on the surface by a protective film, and the external chip pad has a structure exposed on the protective film. The present invention relates to a stud bump formed on a chip pad and an external chip pad, a wire interconnecting the stud bump, a terminal stud bump formed to be spaced apart from the stud bump on the outer chip pad by a predetermined distance, and a solder ball formed on the terminal stud bump surface. And a molding material covering the stud bumps, the wires and the terminal stud bumps to expose the solder balls.

METHODS AND APPARATUS FOR SOLDER CONNECTIONS

솔더 연결들을 위한 방법들 및 장치가 개시된다. 장치는 표면 상에 도전성 단자를 갖는 기판; 기판의 표면 및 도전성 단자 위에 놓이는 패시베이션 층; 도전성 단자의 일부를 노출시키는 상기 패시베이션 층 내의 개구; 개구내의 도전성 단자에 본딩되고 기판의 표면에 수직인 방향으로 연장하는 적어도 하나의 스터드 범프(stud bump); 및 개구내의 도전성 단자 상에 형성되고 적어도 하나의 스터드 범프를 둘러싸는 솔더 연결(solder connection)을 포함한다. 솔더 연결을 형성하기 위한 방법들이 개시된다. Methods and apparatus for solder connections are disclosed. The apparatus includes a substrate having a conductive terminal on a surface; A passivation layer overlying the surface of the substrate and the conductive terminal; An opening in the passivation layer exposing a portion of the conductive terminal; At least one stud bump bonded to the conductive terminal in the opening and extending in a direction perpendicular to the surface of the substrate; And a solder connection formed on the conductive terminals in the opening and surrounding at least one stud bump. Methods for forming a solder connection are disclosed.

ASSEMBLIES COMPRISING A POLYIMIDE FILM AND AN ELECTRODE, AND METHODS RELATING THERETO

SEMICONDUCTOR COMPONENTS AND SYSTEMS HAVING ENCAPSULATED THROUGH WIRE INTERCONNECTS (TWI) AND WAFER LEVEL METHODS OF FABRICATION

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate The through wire interconnect includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side The through wire interconnect also includes a polymer layer which partially encapsulates the through wire interconnect while leaving the first contact exposed The semiconductor component can be used to fabricate stacked systems module systems and test systems A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)

A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.

Semiconductor components having through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding ...

Methods and apparatus for packaging integrated circuit devices

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Bauelement und Verfahren für Lötverbindungen

Bauelement, das Folgendes umfasst:- ein Substrat (13) mit einer Gruppierung von leitfähigen Anschlüssen (7) auf einer Oberfläche;- mindestens zwei Stud-Bondhügel (29) auf jedem von ersten leitfähigen Anschlüssen in der Gruppierung in einer maximalen Distanz (DNP1) von der Mitte der Gruppierung;- einen Stud-Bondhügel (29) auf jedem von zweiten leitfähigen Anschlüssen in der Gruppierung, die weniger als die maximale Distanz von der Mitte der Gruppierung entfernt sind, aber deren Distanz von der Mitte der Gruppierung größer oder gleich einer anderen, kleineren Distanz (DNP2) von der Mitte der Gruppierung ist; und- Lötverbinder (15), die über den leitfähigen Anschlüssen in der Gruppierung ausgebildet sind, wobei die Lötverbinder über den ersten leitfähigen Anschlüssen jeweils die mindestens zwei Stud-Bondhügel auf den ersten leitfähigen Anschlüssen umschließen, und wobei die Lötverbinder über den zweiten leitfähigen Anschlüssen jeweils den einen Stud-Bondhügel auf den zweiten leitfähigen Anschlüssen ...

Semiconductor device with strain relieving bump design

A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation laver (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process ...

Chip package and method for forming the same

Semiconductor package having semiconductor element mounting structure of semiconductor package mounted on circuit board and method of assembling semiconductor package

The semiconductor package including a semiconductor element 11 having a first face 21a and a second face 21b which is opposite to the first face 21a, an electrode 22 provided on the first face 21a, and a conductive lead 23 connected to the electrode 22 comprises an insulating film member 24 provided on the second face 21b for connecting the other end of the lead, the lead 23 is bent as oppose to a side face of the semiconductor element 11, and is connected each other with an elastic force between the electrode 22 and the film member 24, a bent part of the lead between the electrode 22 and the film member 24 turns to be a terminal part 23a. The circuit board has a connection means, connecting to the terminal unit 23a, and having an adequate size for placing the semiconductor package 11. The connection means is constituted of an accommodation groove part 46 or a frame part 50, and a plurality of pattern electrodes 47a, 47b, and the terminal part 23a is connected between the pattern electrodes ...

Method and fixture for chip attachment to physical objects

Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.

Chip package and method of manufacturing the same

Semiconductor chip

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

ASSEMBLIES COMPRISING A POLYIMIDE FILM AND AN ELECTRODE, AND METHODS RELATING THERETO

The assemblies of the present disclosure comprise an electrode, and a polyimide film. The polyimide film comprises a sub-micron filler and a polyimide. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

WIREBOND INTERCONNECT STRUCTURES FOR STACKED DIE PACKAGES

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

Methods of Forming Metal Layers Using Multi-Layer Lift-Off Patterns

Methods of forming interconnections for an electronic device including a substrate may be provided. For example, first and second patterned layers may be formed on the substrate wherein an opening in the first and second patterned layers exposes portions of the substrate, wherein the first and second patterned layers have different compositions, and wherein the first patterned layer is between the second patterned layer and the substrate. A metal layer may be formed on the second patterned layer and on portions of the substrate exposed through the opening in the first and second patterned layers. The second patterned layer and portions of the metal layer thereon may be removed while maintaining portions of the metal layer on the portions of the substrate exposed through the opening. After removing the second mask layer, solder may be provided on the metal layer.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

COVERLAY COMPOSITIONS AND METHODS RELATING THERETO

Joint for connecting semiconductor chips to circuit boards comprises a first coupling element fixed to a first surface and a second coupling element in the form of a step running along a plane

Joint of two objects with different thermal expansion coefficients comprises a first coupling element (5) fixed to a first surface and a second coupling element (3) in the form of a step running along a plane (4). The first section (6) of the step is connected to the second surface and the second section (7) is arranged at a distance from the second surface. The second section of the step is connected to the first coupling element on the side that lies opposite the second surface. An Independent claim is also included for a process for the production of the joint. Preferred Features: The first section of the step lies closer to the center of gravity of the smaller of the two surfaces than the second section of the step.

Semiconductor package and manufacturing method thereof

The invention provides a semiconductor package and a manufacturing method thereof, wherein the semiconductor package comprises: a substrate with a plurality of electrical connection gaskets, a semiconductor assembly having a plurality of electrode gaskets and chipping the substrate, and bonding wire segments arranged on the electrode gaskets. The electrode gaskets are electrically connected with the electrical connection gaskets by the bonding wire segments, and the width of the bonding wire segments are tiny, so the dimension of the electrical connection gaskets can be relatively reduced, thereby reaching demands of fine pitch and miniaturization.

Compliant terminal mountings with vented spaces and methods

A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Semiconductor module system having encapsulated through wire interconnect (TWI)

A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.

VERTIKALE VERBINDUNGSHALBLEITER-STRUKTUR UND VERFAHREN ZUM HERSTELLEN DERSELBIGEN

Die Erfindung betrifft eine vertikale Verbindungshalbleiter-Struktur (100) mit einem Substrat (10) mit einer ersten Hauptoberfläche (11) und einer gegenüberliegenden zweiten Hauptoberfläche (12), einer vertikalen Kanalöffnung (13), die sich zwischen der ersten Hauptoberfläche (11) und der zweiten Hauptoberfläche (12) vollständig durch das Substrat (10) hindurch erstreckt, und einem innerhalb der vertikalen Kanalöffnung (13) angeordneten Schichtstapel (20). Der Schichtstapel (20) weist eine innerhalb der vertikalen Kanalöffnung (13) angeordnete elektrisch leitfähige Schicht (31) und eine innerhalb der vertikalen Kanalöffnung (13) angeordnete Verbindungshalbleiter-Schicht (21) auf. Die Verbindungshalbleiter-Schicht (21) weist einen auf der elektrisch leitfähigen Schicht (31) angeordneten und mit der elektrisch leitfähigen Schicht (31) galvanisch verbundenen Verbindungshalbleiter auf. Die Erfindung betrifft ferner ein Verfahren zum Herstellen einer derartigen vertikalen Verbindungshalbleiter-Struktur ...

Halbleiterbauelement

Es wird ein Halbleiterbauelement offenbart. Eine Ausführungsform beinhaltet ein Halbleitersubstrat und mindestens zwei isolierende Elemente, die sich über dem Halbleitersubstrat oder über einer das Halbleitersubstrat einbettenden Formmasse befinden. Die mindestens zwei isolierenden Elemente weisen eine dem Halbleitersubstrat oder der Formmasse zugewandte erste Fläche und eine von dem Halbleitersubstrat oder der Formmasse abgewandte zweite Fläche auf. Ein leitendes Element für jedes der mindestens zwei isolierenden Elemente erstreckt sich von der ersten Fläche des isolierenden Elements zu der zweiten Fläche des isolierenden Elements.

THIN FILM TRANSISTOR COMPOSITIONS, AND METHODS RELATING THERETO

The present disclosure is directed to a thin film transistor composition. The thin film transistor composition has a semiconductor material and a substrate. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48 52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

SEMICONDUCTOR CHIP

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

SEMICONDUCTOR WITH TOP-SIDE WRAP-AROUND FLANGE CONTACT

A method and apparatus are described for an electronic component package. A standoff is formed on an active side of a substrate. The substrate has an electronic circuit. A conductive layer is deposited over at least a portion of the active side of the substrate. The conductive layer electrically couples a contact area on the active side of the substrate. The standoff is removed to create a flexible conductor.

FLEXIBLE SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Verfahren und Bauelement für Lötverbindungen

Verfahren und Bauelement für Lötverbindungen. Ein Bauelement enthält ein Substrat mit einem leitfähigen Anschluss auf einer Fläche; eine Passivierungsschicht, die über der Oberfläche des Substrats und des leitfähigen Anschlusses liegt; eine Öffnung in der Passivierungsschicht, die einen Abschnitt des leitfähigen Anschlusses frei legt; mindestens einen Stud-Bondhügel, der an den leitfähigen Anschluss in der Öffnung gebondet ist und sich in einer Richtung senkrecht zur Substratoberfläche erstreckt; und eine Lötverbindung, die an dem leitfähigen Anschluss in der Öffnung ausgebildet ist und den mindestens einen Stud-Bondhügel umschließt. Verfahren zum Ausbilden der Lötverbindungen werden offenbart. Method and device for solder joints. A device includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive port in the opening and extending in a direction perpendicular to the substrate surface; and a solder joint formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder joints are disclosed.

Chip size package and method of fabricating the same

Semiconductor apparatus and methods of manufacturing the same

自動車のための電力モジュール

Verfahren zur Herstellung einer Verbindung zweier Gegenstände

METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

An integrally packaged integrated circuit device (10) including an integrated circuit die (22) including a crystalline substrate having first and second generally planar surfaces (26) and edge surfaces (25) and an active surface (24) formed on the first generally planar surface, at least one chip scale packaging layer (20) formed over the active surface and at least one electrical contact being connected to circuitry on the active surface by at least one pad (16) formed on the first generally planar surface.

Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer

A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.

SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR ELEMENT MOUNTING STRUCTURE OF SEMICONDUCTOR PACKAGE MOUNTED ON CIRCUIT BOARD AND METHOD OF ASSEMBLING SEMICONDUCTOR PACKAGE

The semiconductor package including a semiconductor element 11 having a first face 21a and a second face 21b which is opposite to the first face 21a, an electrode 22 provided on the first face 21a, and a conductive lead 23 connected to the electrode 22 comprises an insulating film member 24 provided on the second face 21b for connecting the other end of the lead, the lead 23 is bent as oppose to a side face of the semiconductor element 11, and is connected each other with an elastic force between the electrode 22 and the film member 24, a bent part of the lead between the electrode 22 and the film member 24 turns to be a terminal part 23a. The circuit board has a connection means, connecting to the terminal unit 23a, and having an adequate size for placing the semiconductor package 11. The connection means is constituted of an accommodation groove part 46 or a frame part 50, and a plurality of pattern electrodes 47a, 47b, and the terminal part 23a is connected between the pattern electrodes ...

METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface. © KIPO & WIPO 2007 ...

Semiconductor apparatus

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

The present disclosure is directed to a wire wrap composition having a polyimide layer and a bonding layer. The polyimide layer is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

THIN FILM TRANSISTOR COMPOSITIONS, AND METHODS RELATING THERETO

The present disclosure is directed to a thin film transistor composition. The thin film transistor composition has a semiconductor material and a substrate. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48 52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Halbleiterbauelement, umfassend: ein Halbleitersubstrat (1); mindestens zwei isolierende Elemente (5), die sich über dem Halbleitersubstrat (1) oder über einer das Halbleitersubstrat (1) einbettenden Formmasse (30) befinden, wobei die mindestens zwei isolierenden Elemente (5) eine dem Halbleitersubstrat (1) oder der Formmasse (30) zugewandte erste Fläche (7) und eine von dem Halbleitersubstrat (1) oder der Formmasse (30) weggewandte zweite Fläche (8) aufweisen; ein leitendes Element (6) für jedes der mindestens zwei isolierenden Elemente (5), wobei sich die leitenden Elemente (6) von der ersten Fläche (7) des isolierenden Elements (5) zu der zweiten Fläche (8) des isolierenden Elements (5) erstrecken; wobei jedes isolierende Element (5) ein Hohlpfosten ist, welcher mit dem entsprechenden leitenden Element (6) gefüllt ist; und ein über der zweiten Fläche (8) jedes isolierenden Elements (5) angeordnetes Lotdepot (20), welches elektrisch mit dem entsprechenden leitenden Element (6) verbunden ...

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

In-street integrated circuit wafer via

Vertical holes are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material. After the wafer is cut along the saw-lines, portions of the conductive material on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths between the upper and lower surfaces of the IC chips.

Microelectronic elements with deformable leads

An element such as a semiconductor wafer or other body is provided with flexible leads, the tip ends of which project over the front surface of the element. The tips of the flexible leads are spaced apart from the front surface and are independently moveable with respect to the element. The flexible leads may be curved in a plane parallel to the front surface of the element, or may be curved so that the tip end of each flexible lead is disposed further from the front surface of the element than the main body of the flexible lead.

IR ASSISTED FAN-OUT WAFER LEVEL PACKAGING USING SILICON HANDLER

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Verfahren zum Herstellen eines Durchkontaktes eines Halbleiterbauelements mit einem umgebenden ringförmigen Isolationsgraben und entsprechendes Halbleiterbauelement

Verfahren zum Herstellen eines Durchkontaktes (14) eines Halbleiterbauelements (1) mit einem umgebenden ringförmigen Isolationsgraben (12) mit den Schritten:Bereitstellen von einem leitfähigen Substrat (10);Aufbringen einer dielektrischen Schicht (26) auf die Oberseite des Substrats (10);Bilden von einer Öffnung (40; 44) in der dielektrischen Schicht (26) in einem Bereich (38), wo der Durchkontakt (14) herzustellen ist;Aufbringen wenigstens einer Metallschicht (28) in dem Bereich (38), wo der Durchkontakt (14) herzustellen ist und in einem Bereich (42), wo der Isolationsgraben (12) herzustellen ist;Ausbilden eines Gitters (24) mit Gitteröffnungen (36) in der wenigstens einen Metallschicht (28) in dem Bereich (42), wo der Isolationsgraben (12) herzustellen ist;Öffnen der dielektrischen Schicht (26) in dem Bereich (42), wo der Isolationsgraben (12) herzustellen ist;Ausbilden des Isolationsgrabens (12) unterhalb des Gitters (24) durch ein Ätzverfahren, wobei das Gitter (24) als Maske verwendet ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first metal wiring formed on a semiconductor substrate, a first organic insulating film formed on the first metal wiring, and a second metal wiring formed to cover the first organic insulating film and having a via connected to the first metal wiring. The semiconductor device further includes a second organic insulating film formed on the first organic insulating film and having an opening to expose the second metal wiring, a bump formed on an exposed portion of the second metal wiring in the opening, and a tunnel portion formed in contact with the second metal wiring or the first organic insulating film. The tunnel portion overlaps with the second metal wiring in planar view.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance. 1. A method of forming a packaging device , the method comprising:forming a contact pad over a substrate;forming a passivation layer over the substrate and a first portion of the contact pad yet leaving a second portion of the contact pad exposed;forming a post passivation interconnect (PPI) line and a PPI pad over the passivation layer, the PPI line being coupled to the second portion of the contact pad, the PPI pad being coupled to the PPI line;depositing a first insulating material over the PPI line, the PPI pad, and the passivation layer; andpatterning the first insulating material to expose the PPI pad, wherein after the patterning, the first insulating material has a first sidewall spaced apart from a second sidewall of the PPI pad by a predetermined distance, the first sidewall of the first insulating material extending below a top surface of the PPI pad.2. The method of further comprising:forming a conductive material on the PPI pad.3. The method of further comprising:depositing a second insulating material over the first insulating material and surrounding at least a lower portion of the conductive material, the second insulating material being interposed between the first sidewall of the first insulating material and the second sidewall ...

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals. 1. A manufacturing method of a semiconductor package structure , comprising:forming at least one package structure, wherein the at least one package structure comprises at least one die having a plurality of first conductive terminals thereon, a first encapsulant encapsulating the at least one die and exposing at least part of the first conductive terminals, a redistribution layer over the first encapsulant and electrically connected to the first conductive terminals, and a plurality of second conductive terminals over the redistribution layer;coupling the at least one package structure to a first surface of a redistribution structure, wherein the redistribution structure further has a second surface opposite to the first surface, and the second conductive terminals of the at least one package structure are electrically connected to between the redistribution layer and the redistribution structure; andencapsulating the at least one package structure by a second ...

Semiconductor Package and Method of Forming the Same

A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder. 1. A method of forming a semiconductor package , the method comprising:receiving a carrier;coating the carrier with a bonding layer;forming a first insulator layer over the bonding layer;forming a backside redistribution layer over the first insulator layer;forming a second insulator layer over the backside redistribution layer;patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer;filling the recess with a solder; andcoupling a surface-mount device (SMD) to the solder.2. The method of claim 1 , further comprising providing a molding compound over the SMD.3. The method of claim 2 , further comprising providing a chip adjacent the molding compound claim 2 , wherein providing the molding compound includesproviding the molding compound over the chip, andremoving the molding compound on a top surface of the chip.4. The method of claim 3 , further comprising forming a front redistribution layer coupled to the top surface of the chip.5. The method of claim 4 , further comprising:forming a via hole that extends through the molding compound and the second insulator layer and to the backside redistribution layer; andfilling the via hole with a via material, wherein forming the front redistribution layer includes forming the front redistribution layer coupled to the via material.6. The method of claim 4 , further comprising providing a plurality ...

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals. 1. A semiconductor package structure , comprising:a redistribution structure, having a first surface and a second surface opposite to the first surface; at least one die, having a plurality of first conductive terminals thereon;', 'a first encapsulant, encapsulating the at least one die, wherein the first encapsulant exposes at least part of the first conductive terminals;', 'a redistribution layer over the first encapsulant, wherein the redistribution layer is electrically connected to the first conductive terminals; and', 'a plurality of second conductive terminals, electrically connected between the redistribution layer and the redistribution structure; and, 'at least one package structure over the first surface of the redistribution structure, wherein the at least one package structure comprisesa second encapsulant, encapsulating the at least one package structure, wherein the second encapsulant exposes at least part of the second conductive terminals.2. The ...

Methods and Apparatus for Solder Connections

Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed. 1. A method comprising:providing a substrate having a surface with a plurality of conductive terminals formed thereon;forming a passivation layer over the surface;forming openings in the passivation layer exposing the conductive terminals;forming at least one stud bump bonded to each of a first set of the conductive terminals of the plurality of conductive terminals and extending from each respective conductive terminal in a direction normal to the surface of the substrate, a first conductive terminal and a second conductive terminal of the plurality of conductive terminals having a different number of distinct and separated stud bumps; andforming solder connections over the conductive terminals, the solder connections surrounding the at least one stud bump on each of the at least some of the plurality of conductive terminals.2. The method of claim 1 , wherein providing the substrate comprises providing a semiconductor wafer having integrated circuits fabricated thereon.3. The method of claim 1 , wherein forming the at least one stud bump further comprises forming a stack of stud bumps.4. The method of claim 1 , wherein after forming the at least one stud bump bonded to the first set of conductive terminals claim 1 , remaining ones of the plurality of conductive terminals are free from the stud bumps.5. The method of claim 1 , wherein forming the at least one stud bump ...

SEMICONDUCTOR CHIP

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region. 1. A semiconductor chip comprising:a semiconductor substrate including a bump region and a non-bump region;a bump on the bump region, the non-bump region having no bump; anda passivation layer on the bump region and the non-bump region of the semiconductor substrate, a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region, and the passivation layer including a step between the bump region and the non-bump region.2. The semiconductor chip of claim 1 , further comprising:a lower passivation layer below the passivation layer, whereinthe passivation layer is an upper passivation layer.3. The semiconductor chip of claim 1 , wherein the passivation layer includes one an oxide layer claim 1 , a nitride layer claim 1 , and a photo-sensitive organic layer.4. The semiconductor chip of claim 1 , wherein the bump region extends a distance from opposite side walls of the bump in a horizontal direction.5. The semiconductor chip of claim 1 , further comprising:a barrier metal pad on the bump region, whereinthe bump is on the barrier metal pad.6. The semiconductor chip of claim 1 , further comprising:a bump pad on the bump region; anda barrier metal pad on the bump pad, whereinthe bump is on the barrier metal pad.7. (canceled)8. The semiconductor chip of claim 1 , wherein the passivation layer includes a recess portion in the non-bump region.9. The semiconductor chip of claim 1 , whereinthe semiconductor substrate includes a ...

Ball Amount Process in the Manufacturing of Integrated Circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Ir assisted fan-out wafer level packaging using silicon handler

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors. 1. A semiconductor package , comprising:a first redistribution layer structure;a package structure over the first redistribution layer structure, comprising a plurality of package components; anda bus die and a plurality of connectors, encapsulated by a first encapsulant between the package structure and the first redistribution layer structure, wherein the bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.2. The semiconductor package according to claim 1 , further comprising a circuit board structure claim 1 , wherein the first redistribution layer structure is disposed over the circuit board structure claim 1 , and the circuit board structure includes a core layer claim 1 , a first build-up layer on a first surface of the core layer claim 1 , and a second build-up layer on a second surface of the core layer opposite to the first surface.3. The semiconductor package according to claim 1 , wherein the first encapsulant comprises a molding compound.4. The semiconductor package according to claim 1 , further comprising a second encapsulant claim 1 , wherein the plurality of package components ...

Method for forming a semiconductor package

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Semiconductor components having through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Semiconductor components having encapsulated through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Wafer level package device with an smd form factor

An electronic circuit has a component that includes a semiconductor substrate. The substrate has a passivation layer and one or more connection pads, and lacks a ceramic package. The substrate has one or more electrically conductive terminals attached to the substrate and contacting the one or more connection pads. The component has a standardized SMD configuration. In this manner inexpensive equipment can be used to assemble circuitry conventionally requiring more expensive WLP equipment.

Semiconductor package and its semiconductor mounting structure

Wafer level package device with an smd form factor

An electronic circuit has a component that includes a semiconductor substrate. The substrate has a passivation layer and one or more connection pads, and lacks a ceramic package. The substrate has one or more electrically conductive terminals attached to the substrate and contacting the one or more connection pads. The component has a standardized SMD configuration. In this manner inexpensive equipment can be used to assemble circuitry conventionally requiring more expensive WLP equipment.

Semiconductor device

Metal foil with stool contacts, circuit substrate with the metal foil, and semiconductor device with the circuit substrate

Method of and apparatus for sealing a hermetic lid to a semiconductor die

A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques. An angle between the lid and the semiconductor device can be controlled by adjusting relative widths of one or both the layers of solderable materials.

Ball amount process in the manufacturing of integrated circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Surface mount semiconductor device without lead frame

一种半导体器件，包括：具有顶表面的半导体裸片，接合焊盘形成在所述顶表面上；电连接元件，每个电连接元件具有位于第一平面且电连接至接合焊盘中的一个接合焊盘的第一端以及位于与第一平面不同的第二平面的相对的第二端；以及成型材料，其封装半导体裸片和电连接元件，其中，成型材料限定具有顶表面和一个或多个侧表面的封装体，其中，每个电连接元件的第二端暴露在封装体的顶表面处并暴露在封装体的一个或多个侧表面中的至少一个处。

Semiconductor with bottom-side wrap-around flange contact

A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Method for producing a structure with improved material properties by mildly heat treating a metal coating

(57)【要約】 好適な形状の金属の付着は、パーツ（204）上の被覆物（206）、又は独立した材料（300）、及び改良された機械的特性を得るための二次的な熱処理（106）を含む。特に本方法は、比較的高い降伏強度を備える製品を提供する。しばしばこの製品は、比較的高い弾性率を備え、熱に対して安定であり、25℃をはるかに超える温度において高い降伏強度を維持する。この技術は、選択された添加物の存在下で材料（206）を付着し、その後この付着された材料に穏やかな熱処理（206）を施すことが必要である。この穏やかな熱処理は、より低い温度で及び／又は短い時間で行われる他の一般に実施される「応力除去」熱処理とは異なり、新しい所望の形状に材料を再構成するのにちょうど必要なだけ行うことが好ましい。例えばばね形状の細長い部材を被覆して熱処理することにより、電子機器用途に有用な弾力のある導電性の接点（212、920、1060）が提供される。

Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate

A semiconductor device wherein a circuit substrate of a single or multiple layer is composed in such a manner that bumps (22), which are electrically connected to connection electrodes (12) provided on one face of a surface mount device (10), are arranged in the same planar arrangement as that of the connection electrodes (12). The bumps (22) protrude from one side of a sheet of metal foil (20) on which wiring patterns (16) electrically connected to the bumps (22) are formed. An insulating adhesive agent layer (18) is adhered to the side of the sheet of metal foil (20) having the bumps (22) and is also adhered to one face of the surface mount device (10) while the tips of the bumps (22) come into contact with respective connection electrodes (12).

Semiconductor device, fabrication method thereof and metal substrate for use of the same

반도체 소자 또는 반도체 웨이퍼의 전극 형성면에 응력 완화 구조를 갖는 외부접속 구조를 효율적이고 확실하게 설치한다. An external connection structure having a stress relaxation structure is efficiently and reliably provided on the electrode formation surface of the semiconductor element or the semiconductor wafer. 반도체 소자(10)의 전극단자 형성면에 설치된 접속단자(12)에 리드부(43)의 일단측에 설치된 단자 접속부(40)가 접합되어 리드부(30)가 전극단자 형성면으로부터 떨어져서 지지됨과 동시에, 상기 리드부(30)가 전극단자 형성면과 거의 평행하고, 또한 평면 내에 적어도 하나의 변곡점을 갖는 곡선 형상으로 연출하여 형성되며, 상기 리드부(30)의 타단측에 리드부와 일체로 상기 전극단자 형성면과는 반대 쪽으로 떨어진 방향으로 외부 접점(50)이 돌출하여 설치되어 있다. The terminal connecting portion 40 provided on one end of the lead portion 43 is joined to the connecting terminal 12 provided on the electrode terminal forming surface of the semiconductor element 10 so that the lead portion 30 is supported away from the electrode terminal forming surface. At the same time, the lead portion 30 is formed in a direction substantially parallel to the electrode terminal forming surface and in a curved shape having at least one inflection point in the plane, and integrally with the lead portion on the other end side of the lead portion 30. The external contact 50 protrudes in a direction away from the electrode terminal forming surface.

Wire wrap compositions and methods relating thereto

本公开涉及具有聚酰亚胺层和粘结层的线材包裹组合物。所述聚酰亚胺层由聚酰亚胺和亚微米级填料组成。所述聚酰亚胺衍生自至少一种芳族二酸酐组分和至少一种芳族二胺组分，所述芳族二酸酐组分选自刚棒二酸酐、非刚棒二酸酐以及它们的组合，所述芳族二胺组分选自刚棒二胺、非刚棒二胺以及它们的组合。所述二酸酐与二胺的摩尔比为48-52∶52-48，并且X∶Y的比率为20-80∶80-20，其中X为刚棒二酸酐和刚棒二胺的摩尔百分比，并且Y为非刚棒二酸酐和非刚棒二胺的摩尔百分比。所述亚微米级填料在至少一个尺寸上小于550纳米；具有大于3∶1的长宽比；在所有尺寸上小于所述膜的厚度。

Method of and apparatus for sealing an hermetic lid to a microelectronic machine

一种气密地钝化半导体器件的方法和装置包括将盖直接密封到半导体衬底上。有源器件形成在衬底的表面上,并由基本上平坦的盖密封区环绕,进而由键合焊盘环绕。第一层可焊接材料形成在盖密封区上。提供盖,盖具有结构上对应于第一层的第二层可焊接材料。焊料层提供在可焊接材料的第一层和第二层之间。在优选实施例中,焊料形成在第二层上。加热以将盖气密地结合到半导体器件上同时不需要常规的封装。优选第一和第二层为使用常规半导体技术处理的常规已知可焊接材料的多层结构。通过调节一层或两层可焊接材料的相对宽度可以控制盖和半导体器件之间的角度。

Semiconductor with bottom-side wrap-around flange contact

A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Methods and apparatus for packaging integrated circuit devices

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

A kind of chip packaging method and chip-packaging structure

本发明的实施例提供一种芯片封装方法及芯片封装结构，涉及半导体技术领域，可提高封装效率以及产出效率。一种芯片封装方法，包括：在第一面板级衬底上形成剥离层，并在所述剥离层上各预设区域分别形成重布线层，位于不同区域的所述重布线层之间相互绝缘；在形成所述重布线层的过程中，还形成第一介质层；将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接；对所述芯片进行封装，形成封装层；去除所述第一面板级衬底和所述剥离层，并在所述重布线层一侧形成焊球。

Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate

Semiconductor device including an insulative layer having a gap

A resin-encapsulated semiconductor device includes a semi-conductor substrate having a surface including an insulating film and an electroplated transmission line. To avoid a possible separation and/or peeling of the insulating film with respect to the substrate, a gap is present between the insulating film and the plated line.

Semiconductor chip

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Die attach material for TBGA or flexible circuitry

An attachment material is provided between the die and the solder balls of a TBGA or other flexible circuitry package that is sufficiently compliant to absorb pressure between the two, so as not to apply stress to the solder balls. The attachment material is also sufficiently rigid, with a low coefficient of thermal expansion (CTE), so that the material does not excessively expand and contract during thermal cycling relative to the die. More preferably, the attachment material has a CTE close to that of the die to prevent breakage of the tape at the junction between the tape and the die.

In-street integrated circuit wafer via

Vertical holes (156) are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines (154) along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material (165). After the wafer is cut along the saw-lines, portions of the conductive material (165) on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths (174, 180, 270, 272) between the upper and lower surfaces of the IC chips.

Microelectronic unit forming methods and materials

Releasable leads having an elongated fixed portion extend over a surface defined by a dielectric material of a component or by a semiconductor body. A semiconductor element having a conductive structure connected to a set of contacts is also disclosed. A method of making the conductive structure is disclosed.

Methods and apparatus for packaging integrated circuit devices

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Wafer level chip scale packaging structure and method of fabrication the same

Compliant relief wafer level packaging

A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Semiconductor package having semiconductor element mounting structure of semiconductor package mounted on circuit board and method of assembling semiconductor package

The semiconductor package including a semiconductor element 11 having a first face 21 a and a second face 21 b which is opposite to the first face 21 a, an electrode 22 provided on the first face 21 a, and a conductive lead 23 connected to the electrode 22 comprises an insulating film member 24 provided on the second face 21 b for connecting the other end of the lead, the lead 23 is bent as oppose to a side face of the semiconductor element 11, and is connected each other with an elastic force between the electrode 22 and the film member 24, a bent part of the lead between the electrode 22 and the film member 24 turns to be a terminal part 23 a. The circuit board has a connection means, connecting to the terminal unit 23 a, and having an adequate size for placing the semiconductor package 11. The connection means is constituted of an accommodation groove part 46 or a frame part 50, and a plurality of pattern electrodes 47 a, 47 b, and the terminal part 23 a is connected between the pattern electrodes 47 a, 47 b.

Methods and apparatus for packaging integrated circuit devices

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Semiconductor packages and methods of manufacturing the same

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.

Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Diffusion barriers and method of forming same

An element that is configured to bond to another element to define a bonded structure is disclosed. The element can include a dielectric bonding layer having a cavity that extends at least partially through a thickness of the dielectric bonding layer from a surface of the dielectric bonding layer. The element can also include a conductive feature that is at least partially disposed in the cavity. The conductive feature has a contact surface. The element can include a diffusion barrier layer between the conductive feature and a portion of the dielectric bonding layer. The barrier layer includes a barrier metal. The barrier metal of the diffusion barrier layer has an oxidation propensity that is greater than an oxidation propensity of the conductive feature.

HYBRID CIRCUIT FORMED OF TWO CIRCUITS OF WHICH THE TRACKS ARE CONNECTED BY ELECTRICAL CONNECTION BALLS.

Circuit hybride formé de deux circuits (1, 2) réunis par des billes sphériques de connexion électrique (10). Les pistes conductrices (6) que les billes (10) relient n'adhèrent pas aux circuits (1, 2) en des parties (11) situées autour des billes (10). Il en résulte que ces parties (11) peuvent être soulevées sans dommage et les billes (10) peuvent rouler sur les circuits (1, 2) si ceux-ci sont soumis à un mouvement relatif dû par exemple à des dilatations thermiques différentielles. Les billes (10) ne sont donc pas contraintes. Hybrid circuit formed of two circuits (1, 2) joined by spherical electrical connection balls (10). The conductive tracks (6) that the balls (10) connect do not adhere to the circuits (1, 2) in parts (11) located around the balls (10). As a result, these parts (11) can be lifted without damage and the balls (10) can roll on the circuits (1, 2) if these are subjected to a relative movement due for example to differential thermal expansions. The balls (10) are therefore not constrained.

Method of and apparatus for sealing an hermetic lid to a semiconductor die

A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques. An angle between the lid and the semiconductor device can be controlled by adjusting relative widths of one or both the layers of solderable materials.

Methods of forming metal layers using multi-layer lift-off patterns

Methods of forming interconnections for an electronic device including a substrate may be provided. For example, first and second patterned layers may be formed on the substrate wherein an opening in the first and second patterned layers exposes portions of the substrate, wherein the first and second patterned layers have different compositions, and wherein the first patterned layer is between the second patterned layer and the substrate. A metal layer may be formed on the second patterned layer and on portions of the substrate exposed through the opening in the first and second patterned layers. The second patterned layer and portions of the metal layer thereon may be removed while maintaining portions of the metal layer on the portions of the substrate exposed through the opening. After removing the second mask layer, solder may be provided on the metal layer.

Compliant terminal mountings with vented spaces and methods

A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Interconnections for a semiconductor device

A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Fan out of interconnect elements attached to semiconductor wafer

An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.

Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

用于防止蚀刻重分布层的重分布层制造的系统和方法

描述了用于制造重分布层的系统和方法。在衬底的顶部上没有沉积由铜制成的晶种层。晶种层的缺乏避免了蚀刻晶种层的需要。当未蚀刻晶种层时，同样也不蚀刻由铜制成的再分布层。

반도체 칩

본 발명의 반도체 칩은 배리어 금속 패드 상에 형성된 범프가 배치된 범프 영역과 상기 범프가 배치되지 않은 비범프 영역을 포함하는 반도체 기판; 및 상기 범프 영역 및 비범프 영역의 상기 반도체 기판 상에 형성된 패시베이션층을 포함한다. 상기 범프 영역의 패시베이션층의 두께는 상기 비범프 영역의 패시베이션층의 두께보다 두껍고, 상기 범프 영역과 비범프 영역간에는 단차가 형성되어 있고, 상기 배리어 금속 패드의 일측벽 및 타측벽으로부터 상기 단차까지의 거리는 상기 범프 영역의 패시베이션층의 두께보다 크다. 상기 범프 영역은 상기 반도체 기판 상에 평면적으로 서로 이격되어 배치된 복수개의 범프들로 구성되고, 상기 반도체 기판은 중심부에 형성된 중앙 영역 및 상기 중앙 영역을 둘러싸고 상기 중앙 영역과 분리된 주변 영역으로 구분되고, 및 상기 중앙 영역에 형성된 복수개의 범프들중 일부 또는 전부의 범프를 둘러싸는 상기 패시베이션층의 두께는 상기 비범프 영역의 패시베이션층 두께보다 두껍다.

Memory system packaging structure, and method for forming the same

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

用于重分配层工艺的替代集成

在一个示例中，描述了一种用于再分布层(RDL)工艺的方法。提供衬底。在衬底的上面沉积介电层。使介电层图案化。将阻挡层和铜籽晶层沉积在介电层的上面。将光致抗蚀剂层施加在阻挡层和铜籽晶层的上面。使光致抗蚀剂层图案化以对应于介电层图案。铜电沉积在由光致抗蚀剂层暴露的图案化区域中。去除光致抗蚀剂层。蚀刻铜和籽晶阻挡层。

Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

Inductor on microelectronic die

Systems and methods for fabrication of a redistribution layer to avoid etching of the layer

Systems and methods for fabrication of a redistribution layer are described. There is no deposition of a seed layer, made from copper, on top of a substrate. The lack of the seed layer avoids a need for etching the seed layer. When the seed layer is not etched, the redistribution layer, also made from copper, is not etched.

用于防止蚀刻重分布层的重分布层制造的系统和方法

描述了用于制造重分布层的系统和方法。在衬底的顶部上没有沉积由铜制成的晶种层。晶种层的缺乏避免了蚀刻晶种层的需要。当未蚀刻晶种层时，同样也不蚀刻由铜制成的再分布层。

Flexible semiconductor package and related methods

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

半导体封装

本实用新型公开了半导体封装，所述半导体封装的实施方式可包括管芯，所述管芯包括第一侧以及与所述第一侧相对的第二侧，所述管芯的所述第二侧耦接到层；各自接合到所述管芯的所述第一侧的多条导线的第一端；包封所述管芯和所述多条导线的模塑料，以及各自直接接合到多个凸块中的一个凸块的所述多条导线的第二端，其中所述层的表面通过所述模塑料暴露。

Semiconductor chip

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Alternative integration for redistribution layer process

In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Ir assisted fan-out wafer level packaging using silicon handler

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

半导体芯片

一种半导体芯片包括：半导体衬底，包括其中配置有凸块的凸块区及不包括凸块的非凸块区；以及钝化层，形成在所述半导体衬底的所述凸块区及所述非凸块区上，其中所述凸块区中所述钝化层的厚度厚于所述非凸块区中所述钝化层的厚度，且在所述凸块区与所述非凸块区之间具有台阶。所述半导体芯片具有提高的可靠性。

Semiconductor device and method of manufacturing semiconductor device

According to one embodiment, a semiconductor device includes a plurality of stacked semiconductor chips each of which has a first surface having an electrode formed thereon, a plurality of wires each of which has one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips, a sealing resin that covers the plurality of semiconductor chips, has a second surface having recesses formed therein, and is formed so that the other end portions of the plurality of wires and the recesses overlap each other when viewed from the stacking direction, and a plurality of terminals that is provided so as to fill the recesses, each of which has one end portion connected to the other end portion of each of the plurality of wires and has the other end portion exposed from the sealing resin.

擴散屏障及其形成方法

本發明揭示一種配置以接合至另一元件以界定接合結構之元件。該元件可包括具有空腔之介電質接合層，該空腔從該介電質接合層之表面至少部分地延伸穿過該介電質接合層之一厚度。該元件亦可包括至少部分地安置於該空腔中之導電特徵。該導電特徵具有接觸表面。該元件可包括在該導電特徵與該介電質接合層之一部分之間的擴散屏障層。該屏障層包括屏障金屬。該擴散屏障層之該屏障金屬具有比該導電特徵之氧化傾向更大之氧化傾向。

IR assisted fan-out wafer level packaging using silicon handler

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Inductor on microelectronic die

A device (100) has bump bonds (130) and an inductor (140) on a die (102). The device (100) includes first lateral conductors (108) extending along the die (102). Some of the first lateral conductors (108) contact some of the terminals (104) of the die (102). The device (100) also includes conductive columns (114) on the first lateral conductors (108) and second lateral conductors (120) on the conductive columns (114), opposite from the first lateral conductors (108), extending laterally in a plane. A first set (128) of the first lateral conductors (108), the conductive columns (114), and the second lateral conductors (120) provide the bump bonds (130) of the device. A second set (138) of the first lateral conductors (108), the conductive columns (114), and the second lateral conductors (120) are electrically coupled in series to form the inductor (140). Methods of forming the device (100) are also described.

Interconnections for a semiconductor device and method for forming same

A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Semiconductor device having air cavity

The present disclosure provides a semiconductor device having an air cavity. The semiconductor device includes a substrate, a first patterned conductive layer, a first dielectric layer, and a second patterned conductive layer. The first patterned conductive layer is on the substrate. The first dielectric layer is on the first patterned conductive layer. The second patterned conductive layer is on the first dielectric layer. The semiconductor device has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

防止重分佈層蝕刻的重分佈層製作用系統和方法

本文敘述重分佈層製作用系統及方法。在基板上沒有由銅製成之晶種層的沉積。缺少晶種層防止對於蝕刻晶種層的需求。當晶種層不受蝕刻，亦由銅製成的重分佈層便不受蝕刻。

재분배 층의 에칭을 방지하기 위한 재분배 층의 제조를 위한 시스템들 및 방법들

재분배 층의 제조를 위한 시스템들 및 방법들이 기술된다. 기판의 상단부 상에 구리로 이루어진 시드 층의 증착이 없다. 시드 층의 결여는 시드 층을 에칭할 필요성을 방지한다. 시드 층이 에칭되지 않으면, 또한 구리로 이루어진, 재분배 층은 에칭되지 않는다.

재분배 층의 에칭을 방지하기 위한 재분배 층의 제조를 위한 시스템들 및 방법들

재분배 층의 제조를 위한 시스템들 및 방법들이 기술된다. 기판의 상단부 상에 구리로 이루어진 시드 층의 증착이 없다. 시드 층의 결여는 시드 층을 에칭할 필요성을 방지한다. 시드 층이 에칭되지 않으면, 또한 구리로 이루어진, 재분배 층은 에칭되지 않는다.