Eutectic bonding method and semiconductor device

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

디바이스 다이의 링 구조물

... 다이는 금속 패드, 금속 패드 위에 패시베이션 층 및 패시베이션 층 위에 폴리머 층을 포함한다. 금속 필라가 전기적으로 금속 패드에 위에서 연결된다. 금속 링은 상기 금속 필라와 동일 평면 상에 있다. 상기 폴리머 층은 금속 필라 및 금속 링과 동일 평면 상의 부분을 포함한다.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING INSULATION FILM FORMED ON REAR SURFACE OF SEMICONDUCTOR SUBSTRATE AS MASK WHEN PAD ELECTRODE IS EXPOSED

PURPOSE: A method for manufacturing a semiconductor device is provided to securely contact an electrode inside a via hole with a semiconductor substrate by exposing a pad electrode by selectively removing an insulation film at a bottom portion inside the via hole. CONSTITUTION: A first insulation film(12) is applied on a semiconductor substrate. A pad electrode(11) is formed on the semiconductor substrate. A via hole, which penetrates a surface of the semiconductor substrate from a position corresponding to a pad electrode at a rear surface of the semiconductor substrate, is formed. The first insulation film, which is exposed from a bottom portion of the via hole, is etched away. A second insulation film(17) is formed on the rear surface of the semiconductor substrate. A metal layer(20) is formed on the second insulation film except for the via hole. The second insulation film is etched by using the metal layer as a mask, such that the pad electrode is exposed. The metal layer is removed ...

Solder bump/under bump metallurgy structure for high temperature applications

Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250 DEG C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Semiconductor device and method for manufacturing same

A semiconductor device includes: a semiconductor structure unit; an interconnect layer provided on the major surface side of the semiconductor structure unit; an electrode pad provided on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided, and the electrode pad electrically connected to the interconnect layer; a plurality of metal pillars joined to the electrode pad separately from each other; and an external terminal provided commonly at tips of the plurality of metal pillars, the metal pillars having an area in a plan view smaller than an area in a plan view of the external terminal.

Manufacturing method of package-on-package structure

UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION

Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition.

Cavity formation in interface layer in semiconductor devices

Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming one or more dielectric layers over at least a portion of the electrical connections, and disposing an electrical element at least partially above the one or more dielectric layers, the electrical element being in electrical communication with the FET via the one or more electrical connections. RF device fabrication further involves applying an interface material over at least a portion of the one or more dielectric layers, removing at least a portion of the interface material to form a trench above at least a portion of the electrical element, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity, the electrical element being disposed at least partially within the cavity.

ISOLATION CAVITIES IN SEMICONDUCTOR DEVICES

A semiconductor device includes a transistor implemented over an oxide layer, one or more electrical connections to the transistor, one or more dielectric layers formed over at least a portion of the electrical connections, an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections, a patterned form of sacrificial material covering at least a portion of the electrical element, and an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.

VERFAHREN ZUR HERSTELLUNG EINER VIELZAHL VON HALBLEITERCHIPS, HALBLEITERCHIP UND MODUL MIT EINEM HALBLEITERCHIP

Es werden ein Verfahren zur Herstellung einer Vielzahl von Halbleiterchips, ein Halbleiterchip und ein Modul mit einem Halbleiterchip angegeben. Das Verfahren umfasst dabei die folgenden Schritte: – Bereitstellen einer Anordnung (12) umfassend einen Träger (1) und einen Halbleiterkörper (2), – Ausbilden einer Vielzahl von Ausnehmungen (4) in der Anordnung (12), wobei im Bereich der Ausnehmungen (4) ein Teil des Trägers (1) entfernt wird, – zumindest teilweises Befüllen der Ausnehmungen (4) mit einem elektrisch leitenden Kontaktmaterial (6), und – Trennen der Anordnung (12) entlang einer Vielzahl von Trennlinien (11) in die Vielzahl von Halbleiterchips (10), wobei – die Trennlinien stellenweise durch das elektrisch leitende Kontaktmaterial (6) verlaufen.

REVERSE WIRE BONDING METHOD AT FINE PITCH BUMP FOR PREVENTING FAILURE OF BONDING WIRE AND WIRE BONDING STRUCTURE THEREOF

PURPOSE: A reverse wire bonding method at a fine pitch bump and a wire bonding structure thereof are provided to restrain the failure of a bonding wire such as bending or sweeping. CONSTITUTION: A carrier(100) with a first pad(310) is provided. A semiconductor chip(200) with a second pad(350) is formed on the carrier. The second pad is smaller than the first pad of the carrier. A stud bump(410) is formed on the second pad. A ball bonding type protrusion(510) with a larger diameter that of the stud bump is formed on the first pad and a bonding wire(501) is prolonged from the protrusion to the stud bump in order to connect electrically the first pad with the second pad. © KIPO 2006 ...

IMPROVEMENT OF A SOLDER INTERCONNECT BY ADDING COPPER, WHICH FORMS AN IMC SECTION BETWEEN A SOLDER BUMP AND A BUMP PAD

PURPOSE: An improvement of a solder interconnect by adding copper, which forms an IMC section between a solder bump and a bump pad, is provided to reduce bump malfunction and to improve the mechanical property of a joint between the bump and pad. CONSTITUTION: An improvement of a solder interconnect by adding copper comprises next steps. An electronic device(100) and a substrate(120) are offered. A copper - layer of inclusion is formed on a nickel - layer of inclusion before a reflow process is applied to an electronic device. A solder bump pad(130) is installed on the substrate. COPYRIGHT KIPO 2011 ...

Extended under-bump metal layer for blocking alpha particles in a semiconductor device

An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.

Semiconductor structure and method of manufacturing thereof

Thin 3D die with electromagnetic radiation blocking encapsulation

After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.

Method and apparatus for bonding a wire

A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the first a pad, forming a conductive stud bump on the second pad, and forming a bonding wire that has two terminal portions, which are respectively bonded to the first pad and the stud bump to electrically connect the first pad and the second pad. The stud bump is bonded to the second pad by a ball bonding method which uses a wire that has an approximately smaller diameter than the bonding wire. Further, a prominence formed on one end of the terminal portions is provided which has an approximately larger diameter than the stud bump.

Method of improving copper interconnect of semiconductor devices for bonding

An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

CHIP STRUCTURE AND METHOD FOR FORMING THE SAME

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist

Halbleiterbauelement (200) mit: einem über einem Substrat gebildeten Metallisierungssystem, das mehrere Metallisierungsschichten aufweist, wovon zumindest einige ein dielektrisches Material mit kleinem aufweisen; einer Verspannungspufferschicht (260), die über einer letzten Metallisierungsschicht (140) des Metallisierungssystems (120) gebildet ist, wobei die Verspannungspufferschicht (260) kupferenthaltende Puffergebiete (265) aufweist, die mit kupferenthaltenden Kontaktanschlussflächen (242) in Verbindung stehen, die in der letzten Metallisierungsschicht (140) des Metallisierungssystems (120) vorgesehen und voneinander durch Isoliergräben (266) getrennt sind; bleifreien Kontaktelementen (210), die auf Teilen der kupferenthaltenden Puffergebiete (265) ausgebildet sind; und einem Gehäusesubstrat, das mit dem Metallisierungssystem (120) über die bleifreien Kontaktelemente (210) verbunden ist; und wobei die Verspannungspufferschicht (260) ferner ein dielektrisches Abstandshaltermaterial, das ...

Dichtringstruktur mit Metallpad

Ein Verfahren enthält: Bereitstellen eines Substrats mit einem Dichtringbereich und einem Schaltkreisbereich; Ausbilden einer Dichtringstruktur über dem Dichtringbereich; Ausbilden einer ersten vorderseitigen Passivierungsschicht über der Dichtringstruktur; Ätzen einer vorderseitigen Öffnung in der ersten vorderseitigen Passivierungsschicht benachbart zu einem äußeren Bereich der Dichtringstruktur; Ausbilden eines vorderseitigen Metallpads in der vorderseitigen Öffnung, um das vorderseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln; Ausbilden einer ersten rückseitigen Passivierungsschicht unter der Dichtringstruktur; Ätzen einer rückseitigen Öffnung in die erste rückseitige Passivierungsschicht benachbart zum äußeren Bereich der Dichtringstruktur; und Ausbilden eines rückseitigen Metallpads in der rückseitigen Öffnung, um das rückseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln. Außerdem werden Halbleitervorrichtungen angegeben, die durch ...

Semiconductor device and its making method

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF USING PROTRUDED METAL ELECTRODE

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve connection stability by using a protruded metal electrode arranged on circumference edges of a protective layer. CONSTITUTION: An electrode pad(2) is formed on a semiconductor substrate(1). A wiring(6) is formed adjacent to the surroundings of the electrode pad. A protective layer(4) covers circumference edges of the electrode pad and the wiring. A protruded metal electrode(3) is formed on the electrode pad. The protruded metal electrode is arranged on circumference edges of the protective layer on the wiring. © KIPO 2006 ...

A semiconductor device and the fabrication thereof

The invention relates to create an internal electrode pad (2) on the surface of the semiconductor substrate (1); around the electrode pad (2), there forms surrounding section, wires (6) and the protection films (4) of the semiconductor substrate (1). On the electrode pad (2), there forms a metal protrusion electrode (3), around which, there are wires (6) on the protection films (4) to form the semiconductor device. Because there are wires (6) around the electrode pad (2), surrounding sections of electrode pad (2) and protection film become flat, and the metal protrusion electrode (3) is placed on the protrusion on the flat protection film (4). Therefore, even a small electrode (2) pad is guaranteed to have a flat area on the metal protrusion electrode (3), which assures the connection stability of various conduction sheets such as COG.

Stack bump structure and manufacturing method thereof

A manufacturing method of a stack bump structure including the following steps is provided. First, a substrate having multiple bonding pads disposed on a surface of the substrate is provided. Then, a first bump and a second bump are formed on two neighboring bonding pads on the substrate, respectively. Finally, a third bump is formed between the first bump and the second bump by using the wire bonding technology such that the neighboring bonding pads are electrically connected to each other.

Method for bonding wafers to produce stacked integrated circuits

A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof

A semiconductor chip for flip chip bonding, a mounting structure for the semiconductor chip, and methods for forming a semiconductor chip for flip chip bonding and for fabricating a printed circuit board for a mounting structure of a semiconductor chip are provided which may improve connection between a solder bump of the semiconductor chip and a substrate of the printed circuit board without having to use an underfill material. A polymer core of the solder bump may be supported between a 3-dimensional UBM and a 3-dimensional top surface metallurgy, so as to establish connection strength of the solder bump without using underfill material, and to absorb the stresses which may concentrate on the solder bump due to the difference in coefficients of thermal expansion between metals.

Manufacturing method of semiconductor device

METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT

Fabrication method of electronic device having a sacrificial anode and electronic device fabricated thereby

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Semiconductor device and method for manufacturing same

Semiconductor device with a diffusion barrier film having a spacing for stress relief of solder bump

The present invention provides a semiconductor device exhibiting an improved reliability. A semiconductor device comprises a semiconductor chip having an electrode on a surface thereof and a mounting substrate, and the electrode (aluminum electrode) of the semiconductor chip is coupled to the mounting substrate through a bump (solder bump 104). A plurality of diffusion barrier films (UBM 112) for preventing a diffusion of a material composing the bump is provided between the electrode and the bump, and the diffusion barrier film is formed to have a plurality of divided portions via spacings therebetween.

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME

A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.

RADIO FREQUENCY ISOLATION CAVITY FORMATION USING SACRIFICIAL MATERIAL

Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming one or more dielectric layers over at least a portion of the electrical connections, and disposing an electrical element over the one or more dielectric layers, the electrical element being in electrical communication with the FET via the one or more electrical connections. RF device fabrication further involves covering at least a portion of the electrical element with a sacrificial material, applying an interface material over the one or more dielectric layers, the interface material at least partially covering the sacrificial material, and removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface layer.

TEST AND MANUFACTORING PROCESS Of a JUST ELECTRONIC CIRCUIT

인쇄가능한 반도체소자들의 제조 및 조립방법과 장치

... 본 발명은 인쇄가능한 반도체 소자를 제조하고 기판 표면 상으로 인쇄가능한 반도체 소자를 조립하기 위한 방법 및 장치를 제공한다. 본 발명의 방법, 장치 및 장치 부품은 넓은 범위의 유연한 전자 및 광전자 장치 그리고 중합 재료를 포함하는 기판 상의 장치의 배열 생성이 가능하다. 본 발명은 또한 잡아 늘이거나 압축가능한 반도체 구조물 및 잡아 늘이거나 압축가능한 형태에서 우수한 효율을 보이는 잡아 늘이거나 압축가능한 전자 장치를 제공한다.

Semiconductor device and method

A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.

Method for permanent connection of two metal surfaces

SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM

A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 μm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

POWER MOSFET

A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

Semiconductor device and method of forming low profile fan-out package with vertical interconnection units

A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect ...

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Backside cavity formation in semiconductor devices

Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

SMD/IPD auf Gehäuse oder Vorrichtungsstruktur und Verfahren zu Ihrer Ausbildung

Gehäusestruktur (280), die Folgendes umfasst:einen integrierten Schaltungs-Die (206), der in einem Kapselungsmaterial (212) eingebettet ist;eine Umverteilungsstruktur (258) auf dem Kapselungsmaterial (212) und elektrisch verbunden mit dem integrierten Schaltungs-Die (206), wobei die Umverteilungsstruktur (258) Folgendes umfasst:eine Metallisierungsschicht (234) distal von dem Kapselungsmaterial (212) und dem integrierten Schaltungs-Die (206) undeine dielektrische Schicht (47; 250) distal von dem Kapselungsmaterial (212) unddem integrierten Schaltungs-Die (206) und auf der Metallisierungsschicht (234);eine erste Unter-Metallisierungsstruktur (254) auf der dielektrischen Schicht (47; 250), die Folgendes umfasst:einen ersten Abschnitt (48a), der sich durch eine erste Öffnung der dielektrischen Schicht (47; 250) hin zu einer ersten Struktur der Metallisierungsschicht (44a) erstreckteinen zweiten Abschnitt (48b), der sich durch eine zweite Öffnung der dielektrischen Schicht (47; 250) zu einer ...

IMPROVEMENT OF SOLDER INTERCONNECT BY ADDITION OF COPPER

PROBLEM TO BE SOLVED: To provide a lead-free electronic device that has ensured reliability. SOLUTION: A method of forming an electronic device 100 provides an electronic device substrate having a solder bump pad 130 arranged on the electronic device substrate. A nickel-containing layer is arranged on the solder bump pad and a copper-containing layer is formed on the nickel-containing layer before the electronic device is subjected to a reflow process. COPYRIGHT: (C)2011,JPO&INPIT ...

Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist

Eine Höckerstruktur oder eine Säulenstruktur, die über einem Metallisierungssystem eines komplexen Halbleiterbauelements gebildet ist, enthält eine Verspannungspufferschicht, die resultierende mechanische Verspannung effizient verteilt, die typischerweise während der Wechselwirkung zwischen Chip und Gehäuse auf Grund einer thermischen Fehlanpassung dieser Komponenten auftritt. Die Verspannungspufferschicht enthält kupferbasierte Puffergebiete, die einen wesentlichen Anteil der gesamten Oberfläche abdecken, wobei eine Dicke von ungefähr 3 µm bis 10 µm verwendet wird. Ferner können die Puffergebiet effizient Aluminium als Abschlussmetall ersetzen.

Verbundbauteil und Verfahren zum Herstellen eines Verbundbauteils

Die Erfindung betrifft ein Verbundbauteil (10), mit einem ersten Fügepartner (11) der mittels einer metallischen Zwischenschicht (18) zumindest mittelbar mit einem zweiten Fügepartner (14) verbunden ist, wobei die Zwischenschicht (18) eine Struktur (24) aufweist, in der Zwischenräume (21) ausgebildet sind. Erfindungsgemäß ist es vorgesehen, dass die metallische Zwischenschicht (18) aus wenigstens drei Lagen (19, 20, 22) ausgebildet ist, wobei jeweils eine Lage (19, 20) auf den den beiden Fügepartnern (11, 14) zugewandten Seiten als geschlossene Oberfläche ausgebildet ist und, dass die Struktur (24) zwischen den beiden Lagen als Bestandteil der dritten Lage (22) ausgebildet ist.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor device and method of forming insulating layers around semiconductor die

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.

TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND RELATED BONDED SEMICONDUCTOR STRUCTURES

OF THE DISCLOSURETEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS ANDRELATED BONDED SEMICONDUCTOR STRUCTURESMethods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods. Figure 4 ...

Temporary semiconductor structure bonding methods and related bonded semiconductor structures

Semiconductor device having low dielectric constant film and manufacturing method thereof

A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.

METHOD FOR FABRICATING CHIP PACKAGE

The present invention provides a method for fabricating chip package comprises the following steps: forming a photoresist layer on a metal layer over a passivation layer, an opening in the photoresist layer exposing the metal layer, wherein said forming the photoresist layer comprises exposing the photoresist layer using 1X stepper with at least two of G-line, H-line and I-line; electroplating a gold layer over the metal layer exposed by the opening with an electroplating solution containing gold and sulfite ion; removing the photoresist layer and the metal layer not under the gold layer.

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Method of manufacturing semiconductor device and semiconductor device

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess.

Chip package structure and manufacturing method thereof

A chip package structure including a circuit carrier, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the circuit carrier. The first chip has an active surface and a backside opposite the first active surface, and the first active surface faces the circuit carrier. The frame is disposed on the backside of the first chip and the frame has a plurality of openings. The first conductive connections are disposed on the circuit carrier and are arranged corresponding to the openings. The first encapsulant is disposed between the circuit carrier and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the circuit carrier by the first conductive connections.

INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE WITH A RESILIENT STRESS ABSORBER AND RELATED METHOD OF MANUFACTURE

A semiconductor device (50) having a device substrate (102) is provided The semiconductor device (50) comprises an electrically conductive pad (110) formed overlying the device substrate (102) an electrically conductive platform (160) formed overlying the electrically conductive pad (110) and a pillar interconnect (180) formed on the electrically conductive platform (160) the electrically conductive platform (160) having a perimeter portion (162) extending away from the electrically conductive pad (110) and a capping portion (170) atop the perimeter portion (162), wherein the electrically conductive platform (160) encloses a cavity located between the capping portion (170), the perimeter portion (162) and the electrically conductive pad (110), a cushioning material (140) being disposed in the cavity, the cushioning material (140) being intended to act as a resilient stress absorber upon application of force on the pillar interconnect (180).

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, STRUCTURE FOR MOUNTING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Disclosed is a semiconductor integrated circuit device which can be mounted on a circuit board by capacitive coupling even when the semiconductor integrated circuit device is reduced in dimensions. A passivation film (14) is formed on a main surface (11a) of a semiconductor substrate (11) wherein a plurality of wirings are sequentially laminated with insulating films in between. The passivation film has an opening (15) from which at least a part of a topmost layer wiring (12) is exposed. An electrode (19) is formed to cover the topmost layer wiring (12) exposed from the opening (15) of the passivation film (14) and the periphery of the opening (15) of the passivation film (14), and a dielectric layer (20) is formed to cover the electrode (19). An extending section (19a), which is of the electrode (19) and formed on a surface (14a) of the passivation film (14), and an electrode (4) of the circuit board (2) are capacitively coupled with each other, with a dielectric layer (20) in between.

Semiconductor device and method for producing the semiconductor device

A semiconductor device of the present invention is includes a semiconductor device comprising: a semiconductor chip having a passivation film on an electrode forming surface thereof on which a plurality of electrodes are formed; a protective film which is provided on an upper surface of the passivation film and patterned into a predetermined form; rewiring which is provided on an upper surface of each portion of the protective film divided by patterning and is connected to the electrode; a post connected to the rewiring; and a sealing resin layer which covers the rewiring.

Method of making a semiconductor device comprising a land grid array flip chip bump system with short bumps

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.

Method for producing a metallization having two multiple alternating metallization layers for at least one contact pad and semiconductor wafer having said metallization for at least one contact pad

The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization (40) for at least one contact pad (20) according to the invention comprises the following process steps: applying at least one contact pad (20) to a substrate (10), applying a barrier layer (30) to the top side of the at least one contact pad (20) and applying a metallization (40) to the top side of the barrier layer (30), characterized in that the barrier layer (30) and the metallization (40) are applied by means of physical separation and that the metallization (40) is designed as a layer ...

Method and structure for wafer level packaging with large contact area

A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device having a through-hole electrode is offered to improve reliability and yield of the semiconductor device. A via hole penetrating through a semiconductor substrate is formed at a location corresponding to a pad electrode. An insulation film is formed on a back surface of the semiconductor substrate and a surface of the via hole. A reinforcing insulation film having an overhung portion at a rim of the via hole is formed on the back surface of the semiconductor substrate. The insulation film on a bottom of the via hole is removed by etching using the reinforcing insulation film as a mask, while the insulation film on a side wall of the via hole remains. The through-hole electrode, a wiring layer and a conductive terminal are formed on the back surface of the semiconductor substrate and the via hole. Finally, the semiconductor substrate is divided into a plurality of semiconductor dice by dicing.

Ringstrukturen in Vorrichtungs-Die und Verfahren

Struktur, die Folgendes umfasst:einen Die (100'), der Folgendes umfasst:eine erste Metall-Anschlussstelle (30/30A);eine Passivierungsschicht (32) über der ersten Metall-Anschlussstelle (30/30A);eine Polymerschicht (36) über der Passivierungsschicht (32);eine Metallsäule (40/40A) über der ersten Metall-Anschlussstelle (30/30A) undelektrisch mit ihr verbunden; undeinen Metallring (40/40B), der koplanar mit der Metallsäule (40/40A) ist, wobei die Polymerschicht (36) einen ersten Abschnitt umfasst, der koplanar mit der Metallsäule (40/40A) und dem Metallring (40/40B) ist;eine Formmasse (60) zum Ausformen des Dies (100');mehrere Durchkontaktierungen (58), die die Formmasse (60) durchbrechen;eine dielektrische Schicht (62) mit einer Oberfläche, die die Formmasse (60) kontaktiert; undUmverteilungsleitungen (64) in der dielektrischen Schicht (62) und elektrisch verbunden mit der Metallsäule (40/40A) und den mehreren Durchkontaktierungen (58), wobei der Metallring (40/40B) eine Oberfläche umfasst ...

Seal ring structure with a metal pad

Manufacturing method of package-on-package structure

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

AN INTERCONNECTION STRUCTURE FOR ELECTRONIC COMPONENTS, AN ELECTRONIC COMPONENT AND METHODS FOR PRODUCING THE SAME

An interconnection structure (3; 44) for electronic components comprises a contact pad (6; 46) and an electrically insulating layer (7; 48) which covers the peripheral regions (8; 49) of the contact pad (6; 46). The interconnection structure (3; 44) further comprises an electrically conductive layer (12; 53) disposed on the central portion (9; 52) of the contact pad (6; 46) and on adjacent regions of the electrically insulating layer (7; 48). The inner surface (16; 58) of the electrically conductive layer (12; 53) comprises at least one protrusion (15; 57) disposed in a peripheral region (20; 59).

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Semiconductor device and method of forming low profile fan-out package with vertical interconnect unit

집적 회로 패키지 및 집적 회로 패키지 형성 방법

... 본 발명은 집적 회로 패키지 및 집적 회로 패키지 형성 방법에 관한 것이다. 하나 이상의 재분배 층(RDL)이 캐리어 위에 형성된다. 제1 커넥터가 RDL의 제1 측면에 형성된다. 다이가 제1 커넥터를 이용하여 RDL의 제1 측면에 본딩된다. 캡슐화제가 RDL의 제1 측면에 그리고 다이 주변에 형성된다. 캐리어가 상부의 구조체로부터 디본딩되고, 제2 커넥터가 RDL의 제2 측면에 형성된다. 최종 구조체가 개별 패키지를 형성하도록 다이싱된다.

Samiconductor packaging structure and manufactoring method for the same

A semiconductor packaging structure and a method for manufacturing the same are disclosed. The semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, pads on the top surface, and a passivation layer on the top surface and partly covering the pads. The metal barrier layer is disposed on each of the pads; the dielectric layer is disposed on the passivation layer and the metal barrier layer, and has through recesses to expose the metal barrier layer. The first of metal seed layers is disposed on the dielectric layer and the exposed metal barrier layer, and the second of metal seed layers is disposed on the first metal seed layer. Therefore, the metal barrier layer can effectively prevent the damage of the pads of the chip during the manufacturing process.

SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM

A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 μm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

METHOD FOR PRODUCING A METALLIZATION FOR AT LEAST ONE CONTACT PAD AND SEMICONDUCTOR WAFER HAVING METALLIZATION FOR AT LEAST ONE CONTACT PAD

The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization (40) for at least one contact pad (20) according to the invention comprises the following process steps: applying at least one contact pad (20) to a substrate (10), applying a barrier layer (30) to the top side of the at least one contact pad (20) and applying a metallization (40) to the top side of the barrier layer (30), characterized in that the barrier layer (30) and the metallization (40) are applied by means of physical separation and that the metallization (40) is designed as a layer ...

Method of improving copper interconnects of semiconductor devices for bonding

An improved wire bond with the pond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Method of manufacturing a semiconductor integrated circuit device

The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe area SA are respectively comprised of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. A second pad portion PAD2 as the top of a rewiring 49 on the chip area CA is cleaned. Alternatively, an Au film 53a is formed thereon by an electroles splating method. Further, after the formation of the Au film 53a, a retention test is carried out. Thereafter, further, an Au film 53b is formed and a solder bump electrode 55 is formed. As a result, it is possible to prevent the corrosion of a first pad portion PAD1 of the third layer wiring M3 on the scribe area SA which is TEG due to a plating solution or the like by the TiN film M3c. Further, it is possible to improve the wettability of a solder and the shear ...

FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.

CHIPGEHÄUSE UND VERFAHREN ZUR HERSTELLUNG EINES CHIPGEHÄUSES

Es wird ein Verfahren zur Herstellung eines Chipgehäuses bereitgestellt. Das Verfahren kann Strukturieren mindestens eines Chip-Pads eines Chips zum Bilden einer strukturierten Struktur in dem mindestens einen Chip-Pad, wobei die strukturierte Struktur mindestens eine vordefinierte Aussparung aufweist, und Verkapseln des Chips mit Verkapselungsmaterial, wodurch die mindestens eine vordefinierte Aussparung gefüllt wird, beinhalten.

Improvement of solder interconnect by addition of copper

A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Method for manufacturing semiconductor device

Fan-out type chip packaging structure and manufacturing method thereof

Improvement of solder interconnect by addition of copper

SEALING RING STRUCTURE HAVING A METAL PAD FOR PREVENTING EXFOLIATION BY DIE SAW

PURPOSE: A sealing ring structure having a metal pad is provided to prevent the layer exfoliation of an internal circuit device by secluding a die saw effect at the outer portion of the sealing ring structure by metal pads. CONSTITUTION: A substrate(230) has a sealing ring region and a circuit region. A sealing ring structure(210) is arranged on the sealing ring region. A first front side passivation layer(226) is arranged on the sealing ring structure. A front side metal pad(224) is combined in the outer portion of the sealing ring structure. A second front side passivation layer(222) is arranged on the front side metal pad. A carrier wafer(220) is welded in the second front side passivation layer. COPYRIGHT KIPO 2012 ...

SOLDER BUMP/UNDER BUMP METALLURGY STRUCTURE FOR HIGH TEMPERATURE APPLICATIONS

Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250°C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure. COPYRIGHT KIPO & WIPO 2010 ...

인쇄가능한 반도체소자들의 제조 및 조립방법과 장치

... 본 발명은 인쇄가능한 반도체 소자를 제조하고 기판 표면 상으로 인쇄가능한 반도체 소자를 조립하기 위한 방법 및 장치를 제공한다. 본 발명의 방법, 장치 및 장치 부품은 넓은 범위의 유연한 전자 및 광전자 장치 그리고 중합 재료를 포함하는 기판 상의 장치의 배열 생성이 가능하다. 본 발명은 또한 잡아 늘이거나 압축가능한 반도체 구조물 및 잡아 늘이거나 압축가능한 형태에서 우수한 효율을 보이는 잡아 늘이거나 압축가능한 전자 장치를 제공한다.

Structure and formation method of chip package with fan-out structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Package substrate and fabrication method thereof

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Package with metal-insulator-metal capacitor and method of manufacturing the same

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device having a through-hole electrode is offered to improve reliability and yield of the semiconductor device. A via hole penetrating through a semiconductor substrate is formed at a location corresponding to a pad electrode. An insulation film is formed on a back surface of the semiconductor substrate and a surface of the via hole. A reinforcing insulation film having an overhung portion at a rim of the via hole is formed on the back surface of the semiconductor substrate. The insulation film on a bottom of the via hole is removed by etching using the reinforcing insulation film as a mask, while the insulation film on a side wall of the via hole remains. The through-hole electrode, a wiring layer and a conductive terminal are formed on the back surface of the semiconductor substrate and the via hole. Finally, the semiconductor substrate is divided into a plurality of semiconductor dice by dicing.

METHOD FOR PRODUCING A METALLIZATION FOR AT LEAST ONE CONTACT PAD AND SEMICONDUCTOR WAFER HAVING METALLIZATION FOR AT LEAST ONE CONTACT PAD

Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Method of fabricating electronic device having sacrificial anode, and electronic device fabricated by the same

According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on the substrate. A sacrificial pattern electrically connected to the metal interconnection and serving as a sacrificial anode for cathodic protection against corrosion of the metal interconnection may be formed on the second area. An opening to expose the metal interconnection on the first area may be formed by patterning the insulating layer. An electronic device fabricated by a method according to an example embodiment may include a substrate, a metal interconnection, an insulating layer, and/or a sacrificial pattern.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Protecting bond pad for subsequent processing

A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Method and apparatus of fabricating a pad structure for a semiconductor device

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Three-Dimensional Semiconductor Device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Methods and Structures Involving Terminal Connections

A method for forming a conductive contact includes forming a copper contact region in an intermediary layer, depositing an insulator layer over the copper contact region and the intermediary layer, patterning a photoresist layer on the insulator layer, etching to remove a portion of the insulator layer and expose a portion of the copper contact region, depositing a conductive material layer over the exposed portion of the copper contact region and the photoresist layer, and removing the photoresist layer and the conductive material layer disposed on the photoresist layer.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Semiconductor package including an external circuit element

Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Integrated Inductor

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Integrated circuit and method of making

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Method for separating a plurality of dies and a processing device for separating a plurality of dies

A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Semiconductor package, packaging substrate and fabrication method thereof

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Backside integration of rf filters for rf front end modules and design structure

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Electronic device and electronic component

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

Semiconductor Processing Methods

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Semiconductor device fabrication method

A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Integrated wluf and sod process

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Submicron connection layer and method for using the same to connect wafers

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same

Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Power device and power device module

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Semiconductor device structures and methods for copper bond pads

A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Bonding method and production method

A bonding method of the present invention is a method of bonding two members (A and B) to each other with use of an Au—Sn solder. According to the bonding method of the present invention, after the bonding, an Au—Sn solder (S′) has weight percent of Sn which is not less than 38.0 wt % but not more than 82.3 wt %.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.