Chip package, wafer level chip array and manufacturing method thereof

SEMICONDUCTOR DEVICE

The surface on the mounting substrate side of a semiconductor element is layered with an ohmic contact layer contiguous to said surface, a metal diffusion barrier layer contiguous to the ohmic contact layer, a solder bond barrier layer contiguous to the metal diffusion barrier layer, and a bismuth-containing solder layer contiguous to the solder bond barrier layer. The bonding reliability of a semiconductor device formed by bonding a semiconductor element and a mounting substrate with a solder material having Bi as a main ingredient is improved.

WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF

A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Pad structure for front side illuminated image sensor

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate ...

Backlight Unit and Display Device Including the Same

A backlight unit and a display device including the same are disclosed. More specifically, a backlight unit is disclosed that includes a plurality of light sources disposed on a glass substrate and disposed in a plurality of rows and a plurality of columns, and first and second transistors disposed on the glass substrate and spaced apart from each other, wherein each of the first transistor and the second transistor is disposed so as not to overlap the plurality of light sources disposed at points where two rows and two columns cross each other. Thus, image quality is excellent.

반도체 장치

... 반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

DISPLAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure discloses a display substrate and a display device. The display substrate includes: a base substrate, including a display area and a bonding area located on at least one side of the display area, wherein the bonding area includes terminal areas and spacing areas between any two adjacent terminal areas among the terminal areas; connection terminals arranged in the terminal areas; a first inorganic insulating layer located on a side, where the connection terminals are arranged, of the base substrate; and a first organic insulating layer disposed between the base substrate and the first inorganic insulating layer and surrounding the bonding area.

FABRICATION OF CIRCUIT MODULE

PROBLEM TO BE SOLVED: To provide a fabrication method of a circuit module which can load electric components without giving mechanical and thermal stress. SOLUTION: A laser beam transmitting board 3 is used, a junction material which can thermally fuse a bump 5 to a conductor 4 is provided to a terminal electrode 2 and the laser beam 7 is irradiated to the junction area from the lower surface side of the board 3 after an element 1 is arranged to the mounting surface of the board 3. Thereby, the junction material 6 is thermally fused with the laser beam 7 having transmitted through the board 3 to connect the terminal electrode 2 of the element 1 and conductor 4 of the board 3. COPYRIGHT: (C)1997,JPO ...

Semiconductor structure and method of manufacturing the same

提供了一種半導體結構以及形成該半導體結構的方法。該半導體結構包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面；以及傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積；其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。

INTEGRATED ELECTRONIC DEVICE WITH A REDISTRIBUTION REGION AND A HIGH RESILIENCE TO MECHANICAL STRESSES

An integrated device includes a semiconductor body and a dielectric layer bounded by a surface. A conductive region of a first metal material forms a via region extending into a hole passing through the dielectric layer, and an overlaid redistribution region which extends over the surface. At least one barrier region of a second metal material extends into the hole and surrounds the via region, and the barrier region furthermore extending over the surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the surface. A second coating layer of a fourth metal material extends at a distance from the surface and covers the first coating layer, and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier region extending over the surface.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an AlSi (aluminum-silicon alloy) layer, an AlCu (aluminum-copper alloy) layer and an AlSiCu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Halbleitervorrichtung und Verfahren zu deren Herstellung

Halbleitervorrichtung, mit: einem Halbleitersubstrat; und einer oberen Oberflächenelektrode, die auf einer oberen Oberfläche des Halbleitersubstrates geschichtet ist, wobei zumindest ein Abschnitt der oberen Oberflächenelektrode eine auf einer oberen Oberflächenseite des Halbleitersubstrates ausgebildete erste Schicht, eine auf einer oberen Oberflächenseite der ersten Schicht ausgebildete zweite Schicht, eine in Kontakt mit der oberen Oberfläche der zweiten Schicht befindliche dritte Schicht, sowie eine auf einer oberen Oberflächenseite der dritten Schicht ausgebildete vierte Schicht beinhaltet, die erste Schicht eine Barrierenmetallschicht ist, die zweite Schicht eine Aluminiumschicht ist, die dritte Schicht eine Aluminiumsiliziumschicht, eine Aluminiumkupferschicht oder eine Aluminiumsiliziumkupferschicht ist, und die vierte Schicht eine Lötmittelverbindungsschicht ist.

Flip chip

Semiconductor structure and method of manufacturing the same

提供了一種半導體結構以及形成該半導體結構的方法。該半導體結構包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面；以及傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積；其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Integrated circuits and methods for fabricating the same

本揭露為有關於具有接合墊的積體電路，接合墊具有相對平坦的表面形貌而能減輕對下方層的損害。在一些實施例中，積體電路具有複數個金屬內連線層在基底上方的介電結構中。保護結構設置於介電結構上方，保護結構具有凹口，凹口有著側壁連接保護結構的水平面至保護結構的上表面。接合墊設置於凹口中且具有下表面覆蓋水平面。一個或多個突出部從下表面向外延伸穿過保護結構中的開口，以接觸金屬內連線層中的一個。將接合墊設置於凹口中且位於保護結構上方，使在接合期間能減輕對下方層的應力，而不會負面影響基底中的影像感測元件的效能。

Collars for under-bump metal structures and associated systems and methods

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device is provided that can minimize the occurrence of poor joining between a copper electrode and a copper wire. The semiconductor device includes a semiconductor substrate; a copper electrode layer formed on the semiconductor substrate; a metallic thin-film layer formed on the copper electrode layer for preventing oxidation of the copper electrode layer, the metallic thin-film layer having an opening through which the copper electrode layer is exposed, the opening being located on an inner side relative to an outer periphery of the metallic thin-film layer; and an interconnection member containing copper as a main component, the interconnection member including a joining region covering the opening, the interconnection member being joined to the metallic thin-film layer and joined to the copper electrode layer in the opening.

Method of manufacturing circuit module

The present invention relates to a method of manufacturing a circuit module through the use of a wireless bonding technique. In this invention, in order to achieve component assembly without experiencing thermal and mechanical stresses, in the circuit module manufacturing method in which an external electrode (2) of a component (1) and a conductor (4) of a substrate (3) are connected with each other according to the wireless bonding technique, the substrate has a laser beam (7) transmissible property, and after the component is placed on an assembly surface of the substrate, a laser beam is applied from a surface of the substrate opposite to the assembly surface thereof to a connecting spot. The laser beam passing through the substrate heats the connecting spot so that the connection between the external electrode of the component and the conductor of the substrate is made by phase transition or diffusion. ...

Nickel Alloy for Semiconductor Packaging

A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

Method of manufacturing circuit module

HALBLEITERVORRICHTUNG UND VERFAHREN ZUR HERSTELLUNG VONHALBLEITERBAUELEMENTEN

Es wird ein Halbleiterbauelement aufgezeigt, welches das Auftreten einer schlechten Verbindung zwischen einer Kupferelektrode und einem Kupferdraht minimieren kann. Das Halbleiterbauelement weist Folgendes auf: Ein Halbleitersubstrat (1); eine auf dem Halbleitersubstrat (1) gebildete Kupferelektrodenschicht (2); eine auf der Kupferelektrodenschicht (2) gebildete metallische Dünnschicht (3) zur Verhinderung der Oxidation der Kupferelektrodenschicht (2), wobei die metallische Dünnschicht (3) eine Öffnung (31) aufweist, durch die die Kupferelektrodenschicht (2) freigelegt wird, wobei die Öffnung (31) auf einer Innenseite relativ zu einem Außenumfang der metallischen Dünnschicht (3) angeordnet ist; und ein Verbindungselement (4), das Kupfer als Hauptkomponente enthält, wobei das Verbindungselement (4) einen die Öffnung (31) abdeckenden Verbindungsbereich beinhaltet, wobei das Verbindungselement (4) mit der metallischen Dünnschicht (3) verbunden und mit der Kupferelektrodenschicht (2) in der Öffnung (31) verbunden ist.

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING THE SAME

Nickel alloy for semiconductor packaging

A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

Verfahren zur Herstellung von Halbleitervorrichtungen und entsprechende Vorrichtung

In einer Ausführungsform weist ein Verfahren zum Herstellen von Halbleitervorrichtungen, die Metallisierungen (36, 38, 40) mit peripheren Abschnitten aufweisen, wobei mindestens eine unterliegende Schicht (20, 24) Randbereiche aufweist, die sich den peripheren Abschnitten zugewandt erstrecken, auf: – Bereitstellen einer Opferschicht (26) zum Bedecken der Randbereiche der unterliegenden Schicht (20, 24), – Bereitstellen der Metallisierungen (36, 38, 40), während die Randbereiche der unterliegenden Schicht (20, 24) von der Opferschicht (26) bedeckt sind, und – Entfernen der Opferschicht (26), so dass die Randbereiche der unterliegenden Schicht (20, 24) sich den peripheren Abschnitten ohne eine Kontaktgrenzfläche dazwischen zugewandt erstrecken, wodurch thermomechanische Belastungen vermieden werden.

Method of manufacturing circuit module

The present invention relates to a method of manufacturing a circuit module through the use of a wireless bonding technique. In this invention, in order to achieve component assembly without experiencing thermal and mechanical stresses, in the circuit module manufacturing method in which an external electrode of a component and a conductor of a substrate are connected with each other according to the wireless bonding technique, the substrate has a laser beam transmissible property, and after the component is placed on an assembly surface of the substrate, a laser beam is applied from a surface of the substrate opposite to the assembly surface thereof to a connecting spot. The laser beam passing through the substrate heats the connecting spot so that the connection between the external electrode of the component and the conductor of the substrate is made by phase transition or diffusion.

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

반도체 구조체 및 그 제조 방법

... 반도체 구조체 및 반도체 구조체를 형성하는 방법이 제공된다. 반도체 구조체는: 반도체 칩; 상기 반도체 칩의 활성 표면에 대면하는 기판; 및 상기 반도체 칩의 상기 활성 표면으로부터 상기 기판을 향해 연장되는 도전성 범프를 포함하고, 상기 도전성 범프는: 제1 그룹의 범프 세그먼트들 및 제2 그룹의 범프 세그먼트들을 포함하는 복수의 범프 세그먼트들을 포함하고, 각 범프 세그먼트는 상기 반도체 칩의 상기 활성 표면에 수직인 방향으로 동일한 세그먼트 높이를 갖고, 각 범프 세그먼트는 상기 세그먼트 높이와 상기 범프 세그먼트의 평균 단면적의 곱에 의하여 정의되는 부피를 가지며; 상기 제2 그룹의 범프 세그먼트들의 총 부피에 대한 상기 제1 그룹의 범프 세그먼트들의 총 부피의 비율은 약 0.03과 약 0.8의 사이이다.

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

Wafer level array of chips and method thereof

本發明提供一種晶圓級晶片陣列，包含一半導體晶圓，具有至少二晶片相鄰排列以及一承載層，各該晶片具有一上表面及一下表面，且包含至少一電子元件於該上表面，該承載層覆蓋於各該晶片之上表面；以及至少一外延線保護塊，配置於該承載層之下且位於該至少二晶片之間，該外延線保護塊之厚度小於該晶片之厚度，其中，該外延線保護塊內部具有至少一外延線。此外，本發明亦提供該晶圓級晶片陣列所製作的晶片封裝體及其製造方法。

Pad structure for front side illuminated image sensor

The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.

Pad structure for front side illuminated image sensor

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

Semiconductor device having a barrier layer made of amorphous molybdenum nitride and method for producing such a semiconductor device

A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer having a front face and a back face is disposed over the semiconductor body so that the back face of the front surface metallization layer faces the front face of the semiconductor body and is electrically connected to the active zone. An upper barrier layer made of amorphous molybdenum nitride is disposed on the front face of the front surface metallization layer.

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN DIESER

Eine Halbleitervorrichtung umfasst einen Halbleiterkörper mit einer Vorderseite und einer Rückseite, der eine sich an der Vorderseite befindenden aktive Zone, eine Vorderoberflächenmetallisierungsschicht mit einer Vorderseite und einer der aktiven Zone zugewandten Rückseite, wobei die Vorderoberflächenmetallisierungsschicht auf der Vorderseite des Halbleiterkörpers bereitgestellt ist und mit der aktiven Zone elektrisch verbunden ist, und eine erste Barriereschicht, die amorphes Metallnitrid umfasst und zwischen der aktiven Zone und der Metallisierungsschicht angeordnet ist, aufweist. Zudem wird ein Verfahren zum Herstellen einer solchen Vorrichtung bereitgestellt.

Halbleitervorrichtung und Verfahren zu deren Herstellung

Eine als eine Barrierenmetallschicht dienende erste Schicht, eine als eine Aluminiumschicht dienende zweite Schicht, eine als eine Aluminiumsiliziumschicht, Aluminiumkupferschicht oder Aluminiumsiliziumkupferschicht dienende dritte Schicht, und eine als eine Lötmittelverbindungsschicht dienende vierte Schicht sind als obere Oberflächenelektroden einer Halbleitervorrichtung in dieser Reihenfolge auf einer oberen Oberfläche eines Halbleitersubstrates geschichtet. Die vierte Schicht kann durch einen nichtelektrolytischen Plattierungsvorgang ausgebildet werden, nachdem die dritte Schicht einer Zinksubstitutionsbehandlung unterzogen wurde. Diese obere Oberflächenelektrode kann einen ohmschen Kontakt zwischen dem Halbleitersubstrat und der oberen Oberflächenelektrode sicherstellen, und eine obere Oberfläche der dritten Schicht mit einer vorteilhaften Ebenheit versehen. Durch Durchführen der Zinksubstitutionsbehandlung auf der dritten Schicht kann eine zinksubstituierte Schicht mit ausgezeichneter Anhaftung und Ebenheit durchgeführt werden. Diese Vorgänge können die vierte Schicht als eine Schicht von vorteilhafter Ebenheit ausbilden.

Mounting substrate and method of manufacturing mounting substrate

Solder Ball Pad Structure

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

NIckel Alloy for Semiconductor Packaging

A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound. 1. A method for fabricating a semiconductor wafer , comprising:providing a fully processed semiconductor wafer that includes more than one semiconductor die, the semiconductor wafer having a front side containing copper leads of said more than one semiconductor die and a back side that is opposite to said front side;etching selected portions of a protective overcoat layer from said fully processed semiconductor wafer to expose a top surface of said copper leads;forming a copper seed layer over said front side of said semiconductor wafer; andcoating said front side of said semiconductor wafer with a nickel alloy that includes tungsten and cerium (NiWCe).2. The method of wherein said coating is electroplated.3. The method of wherein said copper seed layer is formed by sputtering.4. The method of wherein an amount of said tungsten in said nickel alloy is 10.0 wt %.5. The method of ...

Method for producing substrate, and substrate

To prevent a tin alloy from coming into contact with a copper wiring layer during reflow of a tin alloy bump layer. One embodiment of the present invention provides a method for producing a substrate which has a bump at an opening of a resist. This method for producing a substrate comprises: a step for forming a copper wiring layer on a substrate by plating at a first temperature; a step for forming a barrier layer on the copper wiring layer by plating at a second temperature that is equivalent to the first temperature; and a step for forming a tin alloy bump layer on the barrier layer by plating.

Mounting substrate and method of manufacturing the same

A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.

Underbump metallization structure

A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

Flip chip

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

Semiconductor Device and Method for Producing the Same

A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Method of manufacturing circuit module

The present invention relates to a method of manufacturing a circuit module through the use of a wireless bonding technique. In this invention, in order to achieve component assembly without experiencing thermal and mechanical stresses, in the circuit module manufacturing method in which an external electrode of a component and a conductor of a substrate are connected with each other according to the wireless bonding technique, the substrate has a laser beam transmissible property, and after the component is placed on an assembly surface of the substrate, a laser beam is applied from a surface of the substrate opposite to the assembly surface thereof to a connecting spot. The laser beam passing through the substrate heats the connecting spot so that the connection between the external electrode of the component and the conductor of the substrate is made by phase transition or diffusion.

Semiconductor device and method for producing the same

A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

Wafer level array of chips and method thereof

A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.

Semiconductor device and manufacturing method thereof

本发明提供了具有改善的可靠性的半导体装置。焊盘包括形成为穿过该焊盘的缝隙部分，并且还包括在平面视图中位于缝隙部分内侧的接合部分，以及在平面视图中位于缝隙部分外侧的边缘部分。在平面视图中，通孔围绕缝隙部分并且与焊盘的接合部分和焊盘的边缘部分接触。

Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

Semiconductor structure having a conductive bump with a plurality of bump segments

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

Array substrate and method for manufacturing the same, and display apparatus

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

Semiconductor device

Nickel alloy for semiconductor packaging

A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead ...

Semiconductor structure having counductive bump with tapered portions and method of manufacturing the same

A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.

SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREOF

A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

SEMICONDUCTOR DEVICE HAVING A MOLECULAR BONDING LAYER FOR BONDING ELEMENTS

A semiconductor device includes a substrate including, on a surface thereof, a first conductive pad and a first insulating layer formed around the first conductive pad, a semiconductor chip including, on a surface thereof, a second conductive pad and a second insulating layer around the second conductive pad, an intermediate layer formed between the substrate and the semiconductor chip, and including a conductive portion between the first and second conductive pads, and an insulating portion between the first and second insulating layers, and a molecular bonding layer formed between the substrate and the intermediate layer, and including at least one of a first molecular portion covalently bonded to a material of the first conductive pad and a material of the conductive portion, and a second molecular portion covalently bonded to a material of the first insulating layer and a material of the insulating portion.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME

METHOD OF MANUFACTURING SUBSTRATE AND THE SAME SUBSTRATE

To prevent a tin alloy from coming into contact with a copper wiring layer when a tin alloy bump layer is reflowed. According to an aspect of the present invention, a method of manufacturing a substrate having a bump at a resist opening is provided. The method of manufacturing a substrate includes a step of forming a copper wiring layer on the substrate by plating at a first temperature, a step of forming a barrier layer on the copper wiring layer by plating at a second temperature that is approximately equal to the first temperature, and a step of forming a tin alloy bump layer on the barrier layer by plating.

SEMICONDUCTOR DEVICE AND A CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

Pad structure for front side illuminated image sensor

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

For front-illuminated Image sensor pad structure and its forming method

Semiconductor Device and Method for Producing a Semiconductor Device

A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Underbump Metallization Structure

A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

Solder ball pad structure

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.

Wafer level array of chips and method thereof

Solder ball pad structure

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.

SEMICONDUCTOR DIE HAVING AN OPTICAL DETECTION MARKER AND METHOD OF PRODUCING THE SEMICONDUCTOR DIE

A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.

Solder Ball Pad Structure

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate. 1. An integrated circuit , comprising:a plurality of metal interconnect layers arranged within a dielectric structure over a semiconductor substrate;a passivation structure arranged over the dielectric structure and having a recess within an upper surface of the passivation structure, wherein the recess comprises sidewalls connecting a horizontal surface of the passivation structure to the upper surface; anda bond pad arranged within the recess and having a lower surface that overlies the horizontal surface, wherein the bond pad comprises one or more protrusions extending outward from the lower surface of the bond pad through openings in the passivation structure to contact one of the plurality of metal interconnect layers.2. The integrated circuit of claim 1 , further comprising:a second recess arranged within a top surface of the dielectric structure and having sidewalls contacting a horizontal surface of the dielectric structure to the top surface, wherein the passivation ...

DISPLAY DEVICE AND TILED DISPLAY DEVICE

Provided are a display device and a tiled display device. The display device according to one or more embodiments includes a substrate, transistors above the substrate, a first organic insulating layer above the transistors, a first connection electrode above the first organic insulating layer, and electrically connected to at least one of the transistors, a second connection electrode above the first organic insulating layer, a first power supply line configured to receive a first power voltage, above the first organic insulating layer, and connected to the second connection electrode, and a second organic insulating layer above the first power supply line, and defining an opening area exposing the first power supply line.

ELECTRONIC COMPONENT

An electronic component includes a chip that has a main surface, an insulating layer that is laminated at a thickness exceeding 2200 nm on the main surface and has a first end on the chip side and a second end on an opposite side to the chip, and a resistive film that is arranged inside the insulating layer such as not to be positioned within a thickness range of less than 2200 nm on a basis of the first end and includes an alloy crystal constituted of a metal element and a nonmetal element.

SEMICONDUCTOR DEVICE AND A CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

MOUNTING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

... (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.

Semiconductor device and manufacturing method for same

A semiconductor device has: a pad electrode 9a formed on the uppermost layer of a plurality of wiring layers; a base insulation film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulation film 11; a rewiring RM formed on the base metal film UM; and a cap metal film CM formed so as to cover the top surface and side surface of the rewiring RM. In the region on the outer side of the rewiring RM, the base metal film UM, which is of a different material from the rewiring RM, and the cap metal film CM, which is of a different material from the rewiring RM, are formed between the cap metal film CM and the base insulation film 11 formed on the side wall of the rewiring RM, and in the region on the outer side of the rewiring RM, the base metal film UM and the cap metal film CM are directly in contact.

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes: a pad electrode 9 a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11 a on the pad electrode 9 a ; a base metal film UM formed on the base insulating film 11 ; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11 , and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Semiconductor device and method for the production thereof

Method of manufacturing semiconductor devices and corresponding device

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

Semiconductor device and method for manufacturing the same

A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al-Si (aluminum-silicon alloy) layer, an Al-Cu (aluminum-copper alloy) layer and an Al-Si-Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.

Semiconductor Device and Method for Producing the Same

半导体器件和用于生产其的方法。半导体器件包括：具有前端面和后端面的半导体主体，其具有位于前端面处的有源区；具有前端面和指向有源区的后端面的前表面金属化层，前表面金属化层被提供在半导体主体的前端面上并电连接到有源区；以及包括非晶金属氮化物的第一阻挡层，其位于有源区和金属化层之间。此外，提供了用于生产这样的器件的方法。

Solder ball pad structure

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.

DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME

A display device includes a substrate including a display area and a pad area; a first conductive layer including a first pad electrode in the pad area; and a second conductive layer the second conductive layer includes a second pad electrode on the first pad electrode in the pad area; the first pad electrode and the second pad electrode overlap in a first direction that is a thickness direction, and do not overlap in a second direction perpendicular to the first direction.

COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM USING THE SAME

Adhesive strength between a rewiring and a solder bump is improved in a semiconductor integrated circuit device in which a bump electrode is connected to a land section of the rewiring. The land section 20A of the rewiring 20 is formed by a five-layer metal film (a barrier metal film 13, a seed film 14, a Cu film 15, a first Ni film 16, and a second Ni film 17) constituting the rewiring 20, the uppermost-layer second Ni film 17 has a larger area than that of the other metal films (the barrier metal film 13, the seed film 14, the Cu film 15, and the first Ni film 16). A solder bump 21 is connected to the surface of the second Ni film 17. At the end portion of the solder bump 21, a polyimide resin film 22 is formed directly under the second Ni film 17.

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

用于凸块下金属结构的套环及相关联的系统及方法

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Collar for under-bump metal structures and related systems and methods

본 기술은 다이-다이 및/또는 패키지-패키지 간의 인터커넥트 및 관련 시스템을 위한 언더-범프 금속(UBM) 구조체용 칼라의 제조에 관한 것이다. 반도체 다이는 반도체 고체 상태 구성요소를 가진 반도체 재료와, 반도체 재료를 통해 적어도 부분적으로 연장되는 인터커넥트를 포함한다. 언더-범프 금속(UBM) 구조체는 반도체 재료 위에 형성되고 대응하는 인터커넥트에 전기적으로 결합된다. 칼라는 UBM 구조체의 측면의 적어도 일부를 둘러싸고, 솔더 재료는 UBM 구조체의 상부면 위에 배치된다. The present technology relates to the manufacture of collars for under-bump metal (UBM) structures for interconnect and related systems between die-die and/or package-package. The semiconductor die includes a semiconductor material having a semiconductor solid state component and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to a corresponding interconnect. The collar surrounds at least a portion of the side of the UBM structure, and the solder material is disposed over the top surface of the UBM structure.

Mounting board manufacturing method

Collar for under bump metal structure and associated systems and methods

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Semiconductor device and manufacturing method for same

Flip chip

本发明一实施例的倒装芯片，其特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。本发明的倒装芯片能够防止超声波焊接时焊盘上产生裂纹。

Semiconductor device

반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

半導体装置、及び半導体装置の製造方法

銅を用いた電極と銅を用いたワイヤとの接合形成における銅電極とワイヤとの接合不良の発生を抑制した半導体装置を得る。半導体基板（１）と、半導体基板（１）上に形成された銅電極層（２）と、銅電極層（２）上に形成され外周部よりも内側に銅電極層（２）を露出した開口部（３１）を有し、銅電極層（２）の酸化を防止する金属薄膜層（３）と、開口部（３１）を覆う接合領域（２０）を有し金属薄膜層（３）と開口部（３１）で銅電極層（２）とに接合する銅を主成分とする配線部材（４）と、を備えた半導体装置。

基板の製造方法及び基板

スズ合金バンプ層のリフロー時にスズ合金が銅配線層に接触することを抑制する。　本発明の一形態によれば、レジスト開口部にバンプを有する基板の製造方法が提供される。この基板の製造方法は、基板上に第１の温度で銅配線層をめっきする工程と、前記銅配線層上に第１の温度と同等の第２の温度でバリア層をめっきする工程と、前記バリア層上にスズ合金バンプ層をめっきする工程と、を有する。

백라이트 유닛 및 이를 포함하는 디스플레이 장치

본 개시의 실시예들은, 백라이트 유닛 및 이를 포함하는 디스플레이 장치에 관한 것으로서, 더욱 상세하게는, 유리 기판 상에 배치되고 다수의 행과 다수의 열에 배치된 다수의 광원, 유리 기판 상에 배치되고 서로 이격된 제1 및 제2 트랜지스터를 포함하며, 하나의 제1 트랜지스터와 하나의 제2 트랜지스터 각각은 두 개의 행과 두 개의 열이 교차하는 지점에 배치된 다수의 광원들과 미 중첩하도록 배치됨으로써, 화상 품위가 우수한 백라이트 유닛 및 이를 포함하는 디스플레이 장치를 제공할 수 있다.

반도체 구조체 및 그 제조 방법

반도체 구조체 및 반도체 구조체를 형성하는 방법이 제공된다. 반도체 구조체는: 반도체 칩; 상기 반도체 칩의 활성 표면에 대면하는 기판; 및 상기 반도체 칩의 상기 활성 표면으로부터 상기 기판을 향해 연장되는 도전성 범프를 포함하고, 상기 도전성 범프는: 제1 그룹의 범프 세그먼트들 및 제2 그룹의 범프 세그먼트들을 포함하는 복수의 범프 세그먼트들을 포함하고, 각 범프 세그먼트는 상기 반도체 칩의 상기 활성 표면에 수직인 방향으로 동일한 세그먼트 높이를 갖고, 각 범프 세그먼트는 상기 세그먼트 높이와 상기 범프 세그먼트의 평균 단면적의 곱에 의하여 정의되는 부피를 가지며; 상기 제2 그룹의 범프 세그먼트들의 총 부피에 대한 상기 제1 그룹의 범프 세그먼트들의 총 부피의 비율은 약 0.03과 약 0.8의 사이이다.

包括含有接合层级介电层的气隙的接合组件及其形成方法

一种接合组件包括第一半导体裸片，该第一半导体裸片包括第一衬底、第一半导体器件和由第一焊盘层级介电层横向围绕的第一接合焊盘。该第一焊盘层级介电层包括至少一个第一包封气隙，该至少一个第一包封气隙位于相邻的第一接合焊盘对之间并且被该第一焊盘层级介电层的第一介电填充材料包封。该接合组件包括第二半导体裸片，该第二半导体裸片包括第二衬底、第二半导体器件和由第二焊盘层级介电层横向围绕的第二接合焊盘。该第二接合焊盘中的每个第二接合焊盘接合到该第一接合焊盘中的相应一个第一接合焊盘。

Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same

A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

阵列基板及显示装置

本公开实施例公开了一种阵列基板及显示装置，涉及显示技术领域，用于避免对源漏导电层造成腐蚀，进而避免应用有该阵列基板的显示装置出现撕膜斜纹不良，改善该显示装置的显示效果。该阵列基板，具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括：衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区，所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。本公开提供的阵列基板及显示装置用于实现触控及显示。

Wafer level chip scale package of power semiconductor and manufacutring method thereof

A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.

Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same

A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

背光单元以及包括背光单元的显示装置

本公开的实施例涉及背光单元以及包括背光单元的显示装置，并且更具体地，可以提供一种背光单元，该背光单元包括：多个光源，其设置在基板上并且被设置成多行和多列；以及第一晶体管和第二晶体管，其设置在基板上并且彼此间隔开，其中，第一晶体管和第二晶体管中的每一个被设置在两行光源和两列光源彼此交叉的区域以不与多个光源交叠，因此图像质量优异。本公开的实施例还可以提供包括该背光单元的显示装置。

Bridging-resistant microbump structures and methods of forming the same

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

接合組裝

接合組裝包括第一結構與第二結構。第一結構包括含有開口於其中的鈍化介電層所圍繞的第一金屬連接結構，以及第一金屬凸塊結構，其具有個別的第一水平接合表面部分自含有鈍化介電層的遠端水平表面的第一水平平面垂直凹陷。第二結構包括第二金屬凸塊結構，其具有個別的第二水平接合表面部分朝第一結構凸起。第一金屬凸塊結構經由焊料材料部分接合至第二金屬凸塊結構。

半導体装置、及び半導体装置の製造方法

銅を用いた電極と銅を用いたワイヤとの接合形成における銅電極とワイヤとの接合不良の発生を抑制した半導体装置を得る。半導体基板（１）と、半導体基板（１）上に形成された銅電極層（２）と、銅電極層（２）上に形成され外周部よりも内側に銅電極層（２）を露出した開口部（３１）を有し、銅電極層（２）の酸化を防止する金属薄膜層（３）と、開口部（３１）を覆う接合領域（２０）を有し金属薄膜層（３）と開口部（３１）で銅電極層（２）とに接合する銅を主成分とする配線部材（４）と、を備えた半導体装置。

Elektronische komponente

Eine elektronische Komponente schließt einen Chip, der eine Hauptoberfläche, eine Isolierschicht, die mit einer Dicke von mehr als 2200 nm auf die Hauptoberfläche laminiert ist und ein erstes Ende auf der Chipseite und ein zweites Ende auf einer dem Chip gegenüberliegenden Seite aufweist, und einen Widerstandsfilm ein, der innerhalb der Isolierschicht so angeordnet ist, dass er nicht innerhalb eines Dickenbereichs von weniger als 2200 nm auf der Basis des ersten Endes positioniert ist, und einen Legierungskristall einschließt, der aus einem Metallelement und einem Nichtmetallelement aufgebaut ist.

制造半导体器件的方法和对应的器件

本申请涉及制造半导体器件的方法和对应的器件。在一个实施例中，一种方法制造半导体器件，该半导体器件包括具有外围部分的金属化结构，该外围部分具有一个或多个下覆层，该下覆层具有面向外围部分延伸的边缘区域。方法包括：提供牺牲层以覆盖下覆层的边缘区域，在由牺牲层覆盖下覆层的边缘区域的同时提供金属化结构，以及移除牺牲层以使得下覆层的边缘区域面向外围部分延伸而在两者之间没有接触界面，由此避免热机械应力。

Pad structure for front side illuminated image sensor

The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.

기판의 제조 방법 및 기판

주석 합금 범프층의 리플로우 시에 주석 합금이 구리 배선층에 접촉하는 것을 억제한다. 본 발명의 일 형태에 의하면, 레지스트 개구부에 범프를 갖는 기판의 제조 방법이 제공된다. 이 기판의 제조 방법은, 기판 상에 제1 온도에서 구리 배선층을 도금하는 공정과, 상기 구리 배선층 상에 제1 온도와 동등한 제2 온도에서 배리어층을 도금하는 공정과, 상기 배리어층 상에 주석 합금 범프층을 도금하는 공정을 갖는다.

表面照射型イメージセンサ用パッド構造及びその形成方法

Semiconductor device

This invention provides a semiconductor device with improved reliability. A pad includes a slit portion formed so as to pass through the pad, and also includes a bonding portion positioned inside the slit portion in plan view, and an edge portion positioned outside the slit portion in plan view. In plan view, a via encloses the slit portion and is in contact with the bonding portion of the pad and the edge portion of the pad.

Bonding element and method for manufacturing the same

A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.

功率半导体的晶圆片级芯片规模封装及其制造方法

公开了功率半导体的晶圆片级芯片规模封装及其制造方法。晶圆片级芯片规模封装包括：具有第一厚度的半导体衬底；形成在半导体衬底上的输入‑输出垫；形成在输入‑输出垫上的具有第二厚度的前金属层；形成在半导体衬底的底部上的具有第三厚度的后金属层；以及形成在半导体衬底上的金属凸块。

전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법

본 발명은 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지에 관한 것이다. 본 발명은 제1 두께의 반도체 기판 상면에 제2 두께의 전면 메탈층과 상기 반도체 기판의 하면에 제3 두께의 백 메탈층을 포함하는 패키지 구조이다. 전면 메탈층과 백 메탈층은 열 팽창계수가 동일한 금속재질로 형성된다. 그래서 패키지를 PCB 기판에 실장하는 SMT 공정시 패키지의 휨 현상을 제거할 수 있어, 조립 불량율을 최소화하는 효과가 있다.

顯示裝置及拼接顯示裝置

本發明提供了一種顯示裝置及拼接顯示裝置，根據一個或多個實施例的顯示裝置包含：基板、電晶體、第一有機絕緣層、第一連接電極、第二連接電極、第一電源線以及第二有機絕緣層，電晶體位於基板上，第一有機絕緣層位於電晶體上，第一連接電極位於第一有機絕緣層上並且電性連接至至少一電晶體，第二連接電極位於第一有機絕緣層上，第一電源線位於第一有機絕緣層上，第一電源線係配置以接收第一電源電壓並且連接第二連接電極，第二有機絕緣層位於第一電源線上並且定義開口區域，以暴露第一電源供應線。

[UNK]

显示设备和拼接显示设备

提供了显示设备和拼接显示设备。根据一个或多个实施方式的显示设备包括：衬底；晶体管，在衬底上方；第一有机绝缘层，在晶体管上方；第一连接电极，在第一有机绝缘层上方，并且电连接到晶体管中的至少一个；第二连接电极，在第一有机绝缘层上方；第一电源线，配置成接收第一电力电压，在第一有机绝缘层上方，并且连接到第二连接电极；以及第二有机绝缘层，在第一电源线上方，并且限定暴露第一电源线的开口区域。

Display device and tiled display device

Provided are a display device and a tiled display device. The display device according to one or more embodiments includes a substrate, transistors above the substrate, a first organic insulating layer above the transistors, a first connection electrode above the first organic insulating layer, and electrically connected to at least one of the transistors, a second connection electrode above the first organic insulating layer, a first power supply line configured to receive a first power voltage, above the first organic insulating layer, and connected to the second connection electrode, and a second organic insulating layer above the first power supply line, and defining an opening area exposing the first power supply line.

接合元件及其製備方法

本揭露提供一種接合元件及其製備方法，其中，製備方法包含以下步驟：提供一承載基板；形成一第一金屬層於承載基板上；形成一第一絕緣層於第一金屬層上，其中第一絕緣層包含一第一穿孔；形成一第一鈍化層及一第一導電層於第一穿孔中，其中第一穿孔中的第一鈍化層與第一導電層形成一第一連接凸塊；形成一第一基板於第一連接凸塊及第一絕緣層上；移除承載基板及第一金屬層，形成一第一子接合元件；以及以第一連接凸塊的第一鈍化層的表面，將第一子接合元件與一第二子接合元件進行一對接製程，形成接合元件。

表面照射型イメージセンサ用パッド構造及びその形成方法

【課題】 比較的平坦な表面形状を有しながら下方にある構造に対するダメージを低減するボンドパッドを有する集積回路およびその製造方法を提供する。 【解決手段】 半導体基板上の誘電体構造内に配置された複数の金属交互接続層と、前記誘電体構造の上に配置され、パッシベーション構造の上表面内に凹部を有し、前記凹部は、前記パッシベーション構造の水平面を前記上表面に連結する側壁を含むパッシベーション構造と、前記凹部内に配置され、前記水平面の上方にある下表面を有し、前記パッシベーション構造の開口を貫通して、前記ボンドパッドの前記下表面から外側に向けて延伸し、前記複数の金属相互接続層の中の１つに接触する１つ以上の凸部を含むボンドパッドとを含む集積回路。 【選択図】図１５

半導体装置とその製造方法

半導体装置の表面電極として、半導体基板の表面側から順に、バリア金属層である第１層、Ａｌ層である第２層、Ａｌ−Ｓｉ層またはＡｌ−Ｃｕ層またはＡｌ−Ｓｉ−Ｃｕ層である第３層、はんだ接合層である第４層を積層する。第４層は、第３層に対してＺｎ置換処理を行った後に無電解めっきによって形成することができる。この表面電極は、半導体基板と表面電極とのオーミック接合を確保しつつ、第３層の表面の平坦性を良好な状態とすることができる。また、第３層に対してＺｎ置換処理を行うと、密着性、緻密性に優れたＺｎ置換膜を形成することができる。これらによって、第４層が平坦性の良い膜となる。

電子部品

電子部品は、主面を有するチップと、前記主面の上に２２００ｎｍを超える厚さで積層され、前記チップ側の第１端、および、前記チップとは反対側の第２端を有する絶縁層と、前記第１端を基準に２２００ｎｍ未満の厚さ範囲に位置しないように前記絶縁層内に配置され、金属元素および非金属元素によって構成された合金結晶を含む抵抗膜と、を含む。

包括含有接合层级介电层的气隙的接合组件及其形成方法

一种接合组件包括第一半导体裸片，该第一半导体裸片包括第一衬底、第一半导体器件和由第一焊盘层级介电层横向围绕的第一接合焊盘。该第一焊盘层级介电层包括至少一个第一包封气隙，该至少一个第一包封气隙位于相邻的第一接合焊盘对之间并且被该第一焊盘层级介电层的第一介电填充材料包封。该接合组件包括第二半导体裸片，该第二半导体裸片包括第二衬底、第二半导体器件和由第二焊盘层级介电层横向围绕的第二接合焊盘。该第二接合焊盘中的每个第二接合焊盘接合到该第一接合焊盘中的相应一个第一接合焊盘。

功率半导体的晶圆片级芯片规模封装及其制造方法

公开了功率半导体的晶圆片级芯片规模封装及其制造方法。晶圆片级芯片规模封装包括：具有第一厚度的半导体衬底；形成在半导体衬底上的输入‑输出垫；形成在输入‑输出垫上的具有第二厚度的前金属层；形成在半导体衬底的底部上的具有第三厚度的后金属层；以及形成在半导体衬底上的金属凸块。

显示装置及其制造方法

公开一种显示装置及其制造方法。根据一实施例的显示装置至少可以包括：基板，定义有显示区域和垫区域；第一导电层，布置于基板上，包括布置于垫区域的第一垫电极；缓冲层，布置于第一导电层上；半导体层，在显示区域中布置于缓冲层上；栅极绝缘层，布置于半导体层上；以及第二导电层，包括，在显示区域中与半导体层重叠的栅极电极和在显示区域中与半导体层的一侧重叠而布置的第一电极，并通过贯通缓冲层和栅极绝缘层的接触孔而与第一信号线连接；第二电极，在显示区域中布置于半导体层的另一侧；以及第二垫电极，在垫区域中布置于第一垫电极上，第一垫电极和第二垫电极在作为厚度方向的第一方向上重叠，并且在与第一方向垂直的第二方向上不重叠。

背光单元以及包括背光单元的显示装置

本公开的实施例涉及背光单元以及包括背光单元的显示装置，并且更具体地，可以提供一种背光单元，该背光单元包括：多个光源，其设置在基板上并且被设置成多行和多列；以及第一晶体管和第二晶体管，其设置在基板上并且彼此间隔开，其中，第一晶体管和第二晶体管中的每一个被设置在两行光源和两列光源彼此交叉的区域以不与多个光源交叠，因此图像质量优异。本公开的实施例还可以提供包括该背光单元的显示装置。

显示装置及其制造方法

公开一种显示装置及其制造方法。根据一实施例的显示装置至少可以包括：基板，定义有显示区域和垫区域；第一导电层，布置于基板上，包括布置于垫区域的第一垫电极；缓冲层，布置于第一导电层上；半导体层，在显示区域中布置于缓冲层上；栅极绝缘层，布置于半导体层上；以及第二导电层，包括，在显示区域中与半导体层重叠的栅极电极和在显示区域中与半导体层的一侧重叠而布置的第一电极，并通过贯通缓冲层和栅极绝缘层的接触孔而与第一信号线连接；第二电极，在显示区域中布置于半导体层的另一侧；以及第二垫电极，在垫区域中布置于第一垫电极上，第一垫电极和第二垫电极在作为厚度方向的第一方向上重叠，并且在与第一方向垂直的第二方向上不重叠。

背光单元以及包括背光单元的显示装置

本公开的实施例涉及背光单元以及包括背光单元的显示装置，并且更具体地，可以提供一种背光单元，该背光单元包括：多个光源，其设置在基板上并且被设置成多行和多列；以及第一晶体管和第二晶体管，其设置在基板上并且彼此间隔开，其中，第一晶体管和第二晶体管中的每一个被设置在两行光源和两列光源彼此交叉的区域以不与多个光源交叠，因此图像质量优异。本公开的实施例还可以提供包括该背光单元的显示装置。

用于凸块下金属结构的套环及相关联的系统及方法

本申请涉及用于凸块下金属结构的套环及相关联的系统和方法。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

阵列基板及显示装置

本公开实施例公开了一种阵列基板及显示装置，涉及显示技术领域，用于避免对源漏导电层造成腐蚀，进而避免应用有该阵列基板的显示装置出现撕膜斜纹不良，改善该显示装置的显示效果。该阵列基板，具有显示区和位于所述显示区的旁侧的绑定区。所述阵列基板包括：衬底、多个第一晶体管、以及多个导电电极。所述多个第一晶体管设置在所述衬底的一侧、且位于所述显示区，第一晶体管包括第一栅极、第一源极和第一漏极。所述多个导电引脚设置在所述衬底的一侧、且位于所述绑定区，所述多个导电引脚与所述第一栅极同层设置。所述多个导电电极分别设置在所述多个导电引脚远离所述衬底一侧表面。本公开提供的阵列基板及显示装置用于实现触控及显示。

显示基板及显示装置

本发明涉及显示技术领域，公开一种显示基板及显示装置。显示基板包括：衬底基板，包括显示区和位于显示区至少一侧的绑定区，绑定区分为用于设置连接端子的端子区和位于端子区之间的间隔区；连接端子，位于衬底基板上，设置在端子区内；第一无机绝缘层，位于衬底基板设有连接端子的一侧；第一无机绝缘层覆盖绑定区，且设有与连接端子一一对应的第一开口，各第一开口在衬底基板上的正投影位于对应的连接端子在衬底基板上的正投影之内；第一有机绝缘层，设置在衬底基板与第一无机绝缘层之间且环绕所述绑定区，第一有机绝缘层与绑定区没有交叠。上述显示基板，可以避免绑定区出现膜层结构不良，提高显示基板整体良率。

半导体装置、以及半导体装置的制造方法

得到抑制使用铜的电极与使用铜的引线的接合形成中的铜电极与引线的接合不良的产生的半导体装置。一种半导体装置，具备：半导体基板(1)；铜电极层(2)，形成于半导体基板(1)上；金属薄膜层(3)，形成于铜电极层(2)上，与外周部相比在内侧具有使铜电极层(2)露出的开口部(31)，所述金属薄膜层(3)防止铜电极层(2)的氧化；以及以铜为主要成分的布线构件(4)，具有覆盖开口部(31)的接合区域(20)，所述布线构件(4)接合于金属薄膜层(3)且在开口部(31)处接合于铜电极层(2)。