Semiconductor device

Technical Field

This specification relates to a method for manufacturing semiconductor device.

One or more embodiments may be applied to for example reduced such as used in automotive and consumer products in the integrated circuit with heat mechanical stress.

Background Art

Various types of integrated circuit (IC) can be adopted such as BCD (bipolar - CMOS - DMOS) technology of.

BCD technology can be advantageously for example for producing power electronic device and logic to control the electronic device of the integrated circuit. BCD technology provides a series of silicon process, each of the silicon technology will be three different technology of forces to on a single chip: used for accurate simulation function of the double-pole, for digital design of CMOS (complementary metal oxide semiconductor), and used for power and the high-voltage component of the DMOS (double-diffused metal oxide semiconductor).

The implementation of the BCD technology may include a redistribution layer (RDL) known as the top layer of the copper metal interconnect.

For example by wire bonding and packaging process during the thermoelastic of the coupling and the stress caused by, the passivation and for the reliability of the intermediate insulating layer hinders the problem can appear need to pay attention to the factors.

In the manufacture of IC can be used in the silicon nitride (SiN) or silicon carbide (SiC) to provide for micro-chip passivation layer, for example to provide resistance to water molecules and the microelectronic device in the stability of the corrosion and other sources of the barrier layer.

In the such as Cu (copper) metallization structure at the top of the RDL metallized structure in the corner of the structure, because thermomechanical mismatch between the different materials can be caused by stress, the different material such as barrier layer (titanium - tungsten (TiW), tantalum (Ta), tantalum nitride (TaN)), metallization structure coated layer (nickel - palladium (Ni - Pd), nickel - palladium - gold (Ni - Pd - Au), nickel - gold (Ni - Au)), the passivation layer (SiN, SiC) triple point).

Content of the utility model

One or more of the embodiment to overcome in the passivation layer on the upper surface of the edge of the Cu RDL structure (for example, in the corner) to contribute to the passivation of the stress.

According to the embodiment of the one aspect, the invention provides a semiconductor device, characterized in that includes: 1st layer, having an edge region; metallization structure, faces the edge area of the 1st layer and does not contact the outer peripheral portion of the edge area.

In one embodiment, the metallization structure includes: metallized structure body, and on the main body with the outer surface coating, wherein the edge region faces the peripheral part in the metallization structure body and the outer surface not in contact with the interface between the coating.

In one embodiment, the semiconductor device further includes a barrier layer, the barrier layer in the metallization structure below the main body and adjacent the outer surface of the coating, the barrier layer and the outer surface of the completely around the coating together with the metallized structure body.

In one embodiment, the 1st layer comprises a passivation layer on the passivation layer and the barrier layer.

In one embodiment, the barrier layer in the metallized structure extending below the main body.

In one embodiment, the barrier layer is only in the edge region on the passivation layer and the said extension.

In one embodiment, the passivation layer comprises a dielectric passivation layer, and/or the barrier layer includes titanium-tungsten.

In one embodiment, the metallized structure comprises a Cu - RDL metallized structure.

According to the embodiment of the on the other hand, provides a semiconductor device, characterized in that includes: a dielectric layer; a passivation layer, on the dielectric layer, said passivation layer having an edge region; 1st metallized layer, passing through the through hole in the passivation layer extends; and 2nd metallization structure layer, coating the top surface of the 1st metallized layer and having a coated the 1st metallized layer of the side surface of the peripheral part, the peripheral part faces the passivation of said marginal area and did not contact the end of the edge region.

In one embodiment, the semiconductor device further includes a barrier layer, the barrier layer in the lower part of the 1st metallization structure layer and adjacent to the 2nd metallized layer, said barrier layer and 2nd metallization structure layer together completely surround the 1st metallization structure layer.

In one embodiment, the semiconductor device further comprises a 3rd metallized layer, the 3rd metallization structure layer coating the outer surface of the metallized layer of the 2nd, the 3rd metallization structure layer has a coating said 2nd metallized layer of the peripheral part of the peripheral portion and faces said passivation layer of said marginal area and did not contact the end of the edge region.

One or more embodiments may by omitting "triple point", for example through will coat the barrier layer (for example, nickel - TiW) interface with the passivation layer (for example, SiN, SiC) coupled to the top surface of the stress caused by the decrease of the SiN passivation layer.

One or more embodiments may include modifications such as Cu RDL process flow, comprising the addition of a passivation layer with a sacrificial insulating layer in order to produce the interval between such as nickel.

In one or more embodiments, can by means of the can be maintained by the nickel (Ni) copper (Cu) completely covers the process flow of the achieve enhanced passivation robustness, in order to prevent copper migration without changing the material and related interface.

One or more embodiments may include double-barrier layer (for example, TiW), the double-barrier layer is adapted for by avoiding the presence of the passivation layer of the critical stress "triple point" and de-coupling nickel and the passivation layer.

One or more embodiments may include double-copper barrier layer deposition, in a gap exists between the nickel and the passivation layer, in contact with the passivation layer of copper on the barrier layer not nickel growth.

One or more embodiments may omit the TiW - Ni - SiN passivation interface, wherein Cu is totally sealed in for example in TiW and Ni (in order to avoid the migration of Cu and corrosion) and in the final barrier layer after etching is not undercut.

According to the proposal of the application, can be avoided in the passivation layer on the upper surface of Cu RDL at edge of the structure (for example, in the corner) of the passivation of the stress.

Description of drawings

Now reference with photos, purely by way of example described one or more embodiments, wherein:

Figure 1 to Figure 15 is one or more of the embodiment of the example of the possible steps,

Figure 16 to Figure 22 is in one or more of the implementation of the example Chinese Library 9 to Figure 15 of the step of the example of possible modifications.

Should be aware of is to statements for the sake of clarity, with photos of some characteristics (for example, the thickness of the layer) does not need to be in accordance with the drawing of the same proportion.

Mode of execution

In the subsequently in the specification, illustrate one or more of the specific details, and aims to provide to the example of the embodiment of the in-depth understanding. Can not adopting one or more of the specific details, or by using other methods, components, materials and the like to obtain the embodiment. In other circumstances, the known structure, material or operation and not shown or described in detail so that the will not fuzzy embodiment in certain characteristics.

In the framework of this specification reference to "one embodiment" or "an embodiment" is intended to indicate on the specific configuration of the embodiment, structure or characteristic is included in at least one embodiment. Therefore, can exist in the specification of one or more point in, such as "in one embodiment" or "in an embodiment" of the phrase does not necessarily to the same embodiment. In addition, the specific structure, structure or characteristics can be in any suitable manner in one or more embodiment combined.

Purely for the sake of convenient to provide in this the reference and is not therefore limit the scope of protection of the embodiment of or range.

In the semiconductor device such as for example an integrated circuit (IC) in said stress reduction of extended field of technical studies.

U.S. Patent no. 8,476,762 is an example of related activities. The literature discloses a process for making a semiconductor chip package with ball limiting metallurgy (BLM) structure of the lead-free controlled collapse chip connection (C4) method, on the chip joint cooling of a back end process (BEOL) levels during the breaking of the chip is reduced. On the chip joint during cooling of the subjected to tensile stress by the BLM structure covers the edge of the corresponding edges of the metal seed layer by electroplating the barrier layer of the metal seed layer to protect against the undercut, the undercut is formed by wet etching the chip from the surface of the chip and removing the metal layer caused by the reflux of the solder.

Figure 1 to Figure 5 is RDL (re-distribution layer) in the process of the example of the possible steps.

In one or more embodiments, Figure 1 to Figure 5 in the example of the step can include:

- A dielectric substrate 10 of Cu chemical mechanical polishing (Cu CMP), wherein the conductive (e.g., copper) structure 12 provided with dielectric landing (for example, SiN) layer 14 (Figure 1);

"Coated" - the deposition of the silicon nitride layer 16, the interlevel dielectric layer 18 and the passivation layer 20, such as SiN, SiC (Figure 2);

- Etching through the passivation layer 20 and the interlayer dielectric layer 18 landing (also landing and to) the nitride coating layer 16 on the through hole 22 (Figure 3).

Figure 4 is a covering layer 16 of the "blanket" open steps of the example, such that the hole 22 landing in the conductive structure 12 (for example, copper) on, for example, has such as approximately 3 microns (3 * 10^-6 M) of the width of the distance between the hole /.

Figure 5 is in fig. 4 of the upper surface of the structure is formed on such as approximately 100 nanometer (100 * 10^-9 M) the thickness of the barrier layer TiW 24 example, then (Figure 6) is at least partially deposited with for example approximately 100 nanometer (100 * 10^-9 M) at the expense of the thickness of the dielectric (for example, SiN) layer 26.

Figure 7 is the area not covered, then (Figure of providing dielectric RDL mask 28 example, the mask covers the lower dielectric layer 26 in the edge area and leaving the provides hole 22 8) is nitride etching, thereby allowing the not etching the dielectric layer 26 (only) is maintained in the mask 28 below.

Figure 9 is the following step of the example, in which the removing ("stripping") mask 28 after, to provide for example approximately 200 nanometer (200 * 10^-9 M) of the 2nd barrier layer 30 (for example, TiN - TiW, TiW), next is deposited for example approximately 200 nanometer (200 * 10^-9 M) of for example copper "seed" layer 32.

Should be aware of is, because the mask 28 below the remaining etching nitride 26 there of, layer 30 and 32 are in the 300 to show the step structure.

Figure 10 is to provide another Cu RDL mask 34 example, through left a step structure 300 are not covered by the leave provides hole 22 of the region not covered.

In one or more embodiments, the mask 34 can be relative to the structure 300 but laterally offset (concave) such as about 1 micron (1 * 10^-6 M).

Figure 11 is in the through hole 22 is formed on the metallized structure 36 such as Cu RDL example. In one or in another embodiment, metallized structure 36 can have for example about 10 microns (10 * 10^-6 M) of thickness. In one or in another embodiment, metallized structure 36 can be formed by electrochemical deposition (ECD) form.

Fig. 12 is an example of the following steps, wherein removing the ("stripping") mask 34 after all reservations from has not been metallized structure 36 surfaces of the removed (for example, by the wet etching process) 2nd barrier layer 30 (for example, TiN - TiW, TiW) and Cu "seed" layer 32.

Should be aware of is, because in the 300 at the presence of the stepped structure, the metallized structure 36 of the periphery TiW layer 30 through the (currently) not etching the dielectric 26 with the TiW barrier layer 24 keep a distance.

Figure 13 is a metallized structure 36 is deposited on the outer surface of the combined coating 38, 40 (for example, Ni - Pd, Ni - Pd - Au, Ni - Au) of the example.

In one or more embodiment, the coating layer 38, 40 can have for example about 2 microns (2 * 10^-6 M) of thickness.

Similarly, should be aware of is, in the absence of etching nitride 26 the existence, in the metallization structure 36 on the outer surface of the coating layer 38, 40 is held in the 1st barrier layer 24 at a distance.

Figure 14 is the example (Figure of nitride 26 removing (e.g., etching) of the example, and extend across the metallized structure 36 of the periphery of the 1st barrier layer 24 may be removed (for example, by etching) 15).

Figure 14 and Figure 15 highlighted in this exemplary process, and predominantly provides sacrificial dielectric layer 26, made it possible to avoid the metallized structure 36 formed at the periphery of the barrier layer coating - - passivation layer interface, that can be a source of high mechanical stress, having a part of the background technology as described in the specification of the defects in succession.

In the such as in this example one or more of in the first embodiment, 2nd barrier layer 30 can be with the coating layer 38 contact to encapsulate the metallization structure 36.

Figure 16 to Figure 22 is an example of the following embodiment, which lead to the forming layer 30 (for example, approximately 200 nm that is 200 * 10^-9 The total thickness of the m) of Figure 9 of the TiN - TiW deposition can include in the layer 30 of the "inner" surface of the TiW layer deposited on 30 (for example, approximately 200 nm that is 200 * 10^-9 The thickness of the m) plus TiN layer 30a (for example, approximately 10 nm that is 10 * 10^-9 The thickness of the m), layer 30 is the inner surface of the layer 30 towards the 1st barrier layer 24 (and the dielectric layer 26) of the surface.

Figure 16 to Figure 22 as shown in the other process steps can in addition be regarded as corresponding to the Figure 9 to Figure 15 as shown in the process steps, namely:

The deposition of the "seed" - Cu layer 32 (Figure 16);

To provide another - Cu RDL mask 34, through the left a step structure 300 are not covered by the leave provides hole 22 of the region not covered (Figure 17);

- In the through hole 22 is formed on the metallized structure 36 such as Cu RDL (Figure 18);

- Remove ("stripping") mask 34, from the left has not been metallized structure 36 covering the surface of the barrier layer to remove 2nd 30 (for example, TiN - TiW) and Cu "seed" layer 32 (Figure 19);

- Metallized structure 36 is deposited on the outer surface of the combined coating 38, 40 (for example, Ni - Pd, Ni - Pd - Au, Ni - Au) (Figure 20);

- Removing the dielectric 26, and may remove the extends beyond the metallization structure 36 1st on the periphery of the barrier layer 24 (for example, by selective etching TiN TiW) (Figure 21 and Figure 22).

Figure 21 and Figure 22 highlighted in this exemplary process, and predominantly provides sacrificial dielectric layer 26, made it possible to avoid the metallized structure 36 formed at the periphery of the barrier layer coating - - passivation layer interface.

Similarly, this avoids the high mechanical stress may form, with the portion of the background technology as described in the specification of the defects in succession.

In as shown in Figure 16 to Figure 22 as shown by a one or more embodiment, TiN layer 30a may be adjacent to the coating layer 38 to seal the metallization structure 36 (in its bottom surface in the TiW layer 30).

In addition should be aware of is, as in the aforesaid as shown in the specific choice of the material is mainly on certain process embodiment, such as the combined RDL process. In one or more embodiments, different embodiments can dispose of such as material and/or thickness of the layer of different choices.

One or more embodiments may thus to provide a method of manufacturing a semiconductor device, the semiconductor device includes a with a peripheral part of the metal structure (such as 36, 38, 40), wherein the peripheral part has at least one next multiple coat (for example 20, 24), with the lower coating facing the peripheral area extending in the edge area.

In one or more embodiments, the method can include:

- Providing sacrificial layer (for example, 26) so as to cover the at least one next multiple coat of said marginal area,

By states the sacrifice - when the layer covering the at least one next multiple coat of said marginal area provides the metallization structure, and

- Removing the sacrificial layer, whereby the at least one next multiple coat of said marginal area facing the peripheral portion to extend but in not in contact with the interface between the two.

In one or in another embodiment, metallized structure can include:

- Metallized structure main body (for example, 36), preferably comprises a copper, and

The outer surface of the main body - coating or "coating layer" (such as 38, 40), the coating preferably comprises a nickel layer and at least one of palladium, wherein the edge region faces the peripheral part to extend but in the metallization structure body and the outer surface not in contact with the interface between the coating.

One or more embodiments may include providing a barrier layer (such as 30, 30a), preferably includes a TiN and TiW, in the metallization structure body (36) and adjacent to the outer surface of the lower part of the coating to provide the metallized structure covering the whole of the body of the, wherein when states the sacrifice layer covered by the at least one next multiple coat to provide the edge of the region (for example, see Figure 9 and Figure 16) the barrier layer (such as 30, 30a).

One or more embodiments may include providing at least one next multiple coat as the passivation layer (for example, 20), preferably in the layer are provided with a corresponding barrier layer (for example 24).

One or more of the embodiment can be included in said passivation layer is provided on the corresponding barrier layer as the extends from the metallized structure below the main body of layer, said at least one of said marginal area at the next multiple coat with provides for covering the the corresponding barrier layer of the sacrificial layer (refer to for example chart 12 and Figure 19).

One or more embodiments may include in addition to the edge area of the passivation layer is removed from the outside of the corresponding barrier layer (refer to for example, Figure 15 and Figure 22).

In one or in a plurality of examples:

- The passivation layer may include a nitride passivation layer, and/or

- The corresponding barrier layer (24) can include TiW barrier layer.

In one or more embodiments, the sacrificial layer (such as 26) can include silicon nitride.

In one or more embodiments, the metallized structure can include the Cu - RDL metallized structure.

One or more of the embodiment can provide a semiconductor device, the semiconductor device includes a metallization structure, the metallized structure has a peripheral portion, the peripheral portion has at least one next multiple coat, the lower coating faces the peripheral part extending in the edge area, wherein the at least one next multiple coat of said marginal area facing the peripheral portion to extend but in not in contact with the interface between the two.

Without prejudice to the principle of the following circumstances, details and embodiments may be relative to the purely by way of example a content change, even greatly change, but was not far from the scope of the protection.

Each embodiment described above can be combined to provide further embodiments. The above specification can be detailed under the guidance of the embodiment made to these and other changes. Usually, in the following in the claims, the terminology used should not be configured to the requirements of the rights defined in the specification and claim to the particular embodiments disclosed, but should the structure in order to include all possible embodiments and these rights requires authorized by the full scope of the equivalent form. Therefore, the claim is not subject to the restrictions.