Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

ELECTRONIC DEVICES UTILIZING CONTACT PADS WITH PROTRUSIONS AND METHODS FOR FABRICATION

An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front- side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front- side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).

Semiconductor devices having metal bumps with flange

A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Elektronische Komponente und Verfahren

In einer Ausführungsform umfasst eine elektronische Komponente eine erste dielektrische Schicht, die eine organische Komponente mit einer Zersetzungstemperatur von mindestens 180°C aufweist, ein in die erste dielektrische Schicht eingebettetes Halbleiter-Die, eine zweite dielektrische Schicht, die auf einer ersten Oberfläche der ersten dielektrischen Schicht angeordnet ist, wobei die zweite dielektrische Schicht eine photodefinierbare Polymerzusammensetzung aufweist und zwei oder mehr abgegrenzte Öffnungen mit leitfähigem Material definiert, und ein erstes Substrat, das auf der zweiten dielektrischen Schicht und auf dem leitfähigen Material angeordnet ist. Ein oder mehrere Kontaktpads sind auf einer äußersten Oberfläche des ersten Substrats angeordnet.

METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WHICH HAS A THROUGH-ELECTRODE

PURPOSE: A manufacturing method of a semiconductor device is provided to prevent substrate contamination during a manufacturing process by forming a through-electrode after performing a process for polishing the rear surface of a substrate. CONSTITUTION: A substrate(10) includes first and second surfaces facing to each other. A sacrificial film pattern is formed on a region for forming a through-electrode. An upper wiring layer which has a wire located on the sacrificial film pattern is formed on the first surface of the substrate. The sacrificial film pattern is exposed by partially eliminating the second surface of the substrate. An opening part(22) for exposing the wire is formed by eliminating the sacrificial film from the second surface of the substrate. A through-electrode(72) is electrically connected to the wire within the opening part. COPYRIGHT KIPO 2012 ...

OPTOELECTRONIC COMPONENT WITH INTEGRATED PROTECTION DIODE AND METHOD FOR PRODUCING SAME

An optoelectronic component (10, 20) comprises an optoelectronic semiconductor chip (100) with a first surface (121), on which a first (130) and a second electrical contact (135) are arranged. The first surface (121) adjoins a moulded body (170). A first (160) and a second pin (165) are embedded in the moulded body (170) and are connected to the first (130) and the second contact (135) in an electrically conductive manner. A protection diode (140) is embedded in the moulded body and is connected to the first (130) and the second contact (135) in an electrically conductive manner.

UBM etching methods for eliminating undercut

A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM.

CMOS-Sensoren und Verfahren zur Bildung derselben

CMOS-Sensoren und Verfahren zur Bildung derselben sind offenbart. Der CMOS-Sensor enthält ein Halbleitersubstrat, eine dielektrische Lage, eine Verbindung, ein Bonding-Pad und eine Dummystruktur. Das Halbleitersubstrat weist eine Pixelregion und eine Schaltkreisregion auf. Die dielektrische Lage ist durch das Halbleitersubstrat in der Schaltkreisregion umgeben. Die Verbindung ist über der dielektrischen Lage in der Schaltkreisregion angeordnet. Das Bonding-Pad ist in der dielektrischen Lage angeordnet und verbindet elektrisch die Verbindung in der Schaltkreisregion. Die Dummystruktur ist in der dielektrischen Lage angeordnet und umgibt das Bonding-Pad in der Schaltkreisregion.

Verfahren zur Herstellung eines Halbleiterbauelements

Die Erfindung bezieht sich auf ein Verfahren zur Herstellung eines Halbleiterbauelements mit einer Durchelektrode in einem Substrat. Ein Halbleiterbauelementherstellungsverfahren der Erfindung umfasst, des Bildens einer Opferschichtstruktur in einem Bereich des Substrats, in dem eine Durchelektrode so gebildet wird, dass sie sich von einer ersten Oberfläche des Substrats in einer Dickenrichtung des Substrats erstreckt, des Bildens einer oberen Verdrahtungsschicht mit einer Verdrahtung (32) auf der Opferschichtstruktur, des teilweise Entfernens der zweiten Oberfläche des Substrats, um die Opferschichtstruktur freizulegen, des Entfernens der Opferschichtstruktur, um eine erste Öffnung zu bilden, welche die Verdrahtung freilegt, und des Bildens der Durchelektrode (72) in der ersten Öffnung, die mit der Verdrahtung elektrisch zu verbinden ist. Verwendung in der Halbleiterbauelementtechnologie.

Semiconductor device and semiconductor packaging structure provided with the same

Method for assembling integrated circuit with another integrated circuit to form three-dimensional integrated structure, involves realizing electrically conducting pillar crossing from integrated circuit front face and leading to metal line

Structure intégrée tridimensionnelle et procédé d'assemblage de circuits intégrés correspondant, ladite structure comprenant un assemblage d'un premier circuit intégré (CI1) et d'un deuxième circuit intégré (CI2), dans lequel la face arrière (BF1) du premier circuit intégré est collée directement à la face avant (FF2) du deuxième circuit intégré et comprenant au moins un pilier électriquement conducteur (PC) traversant le premier circuit intégré depuis le voisinage de la face avant du premier circuit intégré et débouchant sur une ligne métallique (LM2) du deuxième circuit intégré.

Manufacturing method of semiconductor device

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Method for Producing a Connection Between Component Parts, and Component Made of Component Parts

A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

Verfahren zum Sintern, Verfahren zur Schmelzschweissung, Höckerherstellung und Fühler.

Semiconductor devices with compliant interconnects

A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Manufacturing method of ultra-thin semiconductor device package assembly

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Metal wiring structures for uniform current density in C4 balls

In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The area1 density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad.

Method for realizing three-dimensional integrated structure, involves realizing electrically conductive through-connection extending between non-assembled face and metal line of interconnection part of one of two integrated circuits

Procédé de réalisation d'une structure intégrée tridimensionnelle, et structure correspondante, ledit procédé comprenant un collage direct de la face avant d'un premier circuit intégré (CI1) et de la face avant d'un deuxième circuit intégré (CI2), et une réalisation d'au moins une liaison traversante électriquement conductrice s'étendant entre une face non assemblée (BF11) du premier circuit intégré, opposée à sa face avant, et une ligne métallique (LM1) de la partie d'interconnexion d'un des deux circuits intégrés.

IMPROVED METHOD FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

Semiconductor devices, semiconductor structures and methods of manufacture thereof

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

PLUG VIA FORMATION BY PATTERNED PLATING AND POLISHING

Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

Verfahren zur Herstellung einer Verbindung zwischen Bauteilen und Bauelement aus Bauteilen

Es wird ein Verfahren zur Herstellung einer elektrischen Verbindung zwischen einem ersten Bauteil (1) und einem zweiten Bauteil (2) angegeben, bei dem das erste Bauteil mit einer ersten freiliegenden Isolationsschicht (II) und das zweite Bauteil mit einer zweiten freiliegenden Isolationsschicht (21) bereitgestellt werden, wobei die Isolationsschichten jeweils zumindest eine Öffnung (1IC, 2IC) aufweisen. Die Bauteile werden derart zusammengeführt, dass sich die Öffnung (1IC) der ersten Isolationsschicht und die Öffnung (2IC) der zweiten Isolationsschicht in Draufsicht überlappen, wobei in mindestens einer der Öffnungen (1IC, 2IC) eine Au-Schicht (S1, S2) und eine Sn-Schicht (S1, S2) übereinander angeordnet sind. Die Au-Schicht und die Sn-Schicht werden zur Bildung einer AuSn-Legierung aufgeschmolzen, wobei die AuSn-Legierung nach einer Abkühlung eine Durchkontaktierung (12) bildet, welche das erste Bauteil mit dem zweiten Bauteil elektrisch leitend verbindet. Des Weiteren wird ein Bauelement ...

Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 [mu]m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.

Conductive barrier direct hybrid bonding

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Electronic Component and Method

In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.

SOLDERING DEVICE, SOLDERING METHOD, AND SUBSTRATE AND ELECTRONIC COMPONENT PRODUCED BY THE SOLDERING DEVICE OR THE SOLDERING METHOD

Provided are a soldering device and method which allow for oldering at low cost with high yield and high reliability. To solve the above problems, the soldering device has: a first processing section that immerses workpiece member 10 having copper electrode 2 in organic fatty acid-containing solution, and horizontally move immersed workpiece member 10 in organic fatty acid-containing solution 31; a second processing section having ejection unit 33 to spray a jet stream of molten solder 5a to workpiece member 10 while pulling out workpiece member 10 processed in the first processing section to space section 24 that has a pressurized steam atmosphere and is provided above organic fatty acid-containing solution 31; a third processing section having ejection unit 34 to spray organic fatty acid-containing solution 31 to excess molten solder 5a on workpiece member 10 for removal while pulling down workpiece member 10 processed in the second processing section after horizontally moving in space ...

Integrated circuit cooling apparatus

A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

IMPROVED PROCESS FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture.

MICROELECTRONIC CONTACT STRUCTURE AND THE PRODUCTION AND USE METHOD THEREOF

Fabrication method of semiconductor substrate

METHOD FOR PRODUCING MICROBUMPS ON A SEMICONDUCTOR COMPONENT

The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure and method for forming the same

Semiconductor device and manufacturing method

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Methods of manufacturing semiconductor devices

LOW STRESS PAD STRUCTURE FOR PACKAGED DEVICES

Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Substrate bonding with metal germanium silicon material

A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting ...

半導体装置の製造方法

Lithographically defined microelectronic contact structures

Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus

METAL WIRING STRUCTURE FOR UNIFORM CURRENT DENSITY INSIDE A C4 BALL, CAPABLE OF IMPROVING THE RELIABILITY OF THE C4 BALL

PURPOSE: A metal wiring structure for uniform current density inside a C4 ball is provided to implement uniform current density inside a C ball by using a metal pad having an integrated a metal via. CONSTITUTION: Metal wiring structures for uniform current density in c4 balls includes a metal pad(90), an upper level metal line(70A), and a lower level metal line(30). The metal pad is arranged on the metal line. The upper level metal line is contacted with the metal pad. The lower level metal line is arranged under the upper level metal line. COPYRIGHT KIPO 2011 ...

Substrate bonding with metal germanium silicon material

Semiconductor device and method of manufacturing the same, circuit board and electronic instrument

A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal layer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).

Semiconductor package

A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.

SEMICONDUCTOR CHIP WITH A PENETRATION ELECTRODE WITHOUT A DRY REACTIVE ION ETCH PROCESS AND MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor chip and a manufacturing method thereof are provided to improve the reliability and yield of a semiconductor package by reducing attack applied to the semiconductor chip. CONSTITUTION: A conductive pattern is formed on one side of a device layer(110). A bonding pad electrically connected to the conductive pattern is formed on the other side of the device layer. An insulation film pattern(130) is formed on one side of the device layer and includes a via hole to expose the conductive pattern. A penetration electrode(140) is electrically connected to the conductive pattern in the via hole. A seed layer is formed on the inner side of the insulation film pattern exposed by the via hole. The metal layer fills the via hole on the seed layer. COPYRIGHT KIPO 2012 ...

Driving chip and the manufacturing method thereof

Semiconductor device and method of fabricating the same

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Manufacturing method of ultra-thin semiconductor device package assembly

METHOD FOR PRODUCING A STRUCTURE FOR MICROELECTRONIC DEVICE ASSEMBLY

The invention concerns the forming of a microelectronic device comprising a substrate containing at least one conductive pad, the said pad being provided with a bottom surface resting on the substrate and an upper surface opposite said bottom surface, the said upper surface of said pad having a stack applied thereto formed of a conductive layer and a protective dielectric layer comprising an opening called first opening facing said pad and exposing the said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral region of said upper surface of said pad, the said insulating block (120a, 120b) having a cross-section forming a closed contour and comprising an opening called second opening, a conductive pillar (130a, 130b) being located in the centre of said contour in the said second opening.

OPTOELECTRONIC COMPONENT WITH INTEGRATED PROTECTION DIODE AND METHOD FOR PRODUCING SAME

Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 μm or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Semiconductor device and metH1od of forming tH1e same

폴리머에 박형 칩들을 내장하는 방법

... 박형 칩들을 내장하기 위한 시스템 및 방법이 제공된다. 웰 영역이 유연성 폴리머 상에 배치되는 전도성 재료를 포함하는 기판에 형성된다. 스탠드오프 웰 영역이 전도성 재료를 패터닝함으로써 형성될 수 있고, 박형 칩은 스탠드오프 웰 영역에 내장된다. 폴리머 웰 영역을 형성하기 위해 공동이 폴리머 층에 형성될 수 있고, 박형 칩은 폴리머 웰 영역에 내장된다. 일 예에서, 적어도 2개의 웰 영역들이 유연성 폴리머 상에 배치되는 전도성 재료를 포함하는 기판에 형성될 수 있다. 적어도 2개의 웰 영역들 중 적어도 하나는 스탠드오프 웰 영역일 수 있다.

MICROELECTRONIC CONTACT STRUCTURE AND THE PRODUCTION AND USE METHOD THEREOF

Optoelektronisches Bauelement mit integrierter Schutzdiode und Verfahren zu seiner Herstellung

Semiconductor element and manufacturing method thereof

Method of forming semiconductor chip, the semiconductor chip so formed and chip stack package having the same

Semiconductor substrate fabrication method thereof

Disclosed is a semiconductor substrate, comprising a substrate body having electrical contact pads formed thereon, a first insulating protective layer formed on the substrate body and exposing from the electrical contact pads; a metallic layer formed on the exposed electrical contact pads; a second insulating protective layer formed on the first insulating protective layer and exposing parts of the metallic layer; and solder balls having copper material formed on the exposed metallic layer, thereby preventing solder balls from falling off or breaking during the temperature testing process. This invention further provides a method of forming semiconductor substrate as described above.

Interconnect structures and methods of forming same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Embedding thin chips in polymer

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

IDENTIFICATION MECHANISM FOR SEMICONDUCTOR DEVICE DIE

A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Semiconductor device having voids between top metal layers of metal interconnects

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Chip size packaging method and packaging structure

Method for chip scale package and package structure thereof

This invention provides a method for chip scale package and a chip scale package structure. The chip scale package structure includes: a semiconductor substrate, on which sets a plurality of contact bonding pads being connected with semiconductor devices; and a plurality of bumps respectively attached to all of the contact bonding pads. The semiconductor substrate is divided into several regions according to different distances from a central point. The contact bonding pads and the bumps in the region which is closest to the central point are the smallest, while the contact bonding pads and the bumps in the region which is farthest to the central point are the largest. The invention effectively improves the situation that the bumps at the edge tend to flake off easily; in addition, it avoids short-circuit caused by bridging between the bumps.

Method for producing a structure for microelectronic device assembly

Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.

METHODS FOR PROCESSING SUBSTRATES

반도체 다이 어셈블리를 위한 온-다이 온도 제어 및 관련 시스템 및 방법

... 반도체 다이 어셈블리들을 위한 온-다이 온도 제어 및 관련 시스템들 및 방법들이 개시된다. 실시예에서, 반도체 디바이스 어셈블리는 서로 직접 접합된 제1 및 제2 반도체 다이들을 포함한다. 반도체 다이들 각각은 유전체층 내의 전도성 패드들 및 저항성 가열 구성요소들을 포함하며, 저항성 가열 구성요소들은 저항성 가열 구성요소들을 통해 흐르는 전류에 응답하여 국부적인 열 에너지를 전도성 패드들에 공급하기 위해 전도성 패드들에 근접하여 위치된다. 일부 실시예들에서, 제1 반도체 다이의 전도성 패드들은 저항성 가열 구성요소들에 의해 발생되는 국부적인 열 에너지 없이 전도성 패드들의 열 팽창을 위해 제2 온도보다 낮은 제1 온도에서 제2 반도체 다이의 전도 패드들에 직접 접합된다.

Structure and Method for Sealing Cavity of Micro-Electro-Mechanical Device

A cavity package (100) for micrometer-scale MEMS devices surrounding the cavity (210) with the MEMS device (220) with a rim (232) of solder-wettable metal, and then covering the cavity with a roof (240) of solder spanning from rim to rim. A solder body, placed over the cavity to rest on the rim, is reflowed; the surface tension of the liquid solder is reduced by the interfacial tension of the rim metal so that the liquid solder spreads over the rim surface and thereby stretches the liquid ball to a plate-like roof over the cavity. After solidifying the solder, the solder-to-metal seal renders the cavity package hermetic.

SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump. 18-. (canceled)9. A method for fabricating a semiconductor chip comprising:providing a semiconductor wafer having a plurality of devices, each device having a plurality of terminal sites;forming a bond pad over each of the plurality of terminal sites, the bond pad being flat and made of a first metal adhering to semiconductor wafer;depositing a layer of dielectric material across the semiconductor wafer covering the bond pads of all terminal sites;patterning the layer of dielectric material over each bond pad to open a window of a first diameter to each bond pad, the window exposing the surface of the underlying bond pad; sputtering a metallic seed layer of a refractory metal over the semiconductor wafer;', 'subsequently patterning the metallic seed layer to form patches of the refractory metal over the window and the surface of the bond pad at each terminal site, the patches having a second diameter greater than the first diameter; and', 'using the patches as a seed material, plating to form the flange on the bond pad at each terminal site, the flange being a film of a second metal adhering to the first metal as well as to the layer of dielectric material; and, 'forming a flange for bumps on each bond pad; comprisingforming a bump of a third metal on each flange, ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHODS FOR PROCESSING SUBSTRATES

IDENTIFICATION MECHANISM FOR SEMICONDUCTOR DEVICE DIE

A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a substrate-side electrode layer, an intermediate electrode layer, and a front-side electrode layer. The substrate includes a semiconductor layer and a projection portion, the projection portion being formed on a surface of the semiconductor layer. The substrate-side electrode layer is provided on the projection portion. The intermediate electrode layer extends from on a part of the substrate-side electrode layer, which part of the substrate-side electrode layer is located on the projection portion, to just above a region of the substrate in which region the projection portion is not provided. The front-side electrode layer is provided on a surface of the intermediate electrode layer. A Young's modulus E1 of the substrate-side electrode layer, a Young's modulus E2 of the intermediate electrode layer, and a Young's modulus E3 of the front-side electrode layer satisfy a relationship of E3>E1>E2.

Verfahren zum Sintern, Verfahren zur Schmelzschweissung, Höckerherstellung und Fühler.

Conduction barrier directly mixed joint

Semiconductor device having through electrode and method of fabricating the same

SEMICONDUCTOR DEVICE INCLUDING A THROUGH ELECTRODE WHICH IS POSITIONED BETWEEN CELL ARRAY REGIONS AND IS SURROUNDED BY THE SEMICONDUCTOR SUBSTRATE AND AN INSULATING LAYER, AND A METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

PURPOSE: A semiconductor device including a through electrode and a method for manufacturing the same are provided to minimize the process failure by simplifying the fabrication of through electrode which is arranged around the metal layer. CONSTITUTION: A semiconductor device including a through electrode comprises a semiconductor substrate(101), a first insulating layer(110), a wiring(115), a second insulating layer(120), a conductive pad(125), the penetration hole and a through electrode(150). The first insulating layer is formed on the semiconductor substrate. The wire is located on the surface of the first insulating layer and has an opening to expose the first insulating layer. The second insulating layer is formed on the first insulating layer and the wiring while filling up the first opening. The conductive pad is formed on the second insulating layer and includes the second opening for exposing the second insulating layer. The penetration hole is formed through the semiconductor ...

Manufacturing method of ultra-thin semiconductor device package assembly

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and the outer region. Subsequently, a blind trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting jig with the active surface facing thereto, and then a thinning process and a process for deposition of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting jig is removed and a plurality of contacting pads is formed ...

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT BOARD AND ELECTRONIC APPARATUS

A semiconductor device which can be directly connected to a board while securing the reliability of connection without adding any step after the selection of a board material and the connection and which contributes to reduction in size and weight of an electronic apparatus. The semiconductor device includes a semiconductor chip (100) having an electrode (104), a wiring layer (120) connected to the electrode (104), a contact layer (122) provided on the wiring layer (120) in a position avoiding the electrode (104), an underlying metal layer (124) provided on the contact layer (122), having a size larger than the contour of the contact layer (122) and more deformative than the contact layer (122), a bump (200) provided on the underlying metal layer (124), and a resin layer (126) provided around the contact layer (122). A method for manufacturing the device, a circuit board, and an electronic apparatus are also disclosed.

Semiconductor device and method of manufacturing the same, circuit board and electronic instrument

A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal layer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).

Semiconductor device and semiconductor package having the same

The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a semiconductor substrate, a backside dielectric layer, a plurality of first backside under ball metal (UBM) pads and a first backside UBM plane. The backside dielectric layer is disposed adjacent to a backside surface of the semiconductor substrate. The first backside UBM pads are disposed on the backside dielectric layer. The first backside UBM plane is disposed on the backside dielectric layer, and has a plurality of through holes. The first backside UBM pads are located within the through holes, and a gap is between the first backside UBM plane and the first backside UBM pads. Whereby, the cost for forming the first backside UBM pads and the first backside UBM plane is relatively low.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT BOARD AND ELECTRONIC APPARATUS

A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal layer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).

납땜 장치 및 방법 그리고 제조된 기판 및 전자 부품

... [과제] 저비용으로, 제품 수율이 높고, 신뢰성이 높은 납땜을 실시할 수 있고는 납땜 장치 및 방법을 제공한다. [해결 수단] 동전극(2)을 갖는 피처리 부재(10)를 유기 지방산 함유 용액(31)에 침지하고, 침지한 피처리 부재(10)를 유기 지방산 함유 용액(31) 중에서 수평 이동하는 제1 처리부와, 처리한 피처리 부재(10)를 윗방향의 증기 분위기의 공간부(24)로 끌어올리면서, 피처리 부재(10)를 향해서 용융 땜납(5a)의 기류(5')를 분사하는 분사 수단(33)을 구비한 제2 처리부와, 처리한 피처리 부재(10)를 공간부(24) 중에서 수평 이동한 후에 유기 지방산 함유 용액(31) 중으로 강하시키면서, 피처리 부재(10) 상의 잉여의 용융 땜납(5a)에 유기 지방산 함유 용액(31)을 분사하여 제거하는 분사 수단(34)을 구비한 제3 처리부와, 처리한 피처리 부재(10)를 유기 지방산 함유 용액(31) 중에서 수평 이동한 후에 윗방향으로 끌어올려 용액 밖으로 꺼내는 제4 처리부를 구비한 납땜 장치에 의해 상기 과제를 해결했다.

SEMICONDUCTOR SUBSTRATE AND METHOD THEREOF

A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test.

Conductive barrier direct hybrid bonding

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

SEMICONDUCTOR CHIP, A MANUFACTURING METHOD THEREOF, AND A CHIP STACK PACKAGE, WHOSE SIZE IS ADJUSTED ACCORDING TO A SHAPE OR A SIZE OF A BUMP

PURPOSE: A semiconductor chip, a manufacturing method thereof, and a chip stack package are provided to completely suppress a leakage current by arbitrarily adjusting a spacing between the semiconductor chip and a semiconductor substrate. CONSTITUTION: A semiconductor chip includes a bonding pad(5), an electric line(7), a semiconductor support(9), and a protective film(3). The bonding pad is located on a semiconductor substrate. The electric line is contacted with the bonding pad and elongated to outside from a semiconductor substrate edge. The semiconductor support is contacted with the electric line and spaced apart from the semiconductor substrate. The protective film is arranged between the electric line and the semiconductor substrate. A conductive pattern covers a sidewall or a bottom of the semiconductor support and is contacted with the electric line. © KIPO 2008 ...

전도성 배리어 직접 하이브리드 접합

... 직접 하이브리드 접합을 형성하는 방법, 및 하기를 포함하는 직접 하이브리드 접합으로부터 생성된 소자: 전도성 배리어에 의해 캡핑되는, 바람직하게는 소자 또는 회로에 접속되는 제1 세트의 금속 접합 패드를 갖고, 제1 기판 상의 금속 접합 패드에 인접한 제1 비금속 영역을 갖는 제1 기판, 바람직하게는 소자 또는 회로에 접속된, 제1 세트의 금속 접합 패드와 정렬된, 제2 전도성 배리어에 의해 캡핑된 제2 세트의 금속 접합 패드를 갖고, 제2 기판 상의 금속 접합 패드에 인접한 제2 비금속 영역을 갖는 제2 기판, 및 제1 비금속 영역을 제2 비금속 영역에 접촉 접합함으로써 형성된 전도성 배리어에 의해 캡핑된 제1 및 제2 세트의 금속 접합 패드 사이의 접촉-접합된 계면.

Manufacturing method of semiconductor device

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Halbleiterbauelement

Halbleiterbauelement, umfassend: eine Halbleiterschicht, die eine Hauptfläche aufweist; ein Elektrodenpad, das auf der Hauptfläche ausgebildet ist; eine Umverdrahtung, die eine erste Verdrahtungsfläche, die mit dem Elektrodenpad verbunden ist, und eine zweite Verdrahtungsfläche, die aufgeraut ist und auf einer Seite gegenüber der ersten Verdrahtungsfläche angeordnet ist, aufweist, wobei die Umverdrahtung auf der Hauptfläche so ausgebildet ist, dass sie zu einem Bereich außerhalb des Elektrodenpads herausgezogen ist; und ein Harz, das die zweite Verdrahtungsfläche auf der Hauptfläche bedeckt und die Umverdrahtung versiegelt.

Joint with the metal silicon germanium material of the substrate

돌출부들을 갖는 컨택 패드들을 이용하는 전자 소자들 및 제조 방법들

... 전면측, 후면측, 상기 전면측과 상기 후면측 사이의 두께, 상기 전면측으로부터 상기 두께의 일부 속으로 연장되는 하나 이상의 전면측 비아, 및 상기 후면측으로부터 상기 전면측을 향하여 연장되는 상호연결 비아를 포함하는 기판; 상기 전면측 상에서 대응하는 전면측 비아들을 통하여 상기 상호연결 비아 속으로 연장되는 하나 이상의 돌출부들을 포함하는 컨택 패드; 및 상기 상호연결 비아를 통하여 상기 돌출부(들)와 접촉하도록 연장된 상호연결을 포함하는 전자 소자.

BONDED ASSEMBLY CONTAINING LOW DIELECTRIC CONSTANT BONDING DIELECTRIC AND METHODS OF FORMING THE SAME

A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor Processing Methods

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same

Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

SEMICONDUCTOR ELEMENT, RECORDING ELEMENT SUBSTRATE, AND LIQUID DISCHARGE HEAD

A semiconductor element includes an insulation layer and a pad portion for electrical connection to an external portion by wire bonding. The insulation layer includes a plurality of projections projecting from a main surface of the insulation layer. The pad portion is disposed on an upper surface of each of the projections without extending beyond the upper surface of the projection on which the pad portion is formed. 1. A semiconductor element comprising:an insulation layer; anda pad portion for electrical connection to an external portion by wire bonding,wherein the insulation layer includes a plurality of projections projecting from a main surface thereof, andwherein the pad portion is disposed on an upper surface of each of the projections without extending beyond the upper surface of the projection on which the pad portion is formed.2. The semiconductor element according to claim 1 , further comprising a base portion on and in contact with the insulation layer claim 1 , the base having a through hole exposing the main surface of the insulation layer claim 1 , wherein the projections are disposed on the main surface exposed by the through hole.3. The semiconductor element according to claim 1 , wherein each of the projections has a width that decreases in a direction from the main surface toward the upper surface.4. The semiconductor element according to claim 1 , wherein a height of each of the projections is greater than a height of a wire-bonding ball.5. The semiconductor element according to claim 1 , further comprising an etching stop layer at a region adjacent to the projections of the main surface of the insulation layer.6. The semiconductor element according to claim 1 , wherein the insulation layer is an oxide film or a nitride film.7. A recording element substrate comprising:a discharge-port forming member including a discharge port perforating therethrough for discharging liquid; an energy generating element configured to generate energy for ...

SEMICONDUCTOR STRUCTURE CONTAINING PRE-POLYMERIZED PROTECTIVE LAYER AND METHOD OF MAKING THEREOF

A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer. 1. A method of forming a semiconductor structure , comprising:providing a semiconductor wafer including a plurality of semiconductor dies;providing a polymerized material layer;attaching the polymerized material layer to the semiconductor wafer, wherein the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer;applying and patterning an etch mask layer over the polymerized material layer, wherein openings are formed through the etch mask layer;etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process; andremoving the etch mask layer selective to the polymerized material layer.2. The method of claim 1 , wherein the semiconductor wafer comprises:bonding pads located within the plurality of semiconductor dies; anda passivation dielectric layer covering peripheral portions of the bonding pads and covering dielectric material layers of the ...

UNDER BUMP METALLURGY (UBM) AND METHODS OF FORMING SAME

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die. 1. A device package comprises:a die;fan-out redistribution layers (RDLs) over the die; a conductive pad portion; and', 'a trench encircling the conductive pad portion; and, 'an under bump metallurgy (UBM) over the fan-out RDLs, wherein the UBM comprisesa connector disposed on the conductive pad portion of the UBM, wherein the fan-out RDLs electrically connect the connector and the UBM to the die.2. The device package of claim 1 , wherein the UBM further comprises a retaining wall portion encircling the trench.3. The device package of claim 2 , wherein a width of the retaining wall portion is about 10 μm to about 20 μm.4. The device package of claim 2 , wherein the connector is not disposed on the retaining wall portion of the UBM.5. The device package of claim 1 , wherein a width of the trench is between about 10 μm to about 20 μm.6. The device package of claim 1 , wherein the fan-out RDLs comprise a conductive line claim 1 , wherein the UBM is formed on a top surface of the conductive line claim 1 , and wherein the trench exposes a portion of the conductive line.7. The device package of claim 6 , wherein the fan-out RDLs comprise a polymer layer extending over a top surface of the conductive line.8. The device package of claim 7 , wherein an entirety of the UBM is disposed in an opening in the polymer layer.9. The device package of claim 7 , wherein the polymer layer covers edge portions of the UBM.10. The device package of claim 7 , wherein the polymer layer is at least partially disposed in the trench.11. A device package comprising:a device die;a conductive ...

PROCESS FLOW FOR FABRICATION OF CAP METAL OVER TOP METAL WITH SINTER BEFORE PROTECTIVE DIELECTRIC ETCH

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer. 1. A method of forming a semiconductor device , comprising:providing a device substrate containing the semiconductor device, the device substrate including a semiconductor material;forming an active component extending into the semiconductor material;forming an interconnect region on the semiconductor material; andforming a top metal layer in the interconnect region;forming a protective dielectric layer on the top metal layer, the protective dielectric layer being at least 1 micron thick;heating the semiconductor device in a sintering operation while the protective dielectric layer covers the top metal layer;after the sintering operation, removing the protective dielectric layer from a bond pad opening in the protective dielectric layer to expose a portion of the top metal layer; andforming a bond pad cap on the top metal layer in the bond pad opening.2. The method of claim 1 , wherein the sintering operation has a sinter thermal profile sufficient to passivate the active component.3. The method of claim 2 , wherein the sinter thermal profile includes heating the semiconductor device to a sinter temperature for a sinter time claim 2 , wherein a product of the sinter time claim 2 , in minutes claim 2 , and an Arrhenius factor of the sinter temperature is greater than 0.0027 minutes claim 2 , the Arrhenius factor of the sinter temperature being determined by the expression:{'br': None, 'i': E', 'k', '+T, 'sub': A ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Semiconductor structure and method for forming the same

A semiconductor structure includes a first substrate, a metallic pad disposed over the first substrate, a dielectric structure disposed over the first substrate and exposing a portion of the metallic pad, a bonding structure disposed over and electrically connected to the metallic pad, a barrier ring surrounding the bonding structure, and a through-hole penetrating the first substrate and the dielectric structure. The bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

Semiconductor Interconnect Structure and Method

A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line. 1. A semiconductor device comprising:a first interconnect structure over first substrate;a first bonding layer over the first interconnect structure;a plurality of first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch; anda plurality of second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the plurality of second bonding pads comprising a plurality of pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line.2. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the same layer as the second bonding pads.3. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the interconnect structure and connected to the second bonding pads of each respective pair by vias disposed in the bonding layer.4. The semiconductor device of claim 1 , comprising:a second bonding layer over a second substrate; anda plurality of third bonding pads disposed in the second bonding layer, comprising a plurality of pairs of adjacent third bonding pads, ...

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A device comprising: a first dielectric layer; and', a diffusion barrier contacting the first dielectric layer; and', 'a metallic material between opposite portions of the diffusion barrier, wherein in a cross-sectional view of the first metal pad, an edge portion of the metallic material is recessed from a top edge of a nearest portion of the diffusion barrier to form an air gap; and, 'a first metal pad comprising], 'a first device die comprising a second dielectric layer bonded to the first dielectric layer; and', 'a second metal pad bonded to the first metal pad through metal-to-metal direct bonding., 'a second device die comprising2. The device of claim 1 , wherein the air gap further extends into the second metal pad.3. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second metal pad.4. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second dielectric layer.5. The device of claim 1 , wherein a surface of the metallic material in the first metal pad and facing the air gap is rounded.6. The device of claim 1 , wherein a surface of the second metal pad facing the air gap is rounded.7. The device of claim 1 , wherein the first device die further comprises a third metal pad comprising ...

BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS

A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another. 1. A system comprising:a layer of insulating material with holes therein;a seed layer seated within the holes, wherein the seed layer is recessed below a top surface of the insulating material that is opposite a bottom surface of the holes; anda respective bump structure seated in the seed layer of each hole.2. The system as recited in claim 1 , wherein the bump structures are on one of a photodiode array (PDA) or a read-out integrated circuit (ROIC) claim 1 , and wherein the PDA and ROIC are joined together by the bump structures.3. The system as recited in claim 2 , wherein the PDA and ROIC define a plurality of pixels claim 2 , wherein the plurality of pixels have a pitch size claim 2 , wherein the pitch size is less than 10 μm.4. The system as recited in claim 1 , wherein the bump structures each have a diameter less than 5 um.5. The system as recited in claim 1 , wherein the bump structures each have a height to diameter ratio of greater than 1:1.6. The system as recited in claim 1 , wherein a portion of the bump structures extend from the seed layer proud of the top surface of the insulating material.7. The system as recited in claim 1 , further comprising a dielectric layer on the top surface of the insulating material claim 1 , wherein the seed layer is recessed below the insulating material to provide a gap between the bump structures and the insulating material claim 1 , wherein the gap between the bump structures and the insulating material is also ...

Methods and devices for fabricating and assembling printable semiconductor elements

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife. 1. A method of removing material from a semiconductor device , comprising:providing a semiconductor substrate comprising a length L, a first surface, and a second surface opposite the first surface;forming a layer of material over the first surface of the semiconductor substrate;providing a conveyor;providing a first air-knife disposed over the conveyor;providing a second air-knife disposed over the conveyor and offset from the first air-knife by a distance D that is less than the length L of the semiconductor substrate;placing the semiconductor substrate on the conveyor with the layer of material oriented facing away from the conveyor, the semiconductor substrate being placed on the conveyor before the first air-knife and before the second air-knife;advancing the semiconductor substrate along the conveyor and under the first air-knife so that a portion of the semiconductor substrate is disposed between the first air-knife and the second air-knife;forming a pool of etching solution by dispensing an etching solution onto the layer of material over the portion of the semiconductor substrate disposed between ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

PACKAGING METHOD AND PACKAGE STRUCTURE FOR FINGERPRINT RECOGNITION CHIP AND DRIVE CHIP

A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure. 1. A packaging method for a fingerprint recognition chip and a drive chip , comprising:preparing a wafer and a drive chip, wherein the wafer has a first surface and a second surface facing away from the first surface, the first surface of the wafer is provided with a fingerprint recognition chip, the drive chip has a first surface and a second surface facing away from the first surface, and the first surface of the drive chip is provided with a drive circuit and a second contact pad;forming a blind hole from the second surface of the wafer;securing the drive chip in the blind hole, with the first surface of the drive chip being flush with the second surface of the wafer; andcutting the wafer.2. The packaging method according to claim 1 , wherein the fingerprint recognition chip comprises a sensing region and a first contact pad around the sensing region claim 1 , and the blind hole is formed in a region corresponding to the sensing region of the fingerprint recognition chip.3. The packaging method according to claim 2 , wherein after the securing the drive chip in the blind hole and before the cutting the wafer claim 2 , the packaging method further comprises:forming a through hole from ...

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES

The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening. 1. A bond pad structure comprising:a dielectric layer;at least one bond pad in the dielectric layer, having a bond pad top surface;a passivation layer having an interface with a first portion of the bond pad top surface;an opening in the passivation layer over the bond pad, wherein the opening has sidewalls;a low-k barrier layer covering the sidewalls of the opening and a second portion of the bond pad top surface; andprotective structures over the low-k barrier layer at the sidewalls of the opening.2. The bond pad structure of claim 1 , wherein the protective structures are over an end of the interface adjacent to the second portion of the bond pad top surface.3. The bond pad structure of claim 1 , wherein the protective structures have a thickness in a range of 2000 to 5000 Å.4. The bond pad structure of claim 1 , wherein the low-k barrier layer comprises SiCN claim 1 , SiON or SiN.5. The bond pad structure of claim 1 , wherein the low-k barrier layer has a thickness in a range of 50 Å to 125 Å.6. The bond pad structure of further comprising a wire bonded to the bond pad claim 1 , wherein the wire is made of copper.7. A bond pad structure comprising:a dielectric layer;at least one copper bond pad in the dielectric layer, having a bond pad top surface;a passivation layer having an interface with a first portion of the bond pad top surface;an opening in the passivation layer over the bond pad ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS, AND WAFER LIFT PIN-HOLE CLEANING JIG

To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor wafer is processed by the semiconductor manufacturing apparatus in which reaction product in the inside of a wafer lift pin hole was removed using a cleaning jig having a return on its tip part. 1. A method for manufacturing a semiconductor device , comprising the steps of:a) forming a thin film on a principal plane of a semiconductor wafer;b) applying a photoresist film onto the thin film;c) forming a mask pattern by transferring a predetermined circuit pattern to the photoresist film by photolithography; andd) performing dry etching processing on the semiconductor wafer with a dry etching apparatus that removed reaction product inside a wafer lift pin hole using a cleaning jig having a return on its tip part.2. The method for manufacturing a semiconductor device according to claim 1 ,wherein the reaction product is scraped out to the outside of the wafer lift pin hole by the return on the tip part of the cleaning jig.3. The method for manufacturing a semiconductor device according to claim 2 ,wherein the cleaning jig has a through hole for sucking the reaction product that is scraped out and the reaction product that is scraped out is discharged to the outside of the wafer lift pin hole through the through hole.4. The method for manufacturing a semiconductor device according to claim 2 ,wherein the cleaning jig has a through hole that supplies a solvent to the tip part of the cleaning jig, the solvent is supplied to the tip part through the through hole, and the reaction product inside the wafer lift pin hole is solved and removed by the solvent being jetted from the tip part.5. The method for manufacturing a semiconductor device according to claim 1 ,wherein the cleaning jig is such that at least the tip part is formed of a material that is difficult to be electrified.6. The method for manufacturing a ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

INTEGRATION AND BONDING OF MICRO-DEVICES INTO SYSTEM SUBSTRATE

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds. 1. A method of electrically bonding a microdevice into a receiver substrate , the method comprising:bonding at least a part of one surface of at least one bonding pad on a receiver substrate to at least a part of another surface of at least an optoelectronic microdevice on a donor substrate; andwherein a gap between the pads and the optoelectronic microdevice is covered with a coated nanowire.2. The method of claim 1 , wherein the nanowire coating comprises of nanoparticles.3. The method of claim 1 , wherein the nanowire coating is done by deposition of metal on the nanowire.4. The method of claim 1 , wherein the nanowire coating is In claim 1 , Ag or Sn.5. The method of claim 1 , wherein the nanowire is a metal claim 1 , a TOC or a carbon nanotube.6. The method of claim 1 , wherein an electrical energy is applied to the nanowire to reduce the resistivity.7. The method of claim 6 , wherein the electrical energy is applied as a pulsed voltage.8. The method of claim 1 , wherein a bonding material enhances the eutectic bonding to form alloys with Ag nano-wires and lower the thermal input required for bonding9. The method of claim 1 , wherein the dc current is 400 mA applied constantly for 80 seconds.10. The method of claim 1 , wherein a resistance is decreased via a deposition of the bonding material onto Ag nano-wires by applying a 25-800 mA DC current. This application is a continuation of U.S. Nonprovsisional application Ser. No. 16/189,844, filed on ...

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Under Bump Metallurgy (UBM) And Methods Of Forming Same

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die. 1. A method for forming a device package , the method comprising:forming a seed layer over a die;forming a conductive line on the seed layer;forming a first mask layer over the conductive line and the seed layer; a first opening for a conductive pad portion of an under bump metallurgy (UBM); and', 'a second opening for a retaining wall portion of the UBM, wherein the second opening forms a ring around the first opening, and wherein a portion of the first mask layer remains disposed between the first opening and the second opening;, 'patterning openings in the first mask layer, wherein the openings compriseforming the UBM in the first opening and the second opening, the UBM comprising the conductive pad portion contacting a surface of the conductive line, the UBM further comprising the retaining wall portion having a bottom-most portion physically contacting the conductive line;removing the first mask layer; andmounting a solder ball to the conductive pad portion of the UBM.2. The method of claim 1 , wherein forming the UBM comprises filling the first opening and the second opening with conductive material.3. The method of claim 2 , wherein filling the first opening and the second opening with conductive material comprises providing nucleation sites for a plating process claim 2 , wherein the nucleation sites are provided by at least one of the conductive line or the seed layer.4. The method of claim 1 , wherein forming the conductive line comprises:before forming the first mask layer, forming a second mask layer over the seed layer;patterning a third opening in ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

Semiconductor Device and Method of Manufacture

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions. 1. A semiconductor device comprising:a contact pad over a first dielectric layer over an interposer substrate; anda passivation layer over a first portion of the first dielectric layer, wherein a sidewall of the passivation layer is aligned with a first sidewall of the first dielectric layer and wherein the first dielectric layer has a second sidewall facing the first sidewall, the second sidewall being misaligned from the passivation layer.2. The semiconductor device of claim 1 , further comprising a second dielectric layer between the first dielectric layer and the interposer substrate claim 1 , the second dielectric layer having a third sidewall aligned with the first sidewall and a fourth sidewall aligned with the second sidewall.3. The semiconductor device of claim 2 , further comprising a third dielectric layer between the second dielectric layer and the interposer substrate claim 2 , the third dielectric layer having a fifth sidewall aligned with the first sidewall and a sixth sidewall aligned with the second sidewall.4. The semiconductor device of claim 1 , further comprising a semiconductor die electrically connected to contact pad through the passivation layer.5. The semiconductor device of claim 1 , further comprising an encapsulant in physical contact with the first sidewall and the second sidewall.6. The semiconductor device of claim 5 , wherein the encapsulant is in physical contact with at least one conductive element located over the first dielectric layer claim 5 , the at least one conductive element having a sidewall facing the passivation layer.7. The semiconductor device of claim 1 , further comprising through ...

Dishing prevention columns for bipolar junction transistors

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Source Down Semiconductor Devices and Methods of Formation Thereof

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

Semiconductor Die Singulation and Structures Formed Thereby

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. 1. A method comprising:receiving a wafer comprising:a first integrated circuit die;a second integrated circuit die; anda scribe line region between the first integrated circuit die and the second integrated circuit die; andforming a kerf in the scribe line region, wherein the kerf extends through a plurality of dielectric layers into a semiconductor substrate, and wherein the kerf comprises:a first width at an interface between the plurality of dielectric layers and the semiconductor substrate; anda second width at a surface of the plurality of dielectric layers opposite the semiconductor substrate, wherein a ratio of the first width to the second width is at least about 0.6.2. The method of claim 1 , wherein an angle between a bottom surface of the kerf and a sidewall of the kerf is about 90° to about 135°.3. The method of further comprising after forming the kerf claim 1 , using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die.4. The method of claim 3 , wherein the mechanical sawing process comprises using a saw blade having a third width claim 3 , wherein the third width is less than the first width.5. The method of claim 1 , wherein forming the kerf in the scribe line region comprises a laser ablation process.6. The method of claim 5 , wherein the laser ablation process further forms a recast region on a sidewall of the plurality of dielectric layers and a sidewall ...

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads. 1. An integrated circuit (IC) device , comprising:metal circuitry; and a plurality of vertically-extending teeth formed from a first material; and', 'a fill material located between the plurality of vertically-extending teeth formed from a second material different than the first material;', 'wherein the plurality of vertically-extending teeth define an abrasive structure configured to facilitate a bonding of another structure to the multi-material toothed bond pad., 'at least one multi-material toothed bond pad connected to the metal circuitry, each multi-material toothed bond pad comprising2. The IC device of claim 1 , wherein the IC device comprises an interposer.3. The IC device of claim 1 , wherein the IC device comprises an IC die.4. The IC device of claim 1 , wherein the plurality of vertically-extending teeth comprise oxidized teeth including an oxide layer formed on each vertically-extending tooth.5. The IC device of claim 4 , wherein the oxide layer formed on each vertically-extending tooth defines the abrasive structure.6. The IC device of claim ...

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A method of manufacturing a semiconductor device , the method comprising:pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; andannealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.3. The method of claim 1 ...

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a chip having a frontside and a backside, the chip comprising four corner areas;a die bonded to the frontside of the chip by a first set of conductive connectors;a molding layer on the frontside of the chip and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the chip, each of the dam structures being disposed a distance from an edge of the chip, each of the dam structures being circular in a plane parallel to the backside of the chip; anda second set of conductive connectors on the backside of the chip.2. The package of claim 1 , wherein the dam structure is electrically isolated from the chip.3. The package of claim 1 , wherein a distance between the frontside of the chip and a surface of the molding layer distal the frontside of the chip is greater than a distance between the frontside of the chip and a surface of the die distal the frontside of the chip.4. The package of claim 1 , further comprising a through via extending through the chip.5. The package of claim 4 , wherein the through via comprises a metal via and a barrier layer lining sidewalls of the metal via.6. The package of claim 5 , further comprising an insulation layer between the chip and the through via claim 5 , the insulation layer comprising an oxide.7. The package of claim 1 , wherein the dam structure comprises a polymer material.8. The package of claim 1 , wherein a diameter of the dam structure is less than a diameter of each of the conductive ...

SEMICONDUCTOR DEVICE PRODUCTION METHOD

A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4. 1. A semiconductor device production method comprising:forming a first recess portion in a first insulating film formed on a first substrate;forming a first conductive layer on a front surface of the first insulating film located both inside and outside the first recess portion;forming, in the first recess portion, a first pad having a width of 3 μm or less and including the first conductive layer by performing a first process of polishing the first conductive layer at a first polishing rate and, after the first process, a second process of polishing the first conductive layer at a second polishing rate which is lower than the first polishing rate, wherein the second process is performed such that a selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4; andjoining the first pad of the first substrate and a second pad of a second substrate together by annealing the first substrate and the second substrate.2. The semiconductor device production method according to claim 1 , wherein the first conductive layer contains copper.3. The semiconductor device production method according to ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING DEVICE

The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor. 1. A semiconductor device , comprising:a first substrate including a first electrode including a metal; anda second substrate bonded to the first substrate and including a second electrode including a metal,wherein an acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed.2. The semiconductor device according to claim 1 , wherein side roughness is formed in a part of the side surface of the groove claim 1 , anda metal seed corresponding to a shape of the groove, part of which has the side roughness, is formed between the groove and the metal.3. The semiconductor device according to claim 1 , wherein a part of the side surface of the groove has an acute-angled concavo-convex shape claim 1 , anda metal seed corresponding to the shape of the groove is formed between the groove and the metal.4. A semiconductor device manufacturing method claim 1 , comprising:forming side roughness in a part of a side surface of a groove in which an electrode including a metal is formed;forming a metal ...

METHOD FOR FORMING PACKAGE STRUCTURE WITH A BARRIER LAYER

A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC. 1. A method for forming a package structure , comprising:forming an under bump metallization (UBM) layer over a metal pad;forming a photoresist layer over the UBM layer;patterning the photoresist layer to form an opening in the photoresist layer, wherein a first portion of the UBM layer is exposed by the opening;forming a first bump structure over the first portion of the UBM layer, wherein the first bump structure comprises a first barrier layer over a first pillar layer, and a width of the first barrier layer is greater than a width of the first pillar layer;placing a second bump structure over the first bump structure, wherein the second bump structure comprises a second barrier layer over a second pillar layer, and a width of the second barrier layer is greater than a width of the second pillar layer; andreflowing the first bump structure and the second bump structure to form a solder joint, a first inter intermetallic compound (IMC) and a second IMC, wherein the solder joint is between the first IMC and the second IMC.2. The method for forming the package structure as claimed in claim 1 , wherein forming the first bump structure over the first portion of the UBM layer ...

HYBRID BONDING USING DUMMY BONDING CONTACTS

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface. 1. A method for forming a semiconductor device , comprising:forming a first interconnect layer comprising a plurality of first interconnects above a first substrate;forming a first bonding layer comprising a plurality of first bonding contacts above the first interconnect layer, such that each of the first interconnects is in contact with a respective one of the first bonding contacts;forming a second interconnect layer comprising a plurality of second interconnects above a second substrate;forming a second bonding layer comprising a plurality of second bonding contacts above the second interconnect layer, such that at least one of the second bonding contacts is in contact with a respective one of the second interconnects, and at least another one of the second bonding contacts is separated from the second interconnects; andbonding the first substrate and the second substrate in a face-to-face manner, such that each of the first bonding contacts is in contact with one of the ...

Etching liquid, etching method, and method of manufacturing solder bump

An etching liquid which can selectively remove only a copper layer in an etching process of a multilayer structure including a cobalt layer and the copper layer is disclosed. The etching liquid is an etching liquid for etching the copper layer in the multilayer structure including the copper layer and the cobalt layer. This etching liquid includes at least one acid selected from a group consisting of citric acid, oxalic acid, malic acid, and malonic acid, and hydrogen peroxide, the etching liquid having pH in a range of 4.3 to 5.5.

PAD STRUCTURE OF A SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE PAD STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE PAD STRUCTUR

A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection. 1. A method of manufacturing a pad structure of a semiconductor device , the method comprising:pattering an insulating layer to form an insulating layer pattern structure having a plug hole and at least one via hole;forming a plug in the plug hole; andforming a pad on the insulating layer pattern structure, on the plug and in the via hole to electrically connect the plug with the pad,wherein the pad includes a first surface of the pad having a protruded portion filling the via hole, and a second surface of the pad opposite to the first surface, the second surface having a recessed portion and an elevated portion to a location of the protruded portion.2. The method of claim 1 , wherein forming the plug in the plug hole comprises forming the plug on an inner surface of the via hole.3. The method of claim 1 , further comprising forming a passivation layer pattern on the insulating layer pattern structure claim 1 , the passivation layer pattern having an opening configured to expose the upper surface of the pad.4. The method of claim 1 , wherein forming the recessed portion comprises arranging the recessed portion in a direction substantially parallel to side surfaces of the pad claim 1 , and the elevated portion is surrounded by the recessed portion.5. The method of claim 1 , wherein forming the recessed portion and the elevated portion comprises arranging the recessed portion ...

Capacitor in Post-Passivation Structures and Methods of Forming the Same

A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. 1. A method comprising:forming a first dielectric layer on a wafer, wherein the first dielectric layer comprises a first portion and a second portion overlapping a first metal pad and a second metal pad, respectively;etching-through the first portion of the first dielectric layer until the first metal pad is revealed;partially etching the first dielectric layer to remove an upper portion of the second portion of the first dielectric layer, with at least a lower portion of the second portion of the first dielectric layer remaining, and the lower portion overlaps the second metal pad;forming a second dielectric layer over the first dielectric layer; removing a first portion of the second dielectric layer to form a first opening, with the first metal pad exposed through the first opening; and', 'removing a second portion of the second dielectric layer to form a second opening, with the second portion of the first dielectric layer exposed to the second opening; and, 'patterning the second dielectric layer comprisingfilling a conductive material comprising a first portion in the first opening and a second portion in the second opening, wherein the first portion of the conductive material is in contact with the first metal pad, and the second portion of the conductive material is electrically insulated from the second metal pad by the second portion of the first dielectric layer.2. The method of claim 1 , wherein the first dielectric layer comprises a first sub-layer and a second sub-layer over the first sub-layer claim 1 , wherein when the first dielectric layer is ...

BOND PAD STRUCTURE FOR LOW TEMPERATURE FLIP CHIP BONDING

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads. 1. A device comprising:a first and a second semiconductor device having first and second bond pads, respectively, bonded together through the first and second bond pads, the first and second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having a configuration rotated with respect to a configuration of the metal segments of the second bond pad,wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns of segments, the columns being staggered with respect to each other, and the metal segments of the second bond pad on the second semiconductor device comprise only rows of segments, the rows being staggered with respect to each other, wherein the columns of segments are perpendicular to the rows of segments.2. The device according to claim 1 , wherein the first bond pad on the first semiconductor device is larger than the second bond pad on the second semiconductor device.3. The device according to claim 1 , wherein the first and second bond pads each have plural copper segments.4. The device according to claim 1 , wherein the first configuration is rotated at a 45 degree to a 90 degree angle with respect to the second ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING HYBRID BONDING INTERFACE

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases. 1. A method of manufacturing a semiconductor device , comprising:forming a dielectric layer on a substrate;etching the dielectric layer to create a plurality of openings in the dielectric layer;applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;removing the sacrificial layer to form at least one air gap in the dielectric layer; andforming a plurality of protrusions on the bases.2. The method of claim 1 , wherein in a pair of openings claim 1 , only a portion of the dielectric layer is covered by the sacrificial layer.3. The method of claim 1 , wherein the first conductive feature and the bases are arranged in an interleaved configuration.4. The method of claim 1 , wherein the first conductive feature and the bases are formed using a plating process.5. The method of claim 4 , wherein the first conductive feature claim 4 , the bases and the protrusions have the same material.6. The method of claim 1 , wherein the formation of the protrusions comprises:applying a patterned mask comprising a plurality of through holes on the dielectric layer, the ...

BUMP COPLANARITY FOR SEMICONDUCTOR DEVICE ASSEMBLY AND METHODS OF MANUFACTURING THE SAME

Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity. 1. A semiconductor die , comprising:a passivation layer including a dielectric layer over a bond pad and a polyimide layer over the dielectric layer;a first opening in the passivation layer, the first opening extending from a surface of the passivation layer to a surface of the bond pad;a first conductive pillar disposed within the first opening, the first conductive pillar connected to the bond pad and having a first height above the surface of the passivation layer;a second opening in the passivation layer, the second opening extending from the surface of the passivation layer past the polyimide layer; anda second conductive pillar disposed within the second opening, the second conductive pillar having a second height above the surface of the passivation layer, wherein a difference between the first and second heights is less than or equal to a predetermined value.2. The semiconductor die of claim 1 , wherein the predetermined value is greater than or equal to five (5) and less than or equal to seven (7) micrometers.3. The semiconductor die of claim 1 , wherein:the first opening has a first depth; andthe second opening has a second depth less than the ...

Method of manufacturing semiconductor device

To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface. 1. A semiconductor component , comprising:a substrate; anda pad having an upper surface and a slot;wherein the slot is recessed with respect to the upper surface.2. The semiconductor component as claimed in claim 1 , further comprises:a passivation layer having an opening;wherein a first inner sidewall of the opening is aligned with a second inner sidewall of the slot.3. The semiconductor component as claimed in claim 1 , wherein the pad comprises a pad portion and a periphery portion surrounding the pad portion claim 1 , and the slot is located between the pad portion and the periphery portion.4. The semiconductor component as claimed in claim 1 , wherein the slot is a ring-shaped slot.5. The semiconductor component as claimed in claim 4 , wherein the slot is a closed ring-shaped slot.6. The semiconductor component as claimed in claim 1 , wherein the slot has a width ranging between 0.1 micrometers and 2.0 micrometers.7. The semiconductor component as claimed in claim 1 , further comprises:a solder wire partially formed within the slot.8. The semiconductor component as claimed in claim 7 , wherein at least one portion of the slot is filled with the solder wire.9. A manufacturing method for a semiconductor component claim 7 , comprising:forming a pad structure and an etching stop structure on a substrate, wherein the etching stop structure covers the pad structure, wherein the pad structure comprises a pad portion and a periphery portion surrounding the pad portion;removing a periphery portion of the etching stop structure to form a retained portion of the etching stop structure covering the pad portion of the pad structure, wherein the periphery portion of the pad structure is exposed from the retained portion; andforming a slot on the periphery portion of the pad ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Semiconductor device

A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

PHOTOSENSITIVE RESIN COMPOSITION AND ELECTRONIC COMPONENT

Provided is a resin which has high elongation, low stress, high sensitivity and high film retention ratio if used in a photosensitive resin composition. A photosensitive resin composition that contains a resin which has a structure represented by general formula (1) and/or general formula (2), and which is characterized in that (a) 10-80% by mole of an organic group having an alicyclic structure and 4-40 carbon atoms is contained as the Rmoiety of general formulae (1) and (2), and (b) 10-80% by mole of an organic group having a polyether structure with 20-100 carbon atoms is contained as the Rmoiety of general formulae (1) and (2). (In general formulae (1) and (2), Rrepresents a tetravalent organic group having a monocyclic or condensed polycyclic alicyclic structure and 4-40 carbon atoms; Rrepresents a divalent organic group having a polyether structure with 20-100 carbon atoms; Rrepresents a hydrogen atom or an organic group having 1-20 carbon atoms; each of n1 and n2 represents a number within the range of 10-100,000; and p and q represents integers satisfying 0≦p+q≦6.) 4. The photosensitive resin composition according to claim 1 , wherein the resin having a structure represented by the general formula(e) (1) and/or (2) further comprises an organic group as Rat 20 to 90 mol % claim 1 , the organic group containing a fluorine atom.5. The photosensitive resin composition according to claim 1 , further comprising a photo acid generator.6. The photosensitive resin composition according to claim 5 , further comprising a multifunctional acrylate compound.7. A photosensitive sheet formed of the photosensitive resin composition according to .8. A method for producing a photosensitive sheet claim 1 , comprising the step of coating a base material with the photosensitive resin composition according to and drying the composition.9. A cured film obtained by curing the photosensitive resin composition according to .10. A cured film obtained by curing the photosensitive sheet ...

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...

METHODS AND APPARATUS FOR DETERMINING ENDPOINTS FOR CHEMICAL MECHANICAL PLANARIZATION IN WAFER-LEVEL PACKAGING APPLICATIONS

Methods and apparatus for chemical mechanical planarization (CMP) of a polymer or epoxy-based layer. In some embodiments, the method may comprise obtaining an endpoint for polymer or epoxy-based material for use in a CMP process, the CMP process configured to polish polymer or epoxy-based material, monitoring the polymer or epoxy-based layer with an endpoint detection apparatus configured to monitor polymer or epoxy-based material, polishing the polymer or epoxy-based layer with the CMP process, detecting when the polymer or epoxy-based layer has reached the endpoint for the CMP process, and halting the CMP process when the endpoint is detected. The endpoint detection apparatus may further comprise an optical detection apparatus configured to operate at a wavelength of approximately 200 nm to approximately 1700 nm to reduce step height of the polymer or epoxy-based layer. 1. A method for chemical mechanical planarization (CMP) of a polymer or epoxy-based layer , comprising:obtaining an endpoint for polymer or epoxy-based material for use in a CMP process, the CMP process configured to polish polymer or epoxy-based material;monitoring the polymer or epoxy-based layer with an endpoint detection apparatus configured to monitor polymer or epoxy-based material;polishing the polymer or epoxy-based layer with the CMP process;detecting when the polymer or epoxy-based layer has reached the endpoint for the CMP process; andhalting the CMP process when the endpoint is detected.2. The method of claim 1 , further comprising:using an optical detection apparatus as the endpoint detection apparatus, the optical detection apparatus is configured to operate at a wavelength of approximately 200 nm to approximately 1700 nm and is configured to reduce step height of the polymer or epoxy-based layer such that a surface of the polymer or epoxy-based layer has a uniformity that supports a redistribution layer with at least two lead outs with line and spacing of approximately greater than 0 ...

Barrier materials between bumps and pads

Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

FIRST WAFER, FABRICATING METHOD THEREOF AND WAFER STACK

A first wafer, a method of fabricating thereof and a wafer stack are disclosed. The first wafer includes a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer residing on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer. Filling the first contact holes and the first switching holes with different interconnection layers reduces the difficulty in fabricating interconnection structures for the first metal layers. 1. A first wafer , comprising:a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer.2. The first wafer of claim 1 , wherein the first interconnection layer is made of a material comprising tungsten claim 1 , and wherein the second interconnection layer is made of a material comprising copper.3. The first wafer of ...

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate. 1. An apparatus , comprising:a substrate; anda first bonding pad including thermal pathways in direct contact with a backside of the substrate, wherein the thermal pathways are disposed in channels formed in a passivation layer on the backside of the substrate.2. The apparatus of claim 1 , wherein the thermal pathways are formed under the first bonding pad.3. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways form concentric circles or a spiral in the passivation layer.4. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways are distributed in parallel relative to each other and such that the thermal pathways extend along a length of the first bonding pad.5. The apparatus of claim 1 , wherein the substrate further includes a through-via extending from the backside of the substrate to a frontside of the substrate.6. The apparatus of claim 5 , further comprising a second bonding pad disposed on the passivation layer and coupled to the through-via.7. The apparatus of claim 6 , wherein the second bonding is disposed as a circular bonding pad on the through-via.8. The apparatus of claim 6 , wherein the first bonding pad and the second bonding pad are substantially equal in height.9. The apparatus of claim 6 , further comprising electrical interconnections formed on the first bonding pad and the second bonding pad.10. The apparatus of claim 6 , wherein the first bonding pad ...

Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Semiconductor package with air gap

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF

Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions. 1. (canceled)2. The method of wherein forming comprises forming the texturized dielectric region such that the texture pattern has a maximum feature depth less than the thickness of the under-pad dielectric layer.3. The method of wherein forming comprises photolitographically patterning the under-pad dielectric layer to create the texturized dielectric region therein.4. The method of wherein producing comprises:depositing a metal level over the under-pad dielectric layer after patterning thereof; andpatterning the metal level to define the texturized solder pad and at least one interconnect line electrically coupled to the texturized solder pad.5. The method of wherein the interconnect line has an average thickness claim 4 , wherein the texture pattern is produced to have a minimum feature width claim 4 , and wherein the minimum feature width of the texture pattern is at least twice the average thickness of the interconnect line.6. The method of further comprising:depositing a solder mask layer over the texturized solder pad;forming a solder mask opening in the solder mask exposing the texturized solder pad; andforming a solder contact over the solder mask opening and bonded to the texturized solder pad.7. The method of wherein depositing comprises depositing the under-pad dielectric layer over a molded panel in which at least one semiconductor ...

Word Line Hook Up with Protected Air Gap

A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word lines, and forming a dummy structure directly opposite an air gap between neighboring word lines. Subsequently, the contact pad structures are cut into individual contact pads by a contact pad cut that intersects the dummy structure. 1. A semiconductor device comprising:a plurality of word lines separated by air gaps;a plurality of contact pads, an individual contact pad connected to an individual word line;a contact pad cut that extends between neighboring contact pads, the contact pad cut separating the neighboring contact pads; anda dummy structure that is intersected by the contact pad cut, the dummy structure located directly opposite an air gap between neighboring word lines.2. The semiconductor device of wherein the dummy structure is a ring with an inner open area.3. The semiconductor device of wherein the contact pad cut terminates in the inner open area so that a portion of the ring remains between the contact pad cut and the air gap.4. The semiconductor device of further comprising an air gap capping layer that extends over the air gap and extends over a volume immediately adjacent to the portion of the ring that remains between the contact pad cut and the air gap.5. The semiconductor device of wherein the volume and the air gap are isolated from the contact pad cut by the portion of the ring that remains between the contact pad cut and the air gap.6. The semiconductor device of wherein the contact pad cut extends along a line that does not intersect the air gap.7. A method of forming a semiconductor device comprising:forming a plurality of word lines separated by air gaps;forming a plurality of contact pad structures connected to the word lines;forming a dummy structure directly opposite an air gap between neighboring word lines; andsubsequently cutting the contact pad structures into individual ...

SEMICONDUCTOR DEVICE PACKAGE WITH ORGANIC INTERPOSER

A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer. 1. A method for manufacturing an integrated circuit package , the method comprising:a) providing a flexible tape having first and second sets of bond pads on respective first and second surfaces thereof;b) attaching the first surface of the flexible tape to a carrier;c) forming conductive pillars on the second set of bond pads;d) depositing an intermediate layer of polymeric compound on the second surface of the flexible tape;e) grinding a surface of the intermediate layer to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer;f) removing the carrier from the sub-assembly, thereby creating an interposer;g) attaching the interposer to a substrate; andh) attaching at least one die to the interposer.2. The method of wherein the flexible tape has one or more conductive traces and one or more vias configured to interconnecting the first and second sets of bond pads.3. The method of wherein the second set of bond pads has a pitch greater than that of the first set of bond pads.4. The method of claim 1 , wherein step c) comprises:c1) depositing photoresist on the second surface of the flexible tape;c2) ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality of solder pads. The patterned solder resist layer is disposed on the substrate and includes a plurality of stepped openings. The stepped openings expose the solder pads respectively. The solders are disposed on the solder pads and located in the stepped openings respectively. The chip is disposed on the substrate and includes an active surface and a plurality of bond pads. The bond pads are disposed on the active surface and connected to the solder pads by the solders. The polymer gel fills between a top surface of the patterned solder resist layer and the active surface. The polymer gel at least surrounds a disposing region of the solders and fills between two adjacent solders. 1. A manufacturing method of a package structure , comprising:providing a substrate, wherein the substrate comprises a plurality of solder pads;forming a patterned solder resist layer on the substrate, wherein the patterned solder resist layer comprises a plurality of stepped openings exposing the solder pads respectively;disposing a polymer gel on a top surface of the patterned solder resist layer, wherein the polymer gel at least surrounds a disposing region of the solder pads and disposed between adjacent two of the solder pads;disposing a plurality of solders on the solder pads respectively, wherein the solders are located in the stepped openings respectively;disposing a chip on the substrate, wherein the chip comprises an active surface and a plurality of bond pads located on the active surface and the bond pads are connected to the solder pads through the solders; andperforming a reflow process on the solders, such that the polymer gel is filled between a top surface of the patterned solder resist layer and the active surface.2. The manufacturing method of a package structure as claimed in claim 1 , wherein the step of forming ...

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat. 1. A method of fabricating an integrated circuit (IC) chip , the method comprising:etching an opening through a passivation overcoat to a copper metallization layer;depositing a barrier conductive stack on the passivation overcoat and in the opening on the copper metallization layer;depositing a sacrificial conductive stack on the barrier conductive stack; andpolishing to remove the sacrificial conductive stack and the barrier conductive stack from over the passivation overcoat.2. The method of claim 1 , wherein the barrier conductive stack comprises a first layer of tantalum nitride.3. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of nickel.4. The method of claim 3 , wherein the barrier conductive stack further comprises a second layer of tantalum nitride.5. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of tungsten.6. The method of claim 1 , wherein the sacrificial conductive stack comprises any of palladium claim 1 , platinum claim 1 , gold claim 1 , ruthenium or any combination thereof.7. The method of claim 1 , further comprising performing an etching process to remove the sacrificial conductive stack from at ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. 1. A method of forming a direct hybrid bond surface , comprising:forming a first plurality of metallic contact structures in an upper surface of a first substrate, where a top surface of said structures is below said upper surface;forming a first layer of conductive barrier material over said upper surface and said plurality of metallic contact structures; andremoving said first layer of conductive barrier material from said upper surface.2. The method according to claim 1 , comprising:removing said first layer conductive barrier material to leave said conductive barrier material on said plurality of metal contact structures, a top surface of said conductive barrier material on said plurality of metal contact structures being below said upper surface of said substrate by less than 20 nm.3. The method according to claim 1 , comprising:removing said first layer of conductive barrier material to leave said conductive barrier material on said plurality of metal contact structures, a top surface of said conductive barrier material on said plurality of metal contact structures being below said upper surface of said substrate in a ...

Semiconductor chip, semiconductor package including the same, and method of fabricating the same

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.