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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2047. Отображено 100.
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 1
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 2
10-05-2012 дата публикации

Method for manufacturing a semiconductor device having a refractory metal containing film

Номер: US20120115324A1
Автор: Mari Watanabe, Toshiyuki Takewaki
Принадлежит: Renesas Electronics Corp

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

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Номер записи: 3
21-06-2012 дата публикации

Chip Pad Resistant to Antenna Effect and Method

Номер: US20120156870A1
Автор: Ji-Shyang Nieh, Wu-Te Weng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

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Номер записи: 4
19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

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Номер записи: 5
16-08-2012 дата публикации

MEMS and Protection Structure Thereof

Номер: US20120205808A1
Автор: Bang-Chiang Lan, Chao-An Su, Chien-Hsin Huang, Hui-Min Wu, Li-Che Chen, Meng-Jia Lin, Min Chen, Ming-I Wang, Tzung-Han Tan, Tzung-I Su
Принадлежит: United Microelectronics Corp

A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.

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Номер записи: 6
22-11-2012 дата публикации

Methods and structures for forming integrated semiconductor structures

Номер: US20120292748A1
Автор: Mariam Sadaka, Radu Ionut
Принадлежит: Soitec SA

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

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Номер записи: 7
27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1
Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding
Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 8
03-01-2013 дата публикации

Semiconductor Constructions

Номер: US20130001788A1
Автор: Akram Ditali, Tianhong Zhang
Принадлежит: Micron Technology Inc

Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

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Номер записи: 9
17-01-2013 дата публикации

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

Номер: US20130015575A1
Автор: Haijing Cao, Qing Zhang, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

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Номер записи: 10
12-09-2013 дата публикации

Semiconductor device bonding with stress relief connection pads

Номер: US20130234327A1
Автор: Hiroshi Okumura, Masaki Kasai
Принадлежит: ROHM CO LTD

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

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Номер записи: 11
03-10-2013 дата публикации

Bonded processed semiconductor structures and carriers

Номер: US20130256907A1
Автор: Ionut Radu, Mariam Sadaka
Принадлежит: Soitec SA

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

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Номер записи: 12
28-11-2013 дата публикации

Semiconductor integrated circuit device

Номер: US20130313708A1
Автор: Akira Yajima, Hiromi Shigihara, Hiroshi Tsukamoto
Принадлежит: Renesas Electronics Corp

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

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Номер записи: 13
20-02-2014 дата публикации

Semiconductor device including a buffer layer structure for reducing stress

Номер: US20140048933A1
Автор: Masatoshi Tagaki, Takeshi Yuzawa
Принадлежит: Seiko Epson Corp

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer

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Номер записи: 14
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20170005055A1
Автор: Suzuki Shinya
Принадлежит:

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are ...

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Номер записи: 15
05-01-2017 дата публикации

CHIP PACKAGE

Номер: US20170005057A1
Автор: Huang Alex, HURWITZ DROR
Принадлежит: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material. 1. An embedded die package comprising a die having die contract pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material.2. The embedded die package of wherein the die contact pads comprise aluminum.3. The embedded die package of wherein the passivation layer comprises either PI or SiN.4. The embedded die package of wherein the adhesion/barrier layer is selected from the group consisting of Ti/Cu claim 1 , Ti/W/Cu claim 1 , Ti/Ta/Cu claim 1 , Cr/Cu and Ni/Cr.5. The embedded die package of wherein the adhesion/barrier layer has a thickness in the range of from 0.05 microns to 1 microns.6. The embedded die package of wherein the feature layer comprises copper.7. The embedded die package of wherein the feature layer has a thickness in the range of from 1 micron to 25 micron.8. The embedded die package of wherein the layer of pillars has a height in the range of 15 microns to 50 microns.9. The embedded die package of wherein the feature layer has a fan-out form.10. The embedded die package of wherein the feature layer has a fan-in form.11. The embedded die package of wherein said chip and said layer of pillars are embedded in different polymer dielectric materials.12. The embedded die package of wherein said layer of pillars comprises a grid array of pads that serve as contacts for coupling the die to a substrate.13. The embedded die package of wherein the substrate is a PCB.14. The embedded ...

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Номер записи: 16
05-01-2017 дата публикации

CHIP PACKAGE

Номер: US20170005058A1
Автор: Huang Alex, HURWITZ DROR
Принадлежит: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

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Номер записи: 17
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005981A1
Автор: Fujii Kenji, Haga Motoharu, Kasuya Yasumasa, KIMURA Akihiro, NAGAHARA Toichi, Yoshida Shingo
Принадлежит: ROHM CO., LTD.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

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Номер записи: 18
02-01-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20200006275A1
Автор: CHEN Jun, CHENG Weihua, DING Taotao, Hu Siping, HUA Ziqun, WANG Jiawen, WANG TAO, Wang Xinsheng, YANG Shining, ZHU Hongbin, Zhu Jifeng
Принадлежит:

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first bonding layer on the surface of first substrate, the material of first bonding layer includes dielectrics such as Si, N and C, and the first bonding layer of semiconductor structure is provided with higher bonding force in wafer bonding. 1. A semiconductor structure , comprising:a first substrate; anda first bonding layer on a surface of said first substrate, wherein a material of said first bonding layer comprises dielectric materials of silicon, nitrogen and carbon.2. The semiconductor structure of claim 1 , wherein an atomic concentration of carbon in said first bonding layer is larger than 0% and smaller than 50%.3. The semiconductor structure of claim 1 , wherein an atomic concentration of carbon in said first bonding layer is uniform.4. The semiconductor structure of claim 1 , wherein said atomic concentration of carbon in said first bonding layer gradually changes along with the increase of thickness of said first bonding layer.5. The semiconductor structure of claim 1 , wherein a compactness of said first bonding layer gradually changes along with the increase of thickness of said first bonding layer.6. The semiconductor structure of claim 1 , wherein a thickness of said first bonding layer is larger than 100 Å.7. The semiconductor structure of claim 1 , further comprising a second substrate claim 1 , wherein a second bonding layer is formed on a surface of said second substrate claim 1 , and a surface of said second bonding layer is correspondingly bonded to a surface of said first bonding layer.8. The semiconductor structure of claim 7 , wherein said second bonding layer and said first bonding layer have the same material.9. The semiconductor structure of claim 7 , further comprising:a first bonding pad penetrating through said first bonding layer; anda second bonding pad penetrating through said second ...

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Номер записи: 19
12-01-2017 дата публикации

Assembly comprising two elements of different thermal expansion coefficients and a sintered joint of heterogeneous density and process for manufacturing the assembly

Номер: US20170012017A1
Автор: Benoit Thollin, Rabih KHAZAKA
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

An assembly comprises a first element having a first thermal expansion coefficient, a second element having a second thermal expansion coefficient and at least one joint connecting the first element and second element, wherein the joint is heterogeneous and includes a stack of at least one first elementary joint of first density and of a second elementary joint of second density, the first and second densities being different. A process for manufacturing an assembly according to the invention is provided.

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Номер записи: 20
12-01-2017 дата публикации

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

Номер: US20170012030A1
Автор: LI Zeng, Lu Kai, WANG TAO, ZHAO Zhenqing
Принадлежит: DELTA ELECTRONICS,INC.

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

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Номер записи: 21
11-01-2018 дата публикации

RARE EARTH INTERLAYS FOR MECHANICALLY LAYERING DISSIMILAR SEMICONDUCTOR WAFERS

Номер: US20180012858A1
Автор: Clark Andrew, Dargis Rytis, LEBBY MICHAEL, Pelzel Rodney
Принадлежит:

Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon. 1. A structure comprising:a first layer comprising a Group IV semiconductor;a second layer comprising at least one rare earth element, wherein a first portion of the second layer is either lattice matched or strain balanced to the first layer;a third layer comprising a III-V semiconductor, and wherein the structure contains at least one bonded interface.2. The structure of claim 1 , wherein the third layer includes at least one shared element with a second portion of the second layer.3. The structure of claim 1 , wherein the at least one bonded interface is between the second and third layer.4. The structure of claim 1 , wherein the second layer offsets at least a fraction of a lattice mismatch between the first layer and the third layer.5. The structure of claim 1 , wherein the first layer is silicon.6. The structure of claim 1 , wherein the second layer is conductive.7. The structure of claim 1 , wherein the second layer is comprises of at least one rare earth pnictide.8. The structure of claim 1 , wherein:a first region of the second layer comprises a first rare earth pnictide alloy with rare earth elements in first proportions; anda second region of the second layer comprises the first rare earth pnictide alloy with rare earth elements in second proportions.9. The structure of claim 1 , wherein:a first region of the second layer comprises a first rare earth pnictide alloy with Group V elements in first proportions; anda second region of the second layer comprises the first rare earth pnictide alloy with Group V elements in second proportions.10. The structure of claim 1 , wherein the second layer is comprised of ...

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Номер записи: 22
14-01-2021 дата публикации

BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES

Номер: US20210013166A1
Автор: CHOCKALINGAM RAMASAMY, Melville Ian, TAN Juan Boon
Принадлежит:

The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening. 1. A bond pad structure comprising:a dielectric layer;at least one bond pad in the dielectric layer, having a bond pad top surface;a passivation layer having an interface with a first portion of the bond pad top surface;an opening in the passivation layer over the bond pad, wherein the opening has sidewalls;a low-k barrier layer covering the sidewalls of the opening and a second portion of the bond pad top surface; andprotective structures over the low-k barrier layer at the sidewalls of the opening.2. The bond pad structure of claim 1 , wherein the protective structures are over an end of the interface adjacent to the second portion of the bond pad top surface.3. The bond pad structure of claim 1 , wherein the protective structures have a thickness in a range of 2000 to 5000 Å.4. The bond pad structure of claim 1 , wherein the low-k barrier layer comprises SiCN claim 1 , SiON or SiN.5. The bond pad structure of claim 1 , wherein the low-k barrier layer has a thickness in a range of 50 Å to 125 Å.6. The bond pad structure of further comprising a wire bonded to the bond pad claim 1 , wherein the wire is made of copper.7. A bond pad structure comprising:a dielectric layer;at least one copper bond pad in the dielectric layer, having a bond pad top surface;a passivation layer having an interface with a first portion of the bond pad top surface;an opening in the passivation layer over the bond pad ...

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Номер записи: 23
19-01-2017 дата публикации

Semiconductor device

Номер: US20170018470A1
Автор: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Masanao Sato, Naoki Kawanabe, Takuji Ide
Принадлежит: Renesas Electronics Corp

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

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Номер записи: 24
21-01-2016 дата публикации

MOISTURE BARRIER FOR SEMICONDUCTOR STRUCTURES WITH STRESS RELIEF

Номер: US20160020179A1
Автор: Abrokwah Jonathan, Dixon Forest, Dungan Thomas, Halac Greg, Snyder Rick
Принадлежит:

A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

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Номер записи: 25
18-01-2018 дата публикации

SEMICONDUCTOR MODULE AND POWER CONVERTER

Номер: US20180019180A1
Автор: Murakami Haruhiko, OTSUKI Takami, Yamashita Akihiko, YONEYAMA Rei
Принадлежит: Mitsubishi Electric Corporation

A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive. 1. A semiconductor module comprising:an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer;a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member; anda heat sink that is fixed to the second metal pattern with a second metal joining member, whereinthe semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm,the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive, andno terminals are directly connected to the insulating substrate.2. A semiconductor module comprising:an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer;a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member; anda heat sink that is fixed to the second metal pattern with a second metal joining member, whereinthe semiconductor chip has a ...

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Номер записи: 26
18-01-2018 дата публикации

Package with passivated interconnects

Номер: US20180019197A1
Автор: Dilan Seneviratne, Islam A. Salama, Kristof Darmawikarta, Rahul N. Manepalli, Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram
Принадлежит: Intel Corp

Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

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Номер записи: 27
22-01-2015 дата публикации

Semiconductor Device

Номер: US20150021765A1
Автор: Morifuji Tadahiro, Ueda Shigeyuki
Принадлежит:

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor chip comprising:an electrode pad portion formed on a face of a substrate;a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;a barrier metal layer formed on the electrode pad portion;a bump electrode on the barrier metal layer; anda second protection layer covering a region on the first protection layer and a region on the electrode pad portion,wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion,wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening as seen in a plan view,wherein the bump electrode is bonded to the barrier metal layer,wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer,wherein the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and that has an opening width smaller than the first opening, ...

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Номер записи: 28
17-01-2019 дата публикации

SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS

Номер: US20190019773A1
Автор: TAGAKI Masatoshi, YUZAWA Takeshi
Принадлежит: SEIKO EPSON CORPORATION

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer. 1. A semiconductor device comprising: a pad;', 'a wiring made of polysilicon, first and second portions of the wiring having different widths and being connected together at a junction;', 'a conductive material between the junction and the pad; and', 'a diffusion layer, at least a part of which is overlapped with the second portion of the wiring,', 'wherein the pad is above the junction, the diffusion layer is below the wiring, and the conductive material overlaps the pad, the junction, and the diffusion layer in a plan view from above the pad., 'a semiconductor chip having2. The semiconductor device according to claim I , wherein:the first portion of the wiring is disposed along a first direction; andthe second portion of the wiring is disposed along a second direction orthogonal to the first direction.3. The semiconductor device according to claim 2 , wherein:a third portion of the wiring, which has a width different than the width of the first portion of the wiring, is connected to the first portion at a second junction; andthe third portion is disposed along the second direction.4. The semiconductor device according to claim 2 , whereinthe width of the first portion is wider than the width of the second portion.5. The semiconductor device according to claim 3 , whereinthe width of the first portion is width than the widths of ...

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Номер записи: 29
17-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

Номер: US20190019775A1
Автор: EGUCHI Toyokazu, KAWAMURA Takuma
Принадлежит:

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder hump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump, ...

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Номер записи: 30
21-01-2021 дата публикации

Chip Structure, Wafer Structure And Method For Manufacturing The Same

Номер: US20210020596A1
Автор: Wang Jiaqi, YE Guoliang, YI Hongsheng
Принадлежит: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad. 1. A chip structure , comprising:a first chip and a second chip, wherein a front surface of the first chip is covered with a first bonding layer of a first dielectric material, a front surface of the second chip is covered with a second bonding layer of a second dielectric material, and the first bonding layer is bonded to the second bonding layer;a third bonding layer of a third dielectric material covering a back surface of the second chip;bonding via holes, comprising a first bonding via hole extending from the third bonding layer to a first top wiring layer of the first chip and a second bonding via hole extending from the third bonding layer to a second top wiring layer of the second chip;a third chip, comprising a third top wiring layer, a fourth boding layer and bonding pads, wherein the fourth boding layer is made of a fourth dielectric material and is arranged on the third top wiring layer and convers a front surface of the third chip, each of the bonding pads extends through the fourth bonding layer and is connected to the third top wiring layer, the third bonding layer is bonded to the fourth bonding layer, and the bonding via holes are bonded to the bonding pads; anda lead-out pad extending from a back surface of the third chip to the third top wiring layer.2. The chip ...

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Номер записи: 31
26-01-2017 дата публикации

MULTI-LAYER SUBSTRATE WITH AN EMBEDDED DIE

Номер: US20170025358A1
Автор: Capwell John Avery, Crandall Mark Alan, McChesney Bryan
Принадлежит:

The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component. 1. An apparatus comprising:a core layer having a cavity;a die mounted within the cavity by a mounting material, wherein the die includes a die body, a first die conductive element on a top surface of the die body, and a dielectric layer over the first die conductive element; anda first substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the first die conductive element, wherein overlapping portions of the first die conductive element and the first substrate conductive element are separated by the dielectric layer and form an electronic component.2. The apparatus of wherein the electronic component is a capacitor claim 1 , and the overlapping portions of the first die conductive element and the first substrate conductive element are plates for the capacitor.3. The apparatus of wherein the electronic component is a coupler claim 1 , and the first substrate conductive element and the first die conductive element are used as a primary inductive segment and a secondary inductive segment of the coupler claim 1 , respectively.4. The apparatus of wherein the mounting material is one of a group consisting of epoxy claim 1 , resin claim 1 , and epoxy resin.5. The ...

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Номер записи: 32
26-01-2017 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20170025371A1
Автор: Chen Hsien-Wei, Chen Jie
Принадлежит:

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided. 1. A method for manufacturing semiconductor devices , the method comprising:forming a conductive pad and a metal protrusion pattern in a metallization layer;conformally depositing a passivation layer over the metallization layer;forming a first opening in the passivation layer to expose the conductive pad;conformally depositing a protection layer over the passivation layer;forming a second opening to expose the conductive pad through the first opening;conformally forming a post-passivation interconnect (PPI) structure on the protection layer, the PPI structure having a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad; andplacing a solder bump on the landing pad region in contact with the protrusion pattern of PPI structure.2. The method of claim 1 , wherein the protrusion pattern of PPI structure is a rectangular stud in or across the landing pad region and adjacent to the connection line.3. The method of claim 1 , wherein the PPI structure is redistribution lines (RDLs) claim 1 , power lines claim 1 , or passive components.4. The method of claim 1 , wherein conformally depositing the protection ...

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Номер записи: 33
24-04-2014 дата публикации

Semiconductor devices and processing methods

Номер: US20140110838A1
Автор: Michael Rogalli, Wolfgang Lehnert
Принадлежит: INFINEON TECHNOLOGIES AG

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

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Номер записи: 34
24-01-2019 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20190027453A1
Автор: Kim Yong Ho, LEE IN YOUNG, NOH BO IN, PARK SOO JEOUNG
Принадлежит:

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

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Номер записи: 35
28-01-2021 дата публикации

Wafer Structure, Method For Manufacturing The Same, And Chip Structure

Номер: US20210028151A1
Автор: Hu Sheng, LI YANG
Принадлежит: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration. 1. A chip structure , comprising:a first chip, wherein the first chip comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer; anda second chip, wherein the second chip comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer, whereinthe first chip is stacked with the second chip via the first bonding layer and the second bonding layer with a front surface of the first chip facing toward a front surface of the second chip, and the first capacitor plate is arranged facing toward the second capacitor plate with only at least the second dielectric ...

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Номер записи: 36
04-02-2016 дата публикации

STACKED STRUCTURE OF SEMICONDUCTOR CHIPS HAVING VIA HOLES AND METAL BUMPS

Номер: US20160035707A1
Автор: HUA Chang-Hwang, Lin Chih-Hsien
Принадлежит:

A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer. 1. A stacked structure , comprising: a first substrate having at least one first substrate via hole penetrating through said first substrate;', 'at least one first backside metal layer formed on a backside of said first substrate and covering an inner surface of said at least one first substrate via hole and at least part of said backside of said first substrate;', 'at least one first front-side metal layer formed on a front-side of said first substrate, wherein said at least one first front-side metal layer is electrically connected to said at least one first backside metal layer on a top of at least one of said at least one first substrate via hole;', 'at least one first electronic device formed on said front-side of said first substrate, wherein at least one of said at least one first electronic device is electrically connected to said at least one first front-side metal layer; and', 'at least one first metal bump formed on at least one of said at least one first backside metal layer and said at least one first front-side metal layer., 'a first semiconductor chip, which includes2. The stacked structure according to claim 1 , further comprising a second semiconductor chip claim 1 , ...

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Номер записи: 37
01-02-2018 дата публикации

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Номер: US20180033754A1
Автор: Dugas Roger, Trezza John
Принадлежит:

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

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Номер записи: 38
01-02-2018 дата публикации

OPTOELECTRONIC SEMICONDUCTOR COMPONENT

Номер: US20180033931A1
Автор: Gallmeier Hans-Christoph, Grötsch Stefan, Jerebic Simon, Racz David, Ramchen Johann
Принадлежит:

An optoelectronic semiconductor device includes a carrier having a carrier top side, at least one optoelectronic semiconductor chip arranged at the carrier top side and having a radiation main side remote from the carrier top side, at least one bonding wire, at least one covering body on the radiation main side, and at least one reflective potting compound surrounding the semiconductor chip in a lateral direction and extending from the carrier top side at least as far as the radiation main side, wherein the bonding wire is completely covered by the reflective potting compound or completely covered by the reflective potting compound and the covering body, the bonding wire is fixed to the semiconductor chip in an electrical connection region on the radiation main side, and the electrical connection region is free of the covering body and covered partly or completely by the reflective potting compound. 1. An optoelectronic semiconductor device comprisinga carrier having a carrier top side,at least one optoelectronic semiconductor chip arranged at the carrier top side and having a radiation main side remote from the carrier top side,at least one bonding wire via which electrical contact is made with the semiconductor chip,at least one covering body on the radiation main side that projects beyond the bonding wire in a direction away from the carrier top side and traverse or perpendicularly to the radiation main side, andat least one reflective potting compound surrounding the semiconductor chip in a lateral direction and extending from the carrier top side at least as far as the radiation main side, whereinthe bonding wire is completely covered by the reflective potting compound or completely covered by the reflective potting compound and the covering body,the bonding wire is fixed to the semiconductor chip in an electrical connection region on the radiation main side, andthe electrical connection region is free of the covering body and covered partly or completely by ...

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Номер записи: 39
11-02-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160043060A1
Автор: ARAI Hideyuki, Kabe Tatsuya
Принадлежит:

A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element. 1. A semiconductor device comprising:a first substrate including a first substrate body, and a first surface layer that is provided over a principal surface of the first substrate body, and includes a first surface film, a first electrode having a first surface exposed at an outermost surface of the first surface film, and a second electrode having a second surface exposed at the outermost surface of the first surface film;a second substrate including a second substrate body, and a second surface layer that is provided over a principal surface of the second substrate body, and includes a second surface film, a third electrode having a third surface exposed at an outermost surface of the second surface film, and a fourth electrode having a fourth surface exposed at the outermost surface of the second surface film, where the second substrate is directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; anda functional film provided between the second surface of the second electrode and the fourth surface of the fourth electrode, whereinthe first surface of the first electrode and the third surface of the third electrode are bonded together so as to be in contact with each other, andthe second electrode, the functional film, and the fourth electrode constitute a passive element.2. The semiconductor device of claim ...

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Номер записи: 40
09-02-2017 дата публикации

Integrated Fan-Out Package Structures with Recesses in Molding Compound

Номер: US20170040288A1
Автор: CHENG Li-Hui, Hung Jui-Pin, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface. 1. A package comprising:a device die comprising a substrate and a metal pad overlying the substrate; a first portion, wherein a sidewall of the first portion contacts a first sidewall of the device die, and wherein the first portion comprises a first top surface; and', 'a second portion, wherein a sidewall of the second portion contacts a second sidewall of the device die, wherein the first portion and the second portion are on opposite sides of the device die, and the second portion has a second top surface higher than the first top surface., 'an encapsulating material encapsulating the device die, wherein the encapsulating material comprises2. The package of further comprising a dielectric layer comprising:a first portion overlapping and contacting the first portion of the encapsulating material; anda second portion overlapping and contacting the second portion of the encapsulating material.3. The package of claim 2 , wherein the first portion of the dielectric layer has a top surface lower than a bottom surface of the second portion of the dielectric layer.4. The package of claim 2 , wherein the dielectric layer comprises a top surface comprising:a first surface portion overlapping the encapsulating material;a second surface portion overlapping the device die; anda third surface portion connecting the first ...

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Номер записи: 41
08-02-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180040521A1
Автор: IDE Takuji, Ito Hisanori, KAWANABE Naoki, Sato Masanao, TSUCHIYA Fumio, YASUMURA Bunji
Принадлежит:

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad. 119-. (canceled)20. A semiconductor device , comprising:a semiconductor chip having a first main surface, a second main surface opposite the first main surface, a side extending in a first direction, and a plurality of bonding pads formed on the first main surface and extending along the side,each of the bonding pads having a first side and a second side opposite the first side, extending in the first direction,wherein the first main surface of the semiconductor chip is covered by a protective film in which a plurality of openings are formed, andwherein a peripheral portion of an upper surface of each of the bonding pads is covered by the protective film and a portion other than the peripheral portion of the upper surface of each of the bonding pads is exposed from a corresponding one of the openings. The disclosure of Japanese Patent Application No. 2009-121857 filed on May 20, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.The present invention relates to a semiconductor device, in particular, to a technique effective to be applied to a semiconductor device with a semiconductor chip, having bonding pads, mounted thereon.Japanese Patent Laid-Open No. 1991-79055 (Patent Document 1), for example, discloses an electrode pad provided with a first portion to bond a wire or a film lead and a second portion that is integrally linked to the first portion, can be ...

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Номер записи: 42
08-02-2018 дата публикации

INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20180040592A1
Автор: Derderian James M., Gandhi Jaspreet S., Huang Wayne H.
Принадлежит:

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member. 1. A method of forming a semiconductor die assembly , the method comprising:inserting at least a portion of a first conductive member on a first semiconductor die into at least a portion of a depression of a second conductive member on a second semiconductor die, wherein the second semiconductor die includes a dielectric material and a conductive trace, wherein the dielectric material includes an opening that (a) extends at least partially through the dielectric material, and (b) exposes a portion of the conductive trace, and wherein the second conductive member projects outwardly from the exposed portion of the conductive trace; andat least partially filling the depression of the second conductive member with a bonding material.2. The method of wherein the portion of the first conductive member is a first portion claim 1 , the method further comprising:reacting the bond material with a second portion of the first conductive member to form a first intermetallic at least partially within the depression of the second conductive member; andreacting the bond material with a portion of the second conductive member to form a second intermetallic at least partially within the depression of the second conductive member.3. The method of wherein the first and second intermetallics each include tin/nickel (SnNi) or tin/copper (SnCu) claim 2 , and ...

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Номер записи: 43
08-02-2018 дата публикации

Method for manufacturing semiconductor device

Номер: US20180040741A1
Автор: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

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Номер записи: 44
18-02-2016 дата публикации

High-Power Electronic Device Packages and Methods

Номер: US20160049351A1
Автор: McCann Patrick J.
Принадлежит:

A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications. 1. A high-power electronic device package , comprising:a thermally conductive submount having an upper surface and a lower surface;a first thermally conductive interface layer disposed on the upper surface of the thermally conductive submount;a metal frame and a diamond head bonded to the upper surface of the thermally conductive submount via the first thermally conductive interface layer;a second thermally conductive interface layer disposed on the metal frame and the diamond head;at least one eutectic metal contact positioned in at least one via in the second thermally conductive interface layer; anda high-power electronic device having an epitaxial surface,wherein the epitaxial surface is in contact with the at least one eutectic metal contact, andwherein the epitaxial surface is secured to the eutectic metal contact and to the thermally conductive submount by the second thermally conductive interface layer.2. The high-power electronic device package of claim 1 , further comprising a ground plate bonded to a second surface of the high-power electronic device via a eutectic metal bonding layer.3. The high-power electronic device package of claim 2 , further comprising a heat sink bonded to the ground plate by a second eutectic metal bonding layer.4. The high-power electronic device package of ...

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Номер записи: 45
16-02-2017 дата публикации

Stress Tuning for Reducing Wafer Warpage

Номер: US20170047297A1
Автор: CHIOU Ying-Han, Wang Ling-Sung, Wang Yung-Yao
Принадлежит:

A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively. 1. A method comprising:forming a low-k dielectric layer over a substrate of a wafer;forming a first dielectric layer over the low-k dielectric layer;forming a second dielectric layer over the first dielectric layer;forming a stress tuning dielectric layer over the second dielectric layer;forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer;etching the stress tuning dielectric layer and the second dielectric layer to form a trench, wherein the forming the opening and the etching the stress tuning dielectric layer are separate etching steps;etching the first dielectric layer to form a via opening connected to the trench; andfilling the trench and the via opening to form a metal line and a via, respectively.2. The method of claim 1 , wherein the forming the opening and the etching the stress tuning dielectric layer are performed using separate lithography masks.3. The method of further comprising:before the opening is formed in the stress tuning dielectric layer, measuring a stress distribution and a warpage of the wafer; andcalculating a position of the opening based on the measured stress distribution ...

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Номер записи: 46
15-02-2018 дата публикации

COMPOSITE BOND STRUCTURE IN STACKED SEMICONDUCTOR STRUCTURE

Номер: US20180047682A1
Автор: CHANG Chao-Ching, HUANG Chih-Hui, LI Sheng-Chan, LIN Min-Hui, LIN YI-MING, Tsai Jian-Shin, Tsai Wen-Jen, WU Cheng-Yi
Принадлежит:

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer. 1. A semiconductor device , comprising:a substrate;a dielectric structure disposed on the substrate;a top metal layer disposed in the dielectric structure; anda bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:a silicon oxide layer disposed on the dielectric structure;a silicon oxy-nitride layer covering the silicon oxide layer and physically contacting the silicon oxide layer;a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; anda barrier layer covering a sidewall and a bottom of the conductive bonding layer.2. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second elevation ranges from substantially −50 angstroms to substantially 100 angstroms.3. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second ...

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Номер записи: 47
14-02-2019 дата публикации

Thermal interface material with ion scavenger

Номер: US20190048245A1
Автор: Bright ZHANG, Hong Min Huang, HUI Wang, Liang Zeng, Ya Qun Liu
Принадлежит: Honeywell International Inc

A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

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Номер записи: 48
26-02-2015 дата публикации

Semiconductor device with pads of enhanced moisture blocking ability

Номер: US20150054129A1
Автор: Kaoru Saigoh, Kouichi Nagai
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

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Номер записи: 49
03-03-2022 дата публикации

SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS AND METHOD FOR FABRICATING THE SAME

Номер: US20220068848A1
Автор: Huang Tse-Yao
Принадлежит:

The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene.

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Номер записи: 50
13-02-2020 дата публикации

Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer

Номер: US20200051935A1
Автор: Carmela Cupeta, Cosimo CIMINELLI, Francesco Maria Pipia, Ivan Venegoni, Michele Molgg, Paolo Colpani, Samuele Sciarrillo, Simone BOSSI
Принадлежит: STMICROELECTRONICS SRL

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

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Номер записи: 51
21-02-2019 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20190057913A1
Автор: Abe Hiromi, Akiba Toshihiko, Sato Masanao, YASUMURA Bunji
Принадлежит:

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

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Номер записи: 52
03-03-2016 дата публикации

Packaging Devices, Packaged Semiconductor Devices, and Packaging Methods

Номер: US20160064348A1
Автор: Chen-Shien Chen, Kuo Lung Pan, Yu-feng Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Packaging devices, packaged semiconductor devices, and packaging methods are disclosed. In some embodiments, a packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. Microstructures are disposed proximate a side of the integrated circuit die mounting region of the substrate.

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Номер записи: 53
20-02-2020 дата публикации

Via Structure for Packaging and a Method of Forming

Номер: US20200058613A1
Автор: Ho MIng-Che, Hwang Chien Ling, Kuo Hung-Jui, Liu Chung-Shi, Wu Yi-Wen
Принадлежит:

A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps. 1. A method of forming a device , the method comprising:forming ellipsoidal bumps on conductive pads, the conductive pads being disposed on a top surface of a substrate, the ellipsoidal bumps extending through a passivation layer, the passivation layer overlapping top surfaces of the conductive pads, the ellipsoidal bumps overlapping a top surface of the passivation layer;after forming the ellipsoidal bumps, forming a molding compound extending between the ellipsoidal bumps and along sidewalls of the substrate, the molding compound comprising a single layer; andplanarizing the molding compound.2. The method of claim 1 , wherein the ellipsoidal bumps are formed using electroless plating.3. The method of claim 1 , wherein the ellipsoidal bumps comprise Ni claim 1 , Pd claim 1 , Au claim 1 , or Cu.4. The method of claim 1 , wherein the ellipsoidal bumps have a thickness from 3 μm to 15 μm.5. The method of claim 1 , wherein prior to the planarizing the molding compound claim 1 , the ellipsoidal bumps extend a first height above the top surface of the passivation layer and the ...

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Номер записи: 54
02-03-2017 дата публикации

Semiconductor Devices and Methods of Manufacturing the Same

Номер: US20170062308A1
Автор: CHOI Ju-ll, FUJISAKI Atsushi, Kim Hyo-Ju, MOON Kwang-Jin, Park Byung-lyul, PARK Yeun-Sang
Принадлежит:

A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern. 1. A semiconductor device , comprising:a substrate;a via structure in the substrate, wherein a portion of the via structure extends past a surface of the substrate;a protection layer pattern structure on the surface of the substrate, wherein the protection layer pattern includes a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of an exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of a top surface of the first protection layer pattern adjacent to the sidewall of the via structure; anda pad structure on the via structure and the protection layer pattern structure, wherein the pad structure covers the portion of the top surface of the first protection layer pattern that is exposed by the second protection layer pattern.2. The semiconductor device of claim 1 , wherein the via structure comprises:a via electrode including a conductive pattern and a barrier pattern on a sidewall of the conductive pattern; andan ...

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Номер записи: 55
29-05-2014 дата публикации

Semiconductor element comprising a supporting structure and production method

Номер: US20140145349A1
Автор: Hans-Joachim Barth
Принадлежит: INFINEON TECHNOLOGIES AG

One or more embodiments are related to a semiconductor component comprising a supporting structure arranged in a first layer sequence, a second layer arranged above the first layer sequence, and a bonding pad. The layer sequence may comprise a plurality of layers of a dielectric and the bonding pad is arranged above the second layer. The supporting structure may comprise a plurality of supporting substructures and is formed under partial regions of the bonding pad.

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Номер записи: 56
17-03-2022 дата публикации

Semiconductor device with slanted conductive layers and method for fabricating the same

Номер: US20220084967A1
Автор: Kuo-Hui Su
Принадлежит: Nanya Technology Corp

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

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Номер записи: 57
08-03-2018 дата публикации

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

Номер: US20180068965A1
Автор: Chen Sheng-Chau, Chou Cheng-Hsien, Chou Shih Pei, Chu Yen-Chang, HUANG Chih-Hui, Tu Yeur-Luen
Принадлежит:

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

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Номер записи: 58
09-03-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170069600A1
Автор: Watanabe Shinya
Принадлежит:

A semiconductor device includes a substrate, a first electrode located on an upper surface of the substrate, and a second electrode located on a lower surface of the substrate and electrically connected to the first electrode. The semiconductor device further includes a first resist layer located on the upper surface of the substrate so as to surround the first electrode and spaced from the first electrode, and a second resist layer located on the lower surface of the substrate. 1. A semiconductor device comprising:a substrate;a first electrode located at an upper surface of the substrate;a second electrode located at a lower surface of the substrate and electrically connected to the first electrode;a first resist layer located at the upper surface of the substrate so as to surround the first electrode, wherein the first resist layer is spaced from the first electrode; anda second resist layer located at the lower surface of the substrate.2. The device according to claim 1 , whereinthe height of an upper surface of the first electrode extending above the substrate is lower than the height of an upper surface of the first resist layer extending above the substrate.3. The device according to claim 1 , whereinthe first resist layer comprises an inner perimeter surrounding an outer perimeter of the first electrode,the outer perimeter of the first electrode comprises a first diameter, andthe inner perimeter of the first resist layer comprises a second diameter greater than the first diameter.4. The semiconductor device according to claim 3 , further comprising a plurality of first electrodes located within the inner perimeter of the first resist layer and spaced from the first resist layer and from one another.5. The device according to claim 1 , whereinthe second electrode is provided on the lower surface of the substrate and within the substrate.6. The device according to claim 1 , whereinthe second resist layer comprises a plurality of resist portions spaced from the ...

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Номер записи: 59
17-03-2016 дата публикации

Semiconductor device and a method of manufacturing the same

Номер: US20160079202A1
Автор: Shinya Suzuki
Принадлежит: Renesas Electronics Corp

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

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Номер записи: 60
17-03-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE

Номер: US20160079209A1
Автор: Miyajima Hiroki
Принадлежит:

Disclosed herein is a semiconductor device including: a first substrate provided with a first surface layer including a first electrode; an expanded second substrate provided with a second surface layer including a second electrode and directly bonded to the first substrate so that the second surface layer contacts with the first surface layer; and a through electrode running through the first or second substrate. The second surface layer is provided over an expanded second principal surface defined by a second substrate and a resin portion. The second substrate has a smaller planar size than the first substrate. The first and second electrodes are connected together and in contact with each other. 1. A semiconductor device comprisinga first substrate having a first principal surface on which circuit components are provided and over which a first surface layer, including a first electrode, is provided,an expanded second substrate including: a second substrate having a second principal surface on which circuit components are provided; a resin portion provided on a side surface of the second substrate; and a second surface layer which is provided over an expanded second principal surface defined by the second substrate and the resin portion surrounding the second substrate and which includes a second electrode, the expanded second substrate being directly bonded to the first substrate such that the second surface layer contacts with the first surface layer, anda through electrode which either is connected to the first electrode and runs through the first substrate or is connected to the second electrode and runs through the second substrate, whereinthe second substrate has a smaller planar size than the first substrate, andthe first and second electrodes are connected together and are in contact with each other.2. The semiconductor device of claim 1 , whereinthe second substrate includes a second substrate body and an interconnect layer provided between the second ...

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Номер записи: 61
17-03-2016 дата публикации

Method for manufacturing semiconductor device

Номер: US20160079438A1
Автор: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

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Номер записи: 62
15-03-2018 дата публикации

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

Номер: US20180076160A1
Автор: Erwin Brian M., HEDRICK Brittany L., KIM Taeho, Polomoff Nicholas A., Souter Matthew E.
Принадлежит: SUSS MicroTec Photonic Systems Inc.

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A method to form a cap upon a semiconductor chip to package interconnect contact structure comprising:forming a contact structure upon an uppermost organic layer of a semiconductor substrate;forming a capping layer upon the uppermost organic layer covering the contact structure, and;directing a laser beam to eject portions of the capping layer from the uppermost organic layer and form a cap by retaining the capping layer covering the electrically conductive structure.2. The method of claim 1 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate.3. The method of claim 1 , wherein the capping layer is formed from silicon nitride.4. The method of claim 1 , wherein the capping layer covering the contact structure is retained by the contact structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.5. The method of claim 1 , further comprising:removing particulate of the ejected portions of the capping layer ...

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Номер записи: 63
24-03-2022 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS

Номер: US20220093541A1
Автор: Huang Tse-Yao
Принадлежит:

The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene. 1. A method for fabricating a semiconductor device , comprising:providing a substrate;forming a first passivation layer above the substrate;forming a redistribution layer on the first passivation layer;forming a first adjustment layer on the redistribution layer;forming a pad layer on the first adjustment layer;forming a second adjustment layer between the pad layer and the first adjustment layer;forming a second passivation layer on the first passivation layer;wherein the first adjustment layer and the second adjustment layer are formed of graphene.2. The method for fabricating a semiconductor device of claim 1 , wherein forming the pad layer comprises: forming a lower portion on the first adjustment layer and forming an upper portion on the lower portion.3. The method for fabricating a semiconductor device of claim 2 , wherein the second adjustment layer is formed between the lower portion of the pad layer and the first adjustment layer claim 2 , on sidewalls of the lower portion of the pad layer claim 2 , and on bottom surfaces of the upper portion of the pad layer.4. The method for fabricating a semiconductor device of claim 3 , wherein the redistribution layer and the lower portion of the pad layer are formed in the second passivation layer claim 3 , and the upper portion of the pad layer is formed on the second passivation layer.5. The method for ...

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Номер записи: 64
24-03-2022 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SLANTED CONDUCTIVE LAYERS

Номер: US20220093545A1
Автор: Su Kuo-Hui
Принадлежит:

The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers. 1. A method for fabricating a semiconductor device , comprising:providing a substrate;forming a first insulating layer above the substrate;forming first slanted recesses along the first insulating layer; andforming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.2. The method for fabricating the semiconductor device of claim 1 , wherein the step of forming the first slanted recesses along the first insulating layer comprises:forming a first hard mask layer on the first insulating layer;forming first hard mask openings along the first hard mask layer;performing a first slanted etch process on the first insulating layer to form the first slanted recesses along the first insulating layer; andremoving the first hard mask layer;wherein the first slanted etch process uses the first hard mask layer as a pattern guide.3. The method for fabricating the semiconductor device of claim 2 , wherein an angle of incidence of the first slanted etch process is between about 5 degree and about 80 degree.4. The method for fabricating the semiconductor device of claim 3 , wherein the first hard mask layer is formed of a material having etch selectivity to the first insulating layer.5. The method for fabricating the semiconductor device of claim 3 , wherein the first hard mask layer is formed of silicon oxide claim 3 , silicon nitride claim 3 , silicon oxynitride claim 3 , silicon nitride oxide claim 3 , boron nitride claim 3 , silicon boron nitride ...

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Номер записи: 65
31-03-2022 дата публикации

Thermally conductive sheet, method for manufacturing the same, and method for mounting thermally conductive sheet

Номер: US20220098462A1
Автор: Keisuke Aramaki, Marina TOBATA
Принадлежит: Dexerials Corp

A thermally conductive sheet excellent in adhesiveness to an electronic component, handleability and reworkability, a method for manufacturing the same, and a method for mounting a thermally conductive sheet, the sheet includes: a sheet body formed by curing a thermally conductive resin composition containing at least a polymer matrix component and a thermally conductive filler, wherein the volume ratio of the thermally conductive filler to the polymer matrix component is 1.00 to 1.70, the thermally conductive filler contains a fibrous thermally conductive filler, and the fibrous thermally conductive filler projects from the surface of the sheet body and is coated with an uncured component of the polymer matrix component.

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Номер записи: 66
22-03-2018 дата публикации

INFO STRUCTURE WITH COPPER PILLAR HAVING REVERSED PROFILE

Номер: US20180082917A1
Автор: Chang Ching Fu, Cheng Hsi-Kuei, HAN Chih-Kang, Huang Hsin-Chieh
Принадлежит:

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle. 1. A method comprising:forming a first polymer layer to cover a metal pad of a wafer;patterning the first polymer layer to form a first opening, with the metal pad exposed through the first opening, wherein a first sidewall of the first polymer layer exposed from the first opening defines a first tilt angle projectively over an upper surface of the metal pad;forming a metal pillar in the first opening;forming a dielectric layer encircling and covering the metal pillar;sawing the wafer to generate a device die;encapsulating the device die in an encapsulating material;performing a planarization to reveal the metal pillar;forming a second polymer layer over the encapsulating material and the device die; andpatterning the second polymer layer to form a second opening, with the metal pillar exposed through the second opening, wherein a second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.2. The method of claim 1 , wherein the patterning the first polymer layer comprises light-exposing and developing the first polymer layer claim 1 , and ...

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Номер записи: 67
22-03-2018 дата публикации

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

Номер: US20180082965A1
Автор: Erwin Brian M., HEDRICK Brittany L., KIM Taeho, Polomoff Nicholas A., Souter Matthew E.
Принадлежит: SUSS MicroTec Photonic Systems Inc.

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A semiconductor structure comprising:a substrate comprising an uppermost organic layer;a plurality of conductive structures upon the uppermost organic layer; anda cap covering each of the plurality of conductive structures,wherein the uppermost organic layer top surface comprises a laser stich mark crevasse between the plurality of conductive structures.2. The semiconductor structure of wherein the laser stich mark crevasse is a resultant of the laser beam vaporizing the uppermost organic layer to selectively eject portions of a capping layer upon the uppermost organic layer to form the cap covering each of the plurality of conductive structures.3. The semiconductor structure of claim 1 , wherein residual capping layer material is comprised within the stich mark crevasse.4. The semiconductor structure of claim 2 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave.519. The semiconductor structure of claim claim 2 , wherein the conductive structures dissipates heat from the laser that would otherwise vaporize the capping layer upon the conductive structures.6. The ...

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Номер записи: 68
23-03-2017 дата публикации

SEMICONDUCTOR DEVICES WITH SOLDER-BASED CONNECTION TERMINALS AND METHOD OF FORMING THE SAME

Номер: US20170084561A1
Автор: CHO Tae-Je, CHOI Ju-Il, Kwon Yong-hwan, Ryu Seung-kwan, Seo Sun-kyoung
Принадлежит:

An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section. 1. An electronic device , comprising:a substrate having an electrically conductive contact pad thereon; andan electrically conductive connection terminal on the contact pad, said connection terminal comprising an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure, said pillar structure comprising a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer.2. The device of claim 1 , wherein the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer.3. The device of claim 1 , wherein a width of the diffusion barrier layer is greater than a width of the upper pillar layer when viewed in transverse cross-section.4. The device of claim 3 , wherein an upper surface of the diffusion barrier layer directly contacts a bottom surface of the upper pillar layer.5. The device of claim 3 , wherein the width of the ...

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Номер записи: 69
23-03-2017 дата публикации

Cu pillar bump with l-shaped non-metal sidewall protection structure

Номер: US20170084563A1
Автор: Chien Ling Hwang, Chung-Shi Liu, Yi-Wen WU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

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Номер записи: 70
02-04-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20150091169A1
Автор: HIGUCHI Shingo, Kasai Masaki, MIYATA Osamu
Принадлежит: ROHM CO., LTD.

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. 1. A semiconductor device comprising:a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;a stress relieving layer having an upper surface and a side surface provided on the passivation film;a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer; anda connecting metal layer provided on the upper surface of the stress relieving layer, the connecting metal layer having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed from a gap of the connecting metal layer;wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, andthe sealing resin layer entirely covers the stress relieving layer, the passivation film and the connecting metal layer such that the sealing resin layer is formed on most part of the semiconductor device.2. The semiconductor device according to claim 1 , further comprising a metal ball disposed on the sealing resin layer.3. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate of silicon.4. The semiconductor device according to claim 1 , wherein the semiconductor chip has a rectangular shape as seen in plan.5. The semiconductor device according to claim 1 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.6. The semiconductor device according to claim ...

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Номер записи: 71
21-03-2019 дата публикации

Via Structure for Packaging and a Method of Forming

Номер: US20190088609A1
Автор: Ho MIng-Che, Hwang Chien Ling, Kuo Hung-Jui, Liu Chung-Shi, Wu Yi-Wen
Принадлежит:

A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps. 1. A semiconductor device comprising:a substrate;a plurality of conductive pads on the substrate;a passivation layer on the conductive pads and the substrate;a plurality of conductive pillars extending through the passivation layer and connected to the conductive pads; anda molding compound extending between the conductive pillars and encapsulating sidewalls of the substrate, the molding compound comprising a single continuous material.2. The semiconductor device of claim 1 , wherein an upper surface of the conductive pillar has a width of from 5 μm to 40 μm.3. The semiconductor device of claim 1 , wherein uppermost surfaces of the conductive pillars are level with uppermost surfaces of the molding compound.4. The semiconductor device of claim 1 , wherein the conductive pillars have a height of from 2 μm to 5 μm.5. The semiconductor device of claim 1 , wherein the conductive pillars have tapered sidewalls having an angle of from 0° to 10°.6. The semiconductor device of claim 1 , wherein the conductive pillars have an ellipsoidal shape.7. The semiconductor device of claim 6 , ...

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Номер записи: 72
30-03-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20170092605A1
Автор: TONEGAWA Takashi
Принадлежит:

Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region). 1. A semiconductor device , comprising:a first insulating film provided above a semiconductor substrate;a first interconnection provided over the first insulating film;a second insulating film provided over the first interconnection and having a first opening;a plating film provided in the first opening; anda slit provided in a side face of the first opening,wherein a bottom of the first opening is a pad region being part of the first interconnection, andwherein the plating film is also provided in the slit.2. The semiconductor device according to claim 1 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film contains a metal selected from nickel (Ni), gold (Au), and palladium (Pd).3. The semiconductor device according to claim 2 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film includes a first plating film containing nickel (Ni), and a second plating film provided on the first plating film and containing gold (Au).4. The semiconductor device according to claim 3 , further comprising a third plating film containing palladium (Pd) between the first ...

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Номер записи: 73
14-04-2016 дата публикации

Improving the Strength of Micro-Bump Joints

Номер: US20160104685A1
Автор: Chen Chen-Shien, Chen Ming-Fa, Kuo Chen-Cheng, Shen Wen-Wei, Wang Rung-De
Принадлежит:

A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. 1. A bump structure comprising:a metal pad;a passivation layer over the metal pad, the passivation layer having an opening exposing a portion of the metal pad; anda metal bump over the metal pad, the metal bump having a lip extending laterally beneath a lowermost surface of the passivation layer, the lip anchoring the metal bump to the passivation layer.2. The bump structure of claim 1 , wherein the lip has a recess depth measured from a sidewall of the passivation layer to a distal end of the lip claim 1 , the recess depth greater than zero micrometers.3. The bump structure of claim 1 , wherein the passivation layer comprises silicon nitride.4. The bump structure of claim 1 , wherein the metal bump comprises one of nickel claim 1 , Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) claim 1 , Electroless Nickel Immersion Gold (ENIG) claim 1 , and Direct Immersion Gold (DIG).5. The bump structure of claim 1 , wherein the metal pad comprises copper claim 1 , aluminum claim 1 , silver claim 1 , and alloys thereof.6. The bump structure of claim 1 , wherein the bump structure is supported by a bottom die claim 1 , the bottom die configured to be joined with a top die to form a bump joint.7. The bump structure of claim 1 , wherein the metal pad has a recess claim 1 , the recess extending below the passivation layer claim 1 , wherein the metal bump is positioned in the recess.8. A structure comprising:a top die including a first bump structure; anda bottom die mounted to the top die, the bottom die including a second bump structure having a metal bump with a lip extending laterally beneath a lowermost surface of ...

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Номер записи: 74
26-03-2020 дата публикации

Semiconductor Device

Номер: US20200098713A1
Автор: Morifuji Tadahiro, Ueda Shigeyuki
Принадлежит: ROHM CO., LTD.

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor device comprising: an electrode pad portion on a face of a substrate;', 'a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;', 'a barrier metal layer on the electrode pad portion;', 'a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and', 'a plurality of bump electrodes on the barrier metal layer;, 'a semiconductor chip includinga circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; anda resin member filling a gap between the semiconductor chip and the circuit board,wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan ...

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Номер записи: 75
09-06-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220181279A1
Автор: Sakai Mitsuhiko
Принадлежит:

A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface;an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate;a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed;a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; anda metal film disposed on the second surface exposed from between the passivation film and the copper film, whereinthe metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.2. The semiconductor device according to claim 1 , wherein the passivation film is a polyimide film.3. The semiconductor device according to claim 1 , wherein the metal film is an electroless nickel plating film.4. The semiconductor ...

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Номер записи: 76
27-04-2017 дата публикации

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

Номер: US20170117241A1
Автор: Erwin Brian M., HEDRICK Brittany L., KIM Taeho, Polomoff Nicholas A., Souter Matthew E.
Принадлежит: SUSS MicroTec Photonic Systems Inc.

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A semiconductor device fabrication method comprising:forming a electrically conductive structure upon an uppermost organic layer of a semiconductor substrate;forming a capping layer upon the uppermost organic layer covering the electrically conductive structure, and;directing a laser beam to eject portions of the capping layer from the uppermost organic layer and form a cap by retaining the capping layer covering the electrically conductive structure.2. The semiconductor device fabrication method of claim 1 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate.3. The semiconductor device fabrication method of claim 2 , wherein the capping layer is formed from silicon nitride.4. The semiconductor device fabrication method of claim 2 , wherein the capping layer covering the electrically conductive structure is retained by the electrically conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor ...

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Номер записи: 77
25-04-2019 дата публикации

Protrusion Bump Pads for Bond-on-Trace Processing

Номер: US20190122976A1
Автор: LIANG Yu-Min, WU Jiun Yi
Принадлежит:

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. A method of forming a semiconductor structure , the method comprising: a stack of dielectric layers;', 'a first conductive pillar embedded in the stack of dielectric layers;', 'a second conductive pillar embedded in the stack of dielectric layers; and', 'a metal layer extending along an outermost dielectric layer of the stack of dielectric layers, the metal layer disposed between the outermost dielectric layer and the patterned mask layer, wherein the patterned mask layer covers a first portion of the metal layer contacting a first surface of the first conductive pillar while exposing a second portion of the metal layer contacting a second surface of the second conductive pillar; and, 'forming a patterned mask layer on a first side of a build-up layer, wherein the build-up layer comprisesetching the metal layer using the patterned mask layer as an etching mask, wherein after the etching, the first portion of the metal layer remains and the second portion of the metal layer is removed, where etching the metal layer recesses the second surface of the second conductive pillar from a first side of the outermost dielectric layer facing the metal layer.2. The method of claim 1 , wherein each of the first conductive pillar and the second conductive pillar comprises alternating layers of conductive traces and vias claim 1 , wherein the first conductive pillar comprises a first conductive ...

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Номер записи: 78
11-05-2017 дата публикации

FABRICATION METHOD OF PACKAGING SUBSTRATE

Номер: US20170133337A1
Автор: Chuang Chien-Lung, Jiang Yih-Jenn, Lee Meng-Tsung, Wu Po-Yi
Принадлежит:

A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump. 111-. (canceled)12. A fabrication method of a packaging substrate , comprising:providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the at least a conductive pad;forming at least a second opening in the dielectric layer around a periphery of the at least a first opening;forming a metal layer on the dielectric layer and the at least a conductive pad, wherein the metal layer extends to a sidewall of the at least a second opening; andforming at least a solder bump on the metal layer.13. The method of claim 12 , wherein forming the at least a solder bump on the metal layer comprises:forming a resist layer on the metal layer, wherein the resist layer has at least an opening corresponding in position to the at least a conductive pad and the opening has a wall located on the sidewall of the at least a second opening;forming the at least solder bump on the metal layer in the opening of the resist layer;removing the resist layer; andetching a portion of the metal layer uncovered by the at least a solder bump.14. The method of claim 13 , after removing the resist layer claim 13 , further comprising reflowing the at least a solder bump.15. The method of claim 12 , wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body claim 12 , and a second sub-dielectric layer formed on ...

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Номер записи: 79
02-05-2019 дата публикации

Die stack structure and method of fabricating the same and package

Номер: US20190131277A1
Автор: Ching-Jung Yang, Hsien-Wei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

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Номер записи: 80
23-04-2020 дата публикации

Semiconductor device for bonding conductive layers exposed from surfaces of respective interconnection layers

Номер: US20200126941A1
Автор: Atsuko Kawasaki
Принадлежит: Toshiba Memory Corp

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

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Номер записи: 81
19-05-2016 дата публикации

SEMICONDUCTOR POWER MODULE USING DISCRETE SEMICONDUCTOR COMPONENTS

Номер: US20160141275A1
Автор: Bono Richard J., Yoshimoto Koichiro
Принадлежит: LITTELFUSE, INC.

An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate. Electrical leads may be coupled to a printed circuit board (PCB). Other features disclosed include a thermal interface material and an application-specific heat sink. The assembly may be overmolded via injection molding or potted using an encapsulant. Example electronic devices include thyristors, diodes, and transistors. 1. An electronic power module comprising:a baseplate; anda plurality of internally isolated discrete electronic devices mounted to the baseplate;wherein each of the plurality of internally isolated discrete electronic devices includes electrical leads oriented away from the baseplate.2. The electronic power module of further comprising:a thermal interface material disposed between the plurality of internally isolated discrete electronic devices and the baseplate.3. The electronic power module of wherein:the thermal interface material comprises beryllium oxide, aluminum nitride, zinc oxide, or silicon dioxide.4. The electronic power module of wherein:the baseplate comprises copper.5. The electronic power module of wherein:the electrical leads are coupled to a printed circuit board (PCB).6. The electronic power module of wherein:the electrical leads are coupled to the PCB by soldering.7. The electronic power module of wherein:the baseplate is coupled to at least one heat sink.8. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are overmolded via injection molding.9. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are potted using an encapsulant.10. The electronic power module of wherein:each discrete electronic device is either a thyristor, a diode, or a transistor.11. A ...

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Номер записи: 82
26-05-2016 дата публикации

Electronic Circuit Board, Semiconductor Device Using the Same and Manufacturing Method for the Same

Номер: US20160148865A1
Автор: NAOE Kazuaki, NISHIKI Masashi, Tenmei Hiroyuki
Принадлежит:

The present invention aims to provide an electronic circuit board with insulation reliability improved by increasing volume resistivity of a ceramics substrate fabricated by an aerosol deposition method, a semiconductor device using it and a manufacturing method therefor. The present invention provides the electronic circuit board which includes a metal material, and an insulating film formed on a front surface of the metal material and including an inorganic material containing a crystal of a grain diameter of 10 to 20 nm and in which the insulating layer is less than 0.08 g/cmin amount of moisture which it contains. In addition, the present invention provides the manufacturing method for the electronic circuit board in which aerosol which contains particles configuring the insulating layer is injected to the metal material to form the insulating layer on the metal material and either the metal material front surface or the insulating layer front surface is heated. 1. An electronic circuit board , comprising:a metal material; andan insulating layer which has been formed on a front surface of the metal material and includes an inorganic material containing a crystal of a grain diameter of 10 to 20 nm,{'sup': '3', 'wherein the insulating layer is less than 0.08 g/cmin amount of moisture which it contains.'}2. The electronic circuit board according to claim 1 , wherein volume resistivity of the insulating layer at 85° C. is at least 1.0×10Ωm.3. The electronic circuit board according to claim 1 , wherein the insulating layer contains any of SiC claim 1 , AIN claim 1 , SiN claim 1 , AlO.4. A semiconductor device claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the electronic circuit board according to ;'}a conductor property wiring which has been formed on the electronic circuit board; anda semiconductor element which has been connected with the conductor property wiring by a joining member.5. A semiconductor device claim 1 , comprising:{'claim- ...

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Номер записи: 83
25-05-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170148701A1
Автор: HIKITA Masahiro, IKOSHI Ayanori, MATSUNAGA Keiichi, Sato Takahiro, Yanagihara Manabu
Принадлежит:

A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film. 1. A semiconductor device , comprising:a substrate;a semiconductor layer disposed on the substrate;a first protective film disposed on the semiconductor layer;a first adhesive layer disposed on the first protective film, and including at least one metal material selected from Ti, TiN, Ta, and TaN or a laminate including a combination of Ti, TiN, Ta, and TaN;an electrode pad disposed on the first protective film and in contact with side surfaces and part of an upper surface of the first adhesive layer;a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; anda first opening formed in part of the second protective film such that an upper surface of the electrode pad is exposed,wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of a periphery of the electrode pad and continuously surrounding the electrode pad, andthe second protective film is continuously disposed to cover and be in contact with part of the upper surface and part of side surfaces of ...

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Номер записи: 84
25-05-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170148707A1
Автор: KATO Noboru, Nakaiso Toshiyuki
Принадлежит:

An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated. 1. A semiconductor device comprising:a semiconductor substrate with a functional element formed thereon;a metallic film disposed on a surface of the semiconductor substrate and electrically coupled to the functional element; and a wiring electrode opposed to the surface of the semiconductor substrate,', 'a contact hole that electrically couples the metallic film and at least part of the wiring electrode,', 'a protection film layer disposed on the surface of the semiconductor substrate to cover a portion of the metallic film in a region other than a region where the metallic film is in contact with the contact hole and the surface of the semiconductor substrate, and', 'a resin layer having a lower dielectric constant than the protection film layer and disposed between the protection film layer and the wiring electrode to cover the protection film layer,, 'a rewiring layer includingwherein the protection film layer has a cross-sectional shape that increases in thickness as the protection film layer extends away from the contact hole along the surface of the semiconductor substrate in an area in which the protection film layer opposes the wiring electrode,wherein the resin layer ...

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Номер записи: 85
02-06-2016 дата публикации

Semiconductor devices having a tsv, a front-side bumping pad, and a back-side bumping pad

Номер: US20160155686A1
Автор: Byunglyul Park, Ho-Jin Lee, Jinho AN, Jisoon Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

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Номер записи: 86
02-06-2016 дата публикации

Protrusion Bump Pads for Bond-on-Trace Processing

Номер: US20160155697A1
Автор: LIANG Yu-Min, WU Jiun Yi
Принадлежит:

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. An apparatus , comprising:a substrate;a plurality of conductive traces disposed on a side of the substrate;a plurality of conductive members each extending into the substrate from a corresponding one of the conductive traces; anda plurality of bump pads each protruding from one of a first subset of the conductive traces, wherein a second subset of the conductive traces are recessed within the side of the substrate.2. The apparatus of claim 1 , wherein the side is a first side claim 1 , and wherein ones of the plurality of conductive members are conductive pillars extending to corresponding conductive features disposed on a second side of the substrate.3. The apparatus of claim 1 , wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is substantially greater than the minimum trace pitch.4. The apparatus of claim 1 , wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is at least about twice the minimum trace pitch.5. The apparatus of claim 1 , wherein the plurality of conductive traces are ...

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Номер записи: 87
15-09-2022 дата публикации

Integrated circuit package system

Номер: US20220293484A1
Автор: Chih-Ming Chen, Chun-Lung HUANG
Принадлежит: Aptos Technology Inc

An integrated circuit package system includes a substrate, a plurality of leads, N semiconductor devices, N first heat sinks, an encapsulating body, a second heat sink and a plurality of heat-dissipating fins protruding upward from the second heat sink, where N is a natural number. The leads are formed on a lower surface of the substrate. Each of the semiconductor devices is attached on an upper surface of the substrate, and includes a plurality of bonding pads which each is electrically connected to the corresponding lead. Each first heat sink is thermally coupled to a first top surface of the corresponding semiconductor device. The encapsulating body is formed to cover the substrate, the N semiconductor devices and the N first heat sinks such that the leads are exposed. The second heat sink is mounted on the encapsulating body, and is thermally coupled to the N first heat sinks.

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Номер записи: 88
31-05-2018 дата публикации

METHOD FOR MANUFACTURING REDISTRIBUTION LAYER

Номер: US20180151519A1
Автор: Chuang Chiang-Ming, LU Szu-Hsien
Принадлежит:

In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate having a top surface;forming a top metal layer in the top surface of the semiconductor substrate;forming a first passivation layer to cover the top metal layer and the top surface of the semiconductor substrate, wherein the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer;forming a redistribution layer to cover the first passivation layer, said at least one portion of the top metal layer, and a side surface of the at least one via hole, wherein the redistribution layer is formed to comprise at least one overhang structure over the at least one via hole;performing an etching process on the redistribution layer to remove the at least one overhang structure and at least one portion of the redistribution layer, wherein said at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer; andforming a second passivation layer to cover the redistribution layer and said at least one portion of the ...

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Номер записи: 89
31-05-2018 дата публикации

POST PASSIVATION INTERCONNECT AND FABRICATION METHOD THEREFOR

Номер: US20180151520A1
Автор: CHANG C. C., KUO Alan, Lin Yi-An, Shih Yu-Lung
Принадлежит:

A method of manufacturing a semiconductor structure. The method includes depositing a conductive material over a substrate, and removing a portion of the conductive material to form a conductive structure having a barrel shape. A width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure. 1. A method of manufacturing a semiconductor structure , comprising:depositing a conductive material over a substrate; andremoving a portion of the conductive material to form a conductive structure having a barrel shape, wherein a width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure.2. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing an anisotropic etching process to form an upper portion of the conductive structure, wherein the upper portion of the conductive structure has a trapezoidal shape; andperforming an isotropic etching process to form a bottom portion of the conductive structure, wherein the bottom portion of the conductive structure has an undercut.3. The method of claim 2 , wherein performing the isotropic etching process comprises performing a wet etching.4. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing a first reactive ion etching (RIE) process to form an upper portion of the conductive structure; andperforming a second RIE process to form a bottom portion of the conductive structure, wherein a radical/plasma ratio of the first RIE process is greater than a radical/plasma ratio of the second RIE process.5. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing a first plasma etching process to form an upper portion of the conductive structure; andperforming a second plasma etching process to form a bottom portion of the ...

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Номер записи: 90
16-05-2019 дата публикации

3D IC METHOD AND DEVICE

Номер: US20190148222A1
Автор: ENQUIST Paul M., FOUNTAIN, JR. Gaius Gillman, TONG Qin-Yi
Принадлежит:

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. 1. A bonded structure comprising:a first substrate having a front side and a back side opposite the front side;a first non-metallic region located on the back side of the first substrate;a first contact structure comprising a conductive material filled in a first via extending through the first substrate, the conductive material comprising a via first structure;a second substrate;a second non-metallic region located on a front side of the second substrate and directly bonded to the first non-metallic region along an interface; anda second contact structure disposed on the second substrate proximate to the second non-metallic region, the second contact structure directly bonded to the first contact structure, the interface extending substantially to the bonded first and second contact structures.2. The bonded structure of claim 1 , wherein the conductive material is approximately coplanar with the first non-metallic region at the back side of the first substrate.3. The bonded structure of claim 1 , wherein the conductive material protrudes the back side of the first substrate and the dielectric sidewall protrudes the back side of the first substrate.4. The bonded structure of claim 1 , wherein the first contact structure comprises a first portion on the back side of the ...

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Номер записи: 91
11-06-2015 дата публикации

Method for manufacturing semiconductor device and semiconductor device

Номер: US20150162294A1
Автор: Atsuko Kawasaki
Принадлежит: Toshiba Corp

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

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Номер записи: 92
08-06-2017 дата публикации

Epoxy resin composition for electronic material, cured product thereof and electronic member

Номер: US20170158807A1
Автор: Hiroshi Kinoshita, Yasuyo YOSHIMOTO
Принадлежит: DIC Corp

An epoxy resin composition for electronic material, containing a polyfunctional biphenyl type epoxy resin that is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl and at least one of a curing agent and a curing accelerator is provided. Furthermore, the epoxy resin composition for electronic material, further containing a filler, in particular, a thermal conductive filler, is provided. Furthermore, a cured product obtained by curing the epoxy resin composition for electronic material, and an electronic component containing the cured product are provided.

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Номер записи: 93
07-06-2018 дата публикации

INTEGRATED CIRCUIT PACKAGE STRUCTURE AND TESTING METHOD USING THE SAME

Номер: US20180156865A1
Автор: CHEN YANG-CHE, Chou Tsung-Te, LIN CHEN-HUA, LIU CHWEN-MING, Tseng Huang-Wen
Принадлежит:

An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars. 1. An integrated circuit package structure , comprising:a device die comprising a plurality of metal pillars;a molding material directly in contact with at least one side surface of the device die;a first dielectric layer disposed on the device die and on the molding material; anda testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material, wherein the testing pad is electrical isolated from the metal pillars.2. The integrated circuit package structure of claim 1 , further comprising:at least one second dielectric layer disposed on the testing pad and on the first dielectric layer; andtwo vias disposed in the second dielectric layer, wherein the vias are connected to two opposite ends of the testing pad, respectively.3. The integrated circuit package structure of claim 1 , further comprising:a plurality of redistribution lines disposed above the first dielectric layer, wherein the redistribution lines are respectively connected to the metal pillars of the device die, and the redistribution lines and the interface are spaced by the first dielectric layer.4. The integrated circuit package structure of claim 3 , further comprising:at least one second dielectric layer disposed on the first dielectric layer, wherein the redistribution lines are disposed in the second dielectric layer and are electrical isolated from the testing pad.5. The integrated circuit package structure of claim 4 , further comprising:a plurality ...

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Номер записи: 94
07-06-2018 дата публикации

CHIP PACKAGE

Номер: US20180158746A1
Автор: Lin Mou-Shiung
Принадлежит:

A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip. 1. A chip package comprising:a first polymer layer; a first semiconductor device,', 'a first semiconductor substrate to support the first semiconductor device,', 'a first contact pad coupled to the first semiconductor device, and', 'a first conductive interconnect on the first contact pad;, 'a first semiconductor chip in the first polymer layer, in which the first semiconductor chip comprisesa second polymer layer on the first polymer layer and extending across an edge of the first semiconductor chip; anda first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and extending across the edge of the first semiconductor chip.2. The chip package of claim 1 , in which the semiconductor substrate comprises silicon.3. The chip package of claim 1 , in which the first polymer layer comprises an epoxy molding compound.4. The chip package of claim 1 , in which the first polymer layer has a thickness between 250 and 1000 micrometers.5. The chip package of claim 1 , in which the first conductive layer comprises a redistribution layer having a thickness between 1 and 20 micrometers.6. The chip package of claim 1 , in which ...

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Номер записи: 95
08-06-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20170162463A1
Автор: HIGUCHI Shingo, Kasai Masaki, MIYATA Osamu
Принадлежит: ROHM CO., LTD.

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove. 1. A semiconductor device comprising:a semiconductor chip having a passivation film;a stress relieving layer provided on the passivation film; anda groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, whereinthe stress relieving layer is partly disposed in the groove.2. The semiconductor device according to claim 1 , wherein the stress relieving layer extends to a side surface of the passivation film so as to cover the side surface.3. The semiconductor device according to claim 2 , whereinthe groove surrounds a device formation region of the semiconductor chip in a plan view, andthe passivation film includes a center portion covering the device formation region and a peripheral portion disposed on opposite sides of the groove.4. The semiconductor device according to claim 1 , further comprising a sealing resin layer extending to a side surface of the stress relieving layer so as to cover the side surface.5. The semiconductor device according to claim 1 , whereinthe stress relieving layer extends to a side surface of the passivation film so as to cover the side surface,the groove surrounds a device formation region of the semiconductor chip in a plan view,the passivation film includes a center portion covering the device formation region and a peripheral portion disposed on opposite sides of the groove,the stress relieving layer selectively covers the center portion of the passivation film, andthe semiconductor device further includes a sealing resin layer extending to a side surface of the stress relieving layer so as to cover the ...

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Номер записи: 96
08-06-2017 дата публикации

Power module package and method for manufacturing the same

Номер: US20170162468A1
Автор: Jae Hyun Ko
Принадлежит: Hyundai Mobis Co Ltd

Disclosed relates to a power module package and a method for manufacturing the same. The power module package includes a lower substrate on which a pattern is formed, a power semiconductor element and a ribbon which are separated apart from each other at a predetermined distance to be mounted on an upper surface of the lower substrate, a first spacer attached to an upper portion of the power semiconductor element via a first adhesive layer, a second spacer attached to an upper portion of the ribbon via a second adhesive layer, and an upper substrate attached to an upper portion of each of the first and second spacers via a third adhesive layer.

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Номер записи: 97
08-06-2017 дата публикации

COMPOSITION FOR ANISOTROPIC CONDUCTIVE FILM, ANISOTROPIC CONDUCTIVE FILM, AND CONNECTION STRUCTURE USING THE SAME

Номер: US20170162531A1
Автор: HEO Gun Young, HWANG Ja Young, Kim Ha Na, KIM Ji Yeon, KO Youn Jo, KWON Soon Young, Park Young Woo, SEO Hyun Joo
Принадлежит:

An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: 1. An anisotropic conductive film , comprising:a binder resin;a curable alicyclic epoxy compound;a curable oxetane compound;a quaternary ammonium catalyst; andconductive particles, {'br': None, 'i': H', '−H', 'H, 'sub': 0', '1', '0, 'Heat quantity variation rate (%)=[()/]×100\u2003\u2003Equation 1'}, 'wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1{'sub': 0', '1, 'wherein His a DSC heat quantity of the anisotropic conductive film, as measured at 25° C. and a time point of 0 hr, and His a DSC heat quantity of the anisotropic conductive film, as measured after being left at 40° C. for 24 hours.'}3. The anisotropic conductive film as claimed in claim 1 , wherein the oxetane compound is a carbon polymer compound containing 1 to 4 oxetane rings per molecule.5. The anisotropic conductive film as claimed in claim 4 , wherein M is SbF or B(CF).6. The anisotropic conductive film as claimed in claim 1 , wherein the binder resin includes a polyimide resin claim 1 , a polyamide resin claim 1 , a phenoxy resin claim 1 , a polymethacrylate resin claim 1 , a polyacrylate resin claim 1 , a polyurethane resin claim 1 , a polyester resin claim 1 , a polyester urethane resin claim 1 , a polyvinyl butyral resin claim 1 , a styrene-butadiene-styrene (SBS) resin or an epoxylated compound thereof claim 1 , a styrene-ethylene/butylene-styrene (SEBS) resin or a ...

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Номер записи: 98
08-06-2017 дата публикации

Semiconductor device

Номер: US20170162533A1
Автор: Kaoru Yasuda, Motoharu Haga
Принадлежит: ROHM CO LTD

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.

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Номер записи: 99
18-06-2015 дата публикации

REDUCED EXPANSION THERMAL COMPRESSION BONDING PROCESS BOND HEAD

Номер: US20150171047A1
Автор: Dhavaleswarapu Hemanth, Malatkar Pramod, NEEB James
Принадлежит:

Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some embodiments, the bond head includes a thermal compression bonding process heater and a cooling block coupled to the heater through an annular structure. The annular structure surrounds a lower portion of the cooling block and couples the cooling block to the heater such that there is no direct mechanical contact between the cooling block and the heater. 1. A thermal compression bonding process bond head comprising:a heater;a cooling block configured to conduct heat from the heater; anda thermal expansion coefficient compensating structure coupled to a portion of the cooling block and configured to couple the cooling block to the heater such that there is no direct interface between the cooling block and the heater.2. The thermal compression bonding process bond head of wherein the cooling block comprises a recess surrounding a lower periphery wherein the thermal expansion coefficient compensating structure is coupled to the cooling block within the recess.3. The thermal compression bonding process bond head of wherein the thermal expansion coefficient compensating structure is coupled to the cooling block with a first sealant and to the heater with a second sealant.4. The thermal compression bonding process bond head of wherein the thermal expansion coefficient compensating structure comprises a material having a negative coefficient of thermal expansion.5. The thermal compression bonding process bond head of wherein the material having the negative coefficient of thermal expansion comprises one of: zirconium tungstate claim 4 , Siliceous Faujasite claim 4 , or glasses in a titania-silica family.6. The thermal compression bonding process bond head of wherein the thermal expansion coefficient compensating structure comprises a plurality of annular rings.7. The thermal compression bonding process bond head of ...

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Номер записи: 100