АРХИТЕКТУРА НАКРИСТАЛЬНОГО МЕЖСОЕДИНЕНИЯ

Группа изобретений относится к вычислительным системам с большой вычислительной мощностью, реализованным на одном полупроводниковом кристалле. Техническим результатом является повышение масштабируемости сети с низкой задержкой и низким энергопотреблением. В одном варианте система содержит множество площадок, выполненных на полупроводниковом кристалле, по меньшей мере, две из множества площадок имеют множество ядер; и множество сетевых коммутаторов, выполненных на полупроводниковом кристалле, которые связаны с множеством площадок, где первый сетевой коммутатор из множества сетевых коммутаторов содержит множество выходных портов, причем выходные порты первого множества из множества выходных портов предназначены для соединения с соответствующим сетевым коммутатором площадки через межсоединение типа "точка - точка", а выходные порты второго множества выходных портов предназначены для соединения с соответствующими сетевыми коммутаторами множества площадок через межсоединение "точка - группа ...

СОХРАНЕНИЕ ПЕРЕРАСПРЕДЕЛЯЮЩИХ ТОКОПРОВОДЯЩИХ ДОРОЖЕК, ИМЕЮЩИХ МЕЛКИЙ ШАГ

Один вариант воплощения изобретения включает в себя полупроводниковый аппарат, содержащий перераспределяющий слой (RDL-слой), включающий в себя рельефную токопроводящую дорожку перераспределяющего слоя, имеющую две боковые стенки перераспределяющего слоя, причем перераспределяющий слой, содержащий материал, выбранный из группы, содержащей Cu (медь) и Au (золото), защитные боковые стенки, непосредственно контактирующие с этими двумя боковыми стенками перераспределяющего слоя, затравочный слой, включающий в себя этот материал, и барьерный слой, при этом (а) токопроводящая дорожка перераспределяющего слоя имеет ширину токопроводящей дорожки перераспределяющего слоя, ортогональную по отношению к этим двум боковым стенками перераспределяющего слоя и простирающуюся между ними, и (b) затравочный и барьерный слои каждый включают в себя ширину, параллельную ширине токопроводящей дорожки перераспределяющего слоя и более широкую, чем эта ширина. Здесь же представлены и другие варианты воплощения изобретения ...

ANORDNUNG VERFLOCHTENER UND VERSCHLUNGENER WORTLEITUNGEN FUER HALBLEITERSPEICHER

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

Halbleitervorrichtung

Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung

... [Aufgabe] Bereitstellen einer Halbleitervorrichtung, bei der die Erzeugung einer Verzerrung eines Signals unterdrückt wird, und eines Verfahrens zur Herstellung der Halbleitervorrichtung.[Lösung] Eine Halbleitervorrichtung, die Folgendes beinhaltet: ein Transistorgebiet, in dem ein Feldeffekttransistor bereitgestellt ist, und ein Verbindungsgebiet, in dem eine Metallschicht bereitgestellt ist, die elektrisch mit dem Feldeffekttransistor verbunden ist. Das Verbindungsgebiet beinhaltet eine Isolierschicht, die zwischen der Metallschicht und einem Substrat bereitgestellt ist, und eine Schicht mit niedriger Permittivität, die in der Isolierschicht unter der Metallschicht bereitgestellt ist und eine niedrigere Permittivität als die Isolierschicht aufweist.

Halbleitervorrichtung und Verfahren zum Herstellen von dieser

In einem Verfahren zum Herstellen einer Halbleitervorrichtung wird eine dielektrische Schicht über einem Substrat ausgebildet. Eine erste Struktur und eine zweite Struktur werden in der ersten dielektrischen Zwischenschicht ausgebildet. Die erste Struktur weist eine Breite auf, die größer ist als eine Breite der zweiten Struktur. Eine erste Metallschicht wird in der ersten Struktur und der zweiten Struktur ausgebildet. Eine zweite Metallschicht wird in der ersten Struktur ausgebildet. Ein Planarisierungsvorgang wird an der ersten und der zweiten Metallschicht durchgeführt, so dass eine erste Metallverdrahtung durch die erste Struktur und eine zweite Metallverdrahtung durch die zweite Struktur ausgebildet werden. Ein Metallmaterial der ersten Metallschicht ist von einem Metallmaterial der zweiten Metallschicht verschieden. Die erste Metallverdrahtung umfasst die erste und die zweite Metallschicht und die zweite Metallverdrahtung umfasst die erste Metallschicht, umfasst aber nicht die zweite ...

Struktur eines Finnen-Feldeffekttransistorbauelements (FinFET- Bauelement) mit Zwischenverbindungsstruktur

Halbleitervorrichtungsstruktur, die umfasst:eine erste Metallschicht (104), die über einem Substrat (102) gebildet wird;eine dielektrische Schicht (112), die über der ersten Metallschicht (104) gebildet wird;eine Haftschicht (130), die in der dielektrischen Schicht (112) und über der ersten Metallschicht (104) gebildet wird; undeine zweite Metallschicht (142), die in der dielektrischen Schicht (112) gebildet wird, wobei die zweite Metallschicht (142) elektrisch mit der ersten Metallschicht (104) verbunden ist, wobei ein Abschnitt der Haftschicht (130) zwischen der zweiten Metallschicht (142) und der dielektrischen Schicht (112) gebildet wird, und wobei die Haftschicht (130) einen ersten Abschnitt (130a), der einen oberen Abschnitt der zweiten Metallschicht (142) säumt, umfasst und wobei der erste Abschnitt (130a) einen erweiterten Abschnitt entlang einer vertikalen Richtung aufweist;dadurch gekennzeichnet, dass die Haftschicht (130) ferner einen zweiten Abschnitt (130b) unter dem ersten ...

Halbleiterstruktur mit einem im Wesentlichen geraden Kontaktprofil

Die vorliegende Erfindung betrifft Halbleiterstrukturen und insbesondere eine Halbleiterstruktur mit einem im Wesentlichen geraden Kontaktprofil und Verfahren zur Herstellung. Die Struktur umfasst ein Blockmaterial mit einer oberen oxidierten Schicht an einer Grenzfläche zu einem isolierenden Material; und eine Zwischenverbindungskontaktstruktur mit einem im Wesentlichen geraden Profil durch die oxidierte Schicht des Blockmaterials.

Ultrafeine Teilchenstruktur und Verfahren zu ihrer Herstellung

Non-lithographically patterned directed self assembly alignment promotion layers

A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Clock distribution scheme

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

A method for improving integrated circuit by using a patterned bump layout on a metal layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

A highly integrated semi-conductor wiring structure and a method for manufacturng the same

Techniques for enhancing fracture resistance of interconnects

Improving integrated circuit performance and reliability using a patterned bump layout on a power grid

Semiconductor Device and Manufacturing Method Thereof

Integrated circuits

The invention relates to a concept of metallisation for the production of integrated circuit devices in which the components of the integrated circuit are arranged in cells (17) which are all identical, non-functional and assembled in a matrix (14). Components of adjacent cells are interconnected by a metallic sub-network (22) forming blocks (23: 231...2315) representing predetermined logic functions. The blocks (23) have input-output terminals (26) at predetermined points, by which they are interconnected by a metallic sub-network (24:241...). The cells and blocks each have a symmetry with respect to the two axes of the matrix, so that the metallisation is minimal and the distribution may be more concentrated. The invention is applicable more particularly to LSI devices. ...

Aluminium pad power bus and signal routing for integrated circuit device utilizing copper technology interconnect structures

Ultra dense vertical transport FET circuits

METHOD FOR FORMING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT FORMED BY THE METHOD

Array substrate, manufacturing method therefor and flat panel display device thereof

PRODUCTION OF AN ELECTRONIC CIRCUIT UNIT, WHICH STACKING CONTAINS IC SITUATIONS WITH BYPASS LINES

PROGRAMMABLE CONNECTING ARCHITECTURE

LEITBAHNANORNDUNG FOR MAXIMUMINTEGRATED CIRCUITS

HIGH FREQUENCY SIGNAL TRANSMISSION STRUCTURE

INTEGRATED CIRCUIT CHIP MANUFACTURE

NORMALIZED INTERCONNECTION PATTERNS

Herein disclosed is a semiconductor device which includes at least one semiconductor chip forming circuit element thereon and connection patterns being connected to said circuit element or elements. According to the invention, said connection patterns comprise a lower connection pattern, which is normalized and widely applied to many kinds of circuits, and an upper connection pattern, which is positioned on the upper side of said lower connection pattern. Said upper connection pattern and said lower connection pattern are connected in conformity with the circuit to be obtained.

SEMICONDUCTOR INTERCONNECTION STRUCTURE

... 4157-221 An improved field effect transistor utilizes a selfaligned contact structure in which a layer of metal capable of forming silicide is deposited on the source and drain regions as well as external to them. The metal forms metal silicide on the source and drain and, where it extends onto surrounding insulating regions, forms an interconnecting metal contact. In addition, bipolar devices may be formed on the same integrated circuit by employing insulating spacer regions around the edges of polysilicon electrodes to the bipolar devices. Also described are static and dynamic random access memory cells employing the technology.

A SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT

An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g 2+m 2=v 2 and an LCM of g and m is less than 20g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2 > m and the LCM of g, m, and m 2 is less than 20g.

SEMICONDUCTOR INTERCONNECTION STRUCTURE

IMAGER DEVICE WITH INTEGRAL ADDRESS LINE REPAIR SEGMENTS

An imager array data line repair structure for use in high performance imager arrays includes a first and a second plurality of address lines that are disposed in respective layers with an intermediate layer having at least one insulative material disposed therebetween. The imager device further includes at least one integral address line repair segment that is disposed in the same layer as the first address lines and that is electrically isolated from the first address lines; the integral address line repair segment is disposed so as to underlie a repair portion of the second address line, with the intermediate layer disposed therebetween, and has a width substantially the same as the overlying second address line. In initial fabrication, the integral address line repair segment is electrically isolated from the overlying repair segment of the second address line; in the event a repair has been effected, the repair portion of the second address line is electrically coupled to the underlying ...

Three-demensional semiconductor memory devices having double-intersection array and methods of fabricating the same

Three-dimensional storage element and fabrication method thereof

Post-passivation interconnect structure and methods thereof

SERIES-CONNECTED TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device

Contact scheme for landing on different contact area levels

Semiconductor device and a method of manufacturing the same

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Magnetic storage device

Semiconductor device

Semiconductor package

Semiconductor device and manufacturing method thereof

Semiconductor chip manufacturing and wiring design method thereof

Thin film transistor array panel

Semiconductor device and a method of manufacturing the same

2 INTEGRATED CIRCUIT CHIP HAVING TWO TYPES OF MEMORY CELLS

POWER MOS TRANSISTOR STRUCTURE

PORTION OF INTEGRATED CIRCUIT

STRUCTURE OF BARRIER FOR CONDUCTING ELECTRODES, AND ITS MANUFACTORING PROCESS

ELECTRICALLY ERASABLE PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE

INTEGRATED CIRCUIT WITH MACROCELLULES NOYEES IN A SEA OF DOORS OF THE TYPE PREDIFFUSEES AND MANUFACTORING PROCESS

DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS

L'INVENTION CONCERNE UN DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS. DANS CE DISPOSITIF QUI COMPORTE UN MICROPROCESSEUR 1 RELIE PAR DES ELECTRODES DE JONCTION P P A DIVERS CAPTEURS ET A DES CIRCUITS PERIPHERIQUES, IL EST PREVU UNE PREMIERE COUCHE DE CABLAGE 103A FORMEE SUR UN SUBSTRAT ET N'INTERSECTANT AUCUNE COUCHE DE CABLAGE ALIMENTEE PAR UN SIGNAL NUMERIQUE, UN PREMIER CIRCUIT ELECTRONIQUE 14, UNE SECONDE COUCHE DE CABLAGE APTE A ETRE ALIMENTEE PAR UN SIGNAL NUMERIQUE ET UN SECOND CIRCUIT ELECTRONIQUE 12 ACCOUPLE A CETTE COUCHE DE CABLAGE. APPLICATION NOTAMMENT A LA COMMANDE DU FONCTIONNEMENT D'UN MOTEUR D'AUTOMOBILE.

AN INTEGRATED CIRCUIT HAVING A SHARED CONTACT MASK

STRUCTURE AND PROCEEDED OF REPAIR OF JUST CIRCUITS

TWIN MEMORY CELLS INDIVIDUALLY ACCESSIBLE READ

L'invention concerne une mémoire non volatile (MA2) sur substrat semi-conducteur , comprenant : une première cellule mémoire comportant un transistor à grille flottante (TRi,j) et un transistor de sélection (ST) ayant une grille de contrôle verticale enterrée (CSG), une seconde cellule mémoire (Ci,j+i) comportant un transistor à grille flottante (TRi,j+i) et un transistor de sélection (ST) ayant la même grille de contrôle (CSG) que le transistor de sélection de la première cellule mémoire, une première ligne de bit (RBLj) reliée au transistor à grille flottante (TRi,j) de la première cellule mémoire, et une seconde ligne de bit (RBLj+1) reliée au transistor à grille flottante (TRi,j+i) de la seconde cellule mémoire (Ci,j+i).

STRUCTURE AND PROCEEDED OF REPAIR OF JUST CIRCUITS

L'invention concerne un circuit intégré dont une portion (20) au moins comprend au moins un groupe (21) de cellules de secours destinées à être éventuellement reliées à ladite portion (20) du circuit intégré par des connexions de remplacement dont la longueur ne peut dépasser une valeur prédéterminée (Δ). Les entrées et sorties des cellules de secours sont reliées à des pistes métalliques de secours (WB) dont la disposition sur le circuit est telle que tout point de la portion (20) du circuit est distant au maximum de la valeur prédéterminée (Δ) d'un point de ces pistes.

집적 회로 레이아웃으로부터 형성되는 반도체 디바이스

... 임베디드 FinFET SRAM 구조물 및 이의 형성 방법이 제공된다. 임베디드 FinFET SRAM 구조물은 SRAM 셀들의 어레이를 포함한다. SRAM 셀들은 제 1 방향의 제 1 피치, 및 상기 제 1 방향에 직교하는 제 2 방향의 제 2 피치를 갖는다. 제 1 피치 및 제 2 피치는 SRAM 셀들의 핀 활성 라인들 및 게이트 피처들을 주변 로직 회로들의 핀 활성 라인들 및 게이트 피처들과 정렬시키기 위해 구성된다. SRAM 구조물의 레이아웃은 3개의 층들을 포함하고, 여기서, 제 1 층은 핀을 형성하기 위한 맨드릴 패턴을 정의하고, 제 2 층은 더미 핀을 제거하기 위한 제 1 컷 패턴을 정의하며, 제 3 층은 핀 끝단을 단축하기 위한 제 2 컷 패턴을 정의한다. 이러한 3개의 층들은 SRAM 구조물의 핀 활성 라인들을 총괄하여 정의한다.

2가지 타입의 메모리 셀을 가지는 집적 회로 칩

... 집적 회로 칩은 제 1 타입 메모리 셀 및 제 2 타입 메모리 셀을 포함한다. 제 1 타입 메모리 셀은 제 1 기준 라인 랜딩 패드 및 제 1 워드 라인 랜딩 패드를 포함한다. 제 1 타입 메모리 셀의 제 1 기준 라인 랜딩 패드 및 제 1 타입 메모리 셀의 제 1 워드 라인 랜딩 패드는 제 1 방향을 따라 정렬된다. 제 2 타입 메모리 셀은 제 1 방향을 따라 연장되는 제 1 기준 라인 세그먼트 및 제 1 워드 라인 랜딩 패드를 포함한다. 제 2 타입 메모리 셀의 제 1 워드 라인 랜딩 패드 및 제 2 타입 메모리 셀의 제 1 기준 라인 세그먼트는 제 1 방향과 다른 제 2 방향을 따라 이격된다.

INTEGRATED CIRCUIT DEVICE WITH LAYERED TRENCH CONDUCTORS

패턴 구조물 및 이의 형성 방법.

... 패턴 구조물 및 이의 형성 방법에 관한 것으로, 상기 패턴 구조물은 연장 라인과, 상기 연장 라인의 일 단부와 연결되고, 상기 연장 라인보다 넓은 폭을 갖고, 일 측방으로 돌출되는 돌출부를 갖는 패드를 포함한다. 상기 패턴 구조물은 간단한 공정에 의해 제조될 수 있으며, 반도체 소자에 포함되는 다양한 미세 패턴에 사용될 수 있다.

반도체 장치, 표시 장치 및 전자 기기

... 기판상의 제 1의 방향을 따라서 연재되고, 서로 이격 배치된 주배선부 및 분기배선부를 갖는 하나 또는 복수의 제 1의 배선과; 상기 기판상의 상기 제 1의 방향과는 다른 제 2의 방향을 따라서 연재되는 줄기배선부와, 상기 주배선부와 상기 분기배선부와의 간극 영역 내에서 상기 제 1의 방향을 따라서 연재되는 복수의 가지배선부를 갖는 하나 또는 복수의 제 2의 배선과; 상기 복수의 가지배선부가 개별적으로 게이트 전극으로서 기능함과 함께, 상기 주배선부 내 및 상기 분기배선부 내에 형성된 소스 영역과, 상기 복수의 가지배선부 사이에 형성된 드레인 영역을 가지며, 각각이 상기 제 2의 방향을 따라서 복수개로 분할 형성되어 이루어지는 하나 또는 복수의 트랜지스터와; 상기 제 2의 방향을 따라서 연재되고, 상기 트랜지스터의 드레인 영역과 전기적으로 접속된 하나 또는 복수의 제 3의 배선을 구비하는 하는 반도체 장치가 개시된다.

개선된 인터커넥트 대역폭을 갖는 적층된 반도체 디바이스 패키지

... 본 개시는 적층된 반도체 디바이스 패키지 및 연관 기술들 및 구성들의 실시예들을 설명한다. 패키지는, 인터커넥트들, 및 일 측면에 부착되는 제 1 반도체 디바이스 및 대향 측면에 부착되는 제 2 반도체 디바이스를 갖는 패키징 기판을 포함할 수 있다. 디바이스들은, 패드 측면들이 기판의 대향하는 측면들 상에서 서로를 향하는 플립 칩 구성으로 부착될 수 있다. 디바이스들은 인터커넥트들에 의해 전기적으로 커플링될 수 있다. 디바이스들은 기판 상의 팬아웃 패드들에 전기적으로 커플링될 수 있다. 유전체 층은 기판의 제 2 측면에 커플링되고 제 2 디바이스를 캡슐화할 수 있다. 비아들은 전기 신호들을, 유전체 층을 통해 팬아웃 영역으로부터 그리고 유전체 층에 커플링된 재분배 층으로 라우팅할 수 있다. 다른 실시예들이 설명 및/또는 주장될 수 있다.

다이-대-다이 상호연결을 위한 브리지 모듈을 가지는 반도체 어셈블리

... 일 예에서, 반도체 어셈블리는 제 1 IC 다이(104A), 제 2 IC 다이(104B) 및 브리지 모듈(110)을 포함한다. 제 1 IC 다이는 자신의 최상부 측 상에, 복수의 상호연결부들(108) 중 제 1 상호연결부들(108A) 및 복수의 다이간 접촉부들(608) 중 제 1 다이간 접촉부들(608A)을 포함한다. 제 2 IC 다이는 자신의 최상부 측 상에, 복수의 상호연결부들 중 제 2 상호연결부들(108B) 및 복수의 다이간 접촉부들 중 제 2 다이간 접촉부들(608B)을 포함한다. 브리지 모듈은 제 1 상호연결부들과 제 2 상호연결부들 간에 배치되고 자신의 최상부 측 상에 브리지 상호연결부들(112) ― 브리지 상호연결부들은 복수의 다이간 접촉부들에 기계적으로 그리고 전기적으로 커플링됨 ―, 및 제 1 IC와 제 2 IC 사이에서 신호들을 라우팅하기 위하여 자신의 최상부 상에 배치된 전도성 상호연결부(706)의 층(들)을 포함한다. 브리지 모듈의 후면 측(710)은 복수의 상호연결부들의 높이를 넘어 연장되지 않는다.

AN INTEGRATED CIRCUIT RESISTANT TO THE FORMATION OF CRACKS IN A PASSIVATION LAYER

In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer (400) integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material (401). The present invention addresses this problem by providing an interconnect metal layer that comprises rounded corners which are believed to reduce the stresses transferred to a surrounding dielectric layer. COPYRIGHT KIPO & WIPO 2010 ...

METHOD FOR FABRICATING PATTERN OF SEMICONDUCTOR DEVICE

PURPOSE: A method for fabricating a pattern of a semiconductor device is provided to reduce fabricating cost and simplify a fabricating process by forming a fine pattern without using a photolithography process, and to overcome the limit of a line width of the photolithography process by making the line width of the pattern determined by the thickness of a material layer for forming the pattern. CONSTITUTION: A sacrificial layer is formed on a semiconductor substrate(100). The sacrificial layer is patterned to form a sacrificial layer pattern(103a). A conformal material layer is formed on the entire surface of the semiconductor substrate including the sacrificial layer pattern. The entire surface of the material layer is dry-etched until the semiconductor substrate is exposed so that a material layer pattern(110a,110b) is formed on both sidewalls of the sacrificial layer pattern. © KIPO 2003 ...

리세싱된 엣지들을 갖는 반도체 디바이스 및 그 제조방법

... 패키지 엣지를 따라 리세싱된 영역들을 활용하는 디바이스 및 제조 방법이 제공된다. 예를 들어, 집적형 팬 아웃 패키지에 있어서, 단품화 이후 유전체층들이 다이의 엣지들로부터 리세싱 백(recessed back)되도록, 유전체층들, 예컨대 재분배층들의 폴리머층들은 스크라이브 라인을 따라 제거된다. 모서리 영역들은 더욱 리세싱될 수 있다. 리세싱된 영역들은 삼각형, 둥근형, 또는 이와 다른 형상일 수 있다. 몇몇의 실시예들에서, 하나 이상의 모서리 영역들은 남아있는 모서리 영역들에 비해 더욱 리세싱될 수 있다. 재분배층들은 전측면 재분배층들과 후측면 재분배층들 중 하나 또는 이 둘 모두를 따라 리세싱될 수 있다.

Three dimensional semiconductor memory device

Metal Clip for Semiconductor package

INSPECTION METHOD, INSPECTION SYSTEM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SAME

Provided are an inspection method and an inspection system which can easily detect a defect. The inspection method comprises: generating first layout data including information on a shape of a first pattern group; generating second layout data including information on a shape of a second pattern group; obtaining a target image including images of the first and second pattern groups; and detecting a defect pattern from the target image by comparing the target image with the first layout data and the second layout data. The first pattern group, the second pattern group, and the defect pattern are provided at different heights from the upper surface of a substrate. COPYRIGHT KIPO 2018 (S10) Providing a substrate including a first pattern group (S20) Generating first layout data including information on a shape of a first pattern group (S30) Providing a substrate including a second pattern group stacked on the first pattern group (S40) Generating second layout data including information on ...

반도체 장치

ESD 내량이 높은 반도체 장치를 제공하기 위해, 소스 배선 (32a) 은, NMOS 트랜지스터 (30) 의 영역에 있어서 게이트 (31) 및 소스 (32) 상에 형성된다. 소스 배선 (32a) 은, 게이트 (31) 와 소스 (32) 와 접지 단자를 전기적으로 접속한다. 드레인 배선 (33a) 은, NMOS 트랜지스터 (30) 의 영역에 있어서 드레인 (33) 상에 형성된다. 드레인 배선 (33a) 은, 드레인 (33) 과 외부 접속용 전극인 패드 (20) 를 전기적으로 접속한다. 또, NMOS 트랜지스터 (30) 의 영역에 있어서, 드레인 배선 (33a) 은, 소스 배선 (32a) 의 배선폭과 동일한 배선폭을 갖는다.

ARTIFICIALLY TILTED VIA CONNECTION, CAPABLE OF USING A VIA LAYER IN WHICH A DIELECTRIC LAYER IS FORMED

PURPOSE: An artificially tilted via connection is provided to increase the gap between metal wirings by using a via layer in which a dielectric layer is formed as a wiring. CONSTITUTION: In an artificially tilted via connection, a via layer(1220) is formed. A free via hole is formed within the via layers. Dielectric layers(1228,1230) are formed on the via layer and an upper part of the free via hole is buried partly. A mask is formed on the dielectric layer to define a wiring. The wiring is formed within the dielectric layer by using the mask. The via hole is completed within the via layer, and the via hole and the wiring are filled with a conductive material. The wiring(1235) and via are overlapped with each other partly. COPYRIGHT KIPO 2010 ...

THIN FILM TRANSISTOR SUBSTRATE

PURPOSE: A thin film transistor substrate is provided to compensate a difference of an RC(Resistance Capacitance) delay value generated due to inequality of the length of lines in a fan-out of a thin film transistor. CONSTITUTION: An insulating substrate is provided. A plurality of gate lines(121) are formed on the insulating film and include pads to be connected with an external circuit. A plurality of data lines(171) cross the plurality of gate lines and include pads to be connected with an external circuit. A conductive pattern(93) is overlapped with the gate lines and the data lines. The length of the conductive pattern overlapped with the gate lines and the data lines decreases as the length of the gate lines or the data lines increases. © KIPO 2004 ...

DIRECTLY SAWING WAFERS COVERED WITH LIQUID MOLDING COMPOUND

TECHNIQUES FOR MRAM MTJ TOP ELECTRODE CONNECTION

SEMICONDUCTOR PACKAGE DEVICE

A semiconductor package device is provided. The semiconductor package device includes: a lower package including a lower substrate, and a lower semiconductor chip mounted on the lower substrate; an upper package including an upper substrate which is arranged on the lower package and has a protrusion part corresponding to the lower semiconductor chip and a connection part around the protrusion part, and an upper semiconductor chip mounted on the upper substrate; a heat radiation part which is filled between the lower semiconductor chip and the protrusion part of the upper substrate; and a package connection pattern which electrically connects the lower package and the upper package. COPYRIGHT KIPO 2016 ...

직접 플라즈마 고밀화 프로세스 및 반도체 디바이스들

... 본 개시내용의 양태는 반도체 디바이스 상에 장벽 층을 형성하는 방법에 관한 것이다. 이 방법은 반응 챔버 내로 기판을 배치하는 단계, 및 기판 위에 장벽 층을 퇴적하는 단계를 포함한다. 장벽 층은 금속 및 비금속을 포함하고, 장벽 층은 4nm 이하의 퇴적 시의 두께를 나타낸다. 이 방법은, 장벽 층에 근접하여 가스로부터 플라즈마를 형성함으로써 장벽 층을 고밀화하는 단계, 및 장벽 층의 두께를 감소시키고 밀도를 증가시키는 단계를 더 포함한다. 실시예들에서, 고밀화 동안, 300 와트 이하의 전력이 350kHz 내지 40MHz의 주파수에서 플라즈마에 인가된다.

개선된 스루 실리콘 비아

... 스루 비아 홀들이 ALD 및 PEALD 프로세싱을 이용하여 금속화를 위해 준비된다. 각 비아는 20 내지 200 Å 범위의 두께를 갖는 티타늄 질화물 배리어 층으로 코팅된다. 루테늄 시일링 층이 티타늄 질화물 배리어 층 위에 형성되고, 여기서, 시일링 층은 티타늄 질화물 배리어 층의 산화를 방지하기 위해 산소 없이 형성된다. 루테늄 결정핵생성 층이 시일링 층 위에 형성되고, 여기서, 결정핵생성 층은 Ru 결정핵생성 층의 도포 동안 탄소를 산화시키기 위해 산소를 가지고 형성된다. 시일링 층은 산소 대신에 플라즈마 여기된 질소 라디칼들을 이용하여 PEALD 방법에 의해 형성된다.

Semiconductor package

에어 갭을 가지는 후면 유전체 층을 갖는 집적 회로 구조체

... 집적 회로(IC) 구조체는 게이트 구조체, 소스 에피택셜 구조체, 드레인 에피택셜 구조체, 전면 상호연결 구조체, 후면 유전체 층 및 후면 비아를 포함한다. 소스 에피택셜 구조체와 드레인 에피택셜 구조체는 제각기 게이트 구조체의 양측에 있다. 전면 상호연결 구조체는 소스 에피택셜 구조체의 전면 및 드레인 에피택셜 구조체의 전면 상에 있다. 후면 유전체 층은 소스 에피택셜 구조체의 후면 및 드레인 에피택셜 구조체의 후면 상에 있으며 내부에 에어 갭을 갖는다. 후면 비아는 후면 유전체 층을 관통하여 소스 에피택셜 구조체 및 드레인 에피택셜 구조체의 첫 번째 것까지 연장된다.

반도체 패키지

... 본 개시의 일 실시예는, 서로 반대에 위치한 제1 및 제2 면을 가지며, 재배선층을 갖는 연결 구조체와, 상기 연결 구조체의 제1 면 상에 배치되며, 상기 재배선층에 연결된 접속 패드를 갖는 반도체 칩과, 상기 연결 구조체의 제1 면 상에 배치되며, 상기 반도체 칩을 봉합하는 봉합재와, 상기 연결 구조체의 제2 면 상에 배치되며, 상기 재배선층의 제1 및 제2 영역을 각각 노출시키는 복수의 제1 및 제2 개구를 갖는 패시베이션층과, 상기 복수의 제1 개구를 통해 상기 재배선층의 제1 영역에 각각 연결되는 복수의 언더범프 금속을 포함하는 반도체 패키지를 제공한다.

SEMICONDUCTOR DEVICE

Semiconductor device and method of fabricating the same

Semiconductor structure, 3dic structure and method of fabricating the same

Circuit structure and method of manufacturing the same

Layout designs with via routing structures

An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Semiconductor device structure

An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Semiconductor memory device

A semiconductor memory device improving an area efficiency of a page buffer/sense circuit and suppresses erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 forms a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data will be programed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns*m segments within one pitch in the row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.

An integrated circuit resistant to the formation of cracks in a passivation layer

In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded corners which are believed to reduce the stresses transferred to a surrounding dielectric layer.

Semiconductor device, and manufacturing method for same

A semiconductor device has a semiconductor substrate SB, and a wiring structure formed on the principal plane of the semiconductor substrate SB. The first wiring layer, which is topmost among the plurality of wiring layers included in the wiring structure, includes a pad PD, and the pad PD has a first region for joining copper wire, and a second region for making contact with a probe. A second wiring layer, which is one layer below the first wiring layer among the plurality of wiring layers included in the wiring structure, includes a wiring M6 arranged directly below the pad PD, the wiring M6 is arranged directly below a region other than the first region of the pad PD, and a conductor pattern of the same layer as the wiring M6 is not formed directly below the first region of the pad PD.

3D low flux, high-powered MMIC amplifiers

The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system (200) may include a plurality of high electron mobility transistors (212) disposed on a first substrate (210). A first portion of the plurality of high electron mobility transistors (212) are electrically coupled via respective first level interconnects (214) disposed on the first substrate (210). The system (200) also includes a plurality of second level interconnects (224) disposed on a second substrate (220). A second portion of the plurality of high electron mobility transistors (212) are electrically coupled via respective second level interconnects (224). The first substrate (210) and the second substrate (220) are coupled such that the plurality of high electron mobility transistors (212) provides an amplified output signal via at least one of the first level interconnects (214) or the second level ...

Electronic device

Disclosed is an electronic device wherein: a first semiconductor device having a switching power transistor is mounted on a power wiring board PB1; a semiconductor device PKG6 having a drive circuit that drives the first semiconductor device, and a semiconductor device PKG5 having a control circuit that controls the semiconductor device PKG6 are mounted on a first main surface of a control wiring board PB2; and a semiconductor device PKG4 having a regulator circuit is mounted on a second main surface of the control wiring board PB2. The semiconductor device PKG5 and the semiconductor device PKG6 are mounted on, out of a second region and a third region, the second region of the first main surface of the control wiring board PB2, said second region and third region being adjacent to each other by having therebetween a first region where a plurality of holes HC3 are disposed. The semiconductor device PKG4 is mounted on, out of a fourth region positioned on the reverse side of the second region ...

A semiconductor package structure

The present invention provides a semiconductor package structure. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure has an opening aligned with the dicing lane region.

Nonvolatile semiconductor memory device and method for manufacturing same

In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Interconnect Structure for Semiconductor Devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Semiconductor Device

A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Structure for nano-scale metallization and method for fabricating same

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

High-voltage tolerant voltage regulator

Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Chip structure and process for forming the same

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Wiring structure of semiconductor device

A wiring structure may include a first wiring having a first width that extends in a first direction, and a second wiring intersecting the first wiring, the second wiring extending in a second direction and having a second width that is equal to or less than the first width. Furthermore, the first wiring may have a third width that is smaller than the first width and the second wiring may have a fourth width that is smaller than the second width. Portions of the first and second wirings having the third and fourth widths may extend from an intersecting region in which the first wiring and the second wiring intersect each other.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Semiconductor device and substrate

A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Structure with self aligned resist layer on an interconnect surface and method of making same

A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Distributed Metal Routing

A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Method to fabricate copper wiring structures and structures formed tehreby

Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Semiconductor integrated circuit device

A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].

Semiconductor device and method of producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Integrated cmos porous sensor

A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Interconnect Structure to Reduce Stress Induced Voiding Effect

An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Semiconductor device having groove-shaped via-hole

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a. A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Semiconductor device having wiring layer

Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 μm; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 μm from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 μm from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.

Backside Power Delivery Using Die Stacking

In a stacked die device having an active circuit die bonded on top of a power delivery die using, circuit components formed on the active circuit die are connected to receive power from a coarse network of low resistance, high capacitance power and ground conductors in the power delivery die through conductive via structures or through silicon vias (TSVs) formed in the active circuit die so that primary power is provided from the backside of the active circuit die, leaving more resources and space in the metal interconnect structure for input/output signal routing.

Wiring structure and method of forming the structure

Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

Semiconductor structure and method for fabricating semiconductor layout

A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Discontinuous/non-uniform metal cap structure and process for interconnect integration

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Semiconductor device and method of manufacturing the same

A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.

Semiconductor device

In one embodiment, a semiconductor device includes a first wiring provided in a first wiring layer along a first direction, a second wiring provided in a second wiring layer along a second direction orthogonal to the first direction, the second wiring intersecting with the first wiring at a first intersect portion, and a third wiring provided close to and along the second wiring in the second wiring layer, the third wiring intersecting with the first wiring at a second intersect portion, wherein a distance between the second wiring in the first intersection portion and the third wiring in the second intersection portion is narrower than a distance between the second wiring another than the first intersection portion and the third wiring another than the second intersection portion.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor Device and Manufacturing Method of the Same

Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line.

Low energy etch process for nitrogen-containing dielectric layer

A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR ELEMENT

A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad. 1. A method for manufacturing a semiconductor device , the method comprising:preparing a semiconductor element including a plurality of electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element;preparing a wiring substrate including a plurality of connection pads respectively corresponding to the plurality of electrode pads of the semiconductor element, wherein each of the connection pads is rectangular and elongated in a direction orthogonal to a layout direction of the line of electrode pads including the corresponding electrode pad;applying a solder including a bulging central portion on an upper surface of each of the connection pads;forming a plurality of pillar-shaped electrode terminals respectively on the plurality of electrode pads of the semiconductor element so that each of the electrode terminals has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad; andelectrically connecting ...

SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features. 118-. (canceled)19. A semiconductor device comprising:a plurality of line traces including at least one real trace which includes a gate electrode portion and a protruding portion protruding beyond the gate electrode portion by a predetermined distance, and at least one dummy trace placed in parallel with the at least one real trace,wherein two of multiple ones of the dummy trace, and at least one of the line traces interposed between the two dummy traces and including the at least one real trace form parallel extending line traces extending in parallel so as to be evenly spaced,the parallel extending line traces have an identical width while at least one end portions of the parallel extending line traces form line end portions facing a cell perimeter boundary region and being substantially flush with one another,line end portion uniformization dummy traces are formed on extensions of the line end portions of the parallel extending line traces so that the distances between the line end portions and corresponding line end portions of the line end portion ...

Semiconductor device

A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.

Automatic Place and Route Method for Electromigration Tolerant Power Distribution

The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J max ) for mean time to failures (MTTF) to be increased.

Integrated circuit and method of providing electrostatic discharge protection within such an integrated circuit

An integrated circuit with electrostatic discharge (ESD) protection, and a method of providing such ESD protection within the integrated circuit, are disclosed. The integrated circuit comprises functional circuitry having functional components for performing processing functions required by the integrated circuit, and interface circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. The integrated circuit is formed of a plurality of layers, including component level layers within which any of the functional components formed from a standard cell are constructed, power grid layers providing a power distribution infrastructure for the functional components, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further comprises at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.

Method for implementing spare logic of semiconductor memory apparatus and structure thereof

A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE

The semiconductor device has insulating films formed over a substrate ; an interconnection buried in at least a surface side of the insulating films ; insulating films formed on the insulating film and including a hole-shaped via-hole and a groove-shaped via-hole having a pattern bent at a right angle; and buried conductors buried in the hole-shaped via-hole and the groove-shaped via-hole . A groove-shaped via-hole is formed to have a width which is smaller than a width of the hole-shaped via-hole . Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented. 1. A semiconductor device comprising:a first insulating film formed above a substrate; a first interconnection buried in the first insulating film;a second insulating film formed above the first insulating film with the first interconnection;two groove-shaped patterns formed in the second insulating film, the groove-shaped patterns including a first pattern which has a first bent portion with a first angle in a plan view, a second pattern which has a second bent portion with a second angle that is larger than the first angle in a plan view and a third bent portion which has a third angle that is larger than the first angle in a plan view; anda conductive layer formed in the first and the second pattern, the conductive layer electrically coupling to the first interconnection.2. The semiconductor device according to claim 1 , wherein the first angle is 90°.3. The semiconductor device according to claim 1 , wherein the second angle and the third angle are 135°.4. The semiconductor device according to claim 1 , wherein the first interconnection has two bent portions with an angle that is larger than 90°.5. The semiconductor device according to claim 1 , wherein the first interconnection has ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first conductive layer over the semiconductor die;depositing an encapsulant around the semiconductor die;forming a first insulating layer over the semiconductor die; andforming an interconnect structure over the first insulating layer and encapsulant, wherein the first insulating layer provides stress relief for the interconnect structure.2. The method of claim 1 , further including:forming a channel in the semiconductor die; andforming the first insulating layer into the channel.3. The method of claim 1 , further including:forming a channel in the encapsulant; andforming the first insulating layer into the channel.4. The method of claim 1 , further including forming a second insulating layer over the semiconductor die prior to forming the first insulating layer.5. The method of claim 1 , further including removing a portion of the first insulating layer by laser direct ablation.6. The method of claim 1 , ...

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Solid-state imaging device, imaging apparatus, substrate, semiconductor device and method of manufacturing the solid-state imaging device

A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Semiconductor device

A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Power Routing with Integrated Decoupling Capacitance

An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network ( 200 ) which comprises, in a first one (metalz) of the conduction layers, a first mesh structure ( 210 ) of electrically conductive material for distribution of a first electrical potential (POWER) of the power supply. The power-supply distribution network also comprises, in a second one (metalz+1) of the conduction layers, different from the first one of the conduction layers, a second mesh structure ( 220 ) of electrically conductive material for distribution of a second electrical potential (GROUND) of the power supply. In the first one (metalz) of the conduction layers, a first plurality of islands ( 212 ) of electrically conductive material is provided, each island being located in a hole ( 214 ) of the first mesh structure ( 210 ) and being electrically insulated from the first mesh structure with a dielectric material.

Semiconductor device including a first wiring having a bending portion a via

A first wiring ( 1 ) has a bending portion ( 2 ), a first wiring region ( 1 a ) extending from the bending portion ( 2 ) in the X direction, and a second wiring region ( 1 b ) extending from the bending portion ( 2 ) in the Y direction. A via ( 3 ) is formed under the wiring ( 1 ). The via ( 3 ) is formed so as not to overlap with a region of the bending portion ( 2 ) in the first wiring region ( 1 a ). The length of the via ( 3 ) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via ( 3 ) in the Y direction overlap with both ends of the first wiring region ( 1 a ) in the Y direction.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. 16-. (canceled)7. A semiconductor device comprising:a first wiring layer disposed in a first level;a second wiring layer formed at a level above the first wiring layers;a third wiring layer formed at a level below the first wiring layers,a contact hole connecting the second wiring layer and the third wiring layer;a first restriction region including the first wiring layer;a second restriction region including the contact hole;a plurality of dummy wiring layers provided in the first level; andwherein the dummy wiring layers are provided in regions other than the first restriction region and the second restriction region.8. The semiconductor device of claim 7 , wherein at least a part of the dummy wiring layer overlaps the second wiring layer in plan view.9. The semiconductor device of claim 7 , wherein at least one of the dummy wiring layers overlaps the second wiring layer in plan view.10. The semiconductor device of claim 7 , wherein the first wiring layer and the second wiring layer are parallel. This application is a continuation application of U.S. Ser. No. 13/485,165 filed May 31, 2012, which is a divisional application of U.S. ...

SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS

A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit. 122-. (canceled)23. A semiconductor device , comprising:a semiconductor substrate;an integrated circuit on the semiconductor substrate;an insulation layer covering the integrated circuit;a barrier layer covering the insulation layer; anda plurality of metal line patterns on the barrier layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit adjacent to the space.24. The semiconductor device as claimed in claim 23 , further comprising an additional insulation layer between the insulation layer and the barrier layer.25. The semiconductor device as claimed in claim 24 , further comprising a resistive layer between the additional insulation layer and the insulation layer.26. The semiconductor device as claimed in claim 23 , wherein the slits are less than about 4 μm from the space.27. The semiconductor device as claimed in claim 23 , wherein the space is less than about 10 μm.28. The semiconductor device as claimed in claim 27 , wherein the space is less than about 1 μm.29. The semiconductor device as claimed in claim 23 , wherein the slits have a width greater than about 1 μm.30. The semiconductor device as claimed in claim 23 , wherein the first and second metal line patterns have a width greater than about 30 μm.31. The semiconductor device as claimed in claim 23 , wherein each metal line pattern of the plurality of metal line patterns having a width greater ...

Dielectric thin film element, antifuse element, and method of producing dielectric thin film element

A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer 22 . Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Stress Reduction Apparatus

A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Semiconductor Package with Integrated Electromagnetic Shielding

There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Diffusion Barrier Layer, Metal Interconnect Arrangement and Method of Manufacturing the Same

A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.

Interconnect structures

A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE

A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact. 1. A semiconductor device with overlapping contacts comprises:a dielectric layer;a first contact located in the dielectric layer; anda second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.2. The semiconductor device of claim 1 , wherein the second contact completely covers the top surface of the first contact.3. The semiconductor device of claim 1 , wherein the first contact comprises a liner claim 1 , the liner comprising a first outer liner layer located adjacent to the dielectric layer claim 1 , a first inner liner layer located over the first outer liner layer claim 1 , and a first contact fill metal located over the first inner liner layer; andwherein the second contact comprises a second outer liner layer, wherein a first portion of the second outer liner layer is located adjacent to the dielectric layer, and a second portion of the second outer liner layer is located adjacent to the first contact fill metal on the top surface of the first contact, a second inner liner layer located over the second outer liner layer, and a second contact fill metal located over the second inner liner layer.4. The semiconductor device of claim 3 , wherein the first and second outer liner layers comprise titanium claim 3 , the first and second inner liner layers comprises titanium nitride claim 3 , and the first and second contact fill metal comprises tungsten.5. The semiconductor device of claim 1 , wherein the dielectric layer comprises one of an oxide and a nitride.6. The semiconductor device of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. 1. A manufacturing method of a semiconductor device comprising:forming core patterns, onto which a plurality of linear shaped first mask patterns, each of which is offset in three stages by a wiring pitch in an orthogonal direction with respect to a wiring direction, is transferred, on a processing target layer;forming first sidewall patterns on sidewalls of the core patterns;removing the core patterns while leaving the first sidewall patterns on the processing target layer;forming second sidewall patterns on sidewalls of the first sidewall patterns in such a way that sidewalls facing each other with a space between the first sidewall patterns therebetween are brought into contact with each other at a bent portion of the first sidewall patterns; andforming openings in the processing target layer by processing the processing target layer exposed from the first and second sidewall patterns.2. The manufacturing method of a semiconductor device according to claim 1 , wherein the first mask pattern is offset back and forth in an orthogonal direction with respect to the wiring direction of wires.3. The manufacturing method of a semiconductor device according to claim 2 , wherein the first mask ...

NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS

A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device. 1. A method comprising:providing a mask with a semiconductor circuit layout including a plurality of mask lines including at least a first mask line including at least one notch shape;fabricating a portion of said semiconductor circuit using said mask to form a plurality of conductive lines corresponding to said plurality of mask lines and including a first conductive line corresponding to said first mask line and having at least one notch, each of said at least one notch corresponding to one notch shape of said at least one notch shape, wherein said first conductive line is surrounded by an insulator material and interconnects at least two components of said semiconductor circuit and said fabricating results in formation of residual stresses within said plurality of conductive lines and said insulator material; andfurther fabricating further portions of said sera semiconductor circuit to produce said semiconductor circuit,wherein each of said at least one notch generates extra stress components within said first conductive line compared to other conductive lines of said plurality of conductive ...

Decoupling capacitor cell, cell-based ic, cell-based ic layout system and method, and portable device

A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

Optimizing Layout of Irregular Structures in Regular Layout Context

A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch. 1. An integrated circuit , comprising:a plurality of regular wires formed within a given chip level, each of the plurality of regular wires having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction, the plurality of regular wires positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two of the plurality of regular wires is an integer multiple of the fixed pitch; andat least one irregular wire formed within the given chip level and within a region bounded by the plurality of regular wires, the at least one irregular wire having a linear-shape with a length extending in the first direction and a width extending in the second direction, wherein a distance as measured in the second direction between a lengthwise centerline of the at least one irregular wire and any one of the plurality of regular wires is not equal to an integer multiple of the fixed pitch.2. An integrated circuit as recited in claim 1 , wherein the at least one ...

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.

Deformable Network Structure

Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state. 2. The deformable network structure of claim 1 , wherein the connector provides an electrical connection between the first and the second device portions.3. The deformable network structure of claim 1 , wherein a first distance between the first and second centers in the final state varies at least 10% of a second distance between the first and second centers in the initial state contributed by a deformation of the connector.4. The deformable network structure of claim 3 , wherein the first distance between the first and second centers in the final state is less than 90% of the second distance between the first and second centers in the initial state.5. The deformable network structure of claim 3 , wherein the first distance between the first and second centers in the final state is greater than 1.1 fold of the second distance between the first and second centers in the initial state.6. The deformable network structure of claim 1 , wherein the first and second centers are geometric centers claim 1 , mass centers or centers of symmetry.7. The deformable network structure of claim 1 , wherein the first and second device portions and the connector share a common material layer.8. The deformable network structure of claim 1 , wherein the first and second device portions and the ...

Methods of forming conductive structures and methods of forming dram cells

Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Methods for Multi-Wire Routing and Apparatus Implementing Same

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. 1. A semiconductor chip , comprising:a first set of at least two conductors extending in a first direction in a parallel manner, the first set of at least two conductors corresponding to a common electrical node;a second set of at least two conductors extending in a second direction in a parallel manner, the second direction perpendicular to the first direction, the second set of at least two conductors corresponding to the common electrical node, the first and second sets of at least two conductors located on different levels of the semiconductor chip; andat least two interlevel conductors extending between the different levels of the semiconductor chip such that each of the first set of at least two conductors is connected to at least one of the second set of at least two conductors by one or more of the at least two interlevel conductors.2. A semiconductor chip as recited in claim 1 , wherein the at least two interlevel conductors are positioned in a rectangular array defined in accordance with the first and second directions.3. A ...

Method for Producing a Conductor Line

A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

Elongated via structures

An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Semiconductor device

The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

Method to resolve hollow metal defects in interconnects

A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT

A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described. 1. A method for reducing areas of high field density in an integrated circuit , the method comprising:forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit;forming a second curvilinear wiring structure in a second interconnect layer of the integrated circuit, wherein the second curvilinear wiring structure is substantially vertically aligned with the first curvilinear wiring structure; andelectrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure.2. The method of claim 1 , wherein electrically connecting the first curvilinear wiring structure to the second curvilinear wiring structure comprises:forming a curvilinear conductive via to electrically connect the first curvilinear wiring structure to the second curvilinear wiring structure; andextending the curvilinear conductive via between the first curvilinear wiring structure and the second curvilinear wiring structure.3. The method of claim 2 , wherein forming the first curvilinear wiring structure comprises forming a first set of concentric conductive annular structures having a first electrode and a second electrode.4. The method of claim 3 , wherein forming the second curvilinear wiring structure comprises forming a second set of concentric conductive annular structures having a first electrode and a second ...

Semiconductor chip layout with staggered tx and tx data liness

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. 1. A method of forming a semiconductor structure , comprising:forming a stack of conductive materials, wherein adjacent conductive materials of the stack are separated from each other by a respective insulating material;forming first contact regions over portions of the conductive materials to form a stair step structure extending from a top first contact region to a bottom first contact region; andremoving portions of half of the conductive materials of the stack to form second contact regions, each of the second contact regions being offset from a corresponding first contact region and adjacent to the corresponding first contact region in a direction perpendicular to a direction in which the stair step structure extends.2. The method of claim 1 , wherein forming first contact regions over portions of the conductive materials to form a stair step structure comprises:forming a mask over a topmost insulating material of the stack;removing a portion of the mask to expose a portion of the topmost insulating material;removing at least the exposed ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH FORMATION OF CONDUCTIVE LINES

A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region. 117-. (canceled)18. A semiconductor device comprising:a substrate having a first region and second regions disposed on two sides of the first region;a first group of conductive lines extending from the first region to the second regions on the substrate;a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate;interlayer insulating layers formed over the substrate;insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; andcontact plugs contacting the second group of conductive line formed in second open regions of the interlayer insulating layer in the second region.19. The semiconductor device of claim 18 , wherein the insulating layers and the contact plugs are disposed in a zigzag form.20. The semiconductor device of claim 18 , wherein the first group of the insulating layers is aligned in a first line perpendicular with the extending direction of the conductive lines and the second group of contact plugs is aligned in a second line perpendicular with the extending direction of the conductive lines.21. The semiconductor device of claim 18 , wherein the insulating layers and the contact plugs ...

DIE POWER STRUCTURE

A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles. 19.-. (canceled)10. The method of operating a die , comprising:distributing a first power signal having a first voltage across a first plurality of power tiles arranged in a first array and a first plurality of mesh segments;distributing a second power signal having a second voltage across a second plurality of power tiles arranged in a second array and a second plurality of mesh segments,wherein the first plurality of power tiles encloses the second plurality of mesh segments,wherein the second plurality of power tiles encloses the first plurality of mesh segments, andwherein the first array and the second array are offset on the die; andpropagating the first power signal to a first power rail operatively connected to the first plurality of power tiles and the first plurality of mesh segments by a first plurality of vias.11. The method of claim 10 , further comprising:propagating the second power signal to a second power rail operatively connected to the second plurality of power tiles and the second plurality of mesh segments by a second plurality of vias.12. The method of claim 11 , further comprising:injecting the first power signal into the die using a first bump above the second array and operatively connecting to the first plurality of power tiles using a zipper structure;and injecting the second power signal into the die using a second bump above the first array and operatively connecting to the second plurality of power ...

Semiconductor device

In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.

RF CMOS TRANSISTOR DESIGN

An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line, in an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers. 1. An RF CMOS transistor , the transistor comprising:an active area;a plurality of gate fingers;a plurality of local interconnect lines constrained substantially to above the active area of the transistor; anda source terminal and a drain terminal arranged orthogonally to each of the plurality of local interconnect lines, wherein each terminal is electrically connected to at least one local interconnect line wherein the source terminal and the drain terminal are substantially wider than a local interconnect line and the source terminal and drain terminal are routed above the active region, including above the gate fingers,2. The RF CMOS transistor according to claim 1 , wherein the source terminal and the drain terminal are formed in different metal layers.3. The RF CMOS transistor according to claim 1 , further comprising a second drain terminal and wherein the drain terminals are arranged either side of the source terminal.4. The RF CMOS transistor according to claim 1 , further comprising at least one gate strap claim 1 , and wherein the at least one gate strap is routed in a metal layer avoe the source and drain terminals substantially across a center of the transistor in parallel with the plurality of gate fingers.5. The RF CMOS transistor design according to claim 1 , further comprising:a dummy gate electrode structure; anda well-tap adjacent to the dummy gate electrode structure,and wherein the dummy gate ...

Semiconductor memory devices and methods of fabricating the same

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm. 1. A semiconductor device comprising:a semiconductor substrate;a first active region in the semiconductor substrate;a second active region in the semiconductor substrate;{'sup': '-1', 'a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm.'}2. The semiconductor device of claim 1 , further comprising:a third active region in the semiconductor substrate;a fourth active region in the semiconductor substrate; and{'sup': '-1', 'a second conductive line over the semiconductor substrate electrically connected to the third active region and having a second end face adjacent to the fourth active region, and the second end face having an image log slope of greater than 15 μm, and a distance between the first conductive line and the second conductive line is less than 100 nm.'}3. The semiconductor device of claim 2 , further comprising an isolation region between the first conductive line and the second conductive line.4. The semiconductor device of claim 3 , wherein neither the first conductive line nor the second conductive line substantially overlap the isolation region.5. The semiconductor device of claim 1 , wherein the first conductive line comprises at least one of tungsten claim 1 , aluminum claim 1 , copper claim 1 , or conductive polymer.6. A semiconductor device comprising:a semiconductor substrate;a first active region in the ...

Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer

A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.

Device-Manufacturing Scheme for Increasing the Density of Metal Patterns in Inter-Layer Dielectrics

A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Stacked multilayer structure and manufacturing method thereof

A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS

A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. 1. A semiconductor component comprising:a semiconductor substrate; a plurality of elongate first main electrode zones each respectively connected to one of a plurality of overlying first lower islands via at least one through hole,', 'a plurality of elongate second main electrode zones arranged alternately with and parallel to the plurality of elongate first main electrode zones and each respectively connected to one of a plurality of overlying second lower islands via at least another through hole, and', 'a control electrode zone arranged between the first and second main electrode zones;, 'at least one cell formed on the semiconductor substrate and comprising'}a first collective island arranged transversely above the pluralities of overlying first and second lower islands and connected to the plurality of overlying first lower islands;a second collective island arranged transversely above the pluralities of overlying first and second lower islands and connected to the plurality of overlying second lower islands;wherein the pluralities of overlying first and second lower islands and the first and second collective islands comprise sections of metallization layers,wherein longitudinal sections of the overlying first and second lower islands covered by and connected to the first and second collective islands are not more than about four times as wide as the pluralities of elongate first and second main electrode zones respectively connected to the pluralities of overlying first and second lower islands, ...

Semiconductor device

One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer.

Power tsvs of semiconductor device

A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING SAME

Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate. 1. A substrate structure , comprising:a first substrate and a second substrate oppositely arranged,wherein a first surface of the first substrate faces toward a second surface of the second substrate, and a conductive interconnect layer and a bonding layer are provided on the first surface in sequence; andthe first substrate and the conductive interconnect layer are coupled to the second substrate via the bonding layer.2. (canceled)3. The substrate structure according to claim 1 , wherein the conductive interconnect layer comprises at least one conductive layer.4. (canceled)5. The substrate structure according to claim 3 , wherein one of the at least one conductive layer performs a shielding function.6. The substrate structure according to claim 3 , wherein the conductive interconnect layer comprises at least two conductive layers.7. The substrate structure according to claim 1 , further comprising:isolation regions passing through the first substrate, wherein the first substrate is divided into regions mutually insulated by the plurality of isolation regions.8. The substrate structure according to claim 1 , further ...

Semiconductor device including a buffer layer structure for reducing stress

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

SEMICONDUCTOR DEVICE, SOLAR CELL MODULE, SOLAR CELL STRING, AND SOLAR CELL ARRAY

The semiconductor device has a conductive substrate formed from a conductive material, a nonconductive layer provided on at least part of the surface of the conductive substrate, plural semiconductor elements provided on this nonconductive layer, wiring that electrically connects the plural semiconductor elements, and at least one electrical connection part between the nonconductive layer and semiconductor elements or wiring. The semiconductor element for which the potential difference with the conductive substrate is the greatest is disposed in a position other than the geometric terminal of the arrangement created by the plural semiconductor elements. 1. A semiconductor device comprising:a conductive substrate made of a conductive material;a nonconductive layer that is disposed in at least a portion of the surface of the conductive substrate;plural semiconductor elements that are arranged on the nonconductive layer;a wiring that electrically connects the plural semiconductor elements to one another; andat least one electrical connection portion that connects the conductive substrate to the semiconductor elements or the wiring,wherein the semiconductor element that shows a largest potential difference with respect to the conductive substrate is arranged in a position excluding a geometric end of an array composed of the plural semiconductor elements.2. The semiconductor device according to claim 1 ,wherein the at least one electrical connection portion comes into contact with at least one semiconductor element positioned within a range that includes 10% of a number of the plural semiconductor elements from at least one end of the array, andwhen the electrical connection portion comes into contact with plural semiconductor elements, the semiconductors are equipotential to each other.3. The semiconductor device according to claim 1 ,wherein the at least one electrical connection portion comes into contact with at least one semiconductor element positioned within a ...

Semiconductor device

One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal.

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor. 1. A semiconductor device comprising:a lower conductor having a lower conductor sidewall;a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall; anda via formed on a top surface of the lower conductor,wherein a top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.2. The semiconductor device of claim 1 , further comprising:a first insulation film surrounding a combination of the lower conductor and the barrier film, wherein a portion of the first insulation film proximate the recessed top portion of the barrier film sidewall is recessed.3. The semiconductor device of claim 2 , wherein the recessed top portion of the barrier film and the recessed portion of the first insulation film collectively form a recessed region having a width that is upwardly increasing from the top surface of the barrier film.4. The semiconductor device of claim 3 , wherein the via extends to completely fill the recessed region.5. The semiconductor device of claim 1 , wherein a width of the top surface of the lower conductor is less than or equal to a width of a bottom surface of the via.6. The semiconductor device of claim 1 , further comprising:a first upper conductor formed directly on the via and having opposing sidewalls that vertically align with respective opposing sidewalls of the via.7. The semiconductor device of claim 6 , further comprising:a second upper conductor arranged in parallel with the first upper conductor and ...

SEMICONDUCTOR DEVICE

A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. 1. A semiconductor device comprising:a substrate;a transistor formed on the substrate;a multilayer interconnect structure having three or more layers which is formed over the substrate and the transistor;a first conductor pattern formed in the n-th layer of the multilayer interconnect structure (n≧1) and coupled to a ground or power supply; anda signal line formed in the (n+2)th layer of the multilayer interconnect structure or an interconnect layer above it and located in a region in which it overlaps the first conductor pattern in a plan view,wherein at least part of a transmission line is formed by the signal line and the first conductor pattern.2. A semiconductor device according to claim 1 ,Wherein the transistor overlaps the first conductor pattern in a plan view.3. A semiconductor device according to claim 2 , further including an organic resin layer formed over the multilayer interconnect structure claim 2 , wherein the signal line is formed over the organic resin layer.4. A semiconductor device according to claim 3 , further including two second conductor patterns which are formed in an interconnect layer above the n-th layer of the multilayer interconnect structure and extend parallel to the signal line with the signal line between them claim 3 , in a plan view claim 3 ,wherein the second conductor patterns are electrically coupled to the ground or the power supply.5. A semiconductor device according to claim 4 ,wherein the second conductor patterns are formed in the same layer as the signal line.6. A semiconductor device according to claim 5 ,wherein the height form the first conductor pattern to the signal line ...

Sensor packaging method and sensor packages

A method ( 80 ) entails providing ( 82 ) a structure ( 117 ), providing ( 100 ) a controller element ( 102, 24 ), and bonding ( 116 ) the controller element to an outer surface ( 52, 64 ) of the structure ( 117 ). The structure includes a sensor wafer ( 92 ) and a cap wafer ( 94 ). Inner surfaces ( 34, 36 ) of the wafers ( 92, 94 ) are coupled together, with sensors ( 30 ) interposed between the wafers ( 92, 94 ). One wafer ( 94, 92 ) includes a substrate portion ( 40, 76 ) with bond pads ( 42 ) formed on its inner surface ( 34, 36 ). The other wafer ( 94, 92 ) conceals the substrate portion ( 40, 76 ). After bonding, methodology ( 80 ) entails forming ( 120 ) conductive elements ( 60 ) on the element ( 102, 24 ), removing ( 126 ) material sections ( 96, 98, 107 ) from the wafers ( 92, 94, 102 ) to expose the bond pads ( 42 ), forming ( 130 ) electrical interconnects ( 56 ), applying ( 134 ) packaging material ( 64 ), and singulating ( 138 ) to produce sensor packages ( 20, 70 ).

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Microelectronic packages having trench vias and methods for the manufacture thereof

Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.