ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

PACKAGE WITH UBM AND FORMING METHOD

Disclosed are a package structure and a method of forming package structures. The package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer. COPYRIGHT KIPO 2016 ...

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion protrudes from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Through via connected backside embedded circuit features structure and method

A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Projection-electrode fabrication method

A projection-electrode fabrication method having the steps of: (a) fabricating at least one projection electrode directly on a substrate; and (b) forming a semiconductor circuit layer adjacent to the projection electrode on the substrate so as to contact at least one projection electrode after the step of fabricating the projection electrode. The projection electrode is projected higher as compared to the semiconductor circuit layer.

Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof

A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Elektronische Komponente

In einer Ausführungsform schließt eine elektronische Komponente eine dielektrische Schicht, ein in die dielektrische Schicht eingebettetes Halbleiterbauelement, ein elektrisch leitendes Substrat, eine Umverteilungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, die mindestens einen Außenkontakt vorsieht, und ein erstes elektrisch leitendes Bauteilelement ein. Das Halbleiterbauelement weist eine erste Oberfläche, die mindestens ein erstes Kontaktpad einschließt, und eine zweite Oberfläche, die mindestens ein zweites Kontaktpad einschließt, auf. Das zweite Kontaktpad ist auf dem elektrisch leitenden Substrat montiert. Das erste elektrisch leitende Bauteilelement schließt mindestens einen Bolzenhöcker ein und erstreckt sich zwischen dem elektrisch leitenden Substrat und der ersten Oberfläche der Umverteilungsschicht.

NOVEL THREE DIMENSIONAL INTEGRATED CIRCUIT STACKING METHOD

Provided are a method for forming a semiconductor package having one or more dies on an interposer die, and a semiconductor package. A die bonded to an interposer die can have an edge over a boundary of the interposer die by forming a first redistribution structure on an interposer having a TSV. Also, a second redistribution structure can be formed on an opposite surface to the interposer die from the redistribution structure. The second redistribution structure enables the reconstitution of the bonding structure and fan-out for an external connector of the interposer die. COPYRIGHT KIPO 2016 ...

Semiconductor package and method for manufacturing the same

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die (s) bonded to the interposer die can have edge (s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Semiconductor structure and method of manufacturing thereof

Segregated power and ground design for yield improvement

A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.

Method of fabricating a carrier-less silicon interposer using photo patterned polymer as substrate

A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Semiconductor packaging structure and manufacturing method thereof

A semiconductor structure includes a plurality of devices; a molding surrounding the plurality of devices and including a first surface adjacent to an active component of at least one of the plurality of devices and a second surface opposite to the first surface; and a shielding structure disposed within the molding and between two or more of the plurality of devices, wherein the shielding structure includes a first surface adjacent to the first surface of the molding and a second surface adjacent to the second surface of the molding, and the second surface of the shielding structure includes a recessed portion recessed towards the first surface of the molding.

Semiconductor Device with Bond Pad Extensions Formed on Molded Appendage

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Semiconductor structure and fabrication method thereof

A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Chip on package structure and method

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Halbleitervorrichtung

Die vorliegende Erfindung hat zur Aufgabe, eine Halbleitervorrichtung mit einer erreichbaren verbesserten Bestückungsleistung und Verkleinerung bereitzustellen. Eine Halbleitervorrichtung (1) gemäß der vorliegenden Erfindung umfasst: einen IGBT, der in einem Si-Substrat (13) ausgebildet ist; eine Temperaturerfassungsdiode (2), die im Si-Substrat (13) ausgebildet ist; eine Emitter-Elektrodenanschlussfläche (6) für den IGBT, wobei die Emitter-Elektrodenanschlussfläche auf dem Si-Substrat (13) vorgesehen ist; und eine Kathoden-Emitter-Verbindungsleiterbahn (19), die über dem Si-Substrat (13) vorgesehen ist und eine Kathodenelektroden-Anschlussfläche (3) für die Temperaturerfassungsdiode (2) und die Emitter-Elektrodenanschlussfläche (6) elektrisch verbindet.

Double-sided marking of semiconductor wafers and method of using a double-sided marked semiconductor wafer

By forming the groove caused by the elimination of the stripping of the sawing

캐비티를 갖는 폴리머-기반 반도체 구조체

... 본 발명에 따른 구조체는 디바이스 다이와, 이 디바이스 다이를 그 안에 피포하는 피포 재료를 포함한다. 상기 피포 재료는 상기 디바이스 다이의 상면과 동일 평면 상에 있는 상면과, 피포 재료 내의 캐비티를 갖는다. 캐비티는 피포 재료를 관통한다.

반도체 패키지

... 본 발명의 일 실시예는, 하부 절연층 및 상기 하부 절연층 상에 배치된 하부 재배선층을 포함하는 하부 재배선 구조물; 상기 하부 재배선 구조물 상에 배치되고, 상기 하부 재배선층에 전기적으로 연결된 접속 패드를 포함하는 반도체 칩; 상기 하부 재배선 구조물 상에서 상기 반도체 칩의 주변에 배치되고, 상기 하부 재배선층에 전기적으로 연결된 연결 도체들; 상기 반도체 칩 및 상기 연결 도체들의 적어도 일부를 봉합하는 봉합재; 및 상기 봉합재 상에 배치된 상부 절연층, 및 상기 상부 절연층 상에 배치되고 상기 연결 도체들과 전기적으로 연결된 상부 재배선층들을 포함하는 상부 재배선 구조물을 포함하고, 상기 연결 도체들은 상기 봉합재의 상면보다 돌출되며, 상기 연결 도체들 각각의 상면 및 상기 봉합재의 상기 상면은 상기 하부 재배선 구조물의 상면에 수직한 제1 방향으로 제1 단차를 갖고, 상기 상부 재배선층들은, 상기 제1 방향으로, 상기 연결 도체들과 중첩되지 않는 제1 상부 재배선층 및 상기 연결 도체들과 중첩되는 제2 상부 재배선층을 포함하며, 상기 제1 상부 재배선층의 하면 및 제2 상부 재배선층의 하면은 상기 제1 방향으로 상기 제1 단차와 실질적으로 동일하거나 작은 제2 단차를 갖는 반도체 패키지를 제공한다.

Electronic component package

An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Substrate-free system in package design

Apparatuses and processes are disclosed for a substrate-free system in package that includes a through mold via Embodiments may include providing a circuit trace layer on top of a first side of a carrier, coupling a first set of one or more surface mount components to a first side of the circuit trace layer opposite the carrier, embedding the first set of the one or more surface mount components in a molding compound, exposing a second side of the circuit trace layer opposite the first side of the circuit trace layer, and coupling one or more electrical interconnects to serve as TMVs to the second side of the circuit trace layer. Embodiments may also include exposing the second side of the circuit trace layer by grinding the carrier. Other embodiments may be described and/or claimed.

MICROELECTRONIC PACKAGES HAVING EMBEDDED SIDEWALL SUBSTRATES AND METHODS FOR THE PRODUCING THEREOF

Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Methods of packaging semiconductor devices including placing semiconductor devices into die caves

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Integrated circuit chip using top post-passivation technology and bottom structure technology

반도체 패키지, 이의 제조 방법 및 시스템 인 패키지

... 반도체 패키지, 이의 제조 방법 및 시스템 인 패키지가 개시된다. 본 발명의 실시예에 따른 반도체 패키지는 절연층 및 배선층을 포함하는 배선부, 상기 배선부 상에 실장되고, 상기 배선층과 본딩 패드를 통하여 전기적으로 연결되는 반도체 칩 및 상기 반도체 칩 및 상기 배선부를 커버하며, 상기 배선층과 연결되는 커버부재를 포함한다. 따라서, 커버부재가 반도체 칩을 커버하며 배선층과 연결되어 전자파 간섭현상을 줄이는 것이 가능하며, 반도체 패키지의 동작 간 노이즈를 최소화하고 신호 속도를 향상시킬 수 있다.

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

CHIP USING TRIPLE PAD STRUCTURE AND PACKAGING METHOD THEREOF

According to the present invention, a chip comprises: a core circuit; at least one rewiring layer formed on the core layer; and at least one triple pad connected to a pad of the core circuit through the at least one rewiring layer or at least one via connected to the at least one rewiring layer. The triple pad comprises: a bonding pad for performing bonding; a rewiring pad connected to the at least one rewiring layer; and a test pad configured to perform a wafer level test. The bonding pad, the rewiring pad and the test pad are connected to one another through the at least one rewiring layer, and the test pad is arranged in a core area which overlaps the core circuit. Therefore, the chip can significantly reduce a chip size. COPYRIGHT KIPO 2016 ...

FAN-OUT SEMICONDUCTOR PACKAGE

The present disclosure relates to a fan-out semiconductor package which includes a first connection member including a through hole, a semiconductor chip including an active surface which is disposed in the through hole of the first connection member and on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, a sealing material which seals at least a part of the inactive surface of the semiconductor chip, a second connection member which is disposed on the active surface of the semiconductor chip and includes a rewiring layer electrically connected to the connection pad of the semiconductor chip, a passivation layer disposed on the second connection member, and an under bump metal layer which includes an external connection pad formed on the passivation layer and a plurality of vias connecting the rewiring layer of the second connection member to the external connection pad. The first connection member includes a rewiring layer ...

Wafer level chip scale package having continuous TSV configuration and its fabrication method

Disclosed is a wafer level chip scale package having continuous TSV configuration, primarily comprising a device chip, a carrier chip attached onto the device chip, a transparent plate and a TSV mechanism. A parallel pad combination of metallization interconnection is embedded in the device chip. An offset pad is disposed on the device chip and is connected with the parallel pad combination. A spacing conductive bump is bonded onto the offset pad. A spacing adhesive layer is formed on the device chip and encapsulates the spacing conductive bump. The transparent plate is bonded onto the spacing adhesive layer. The TSV mechanism includes a through hole and a hole metallization layer. The through hole is slightly biased to align to the offset pad so that the device chip and the carrier chip are penetrated through. The hole metallization layer is formed in the through hole to connect with the offset pad. Thereby, the through hole is positioned under the spacing conductive bump in non-center-to-center ...

ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN

A structure including a first semiconductor chip 20 with front and rear surfaces 24, 26 and a cavity 36 in the rear surface. A second semiconductor chip 70 is mounted within the cavity. The first chip 20 may have vias 48 extending from the cavity to the front surface and via conductors 54 within these vias serving to connect the additional microelectronic element 70 to the active elements of the first chip 20. The structure may have a volume comparable to that of the first chip 20 alone and yet provide the functionality of a multi-chip assembly. A composite chip 720 incorporating a body 722 and a layer 702 of semiconductor material mounted on a front surface 724 of the body similarly may have a cavity 736 extending into the body from the rear surface 726 and may have an additional microelectronic element 770 mounted in such cavity 736.

Semiconductor package, semiconductor device and methods of forming the same

Packaging structural member

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Chip using triple pad configuration and packaging method thereof

A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.

Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.

새로운 3차원 집적 회로 적층 방법

... 인터포저 다이 위에 하나 이상의 다이를 구비한 반도체 패키지를 형성하기 위한 방법 및 반도체 패키지가 제공된다. TSV를 가진 인터포저 위에 제1 재분배 구조를 형성함으로써, 인터포저 다이에 본딩된 다이는 인터포저 다이의 경계를 넘는 엣지를 가질 수 있다. 또한, 재분배 구조로부터 인터포저 다이의 반대 표면 상에 제2 재분배 구조가 형성될 수 있다. 제2 재분배 구조는 인터포저 다이의 외부 커넥터를 위해 본딩 구조의 재구성 및 팬-아웃을 가능하게 한다.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies.

Integrated circuit having electromagnetic shielding capability and manufacturing method thereof

Chip package and fabrication method thereof

Microelectronic packages having embedded sidewall substrates and methods for the producing thereof

Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Chip packaging method and package structure

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package ...

Semiconductor structure having a composite barrier layer

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.

CHIP USING TRIPLE PAD CONFIGURATION AND PACKAGING METHOD THEREOF

A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.

Double-sided ID marking of Semiconductor Wafers

A method for marking a semiconductor wafer comprising a front-side surface 12 and a rear-side surface 13, each surface provided with a durable, machine-readable marking 15 (only front side shown); the rear-side surface 13 also provided with a recessed portion bounded by a supporting structure; the method further comprising reading the respective markings 15, retrieving a processing step for the front-side surface 12 and/or the rear-side surface 13, and performing either/or processing step. Also disclosed is a wafer comprising a front-side surface 12 and a rear-side surface 13, each surface provided with a durable, machine-readable marking 15. Also disclosed is a semiconductor wafer comprising a front-side surface 12 and a rear-side surface 13, each surface provided with a durable, machine-readable marking 15; the rear-side surface 11 also provided with a recessed portion 40 bounded by a supporting structure 42.

Chip package and fabrication method thereof

The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Substrate-less package structure

After the utilization of the through hole technology 3 D on the substrate on the wafer chip structure

HIGH DENSITY FILM FOR IC PACKAGE

In the present invention, disclosed is a high density film for an integrated circuit (IC) package. A process comprises: forming a plurality of lower pads in a lower part; forming a plurality of first upper pads in an upper part; manufacturing a redistribution layer according to an IC design rule; forming a plurality of second upper pads in the upper part; and manufacturing an upper redistribution layer as a starting point by using the first upper pads according to a printed circuit board (PCB) design rule. The density of the lower pads is higher than that of the first upper pads, and the density of the first upper pads is higher than that of the second upper pads. COPYRIGHT KIPO 2016 (AA) Process flow for manufacturing a high density film including a step where density of the lower pads(341) is higher than that of a plurality of first upper part pads(343), as a step of manufacturing a lower part redistribution layer(RDL I) in accordance with an IC design role below in a state where a plurality ...

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Semiconductor package

Methods of bonding the strip-shaped under bump metallization structures

A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a plurality of devices; a molding surrounding the plurality of devices and including a first surface adjacent to an active component of at least one of the plurality of devices and a second surface opposite to the first surface; and a shielding structure disposed within the molding and between two or more of the plurality of devices, wherein the shielding structure includes a first surface adjacent to the first surface of the molding and a second surface adjacent to the second surface of the molding, and the second surface of the shielding structure includes a recessed portion recessed towards the first surface of the molding.

Eliminate Sawing-Induced Peeling Through Forming Trenches

A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.

NOVEL THREE DIMENSIONAL INTEGRATED CIRCUITS STACKING APPROACH

PACKAGING STRUCTURAL MEMBER

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

Microelectronic packages having embedded sidewall substrates and methods for the producing thereof

Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same

In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.

FAN-OUT SEMICONDUCTOR PACKAGE

Disclosed is a fan-out semiconductor package comprising: a first connection member having a through-hole; a semiconductor chip arranged in the through-hole of the first connection member, and having an active surface on which a connection pad is arranged and an inactive surface which is arranged on the opposite side of the active surface; an encapsulant for encapsulating at least a part of the inactive surface of the semiconductor chip and the first connection member; a second connection member arranged on the active surface of the semiconductor chip and the first connection member; and a passivation layer arranged on the second connection member. Each of the first and second connection members includes a redistribution layer electrically connected to the connection pad. The second connection member includes an insulation layer on which the redistribution layer of the second connection member is arranged. The passivation layer has a greater elastic modulus than the insulation layer of the ...

Package structure

A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating ...

DUAL-DIE MEMORY PACKAGE

A dual-die memory package includes a package substrate, a first die, a second die, a bonding wire, and a conductive pillar. The first die is disposed on the package substrate and includes a first conductive pad and a first bonding pad. The first conductive pad and the first bonding pad are disposed on a surface of the first die facing away from the package substrate. The second die is disposed on a side of the first die away from the package substrate. The second die includes a second conductive pad disposed on a surface of the second die facing the first die. The first bonding pad is electrically coupled to the package substrate through the bonding wire. The first conductive pad is electrically coupled to the second conductive pad through the conductive pillar.

STACK PACKAGES INCLUDING BRIDGE DIES

A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.

Scheme for connector site spacing and resulting structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

Double-sided marking of semiconductor wafers and method of using a double-sided marked semiconductor wafer

집적 수동 소자 패키지 및 그 형성 방법

... 실시형태의 소자 패키지는 제1 다이, 제2 다이, 및 제1 다이 및 제2 다이의 측벽을 따라 연장되는 몰딩 화합물을 포함한다. 패키지는, 제1 다이 및 제2 다이의 에지를 지나 횡방향으로 연장되는 재분배층(RDL)을 더 포함한다. RDL은, 제1 다이 및 제2 다이에 전기적으로 연결되는 입/출력(I/O) 콘택트를 포함하고, I/O 콘택트는 RDL과 대향하는 몰딩 화합물의 표면에 실질적으로 수직인 소자 패키지의 측벽에서 노출된다.

반도체 패키지 및 이의 제조 방법

... 반도체 패키지 및 이의 제조 방법이 개시된다. 본 발명의 실시예에 따른 반도체 패키지는 절연층 및 배선층을 포함하는 배선부, 상기 배선부 상에 실장되고, 상기 배선층과 본딩 패드를 통하여 전기적으로 연결되는 반도체 칩, 상기 반도체 칩과 이격되어 상기 배선부 상에 배치되며, 상기 배선층과 접촉하는 메탈 프레임 및 상기 반도체 칩 및 상기 메탈 프레임을 커버하며, 상기 메탈 프레임과 접촉하는 커버부재를 포함한다. 따라서, 커버부재가 반도체 칩을 커버하며, 커버부재는 배선부와 접촉하는 메탈 프레임과 접촉하여 전자파 간섭현상을 줄이는 것이 가능하며, 반도체 패키지의 동작 간 노이즈를 최소화하고 신호 속도를 향상시킬 수 있다.

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

Semiconductor package structure

Semiconductor structure and fabrication method thereof

SEMICONDUCTOR STRUCTRURE WITH COMPOSITE BARRIER LAYER UNDER REDISTRIBUTION LAYER AND MANUFACTURING METHOD THEREOF

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.

Semicondcutor package and manufacturing method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one chip, through interlayer vias aside the chip and a composite molding compound encapsulating the chip and the through interlayer vias. The semiconductor package may further include a redistribution layer and conductive elements disposed on the redistribution layer.

Advanced structure for info wafer warpage reduction

A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers.

Chip on package structure and method

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

3D chip-on-wafer-on-substrate structure with via last process

Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

Electronic device package

Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.

BESEITIGEN VON DURCH SÄGEN HERVORGERUFENES ABLÖSEN DURCH AUSBILDEN VON GRÄBEN

Ein Gehäuse umfasst einen Vorrichtungs-Die, ein Formmaterial, das den Vorrichtungs-Die umgibt, wobei eine obere Fläche des Formmaterials im Wesentlichen plan mit einer oberen Fläche des Vorrichtungs-Dies ist, und eine untere dielektrische Schicht über dem Vorrichtungs-Die und dem Formmaterial. Mehrere Umverteilungsleitungen (RDLs) erstrecken sich in die untere dielektrische Schicht und werden mit dem Vorrichtungs-Die elektrisch verbunden. Eine obere Polymerschicht liegt über der unteren dielektrischen Schicht, wobei ein Grabenring die obere Polymerschicht durchdringt. Der Grabenring ist benachbart zu Rändern des Gehäuses. Das Gehäuse umfasst weiter Under-Bump-Metallurgien (UBMs), die sich in die obere Polymerschicht erstrecken.

WRAP-AROUND-SOURCE/DRAIN-VERFAHREN ZUR HERSTELLUNG VON KONTAKTEN FÜR RÜCKSEITENMETALLE

Eine Vorrichtung, die eine Schaltungsstruktur, die eine erste Seite, die eine Einrichtungsschicht enthält, die mehrere Einrichtungen enthält, und eine gegenüberliegende zweite Seite enthält; einen elektrisch leitfähigen Kontakt, der an eine der mehreren Einrichtungen auf der ersten Seite gekoppelt ist; und eine elektrisch leitfähige Zwischenverbindung, die auf der zweiten Seite der Struktur angeordnet und an den leitfähigen Kontakt gekoppelt ist, enthält. Ein Verfahren, das ein Bilden einer Transistoreinrichtung, die einen Kanal zwischen einer Source und einem Drain und eine Gate-Elektrode auf dem Kanal enthält, eine erste Seite der Einrichtung definierend; ein Bilden eines elektrisch leitfähigen Kontakts zu einem von der Source und dem Drain von der ersten Seite; und ein Bilden einer Zwischenverbindung auf einer zweiten Seite der Einrichtung, wobei die Zwischenverbindung an den Kontakt gekoppelt ist, enthält.

Methods of packaging semiconductor devices including placing semiconductor devices into die caves

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Carrier-Less Silicon Interposer Using Photo Patterned Polymer as Substrate

A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC)

A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.

SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

Semiconductor device and semiconductor package

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

GETRENNTES STROM- UND ERDUNGSDESIGN ZUR ERTRAGSVERBESSERUNG

Ein Verfahren umfasst Verkapseln einer Vielzahl von Package-Komponenten in einem Verkapselungsmaterial und Herstellen einer ersten Vielzahl von Umverteilungsschichten über und elektrisches Koppeln mit der Vielzahl von Package-Komponenten. Die erste Vielzahl von Umverteilungsschichten weist eine Vielzahl von Strom-/Erdungspadstapeln auf, wobei jeder der Vielzahl von Strom-/Erdungspadstapeln ein Pad in jeder der ersten Vielzahl von Umverteilungsschichten aufweist. Die Vielzahl von Strom-/Erdungspadstapeln weist eine Vielzahl von Strompadstapeln und eine Vielzahl von Erdungspadstapeln auf. Mindestens eine zweite Umverteilungsschicht ist über der ersten Vielzahl von Umverteilungsschichten gebildet. Die zweite(n) Umverteilungsschicht(en) weist (weisen) Stromleitungen und elektrische Erdungsleitungen auf, die die Vielzahl von Strom-/Erdungspadstapeln elektrisch verbinden.

Making the back side of the winding of the metal of the contact part of the source/drain method

ELECTRONIC DEVICE PACKAGE

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME

Integrated fan-out package

An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.

Package structures

Multi-device packages and related microelectronic devices

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Semiconductor device and method of designing a wiring of a semiconductor device

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

Chip stacked structure

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Method and apparatus of fabricating a pad structure for a semiconductor device

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Apparatus and method of applying a film to a semiconductor wafer and method of processing a semiconductor wafer

Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid

Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid.

On-Chip RF Shields with Backside Redistribution Lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Wafer Level Packaging of Electronic Devices

Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

Microelectronic devices having conductive through via electrodes insulated by gap regions

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Back-side contact formation

In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Bond pad design for improved routing and reduced package stress

A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Wafer level packaging method of encapsulating the bottom and side of a semiconductor chip

A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

UBM Structures for Wafer Level Chip Scale Packaging

A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Semiconductor Package with Integrated Electromagnetic Shielding

There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Interposer substrate manufacturing method and interposer substrate

A method for manufacturing an interposer substrate includes: forming a conductive portion on a first surface of a semiconductor substrate via a first insulating layer, the conductive portion being formed of a first metal; forming a through hole at a second surface side of the semiconductor substrate located on an opposite side to the first surface so as to expose the first insulating layer; forming a second insulating layer on at least an inner wall surface and a bottom surface of the through hole; exposing the conductive portion by removing portions of the first and second insulating layers using a dry etching method that uses an etching gas containing a fluorine gas, the portions of the first and second insulating layers being located on the bottom surface of the through hole; and forming a conductive layer on the second insulating layer and electrically connecting the conductive layer to the conductive portion, wherein when exposing the conductive portion, forming a tapered portion is performed.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Through-Substrate Vias and Methods for Forming the Same

A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Method for producing semiconductor device

A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.

Stacked Integrated Chips and Methods of Fabrication Thereof

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Chip package and method for forming the same

An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Edge connect wafer level stacking

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Integrating through substrate vias from wafer backside layers of integrated circuits

A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

Emi shielding semiconductor element and semiconductor stack structure

A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Microelectronic packages having trench vias and methods for the manufacture thereof

Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Solid-state image pickup element and solid-state image pickup element mounting structure

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Novel three dimensional integrated circuits stacking approach

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Thermally Enhanced Package-on-Package (PoP)

A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

3D Chip-On-Wafer-On-Substrate Structure With Via Last Process

Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate. 1. A package comprising:a first redistribution layer (RDL) disposed on a first semiconductor substrate;a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL;an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate;a first conductive element disposed in the first RDL;a via extending from a top surface of the insulating film, through the first semiconductor substrate to the first conductive element; anda first spacer disposed between the first semiconductor substrate and the via, wherein the first spacer extends through the first semiconductor substrate.2. The package of claim 1 , wherein a first sidewall of the first spacer is aligned with a sidewall of the insulating film claim 1 , and wherein a second sidewall of the first spacer opposite the first sidewall contacts the first semiconductor substrate.3. The package of claim 1 , wherein top surfaces of the first spacer and the first semiconductor substrate are substantially level claim 1 , and wherein bottom surfaces of the first spacer and the first semiconductor substrate are substantially level.4. The package of further comprising a second spacer disposed between the via and the first spacer.5. The package of claim 4 , wherein the second ...

Semiconductor Package System and Method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. 1. A semiconductor device comprising:a semiconductor die with a first sidewall;a first protective layer over the semiconductor die, wherein a second sidewall of the first protective layer is recessed from the first sidewall of the semiconductor die;an opening through the first protective layer;an encapsulant covering the first sidewall and the second sidewall, wherein the encapsulant has a top surface that is planar with the first protective layer; anda conductive material filling the opening and extending over the encapsulant.2. The semiconductor device of claim 1 , further comprising a second protective layer over the conductive material.3. The semiconductor device of claim 2 , further comprising an underbump metallization extending through the second protective layer to make electrical contact with the conductive material.4. The semiconductor device of claim 2 , wherein the second protective layer has a third sidewall aligned with a fourth sidewall of the encapsulant.5. The semiconductor device of claim 1 , further comprising a through via extending through the encapsulant and in electrical connection with the conductive material.6. The semiconductor device of claim 1 , wherein the conductive material is in physical contact with the encapsulant.7. The semiconductor device of claim 6 , wherein the conductive material is copper.8. A semiconductor device comprising:a protective material overlying a first surface of a semiconductor die, the protective material having a second surface facing away from the first surface;an encapsulant encapsulating the ...

UNDER BUMP METALLURGY (UBM) AND METHODS OF FORMING SAME

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die. 1. A device package comprises:a die;fan-out redistribution layers (RDLs) over the die; a conductive pad portion; and', 'a trench encircling the conductive pad portion; and, 'an under bump metallurgy (UBM) over the fan-out RDLs, wherein the UBM comprisesa connector disposed on the conductive pad portion of the UBM, wherein the fan-out RDLs electrically connect the connector and the UBM to the die.2. The device package of claim 1 , wherein the UBM further comprises a retaining wall portion encircling the trench.3. The device package of claim 2 , wherein a width of the retaining wall portion is about 10 μm to about 20 μm.4. The device package of claim 2 , wherein the connector is not disposed on the retaining wall portion of the UBM.5. The device package of claim 1 , wherein a width of the trench is between about 10 μm to about 20 μm.6. The device package of claim 1 , wherein the fan-out RDLs comprise a conductive line claim 1 , wherein the UBM is formed on a top surface of the conductive line claim 1 , and wherein the trench exposes a portion of the conductive line.7. The device package of claim 6 , wherein the fan-out RDLs comprise a polymer layer extending over a top surface of the conductive line.8. The device package of claim 7 , wherein an entirety of the UBM is disposed in an opening in the polymer layer.9. The device package of claim 7 , wherein the polymer layer covers edge portions of the UBM.10. The device package of claim 7 , wherein the polymer layer is at least partially disposed in the trench.11. A device package comprising:a device die;a conductive ...

3DIC Stacking Device and Method of Manufacture

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

Stacked Integrated Circuits with Redistribution Lines

An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad. 1. A method comprising:bonding a first wafer to a second wafer, wherein a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer are bonded between a firs substrate of the first wafer and a second substrate in the second wafer;forming a first opening in the first substrate;etching the first plurality of dielectric layers and the second wafer through the first opening to form a second opening, wherein a first metal pad in the second plurality of dielectric layers is exposed to the second opening;filling a conductive material to form a first conductive plug extending into the first opening and the second opening;forming a first dielectric layer over the first substrate; andforming a redistribution line comprising a portion over the dielectric layer, wherein the redistribution line is electrically coupled to the first conductive plug through a portion in the dielectric layer.2. The method of further comprising claim 1 , after the first opening is formed claim 1 , depositing a second ...

PACKAGING STRUCTURAL MEMBER

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. 1. A method of assembling devices comprising:providing a temporary carrier substrate with first and second surfaces, the first surface is prepared with an adhesive; a package region comprises a die attach region surrounded by a peripheral region, and', 'the through-vias extend from the first to the second major surface of the structural member, wherein the through-vias comprise a conductive material; and, 'mating a structural member having first and second major surfaces on the temporary carrier substrate, the structural member comprises a plurality of die package regions and through-vias disposed in the package regions, wherein'}attaching dies in the die attach regions of the structural member.2. The method of wherein the conductive material of the through-vias comprises top and bottom surfaces which are coplanar with the first and second major surfaces of the structural member.3. The method of wherein:the die attach regions comprise openings extending through the first and second major surfaces of the structural member;attaching dies comprises disposing dies in the openings for temporary attachment to the temporary carrier substrate, wherein gaps exist between the dies and sidewalls of the openings; andthe ...

SEMICONDUCTOR DEVICE

A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper. 1. A semiconductor device comprising:a first wiring disposed on a semiconductor substrate;a first insulating film disposed on the first wiring;a first via disposed in the first insulating film so as to be connected to the first wiring;a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via;a first organic insulating film disposed on the second wiring;a second via disposed in the first organic insulating film so as to be connected to the second wiring;a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; anda second organic insulating film disposed on the first organic insulating film,wherein:a pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, andthe first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper.2. The semiconductor device according ...

Fan-Out Package and Methods of Forming Thereof

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. 1. A package comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip;a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad;a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound;a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; anda second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.2. The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.3. The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.4. The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.5. The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.6. The package ...

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. 1. A method for manufacturing an integrated device , the method comprising:forming a first reconstitution wafer comprising first components;forming a second reconstitution wafer comprising second components;dicing the second reconstitution wafer into second packaged components, the second packaged components comprising the second components;placing the second packaged components on a first main surface of the first reconstitution wafer; anddicing the first reconstitution wafer into integrated devices, each integrated device comprising a first packaged component and a second packaged component.2. The method of claim 1 , further comprising:placing an integrated device on a carrier;bonding the integrated device to the carrier; andencapsulating the integrated device.3. The method of claim 1 , further comprising disposing a first redistribution layer (RDL) on the first main surface of the first reconstitution wafer.4. The method of claim 3 , further comprising claim 3 , before dicing the second reconstitution wafer claim 3 , disposing a second RDL on a first main surface of the second reconstitution wafer claim 3 , wherein placing the second packaged components on the first main surface of the first reconstitution wafer comprises placing the second packaged components with second RDL regions facing ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view. 1. A semiconductor device , including:a first pad;an insulating film covering the first pad;a first opening exposing part of a surface of the first pad from the insulating film;a first polyimide film having a second opening in communication with the first opening;a first interconnection filling the first opening and the second opening, and provided on the first polyimide film;a second polyimide film covering the first interconnection; anda third opening exposing part of the first interconnection from the second polyimide film,wherein the first polyimide film is provided only in a region that is planarly superposed on the first interconnection.2. The semiconductor device according to claim 1 , wherein when an interconnection length direction of the first interconnection is defined as first direction claim 1 , and an interconnection width direction claim 1 , intersecting with the first direction claim 1 , of the first interconnection is defined as second direction claim 1 , width in the second direction of the first polyimide film is equal to width in the second direction of the first interconnection.3. A method of manufacturing a semiconductor device claim 1 , the method comprising:(a) forming an insulating film covering a first pad;(b) forming a first opening in the insulating film, the first opening exposing part of a surface of the first pad;(c) forming a first polyimide film over the insulating film;(d) forming a second opening in the first polyimide film, the ...

INTEGRATED CIRCUIT PACKAGE STACK

Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package. 1. An integrated circuit (IC) package stack , comprising: a first die;', 'a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side;', 'a first set of vias that communicatively couples the contacts on the first side of the first IC package to the first redistribution layer; and', 'a second set of vias that communicatively couples the first redistribution layer to the contacts on the second side of the first IC package, wherein the first set of vias are formed within a substrate of the first IC package and the second set of vias are formed within a molded layer of the first IC package; and, 'a first IC package, a first side of the first IC package to be mounted to a circuit board, the first IC package includes a second die;', 'a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package., 'a second ...

SEMICONDUCTOR STRUCTURE AND A MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member. 2. The semiconductor structure of claim 1 , wherein the first die is bonded with a sidewall of the recess.3. The semiconductor structure of claim 1 , wherein a thickness of the first die is substantially greater than a depth of the recess.4. The semiconductor structure of claim 1 , wherein a portion of the first die is protruded from the recess.5. The semiconductor structure of claim 1 , wherein the first die is at least partially surrounded by the substrate.6. The semiconductor structure of claim 1 , wherein a distance between a sidewall of the first die and a sidewall of the recess is about 5 um to about 30 um.7. The semiconductor structure of claim 1 , wherein a depth of the recess is about 20 um to about 60 um.8. The semiconductor structure of claim 1 , wherein a thickness of the first die is about 30 um to about 70 um.9. The semiconductor structure of claim 1 , further comprising a dielectric material disposed within the recess and surrounding the first die or the second die.10. The semiconductor structure of claim 9 , wherein the dielectric material is disposed between the substrate and the RDL.11. The semiconductor structure of claim 9 , further comprising a via extending from the first bonding member towards the RDL and passing through a ...

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad. 1. An electronic package , comprising: a cavity that passes through the interposer;', 'a through interposer via (TIV); and', 'an interposer pad electrically coupled to the TIV;, 'an interposer, wherein the interposer comprisesa nested component in the cavity, wherein the nested component comprises a component pad; and an intermediate pad; and', 'a bump over the intermediate pad., 'a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect, wherein the first interconnect and the second interconnect each comprise2. The electronic package of claim 1 , further comprising:a polymer layer over and around the interposer and the nested component.3. The electronic package of claim 2 , wherein the intermediate pads are over a surface of the mold layer.4. The electronic package of claim 3 , wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the mold layer claim 3 , and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the mold layer.5. The electronic package of claim 3 , wherein the intermediate pad of the first ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising: a device top surface;', 'a device bottom surface opposite to the device top surface; and', 'a device side surface extending between the device top surface and the device bottom surface;, 'an electronic device comprising a first region that extends from the device top surface in an upward direction; and', 'a second region coupled to the first region, wherein the second region extends from the first region in a lateral direction; and, 'an interconnect directly attached at the device top surface comprising a first portion of the second region is exposed from a first surface of the encapsulant;', 'a second portion of the second region is exposed from a second surface of the encapsulant; and', 'the encapsulant covers a third portion of the second region., 'an encapsulant that covers the device top surface, the device side surface, and a periphery of the first region, wherein2. The semiconductor device of claim 1 , wherein:the interconnect comprises a severed leadframe lead;the lateral direction is substantially parallel to the device top surface; andthe second portion extends to overlap the device side surface so as to extend outside a perimeter of the electronic device.3. The semiconductor device of ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump. 1. A chip package structure , comprising:a substrate having a first surface and a second surface opposite to the first surface;a first chip structure and a second chip structure over the first surface;a protective layer over the first surface and surrounding the first chip structure and the second chip structure, wherein a portion of the protective layer is between the first chip structure and the second chip structure;a first anti-warpage bump over the second surface and extending across the portion of the protective layer; anda conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure, wherein the first anti-warpage bump is wider than the conductive bump, and wherein the first anti-warpage bump and the conductive bump are exposed.2. The chip package structure as claimed in claim 1 , wherein a width of the first anti-warpage bump is greater than a distance between the first chip structure and the second chip structure.3. The chip package structure as claimed in claim 1 , wherein the first anti-warpage bump is thinner than ...

Process Control for Package Formation

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Photonic Integrated Package and Method Forming Same

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die. 1. A method comprising:placing an electronic die and a photonic die over a carrier;encapsulating the electronic die and the photonic die in an encapsulant;planarizing the encapsulant until the electronic die and the photonic die are revealed;forming redistribution lines over the encapsulant, the electronic die and the photonic die, wherein the redistribution lines electrically connect at least the electronic die; andattaching an optical coupler to the photonic die, wherein an optical fiber attached to the optical coupler is configured to optically couple to the photonic die.2. The method of further comprising:removing a sacrificial material of the photonic die to reveal an opening extending from a front surface and an edge of the photonic die into the photonic die, wherein a waveguide in the photonic die is revealed to the opening, and the optical coupler comprises an edge coupler having a portion extending into the opening, and the optical fiber has a portion extending into a groove in the photonic die, with the groove being a part of the opening.3. The method of further comprising claim 2 , before placing the photonic die over the carrier:forming the opening in the photonic die; andfilling the sacrificial material into the opening.4. The method of claim 1 , ...

Cross-Wafer RDLs in Constructed Wafers

A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer. 1. A method of forming a semiconductor device , the method comprising:placing a plurality of package components over a carrier;encapsulating the plurality of package components in an encapsulant;forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant;exposing the light-sensitive dielectric layer using a first lithography mask;developing the light-sensitive dielectric layer to form a plurality of openings, wherein conductive features of the plurality of package components are exposed through the plurality of openings; andforming redistribution lines extending into the openings, wherein one of the redistribution lines has a length greater than about 26 mm, and the redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.2. The method of claim 1 , wherein the first lithography mask is large enough to cover all package components over the carrier.3. The method of claim 1 , wherein the forming the redistribution lines comprises:coating a plating mask;patterning the plating mask using a second lithography mask large enough to cover all package components over the carrier; andplating the ...

Package-on-package structure and method of manufacturing package

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

Method of Fabricating Redistribution Circuit Structure

A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via. 1. A method of fabricating a semiconductor device , the method comprising:forming a conductive via;forming a photosensitive dielectric layer to cover the conductive via;thinning the photosensitive dielectric layer to reveal the conductive via, thinning the photosensitive dielectric layer being performed at least through an exposure and development process; andafter thinning the photosensitive dielectric layer, forming a redistribution wiring on the photosensitive dielectric layer and the conductive via.2. The method as claimed in further comprising:after thinning the photosensitive dielectric layer, partially removing the conductive via such that an upper surface of the conductive via is lower than an upper surface of the photosensitive dielectric layer by a first distance; andafter partially removing the conductive via, partially removing the photosensitive dielectric layer to reduce the first distance.3. The method as claimed in claim 2 , wherein partially removing the photosensitive dielectric layer is performed at least in part by an etch process.4. The method as claimed in claim 1 , wherein thinning the photosensitive dielectric layer to reveal the conductive via comprises:performing the exposure and development process to remove a first portion of the photosensitive dielectric layer;after performing the exposure and development process, curing remaining portions of the photosensitive dielectric layer; andafter curing the remaining portions of the photosensitive dielectric layer, removing a second portion of the ...

BONDING SUPPORT STRUCTURE (AND RELATED PROCESS) FOR WAFER STACKING

In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC. 1. A method for bonding semiconductor wafers , the method comprising:forming a first integrated circuit (IC) over a central region of a first semiconductor wafer;forming a first ring-shaped bonding support structure over a ring-shaped peripheral region of the first semiconductor wafer, wherein the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer; andbonding a second semiconductor wafer to the first semiconductor wafer, such that a second IC disposed on the second semiconductor wafer is electrically coupled to the first IC.2. The method of claim 1 , wherein forming the first IC comprises:forming an etch stop layer over an interconnect structure, wherein the interconnect structure is disposed over the first semiconductor wafer; andforming a dielectric layer over the interconnect structure and over the first ring-shaped bonding support structure, wherein the first ring-shaped bonding support structure is formed after the etch stop layer.3. The method of claim 2 , wherein forming the first IC further comprises:performing a first planarization process on the dielectric layer to form a redistribution dielectric layer.4. The method of claim 3 , wherein the redistribution dielectric layer contacts both the etch stop layer and the first ring-shaped bonding support structure.5. The ...

Semiconductor devices having cutouts in an encapsulation material and associated production methods

A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

Fan-out Package with Controllable Standoff

A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure. 1. A method comprising: forming a rigid dielectric layer; and', 'removing portions of the rigid dielectric layer;, 'forming an interposer comprisingbonding a package component to an interconnect structure;bonding the interposer to the interconnect structure, wherein a spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer comprises a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof; andperforming a die-saw on the interconnect structure.2. The method of further comprising forming the interconnect structure on a carrier claim 1 , with the package component bonded to the interconnect structure when the interconnect structure is located on the carrier.3. The method of further comprising:forming the metal feature, with the rigid dielectric layer being formed to embed the metal feature therein; andperforming a planarization process to level a surface of the metal feature with a surface of the rigid dielectric layer.4. The method of claim 1 , wherein in the removing the portions of the rigid dielectric layer claim 1 , an entirety of the rigid dielectric layer is removed.5. The method of further comprising forming a solder region on the metal feature and as a part of the interposer claim 4 , wherein the solder region contacts the package component after the interposer is bonded to ...

CHIP PACKAGE AND METHOD OF FABRICATING THE SAME

A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. 1. A method of fabricating a chip package , the method comprising:attaching an integrated circuit component on a carrier through a first thermal paste, wherein thermal conductivity of the first thermal paste ranges from about 10 W/mK to about 250 W/mK;forming an insulating encapsulant to encapsulate the integrated circuit component attached on the carrier; andforming a redistribution circuit structure on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.2. The method as claimed in further comprising:forming a plurality of conductive through vias on the carrier before forming the insulating encapsulant such that the conductive through vias are encapsulated by the insulating encapsulant,wherein the conductive through vias are electrically connected to the integrated circuit component through the redistribution circuit structure after forming the redistribution circuit structure.3. The method as claimed in further comprising:after forming the redistribution circuit structure, de-bonding the first thermal paste and the ...

Semiconductor Device and Method of Manufacture

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate. 1. A method of forming a semiconductor device , the method comprising:arranging a plurality of interconnect structures on a carrier substrate to form a reconstructed wafer;encapsulating the plurality of interconnect structures in a first encapsulant;electrically coupling at least one semiconductor component of each of a plurality of semiconductor dies to one or more of the plurality of interconnect structures;encasing the plurality of semiconductor dies and portions of the first encapsulant in a second encapsulant to form a wafer level package;removing the carrier substrate from the plurality of interconnect structures; andbonding a plurality of external contacts to first sides of the plurality of interconnect structures.2. The method of claim 1 , further comprising:exposing a plurality of first contact areas on second sides of each of the plurality of interconnect structures, the second sides of the plurality of interconnect structures being opposite the first sides of the plurality of interconnect structures.3. The method of claim 2 , wherein the electrically coupling the at least one semiconductor component of each of the plurality of semiconductor dies to one or more of the plurality of interconnect structures includes placing at least one semiconductor die of the plurality of semiconductor ...

Multi-Chip Structure and Method of Forming Same

A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip. 1. A device comprising:a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction;a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction; anda plurality of bumps between the first chip and the second chip.2. The device of claim 1 , further comprising:a redistribution layer over the molding compound layer;a dielectric layer over the redistribution layer;an under bump metallization structure over the dielectric layer; anda solder ball over the under bump metallization structure.3. The device of claim 2 , wherein:the first chip comprises a plurality of logic circuits, wherein the first chip comprise a plurality of through vias connected to the redistribution layer; andthe second chip comprises a plurality of memory dies stacked together, wherein the second chip is electrically connected to the first chip through the plurality of bumps.4. The device of claim 2 , wherein:the redistribution layer extends beyond at least one outmost edge of the first chip.5. The device of claim 2 , wherein:the second chip and the redistribution layer are separated by the molding compound layer.6. The device of claim 1 , wherein:a top surface of the second chip is exposed outside the molding compound layer.7. The device of claim 1 , wherein:a first sidewall of the first chip is exposed outside the molding compound layer;a second sidewall of the first chip is covered by the molding compound layer and underneath the second chip;a first sidewall of the second ...

Semiconductor Interconnect Structure and Method

A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line. 1. A semiconductor device comprising:a first interconnect structure over first substrate;a first bonding layer over the first interconnect structure;a plurality of first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch; anda plurality of second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the plurality of second bonding pads comprising a plurality of pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line.2. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the same layer as the second bonding pads.3. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the interconnect structure and connected to the second bonding pads of each respective pair by vias disposed in the bonding layer.4. The semiconductor device of claim 1 , comprising:a second bonding layer over a second substrate; anda plurality of third bonding pads disposed in the second bonding layer, comprising a plurality of pairs of adjacent third bonding pads, ...

Method of packaging chip and chip package structure

A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress than the second substrate; applying an adhesive layer on the second substrate; bonding the chip on the adhesive layer; and forming an encapsulation layer that covers at least the chip.

OFFSET TEST PADS FOR WLCSP FINAL TEST

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. 1. A device configured for wafer level chip scale packaging (WLCSP) , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first redistribution layer (RDL) path that connects the first pad to the test pad; andd) a second RDL path that connects the test pad to a solder ball.2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.4. The device of claim 1 , wherein the first and second RDL paths are in different layers.5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad claim 1 , and leaves a portion of the test pad exposed.6. The device of claim 1 , wherein the device further comprises:a) a plurality of the first pads; andb) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.7. A device configured for WLCSP claim 1 , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first RDL path that connects the first pad to a solder ball; andd) a second RDL path that connects the test pad to the solder ball.8. The device of claim ...

PHOTONIC SEMICONDUCTOR DEVICE AND METHOD

A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove. 1. A method comprising:forming a plurality of openings through a photonic substrate, wherein the photonic substrate comprises a groove configured to receive an optical fiber, wherein the groove is formed in a top surface of the photonic substrate;forming a plurality of through-vias over and electrically connected to a first redistribution structure;placing the photonic substrate over the first redistribution structure, wherein the plurality of through-vias extend through the plurality of openings in the photonic substrate;forming a sacrificial material in the groove;forming a molding compound within the plurality of openings in the photonic substrate, wherein the molding compound surrounds the plurality of through-vias;forming a second redistribution structure over the top surface of the photonic substrate, wherein the second redistribution structure is electrically connected to the plurality of through-vias and the photonic substrate;removing a portion of the second redistribution structure to expose the sacrificial material;removing the sacrificial material to expose the groove; andmounting an optical fiber within the groove.2. The method of claim 1 , further comprising performing a planarizing process on the molding compound to expose the ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

MANUFACTURING METHOD OF PACKAGE ON PACKAGE STRUCTURE

A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion. 1. A manufacturing method of a package on package structure , comprising:providing a first package on a tape carrier, wherein the first package comprises an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier; andmounting a second package on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps,wherein each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.2. The manufacturing method of the package on package structure as claimed in claim 1 , wherein a maximum diameter of the tip portion is substantially smaller than a maximum diameter of the base portion.3. The ...

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps. 1. A surface mounting semiconductor component , comprising:a semiconductor device including a plurality of die pads;a circuit board including a plurality of contact pads;a plurality of first solder bumps configured to bond the semiconductor device and the circuit board, wherein each of the plurality of first solder bumps connects at least two die pads with a corresponding contact pad; anda plurality of second solder bumps, wherein each of the plurality of second solder bumps connects a die pad with a corresponding contact pad.2. The component of claim 1 , wherein the contact surface between each of the plurality of first solder bumps and the semiconductor device is at least 30% larger than the contact surface between the same first solder bumps and the circuit board.3. The component of claim 2 , wherein the contact surface between each of the plurality of first solder sumps and the semiconductor device is two times greater than the contact surface between the same first solder bumps and the circuit board.4. The component of claim 1 , wherein the semiconductor device further includes a trace claim 1 , wherein the trace connects at least two die pads.5. The component of claim 1 , wherein the wetting angle of each of the plurality of second solder bumps is smaller than ...

Package Systems Having Interposers

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. 1. A method comprising:providing a first substrate;forming a first interconnect layer on the first substrate;attaching the first interconnect layer to a second substrate;removing the first substrate;forming electrical connections on the first interconnect layer;forming a molding compound over the first interconnect layer, the molding compound encircling each of the electrical connections;forming a second interconnect layer on the molding compound; andremoving the second substrate.2. The method of claim 1 , wherein the forming the electrical connections on the first interconnect layer comprises:forming a patterned layer over the first interconnect layer, the patterned layer having openings;forming a conductive material in the openings; andremoving the patterned layer.3. The method of claim 2 , further comprising forming a conductive seed layer over the first interconnect layer prior to the forming the patterned layer claim 2 , and further comprising removing exposed portions of the conductive seed layer after the removing the patterned layer.4. The method of claim 1 , further comprising attaching a semiconductor substrate between adjacent ones of the electrical connections prior to the forming the molding compound.5. The method of claim 4 , wherein the molding compound extends over the semiconductor substrate.6. The method of claim 1 , further comprising forming external electrical connectors on the first interconnect layer prior to attaching to ...

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

FABRICATING PROCESS FOR REDISTRIBUTION LAYER

A metal sputtering or metal evaporating process is adopted in an initial fabricating step to fabricate a plurality of metal pads without having substantial dimensional change during fabrication. So that a bottom side of the plurality of metal pads is adapted to electrically couple to a nanochip in a later process. In addition, at least a first fan out circuitry is then built up on a top side of the plurality of metal pads. The bottom side of the redistribution layer is made adapted to electrically couple to a nanochip (Chip side), and the top side of the redistribution layer is made adapted to electrically couple to a printed circuit board side (PCB side) which has a plurality of top metal pads and is made adapted to electrically couple to a mother board in a later process. 1. A fabricating process for a redistribution layer , comprising:preparing a temporary carrier with an adhesive layer formed on a top surface of the temporary carrier;applying photoresist on a top surface of the adhesive layer;patterning the photoresist to form a plurality of grooves with undercut at a bottom of each groove, and to reveal a top surface of the adhesive layer at the bottom of each groove;sputtering or evaporating to form metal on a top surface of the exposed adhesive layer at the bottom of each groove; andstripping the photoresist to leave a plurality of first bottom metal pads on the top surface of the adhesive layer.2. A fabricating process for a redistribution layer as claimed in claim 1 , further comprising:a first redistribution circuitry formed on a top surface of the plurality of first bottom metal pads; anda second redistribution circuitry formed on a top surface of the first redistribution circuitry.3. A fabricating process for a redistribution layer as claimed in claim 2 , further comprising:removing the temporary carrier and the adhesive layer.4. A fabricating process for a redistribution layer as claimed in claim 3 , further comprising:mounting a chip on a bottom ...

Method for Producing an Integrated Circuit Device with Enhanced Mechanical Properties

Devices and methods for producing an integrated circuit device, comprising a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, are disclosed. The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within the dielectric layers. In an exemplary device, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In some implementations, a mask layer is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, the mask layer covering portions of the stack area and exposing other portions of the area. Then, a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in areas uncovered by the mask layer. 1. A method for producing an integrated circuit device comprising a front-end-of-line portion and a back-end-of-line portion , the BEOL portion comprising a metallization stack comprising metallization layers , each metallization layer comprising a layer of dielectric material with metal lines and/or metal vias embedded in the dielectric layer , the stack having a stack surface area , the method comprising the steps of:building the metallization stack by a sequence of processing steps wherein subsequent metallization layers are formed;during or after the sequence, producing a mask layer on the partially or fully completed stack, the mask layer covering one or more portions of the stack surface area and leaving one or more portions of the stack surface area exposed; andperforming a treatment that changes the elastic modulus of the dielectric material of one or more of the metallization layers on which the mask layer is produced, only in the exposed portion(s) of the stack surface area.2. The method according to ...

THROUGH-BODY VIA FORMATION TECHNIQUES

Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV. In some instances, the disclosed techniques may be used to address poor step coverage, low run rate, and/or high cost issues associated with existing physical vapor deposition (PVD)-based far-back-end-of-line (FBEOL) processes. 1. An integrated circuit comprising:a semiconductor layer; and an electrically conductive interconnect; and', 'a polymer-based barrier layer disposed between the interconnect and the semiconductor layer., 'a through-body via (TBV) formed within the semiconductor layer, the TBV comprising2. The integrated circuit of claim 1 , wherein the semiconductor layer comprises at least one of silicon (Si) and/or silicon germanium (SiGe) claim 1 , and wherein the interconnect comprises at least one of copper (Cu) claim 1 , nickel (Ni) claim 1 , cobalt (Co) claim 1 , and/or a combination of any one or more thereof3. The integrated circuit of further comprising an electrically conductive seed layer disposed between the interconnect and the polymer-based barrier layer.4. The integrated circuit of claim 3 , wherein the seed layer comprises at least one of copper (Cu) claim 3 , silver (Ag) claim 3 , and/or a combination of any one or more thereof.5. The ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME

The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed. 1. A semiconductor package structure , comprising:an insulating substrate in the absence of metal members, comprising a front side and a back side;a first insulating layer disposed on the front side of the substrate; anda die disposed on the first insulating layer;wherein the die comprises a first die pad and a second die pad, the first die pad is coupled to a first portion of a metal layer, the second die pad is coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer are spaced apart by a second insulating layer.2. The semiconductor package structure of claim 1 , further comprising a protection layer disposed on the back side of the substrate.3. The semiconductor package structure of claim 1 , wherein the metal layer is selected from at least one of palladium claim 1 , aluminum claim 1 , chromium claim 1 , nickel claim 1 , titanium claim 1 , gold claim 1 , copper and platinum.4. The semiconductor package structure of claim 1 , wherein the first insulating layer and the second insulating layer are photosensitive dry films comprising constituents selected from at least one of polyimide claim 1 , epoxy resin claim 1 , benzocyclobutene resin and polymer.5. The semiconductor package structure of claim 1 , wherein at least a portion of the ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME

The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second. portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed. 1. A semiconductor package structure , comprising:a substrate;a first insulating layer disposed on the substrate;a first die disposed on the first insulating layer; anda second die disposed on the first insulating layer; andwherein the first die comprises a first die pad and a second die pad, the second die comprises a third die pad and a fourth die pad, the first die pad is coupled to a first portion of a metal layer, the second die pad is coupled to the third die pad via a second portion of the metal layer, the fourth die pad is coupled to a third portion of the metal layer, and the first portion, the second portion and the third portion of the metal layer are spaced apart by a second insulating layer.2. The semiconductor package structure of claim 1 , wherein at least a portion of each of the first portion and the third portion of the metal layer above two terminals of the substrate is exposed.3. The semiconductor package structure of claim 2 , wherein the semiconductor package structure comprises a first metal terminal disposed on a terminal of the substrate and coupled to the first portion of the metal layer claim 2 , and the semiconductor package structure comprises a second metal terminal disposed on another terminal of the substrate and coupled to the third portion of the metal layer.4. The semiconductor ...

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability. 1. A package structure , comprising:an electronic element having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;an encapsulant encapsulating the electronic element and having a first surface exposing the active surface of the electronic element and a second surface opposite to the first surface;a plurality of conductive elements penetrating the first and second surfaces of the encapsulant, wherein the conductive elements are metal balls; anda redistribution layer formed on the first surface of the encapsulant and the active surface of the electronic element and electrically connected to the electrode pads of the electronic element and the conductive elements.2. The structure of claim 1 , wherein the metal balls are solder balls.3. The structure of claim 1 , wherein the first surface of the encapsulant is flush with the active surface of the electronic element.4. The structure of claim 1 , wherein the redistribution layer has: a dielectric layer ...