LOW STRESS MOISTURE RESISTANT STRUCTURE OF SEMICONDUCTOR DEVICE

一種半導體元件之低應力抗濕氣結構包括一低應力抗濕氣層。其中一半導體元件係形成於一半導體晶圓之上。半導體元件包括至少一焊墊。低應力抗濕氣層係塗佈於半導體晶圓以及半導體元件之上，使得焊墊之焊墊頂中央表面露出。其中低應力抗濕氣層包括一材料係包含交聯之氟聚合物。在低應力抗濕氣層被塗佈之前於半導體晶圓之上所量測到之一塗佈前應力以及在低應力抗濕氣層被塗佈並固化之後於半導體晶圓之上所量測到之一固化後應力之差係為一應力差，其中應力差係大於或等於-5×10 7 dyne/cm 2 且小於或等於5×10 7 dyne/cm 2 。

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

SEMICONDUCTOR PACKAGE

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Halbleiteranordnung und Verfahren zur Herstelllung von Halbleiteranordnungen

Die vorliegende Anmeldung betrifft eine Halbleiteranordnung umfassend einen Halbleiterchip, einen den Halbleiterchip überdeckenden ausgeformten Körper, wobei der ausgeformte Körper ein Array ausgeformter Strukturelemente umfasst, und erste Lotelemente in Eingriff mit den ausgeformten Strukturelementen.

HYBRIDIZATION TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEAL UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : ▪ à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; ▪ à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; ▪ à reporter les premier et second composants (12, 14) l'un sur l'autre ; et ▪ à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en œuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre.

3di solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

Semiconductor device and method for bonding semiconductor structures

Anschlussflächen mit Seitenwandabstandshaltern und Verfahren zum Herstellen von Anschlussflächen mit Seitenwandabstandshaltern

Es werden eine Chip-Anschlussfläche (215) und ein Verfahren zum Herstellen einer Chip-Anschlussfläche (215) offenbart. Eine Ausführungsform der vorliegenden Erfindung enthält das Bilden mehrerer Anschlussflächen (215) auf einem Werkstück, wobei jede Anschlussfläche (215) untere Seitenwände und obere Seitenwände besitzt, und das Verringern einer unteren Breite jeder Anschlussfläche (215), so dass eine obere Breite jeder (215) Anschlussfläche größer ist als die untere Breite. Das Verfahren enthält ferner das Bilden eines Photoresists über den mehreren Anschlussflächen (215) und das Entfernen von Abschnitten des Photoresists, um dadurch längs der unteren Seitenwände Seitenwandabstandshalter (217) zu bilden. A die pad (215) and a method of making a die pad (215) are disclosed. One embodiment of the present invention includes forming a plurality of pads (215) on a workpiece, each pad (215) having lower sidewalls and upper sidewalls, and decreasing a lower width of each pad (215) so that an upper width of each (215 ) The connection area is larger than the lower width. The method further includes forming a photoresist over the plurality of pads (215) and removing portions of the photoresist to thereby form sidewall spacers (217) along the lower sidewalls.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER

A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes. 1. A semiconductor device manufacturing method comprising the steps of:(a) preparing a semiconductor wafer having a principal plane, a circumferential edge surrounding the principal plane, a plurality of first chips formed over the principal plane and including semiconductor elements, and a plurality of second chips surrounding the first chips and contiguous with the circumferential edge, each of the first chips having a plurality of bonding pads formed therein;(b) forming an insulating film over the principal plane;(c) forming a plurality of first openings in the insulating film of the first chips to expose the bonding pads at the bottom of the first openings;(d) forming a first protective film over the principal plane;(e) forming a plurality of second openings in the first protective film of the first and the second chips in such a manner that the bonding pads are exposed at the bottom of the first openings coinciding with the second openings in planar view of the first chips and that the insulating film is exposed at ...

Halbleiterbauelement, Leistungshalbleiterbauelement und Verfahren zum Verarbeiten eines Halbleiterbauelements

Gemäß verschiedenen Ausführungsformen kann ein Halbleiterbauelement (100) Folgendes enthalten: einen Schichtenstapel, der auf einer Oberfläche des Halbleiterbauelements (100) ausgebildet ist, wobei der Schichtenstapel aufweist: eine Metallisierungsschicht (106), die ein erstes Metall oder eine erste Metalllegierung enthält; eine Schutzschicht (108), die die Metallisierungsschicht (106) abdeckt, wobei die Schutzschicht (108) ein zweites Metall oder eine zweite Metalllegierung enthält, das weniger edel als das erste Metall oder die erste Metalllegierung ist.

HYBRIDIZATION FACE-TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEALING UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : * à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; * à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; * à reporter les premier et second composants (12, 14) l'un sur l'autre ; et * à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en oeuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre. This method of manufacturing a microelectronic device comprising a first component (12) hybridized to a second component (14) by means of electrical interconnections, consists of: * producing first and second components (12, 14), the second component (14) being transparent to ultraviolet radiation at least to the right of the locations provided for the interconnects; * forming interconnection elements (22) comprising copper oxide on the second component (14) at the locations provided for the interconnections; * to transfer the first and second components (12, 14) one on the other; and * applying ultraviolet radiation through the second component (14) on the elements comprising copper oxide so as to carry out ultraviolet annealing transforming the copper oxide into copper.

Bond Pad Having Ruthenium Covering Passivation Sidewall

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. 1. A device , comprising:a semiconductor substrate;a metal layer formed above the semiconductor substrate;a bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; anda ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.2. The device of claim 1 , wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area.3. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.4. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.5. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer interfacing the ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a semiconductor device having a bump electrode on a pad electrode for effectively using the lower region of a pad electrode having the bump and preventing a local large force from being applied to a semiconductor substrate located at the lower side of the bump during mounting and a method of manufacturing the same. SOLUTION: A first layer metal wiring 5 that is formed on a semiconductor substrate and a pad electrode 7 that is formed on the first layer metal wiring 5 through an interlayer dielectric and connected with the first layer metal wiring 5 through via holes 10 that are formed on the interlayer dielectric are provided. Moreover, a protective film 8 that is formed on a pad electrode 7 and provided with an opening that exposes the pad electrode 7 and island-shaped protective films 9 in the opening and an Au bump 11 that is formed on the pad electrode 7 and connected with the pad electrode 7 through the opening of the protective film 8 are provided.

SEMICONDUCTOR DEVICES AND METHODS FOR PRODUCING THE SAME

Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

CHIP-SCALE PACKAGE

A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

HALBLEITERVORRICHTUNG, DIE EIN BONDPAD UND EINEN BONDDRAHT ODER -CLIP ENTHÄLT

Eine Halbleitervorrichtung (500) enthält ein Bondpad (300), das einen Basisbereich (310) mit einer Basisschicht (317) umfasst. Ein Bonddraht oder -clip (410) ist an ein Bondgebiet (305) einer Hauptoberfläche (301) des Bondpads (300) gebondet. Eine ergänzende Struktur (350) ist neben dem Bondgebiet (305) in direktem Kontakt mit dem Basisbereich (310). Eine spezifische Wärmekapazität der ergänzenden Struktur (350) ist höher als eine spezifische Wärmekapazität der Basisschicht (317).

Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Method of forming a semiconductor device comprising top conductive pads

A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.

Semiconductor device and methods of manufacturing semiconductor devices

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

POWER SEMICONDUCTOR DEVICE LOAD TERMINAL

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms. 1. A method of processing a power semiconductor device , the method comprising:providing a semiconductor structure having a surface; and forming a conductive layer that is in contact with the semiconductor structure at said surface;', 'depositing at least one support block on top of the conductive layer; and', 'mounting a bonding block on top of the at least one support block;, 'creating a first load terminal structure on top of the surface, wherein creating the first load terminal structure on top of the surface compriseswherein the at least one support block exhibits a hardness greater than the hardness of each of the conductive layer and the bonding block, andthe bonding block is configured to be contacted by an end of at least one bond wire and to receive at least a part of a load current from at least one of the at least one bond wire and the conductive layer.2. The method of claim 1 , wherein forming the conductive layer includes forming a diffusion barrier at the surface of the semiconductor structure and forming a metallization on top of ...

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Flip chip

Halbleiter-Chip und Halbleitergehäuse, welches diesen umfasst

Offenbarte Ausführungsformen umfassen einen Halbleiter-Chip umfassend ein Halbleitersubstrat aufweisend eine obere Fläche mit einem darin angeordneten oberen Verbindungs-Pad und eine Schutzisolierschicht, die eine Öffnung darin aufweist, wobei die Schutzisolierschicht mindestens einen Abschnitt des oberen Verbindungs-Pads auf dem Halbleitersubstrat nicht bedeckt. Die Schutzisolierschicht kann umfassen: eine untere Schutzisolierschicht, eine Deckisolierschicht aufweisend einen Seitendeckteil, der mindestens einen Abschnitt einer Seitenfläche der unteren Schutzisolierschicht bedeckt, und einen oberen Deckteil, der von dem Seitendeckteil beabstandet angeordnet ist, sodass er mindestens einen Abschnitt einer oberen Fläche der unteren Schutzisolierschicht bedeckt. Die Schutzisolierschicht kann ferner eine obere Schutzisolierschicht auf dem oberen Deckteil umfassen.

Semiconductor package

Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same

Semiconductor copper metallization structure and related methods

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

SEMICONDUCTOR BACKMETAL AND OVER PAD METALLIZATION STRUCTURES AND RELATED METHODS

Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer. 1. A semiconductor device comprising:a silicon substrate comprising a first side and a second side, the second side comprising an active area; and a back metallization on the first side of the substrate;', 'an electroplated metal layer on the back metallization; and', 'an evaporated gold metal layer on the electroplated metal layer., 'a metal stack comprising2. The semiconductor device of claim 1 , wherein the active area comprises one of an insulated-gate bipolar transistor (IGBT) claim 1 , fast recovery diode (FRD) claim 1 , or metal oxide semiconductor field-effect transistor (MOSFET).3. The semiconductor device of claim 1 , wherein the stack comprises aluminum/copper claim 1 , nickel/gold claim 1 , and one of gold or gold/chromium.4. The semiconductor device of claim 1 , wherein the silicon substrate comprises a thickness of approximately 100 microns.5. The semiconductor device of claim 1 , wherein the back metallization comprises aluminum/copper.6. The semiconductor device of claim 1 , wherein the electroplated metal layer comprises nickel/gold.7. The semiconductor device of claim 1 , wherein the evaporated metal layer comprises gold.8. A method of forming a plurality of semiconductor devices claim 1 , the method comprising:providing a wafer comprising a first side and a second side;forming a plurality of devices on the second side of the semiconductor wafer;reducing a thickness of the wafer;forming a back metallization on the first side of the wafer;plating a plated metal layer on the back metallization;evaporating a metal layer on the plated metal layer; ...

Semiconductor device and semiconductor package

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

Semiconductor packages and manufacturing methods for the same

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Collars for under-bump metal structures and associated systems and methods

Solder limiting layer for integrated circuit die copper bumps

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Semiconductor device and method of fabricating the same

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Semiconductor device with edge-protecting spacers over bonding pad

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

반도체 구조물 및 이의 제조 방법

... 본 개시는 반도체 구조물을 제공한다. 반도체 구조물은, 반도성 기판, 포스트 패시베이션 상호접속부(PPI) 및 폴리머 층을 포함한다. PPI는 반도성 기판 위에 배치되고 전도체를 수용하기 위한 랜딩 영역을 포함한다. 폴리머 층은 PPI 상에 있으며, 전도체는 폴리머 층에 의해 실질적으로 둘러싸이는 타원 부분을 포함하도록 전환점에서 네킹이 이루어진다.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.

LASTANSCHLUSS EINES LEISTUNGSHALBLEITERBAUELEMENTS, LEISTUNGSHALBLEITERMODUL DAMIT UND HERSTELLUNGSVERFAHREN DAFÜR

Leistungshalbleiterbauelement (1), das Folgendes umfasst:- eine erste Lastanschlussstruktur (11) und eine zweite Lastanschlussstruktur (12), die getrennt von der ersten Lastanschlussstruktur (11) angeordnet ist;- eine Halbleiterstruktur (10), die elektrisch mit sowohl der ersten Lastanschlussstruktur (11) als auch der zweiten Lastanschlussstruktur (12) gekoppelt ist und die dazu konfiguriert ist, einen Laststrom zu führen, wobei die erste Lastanschlussstruktur (11) Folgendes umfasst:- eine leitfähige Schicht (111), die sich in Kontakt mit der Halbleiterstruktur (10) befindet;- einen Bonding-Block (112), der dazu konfiguriert ist, von einem Ende (31) wenigstens eines Bonddrahtes (3) kontaktiert zu werden und wenigstens einen Teil des Laststroms von dem wenigstens einen Bonddraht (3) und/oder der leitfähigen Schicht (111) zu empfangen;- einen Verstärkungsblock (113), der eine Härte aufweist, die größer als sowohl die Härte der leitfähigen Schicht (111) als auch des Bonding-Blocks (112) ist, wobei der Bonding-Block (112) mittels des Verstärkungsblocks (113) auf der leitfähigen Schicht (111) montiert ist; wobei- in der leitfähigen Schicht (111) und/oder in dem Verstärkungsblock (113) Stickstoffatome eingebracht sind, wobei:- sowohl der Bonding-Block (112) als auch die leitfähige Schicht (111) Kupfer umfassen;- eine Dicke der leitfähigen Schicht (111) und/oder die Dicke des Verstärkungsblocks (113) in einer Richtung parallel zur Richtung des Laststroms kleiner ist/sind als ein Zehntel von der Dicke des Bonding-Blocks (112) in dieser Richtung. A power semiconductor component (1) comprising: - a first load connection structure (11) and a second load connection structure (12) which is arranged separately from the first load connection structure (11); - a semiconductor structure (10) which is electrically connected to both the first load connection structure (11) and the second load connection structure (12) is coupled and which is configured to carry a load current, wherein ...

언더-범프 금속 구조체용 칼라 및 관련 시스템 및 방법

... 본 기술은 다이-다이 및/또는 패키지-패키지 간의 인터커넥트 및 관련 시스템을 위한 언더-범프 금속(UBM) 구조체용 칼라의 제조에 관한 것이다. 반도체 다이는 반도체 고체 상태 구성요소를 가진 반도체 재료와, 반도체 재료를 통해 적어도 부분적으로 연장되는 인터커넥트를 포함한다. 언더-범프 금속(UBM) 구조체는 반도체 재료 위에 형성되고 대응하는 인터커넥트에 전기적으로 결합된다. 칼라는 UBM 구조체의 측면의 적어도 일부를 둘러싸고, 솔더 재료는 UBM 구조체의 상부면 위에 배치된다.

Used in the wafer bonding the sacrificial aligned welding hole

Semiconductor element and manufacturing method thereof

Package substrates and methods for fabricating the same

A package substrate and a method of fabricating the same are provided, the method includes providing a substrate body having a first surface and a second surface opposite thereto, a plurality of first electric connection pads formed on the first surface; and disposing a metal plate on the plurality of first electric connection pads, then patterning the metal plate so as to define a metal column corresponding to each first electric connection pad. According to the present invention, drawbacks of raw edges and unequal heights of the metal columns can be obviated.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses. 19.-. (canceled)10. A semiconductor device , comprising:a first layer having a marginal region;metallizations having peripheral portions facing the marginal region of said first layer without contacting the marginal region.11. The semiconductor device of claim 10 , wherein said metallizations include:a metallization body, andan outer surface coating on said body, wherein said marginal region faces said peripheral portions without a contact interface with both said metallization body and said outer surface coating.12. The semiconductor device of claim 11 , further comprising a barrier layer underlying said metallization body and adjoining said outer surface coating claim 11 , the barrier layer and output surface coating together completely surround said metallization body.13. The semiconductor device of claim 11 , wherein said first layer includes a passivation layer and a barrier layer on the passivation layer.14. The semiconductor device of claim 13 , wherein said barrier layer extends under said metallization body.15. The semiconductor device of claim 13 , wherein said barrier layer extends on said passivation layer only at said marginal region.16. The semiconductor device of claim 13 , wherein:said passivation layer include a dielectric passivation layer, and/orsaid barrier layer includes titanium tungsten.17. The ...

CHIP PACKAGE AND CHIP THEREOF

A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Semiconductor device having voids between top metal layers of metal interconnects

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Wafer bonding process and structure

Chip package and chip thereof

Semiconductor device and manufacturing method

SEMICONDUCTOR DEVICE, A POWER SEMICONDUCTOR DEVICE, AND A METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE

According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

METHOD OF FORMING A SEMICONDUCTOR DEVICE COMPRISING TOP CONDUCTIVE PADS

A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A method comprising:forming an interconnect structure on a semiconductor die by plating a conductive material onto a surface of the semiconductor die and at least partially over a conductive contact of the semiconductor die so that the interconnect structure is electrically coupled to the conductive contact;forming a containment layer on at least a first portion of a top surface of the interconnect structure; anddisposing a solder material on a second portion of the top surface of the interconnect structure, wherein the second portion of the top surface of the interconnect structure is at least partially laterally offset from the conductive contact of the semiconductor die, and wherein the containment layer is configured to inhibit wicking of the solder material from the second portion to the first portion of the top surface of the interconnect structure.2. The method of wherein forming the interconnect structure includes—plating a first conductive material onto the conductive contact and an insulating material at the surface of the semiconductor die; andplating a second conductive material onto the first conductive material.3. ...

SOLDER BUMP CONFINEMENT SYSTEM FOR AN INTEGRATED CIRCUIT PACKAGE

A solder bump confinement system is provided including providing a substrate, patterning a contact material on the substrate, depositing an inner passivation layer over the contact material and the substrate, forming an under bump material defining layer over the contact material by sputtering, and forming a system interconnect over the contact material and on the under bump material defining layer.

INTERLOCKED REDISTRIBUTION LAYER INTERFACE FOR FLIP-CHIP INTEGRATED CIRCUITS

This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation.

Wafer Bonding Process and Structure

A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method. 1. A semiconductor device comprising:a first substrate having a first dielectric layer thereon;a first passivation layer overlying the first dielectric layer, the first passivation layer having a first recess;a first barrier layer along sidewalls of the first recess; anda first external contact pad in the first recess, the first barrier layer being interposed between the first external contact pad and the first passivation layer.2. The semiconductor device of claim 1 , wherein the first passivation layer comprises a first passivation sublayer comprising undoped silicon glass (USG) claim 1 , a second passivation sublayer comprising silicon nitride (SiN) claim 1 , a third passivation sublayer comprising USG claim 1 , and a fourth passivation sublayer comprising silicon oxynitride (SiON).3. The semiconductor device of claim 1 , wherein the first barrier layer comprises a first barrier sublayer comprising tantalum nitride (TaN) and a second barrier sublayer comprising cobalt (Co) claim 1 , nickel (Ni) claim 1 , or iron (Fe).4. The semiconductor device of claim 1 , wherein the first barrier layer extends along a bottom of the first recess.5. The semiconductor device of claim 1 , wherein the first external contact pad comprises voids of size less than about 500 Å.6. The semiconductor device of claim 1 , further comprising:a second substrate having a second dielectric layer thereon;a second passivation layer overlying the second dielectric layer, the second passivation layer ...

Semiconductor device and method of manufacturing same

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Semiconductor device with spacer over bonding pad

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Verfahren zum Herstellen einer Halbleitervorrichtung

Verfahren zum Herstellen einer Halbleitervorrichtung (200), wobei das Verfahren Folgendes aufweist:Bilden mehrerer Anschlussflächenstrukturen (215, 265, 320) auf einem Werkstück, wobei jede Anschlussflächenstruktur (215, 265, 320) untere Seitenwände (326) und obere Seitenwände (327) besitzt und die unteren Seitenwände (326) in direktem Kontakt mit der Oberfläche des Werkstücks stehen;Verringern einer unteren Breite jeder Anschlussflächenstruktur (215, 265, 320), so dass eine obere Breite jeder Anschlussflächenstruktur (215, 265, 320) größer ist als die untere Breite derart, dass ein Überhang gebildet wird;Bilden eines Photoresists auf den mehreren Anschlussflächenstrukturen (215, 265, 320);Entfernen von Abschnitten des Photoresists mit Ausnahme des Bereichs unterhalb des Überhangs, um dadurch längs der unteren Seitenwände (326) Seitenwandabstandshalter (217, 267, 332) zu bilden; undAufbringen eines Einkapselungsmaterials (240, 290, 340) auf die Anschlussflächenstrukturen (215, 265, 320) ...

SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE RESISTANT TO PLASMA DAMAGE AND METHOD FOR FORMING THE SAME

Interconnect structures for preventing solder bridging, and associated systems and methods

本文中揭示其上形成有互連結構之半導體晶粒及相關系統及方法。在一項實施例中，一互連結構包含電耦合至一半導體晶粒之一導電接觸件的一導電材料。該導電材料包含與該導電接觸件垂直對準之一第一部分、及橫向延伸遠離該導電接觸件之一第二部分。一焊錫材料安置於該互連結構之該第二部分上使得該焊錫材料至少部分橫向偏離該半導體晶粒之該導電接觸件。在一些實施例中，一互連結構可進一步包含在一回熔程序期間預防該焊錫材料之芯吸或其他非所要移動的一圍阻層。

Sacrificial alignment ring and self-soldering vias for wafer bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad ...

METHOD OF FORMING A SEMICONDUCTOR DEVICE

Sacrificial alignment ring and self-soldering vias for wafer bonding

一種將一第一基材接合至一第二基材之方法，其中該第一基材包括在該第一基材之一頂部表面上之第一電氣接觸件，且其中該第二基材包括在該第二基材之一底部表面上之第二電氣接觸件。該方法包括在該第一基材之該頂部表面上形成聚醯亞胺之一塊體，其中聚醯亞胺之該塊體具有一圓化上隅角，且將該第一基材之該頂部表面及該第二基材之該底部表面朝向彼此垂直移動，直到該等第一電氣接觸件毗連該等第二電氣接觸件，其中該第二基材在該移動期間與該聚醯亞胺之該圓化上隅角接觸，造成該第一基材及該第二基材相對於彼此橫向移動。

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Semiconductor device with spacer over bonding pad

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

Kontakthöckerkissenumfassung, Kontakthöckerverbinder, elektrisches Bauteil, elektrische Vorrichtung und Verfahren zum Herstellen

Es ist eine Kontakthöckerkissenumfassung bereitgestellt, die eine verbesserte Zuverlässigkeit einer Kontakthöckerverbindung bereitstellt. Die Kontakthöckerkissenumfassung umfasst ein Elektrodenkissen, eine UBM und eine erste Abschirmung. Die erste Abschirmung deckt wenigstens einen ersten Umfangsbereich des Elektrodenkissens ab. Die erste Abschirmung ist bereitgestellt und ist dazu ausgelegt, den ersten Umfangsbereich von einem schädlichen Einfluss der Umgebung abzuschirmen.

CHIP PACKAGE AND CHIP THEREOF

DIMENSIONALLY DECOUPLED BALL LIMITING METALURGY

A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.

CHIP-SCALE PACKAGE

Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Verfahren zur Herstellung von Halbleitervorrichtungen und entsprechende Vorrichtung

In einer Ausführungsform weist ein Verfahren zum Herstellen von Halbleitervorrichtungen, die Metallisierungen (36, 38, 40) mit peripheren Abschnitten aufweisen, wobei mindestens eine unterliegende Schicht (20, 24) Randbereiche aufweist, die sich den peripheren Abschnitten zugewandt erstrecken, auf: – Bereitstellen einer Opferschicht (26) zum Bedecken der Randbereiche der unterliegenden Schicht (20, 24), – Bereitstellen der Metallisierungen (36, 38, 40), während die Randbereiche der unterliegenden Schicht (20, 24) von der Opferschicht (26) bedeckt sind, und – Entfernen der Opferschicht (26), so dass die Randbereiche der unterliegenden Schicht (20, 24) sich den peripheren Abschnitten ohne eine Kontaktgrenzfläche dazwischen zugewandt erstrecken, wodurch thermomechanische Belastungen vermieden werden.

Integrated circuit chip and integrated circuit wafer with guard ring

A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

LASTANSCHLUSS EINES LEISTUNGSHALBLEITERBAUELEMENTS

Leistungshalbleiterbauelement (1), das Folgendes umfasst: eine erste Lastanschlussstruktur (11) und eine zweite Lastanschlussstruktur (12), die getrennt von der ersten Lastanschlussstruktur (11) angeordnet ist; eine Halbleiterstruktur (10), die elektrisch mit sowohl der ersten Lastanschlussstruktur (11) als auch der zweiten Lastanschlussstruktur (12) gekoppelt ist und die dazu konfiguriert ist, einen Laststrom zu führen, wobei die erste Lastanschlussstruktur (11) Folgendes umfasst: eine leitfähige Schicht (111), die sich in Kontakt mit der Halbleiterstruktur (10) befindet; einen Bonding-Block (112), der dazu konfiguriert ist, von einem Ende (31) eines wenigstens einen Bonddrahtes (3) kontaktiert zu werden und wenigstens einen Teil des Laststroms von dem wenigstens einen Bonddraht (3) und/oder der leitfähigen Schicht (111) zu empfangen; einen Verstärkungsblock (113), der eine Härte aufweist, die größer als sowohl die Härte der leitfähigen Schicht (111) als auch des Bonding-Blocks (112) ist ...

With sacrificial anode semiconductor structure and its forming method

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE RESISTANT TO PLASMA DAMAGE AND METHOD FOR FORMING THE SAME

... 반도체 디바이스들을 본딩하기 위한 연결 구조물 및 이의 형성 방법이 제공된다. 본딩 구조물은 alpad 구조물(즉, 두꺼운 알루미늄 함유 연결 패드), 및 적어도 금속전층(pre-metal layer) 및 장벽층을 포함하는 알루미늄 함유 연결 패드 밑의 서브구조물을 포함한다. 금속전층은 고밀도 물질층이고 장벽층보다 큰 밀도를 포함하고 낮은 표면 조도 막이다. 고밀도 전금속층은 플라즈마 손상이 밑에 놓여 있는 유전체를 충전하지 못하게 하거나 아래의 반도체 디바이스를 파괴하지 못하게 한다.

Sacrificial alignment ring and self-soldering vias for wafer bonding

一種將一第一基材接合至一第二基材之方法，其中該第一基材包括在該第一基材之一頂部表面上之第一電氣接觸件，且其中該第二基材包括在該第二基材之一底部表面上之第二電氣接觸件。該方法包括在該第一基材之該頂部表面上形成聚醯亞胺之一塊體，其中聚醯亞胺之該塊體具有一圓化上隅角，且將該第一基材之該頂部表面及該第二基材之該底部表面朝向彼此垂直移動，直到該等第一電氣接觸件毗連該等第二電氣接觸件，其中該第二基材在該移動期間與該聚醯亞胺之該圓化上隅角接觸，造成該第一基材及該第二基材相對於彼此橫向移動。

Semiconductor device, a power semiconductor device, and a method for processing a semiconductor device

According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

Power Semiconductor Device Load Terminal

本发明涉及功率半导体器件负载端子。根据本发明的功率半导体器件包括：第一负载端子结构和与所述第一负载端子结构分开布置的第二负载端子结构；以及半导体结构，其电耦接到第一负载端子结构和第二负载端子结构中的每一个，并且被配置成承载负载电流，其中，第一负载端子结构包括：与所述半导体结构接触的导电层；接合块，其被配置成由至少接合线的端部接触，并且接收来自至少一条接合线和导电层中的至少一个的负载电流的至少一部分；支承块，其硬度大于导电层和接合块中的每一个的硬度，其中，接合块经由支承块安装在导电层上；以及设置在导电层和接合块中的至少一个内的区域，所述区域具有氮原子。

BONDED ASSEMBLY CONTAINING A DIELECTRIC BONDING PATTERN DEFINITION LAYER AND METHODS OF FORMING THE SAME

A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads. 1. A bonded assembly , comprising:a first semiconductor die comprising a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices;a second semiconductor die comprising a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices; anda dielectric bonding pattern definition layer located between the first semiconductor die and the second semiconductor die and including bonding pattern definition openings therethrough,wherein each of the second bonding pads comprises a respective second bonding-side surface having a second-bonding-surface center region that is bonded to a respective one of the first bonding pads through a respective one of the bonding pattern definition openings in the bonding pattern definition layer, and having a second-bonding-surface peripheral region that laterally surrounds the second-bonding-surface center region and contacts a surface of the dielectric bonding pattern definition layer.2. The bonded assembly of claim 1 , ...

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements. 1. A method , comprising:providing a semiconductor chip;applying mold material over at least a portion of the semiconductor chip to mold a molded body;generating at least one molded structure element on the molded body; andapplying solder over the molded structure element.2. The method according to claim 1 , wherein the molded structure element is generated during the molding of the molded body.3. The method according to claim 1 , wherein the of molded structure element is generated after the molding of the molded body.4. The method according to claim 1 , wherein the generating act generates a plurality of molded structure elements on the molded body claim 1 , and the applying act applies solder over each of the plurality of molded structure elements.5. The method according to claim 4 , further comprising:placing the semiconductor chip on a carrier, the carrier including at least one recess; andfilling the at least one recess with mold material to form the at least one molded structure element.6. The method according to claim 4 , wherein the applying act provides a molded body having a surface coplanar with a surface of the semiconductor chip.7. The method according to claim 6 , wherein the surface of the semiconductor includes at least one connection element.8. A method claim 6 , comprising:providing a plurality of semiconductor chips;applying mold material over the plurality of semiconductor chips to mold a molded workpiece;generating an array of molded structure elements on the molded workpiece; andapplying solder elements over the molded structure elements.9. The method according to claim 8 , wherein the array of molded structure elements is generated during the molding of the molded workpiece ...

Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same

A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Bump stress mitigation layer for integrated circuits

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Semiconductor device manufacturing method and semiconductor wafer

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A semiconductor die , comprising:a substrate having a center portion and an outer edge portion;an insulating material over a surface of the substrate;an electrically conductive contact at the surface of the substrate;an interconnect structure electrically coupled to the conductive contact, wherein the interconnect structure includes a top surface having a first portion and a second portion, wherein the first portion is vertically aligned with the conductive contact, and wherein the second portion extends (a) laterally away from the first portion in a direction away from the center portion and toward the outer edge portion of the substrate and (b) over at least a portion of the insulating material; anda solder material disposed at least partially on the second portion of the top surface.2. The semiconductor die of wherein the conductive contact is exposed at an opening in the insulating material.3. The semiconductor die of claim 1 , further comprising a containment layer over substantially all of the first portion of the top surface of the interconnect structure.4. The semiconductor die of wherein the containment layer is ...

Final passivation for wafer level warpage and ULK stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

Dimensionally decoupled ball limiting metalurgy

A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.

SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD

CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

웨이퍼 본딩 공정 및 구조물

... 반도체 디바이스 및 그 제조 방법이 개시된다. 일실시예에서 하나 이상의 패시베이션층이 제1 기판 상부에 형성된다. 리세스가 패시베이션층 내에 형성되고, 하나 이상의 도전성 패드가 리세스 내에 형성된다. 하나 이상의 배리어층이 패시베이션층과 도전성 패드 사이에 형성된다. 제1 기판의 도전성 패드들이 제2 기판의 도전성 패드들과 정렬되어 직접적인 본딩 방법을 이용하여 본딩된다.

Reduced stress under bump metallization structure

An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer fills the vias and forms a metallization pad that is suitable for supporting a solder bump. Preferably the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad. Each metallization pad is electrically connected to the contact pad through a plurality of the vias. The described under bump structures can be formed at the wafer level.

DIFFUSION BARRIER COLLAR FOR INTERCONNECTS

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.

FLIP-CHIP HYBRIDISATION OF TWO MICROELECTRONIC COMPONENTS USING A UV ANNEAL

This process for fabricating a microelectronic device comprising a first component (12) hybridised with a second component (14) by means of electrical interconnects consists in: producing first and second components (12, 14), the second component (14) being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; forming interconnecting elements (22) comprising copper oxide on the second component (14) in the locations provided for the interconnects; placing the first and second components (12, 14) one on the other; and applying ultraviolet radiation, through the second component (14), to the elements comprising copper oxide so as to implement an ultraviolet anneal converting the copper oxide into copper.

Power semiconductor device load terminal

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

Semiconductor device having a metallic oxide or metallic hydroxide barrier layer

A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween. 1. A semiconductor device , comprisinga first polyimide film;a wiring formed over the first polyimide film;a conductor pattern formed over the first polyimide film;a second polyimide film that covers the wiring and the conductor pattern; andan opening portion that exposes a portion of the wiring in the second polyimide film,wherein, in plan view, the conductor pattern is comprised of a closed pattern surrounding the wiring, while having a space therebetween.2. The semiconductor device according to claim 1 ,wherein the wiring and the conductor pattern are placed each other separately with a predetermined distance.3. The semiconductor device according to claim 1 ,wherein the wiring comprises:a barrier conductor film;a first conductor film formed over the barrier conductor film; anda second conductor film formed over the first conductor film.4. The semiconductor device according to claim 3 ,wherein the second conductor film is formed over the top surface and the side surface of the wiring.5. The semiconductor device according to claim 4 ,wherein the first conductor film is comprised of a copper film, andwherein the second conductor film is comprised of a titanium film and a palladium film formed over the titanium film.6. The semiconductor device according to claim 5 ,wherein a copper wire is coupled to the second conductor film exposed from the opening portion.7. The semiconductor device according to claim 1 ,wherein the conductor ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

In a semiconductor package in which a semiconductor substrate is mounted, thermal resistance of the semiconductor substrate is reduced. The semiconductor package includes a semiconductor substrate, an insulating layer, a metal layer, an interposer substrate, a mounting substrate, a signal transmission solder ball, and a solder member. A pad is provided on one surface of the semiconductor substrate. A different surface of the semiconductor substrate is covered with the insulating layer. The metal layer covers the insulating layer. A wire to be connected to the pad is formed on the interposer substrate. The signal transmission solder ball is jointed to the wire and the mounting substrate, and transmits a predetermined electrical signal. The solder member is jointed to the metal layer and the mounting substrate. 1. A semiconductor package comprising:a semiconductor substrate having one surface on which a pad is provided;an insulating layer configured to cover a different surface of the semiconductor substrate;a metal layer configured to cover the insulating layer;an interposer substrate on which a wire to be connected to the pad is formed;a signal transmission solder ball that is to be jointed to the wire and a predetermined mounting substrate, and configured to transmit a predetermined electrical signal; anda solder member to be jointed to the metal layer and the mounting substrate.2. The semiconductor package according to claim 1 ,wherein the solder member includes a plurality of heat release solder balls.3. The semiconductor package according to claim 1 ,wherein a shape of the solder member is a plate shape.4. The semiconductor package according to claim 1 ,wherein an opening is formed on the different surface of the semiconductor substrate,the insulating layer covers the opening, andthe metal layer is buried in the opening.5. The semiconductor package according to claim 1 ,wherein material of the insulating layer is ceramic.6. The semiconductor package according to ...

SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same are provided. The semiconductor chip includes an integrated circuit on a substrate, a pad electrically connected to the integrated circuit, a lower insulating structure having a contact hole exposing the pad, and a conductive pattern including a contact portion filling the contact hole, a conductive line portion provided on the lower insulating structure to extend in a specific direction, and a bonding pad portion. The contact portion has a first thickness in a direction substantially perpendicular to a top surface of the substrate and a second thickness in another direction substantially parallel to the top surface of the substrate, the first thickness is greater than the second thickness, and the lower insulating structure includes a plurality of air gaps formed therein. 1. A semiconductor chip , comprising:an integrated circuit on a substrate;a pad electrically connected to the integrated circuit;a lower insulating structure having a contact hole exposing the pad; anda conductive pattern including a contact portion filling the contact hole, a conductive line portion on the lower insulating structure and extending in a specific direction, and a bonding pad portion, wherein,the contact portion has a first thickness in a direction substantially perpendicular to a top surface of the substrate and a second thickness in another direction substantially parallel to the top surface of the substrate,the first thickness is greater than the second thickness, andthe lower insulating structure includes a plurality of air gaps.2. The semiconductor chip of claim 1 , whereinthe lower insulating structure comprises a plurality of lower insulating layers stacked on the substrate.3. The semiconductor chip of claim 2 , whereinthe air gaps are provided in the uppermost layer of the lower insulating layers.4. The semiconductor chip of claim 2 , whereinthe lower insulating structure ...

METHOD OF FORMING A SEMICONDUCTOR DEVICE COMPRISING TOP CONDUCTIVE PADS

A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate comprising semiconductor device elements;patterning a top conductive pad and an anti-reflective coating over the substrate, the anti-reflective coating disposed on the top conductive pad;forming at least one passivation film over the substrate and the anti-reflective coating; andetching the at least one passivation film and the anti-reflective coating to form a recess therein so as to expose the top conductive pad.2. The method of claim 1 , wherein the semiconductor device elements include transistors formed on a semiconductor wafer claim 1 , and multilayered interconnect structures comprising vias embedded inside one or more interlayer dielectric layers.3. The method of claim 1 , wherein the patterning the top conductive pad and the anti-reflective coating comprises:forming a conductive layer for the top conductive pad and an anti-reflective layer over the substrate;patterning a first photoresist on the anti-reflective layer; andetching the conductive layer and the anti-reflective layer so as to form the top conductive pad and the anti-reflective coating.4. The method of claim 1 , wherein the anti-reflective coating comprises silicon oxynitride.5. The method of claim 1 , wherein the at least one passivation film comprises a first passivation film claim 1 , and a second passivation film disposed over the first passivation film.6. The method of claim 5 , wherein the ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor. 1. A method for manufacturing a semiconductor structure , comprising:receiving a semiconductive substrate with a post passivation interconnect (PPI) including an oval landing area;forming a first conductor on the oval landing area;forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor;polishing the polymer layer and the first conductor in order to form a planarized surface; andforming a second conductor on the polished first conductor.2. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises exposing a top surface of the first conductor.3. The method of claim 2 , further comprising planarizing the top surface of the first conductor.4. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises applying a diamond disk on the polymer layer and the first conductor.5. The method of claim 1 , wherein receiving the semiconductive substrate comprises chucking the semiconductive substrate on a stage.6. The method of claim 1 , further comprising measuring a thickness of the polymer layer or the first conductor after polishing the polymer layer and the first conductor.7. A method for manufacturing a semiconductor structure claim 1 , comprising:receiving a semiconductive substrate with a metal pad thereon;depositing a layer on the metal pad and above the semiconductive substrate;removing a portion of the layer, thereby forming an oval area; ...

Final passivation for wafer level warpage and ulk stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;a first copper layer coupled directly over and to the pad;a second copper layer coupled over the first copper layer; anda metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers claim 1 , the metal coating applied through one of electroless plating or electrolytic plating.4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel claim 3 , palladium claim 3 , and gold (Ni/Pd/Au); ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface;an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate;a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed;a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; anda metal film disposed on the second surface exposed from between the passivation film and the copper film, whereinthe metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.2. The semiconductor device according to claim 1 , wherein the passivation film is a polyimide film.3. The semiconductor device according to claim 1 , wherein the metal film is an electroless nickel plating film.4. The semiconductor ...

Molded semiconductor package with high voltage isolation

A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A breakdown voltage of the electrically insulative material is greater than a breakdown voltage of the mold compound.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. (canceled)2. The assembly of claim 8 , wherein the solder cup and UBM form an interconnect that electrically connects the first substrate and the second substrate.3. The assembly of claim 2 , wherein the first substrate further comprises a first semiconductor device and the second substrate further comprises a second semiconductor device.4. The assembly of claim 3 , wherein the second end of the barrier engages the first surface of the first semiconductor device and supports the second semiconductor device.5. (canceled)6. The assembly of claim 8 , wherein the second end of the barrier surrounds the UBM.7. (canceled)8. A semiconductor device assembly comprising:a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A method for making a semiconductor package , the method comprising:providing a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;applying a passivation layer over at least a portion of the first side of the die;applying and patterning one of a polyimide (PI) layer and a polybenzoxazole layer (PBO) over the passivation layer;applying a seed layer to the pad;patterning a first photoresist layer over the seed layer;electroplating a first copper layer directly over and to the seed layer, the first copper layer having a thickness of between 1 microns and 20 microns;patterning a second photoresist layer over the first copper layer;electroplating a second copper layer over the first copper layer, the second copper layer having a thickness of between 5 microns and 40 microns;removing the first photoresist layer;removing the second photoresist layer;stripping the seed layer;wherein a width of the first copper layer is wider that a width of the second copper layer; andwherein the second ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion. 1. A method of fabricating a semiconductor package , the method comprising:preparing a semiconductor substrate including a chip region in which first pads are disposed and a scribe lane region in which second pads are disposed, wherein the scribe lane region surrounds the chip region;forming a dielectric layer on the semiconductor substrate so as to reveal the first and second pads;forming first redistribution layer patterns connected to the first pads and second redistribution layer patterns connected to the second pads on the dielectric layer, wherein the first redistribution layer patterns extend to provide bonding pads and the second redistribution layer patterns extend to provide edge pad portions located on the scribe lane region;forming a polymer pattern covering the first and second redistribution layer patterns, wherein the polymer pattern is formed so as to reveal the bonding pad portions and a boundary region including a portion of the dielectric layer on the scribe lane region and portions of the edge pad portions;setting a dicing line extending to surround the chip region in the ...

Flip-Chip Hybridisation Of Two Microelectronic Components Using A UV Anneal

A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

POWER SEMICONDUCTOR DEVICE LOAD TERMINAL

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms. 1. A power semiconductor device , comprising:a first load terminal structure;a second load terminal structure arranged separately from the first load terminal structure; anda semiconductor structure electrically coupled to each of the first load terminal structure and the second load terminal structure and configured to carry a load current, a conductive layer in contact with the semiconductor structure;', 'a bonding block configured to be contacted by an end of at least one bond wire and to receive at least a part of the load current from at least one of the at least one bond wire and the conductive layer;', 'a support block having a hardness greater than the hardness of each of the conductive layer and the bonding block, wherein the bonding block is mounted on the conductive layer via the support block; and', 'a zone that is arranged within at least one of the conductive layer and the bonding block, the zone exhibiting nitrogen atoms., 'wherein the first load terminal structure comprises2. The power semiconductor device of claim 1 , wherein the ...

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

LARGE SCALE INTEGRATED CIRCUIT CHIP AND LARGE SCALE INTEGRATED CIRCUIT WAFER

A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring. 1. A large scale integrated circuit chip comprising:a semiconductor substrate;a semiconductor circuit formed above the semiconductor substrate and having a vertically multilayered wiring structure;a metal guard ring formed above the semiconductor substrate and surrounding the semiconductor circuit; anda plurality of external connection terminals connecting to a predetermined wiring of the multilayered wiring structure of the semiconductor circuit and exposed on a surface of the large scale integrated circuit chip,wherein a predetermined external connection terminal among the plurality of external connection terminals conducts to the predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring, andwherein the conductive piece is a piece of a test lead-out wiring and is a wiring having a cut surface that is exposed by dicing.2. The large scale integrated circuit chip according to claim 1 , wherein the external connection terminals are made of a noble ...

LOW STRESS MOISTURE RESISTANT STRUCTURE OF SEMICONDUCTOR DEVICE

A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to −5×10dyne/cmand less than or equal to 5×10dyne/cm. 1. A low stress moisture resistant structure of semiconductor device ,wherein a semiconductor device is formed on a semiconductor wafer,wherein said semiconductor wafer has a wafer outer surface,wherein said semiconductor device comprises at least one pad,wherein said semiconductor device has a device outer surface,wherein said device outer surface includes a pad top outer surface of each of said at least one pad and an outside pad top device outer surface,wherein said pad top outer surface of each of said at least one pad includes a pad top center surface and a pad top peripheral surface, 'a low stress moisture resistant layer coated on said wafer outer surface, said outside pad top device outer surface, and said pad top peripheral surface of said pad top outer surface of each of said at least one pad so that said pad top center surface of said pad top outer surface of each of said at least one pad is exposed,', 'wherein said low stress moisture resistant structure compriseswherein said low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer,wherein a before-coated stress ...

Sacrificial Alignment Ring And Self-Soldering Vias For Wafer Bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. 1. A method of fabricating a semiconductor device , comprising:providing a substrate, the substrate comprising a non-device region and a device region;forming a dielectric layer on the non-device region and the device region;forming a first metal interconnect in the dielectric layer of the non-device region;forming a buffer layer on the dielectric layer of the device region, wherein the buffer layer comprises a metal, metal nitride, or a combination thereof;forming a conductive layer on the dielectric layer; andpatterning the conductive layer to form a dummy bonding pad, a bonding pad, and a redistribution layer, wherein the dummy bonding pad is on the non-device region and is electrically connected to the first metal interconnect, the bonding pad is on the buffer layer of the device region, and the redistribution layer connects the dummy bonding pad and the bonding pad.2. The method of claim 1 , wherein a material of the buffer layer comprises tungsten claim 1 , tantalum claim 1 , tantalum/tantalum nitride/tantalum claim 1 , or a combination thereof.3. The method of claim 1 , wherein a material of the bonding pad comprises aluminum claim 1 , copper claim 1 , or ...

SEMICONDUCTOR PACKAGE

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3. 1. A semiconductor package , comprising:a semiconductor die having a metal pad, a first passivation layer contacting a first side of the metal pad, and a second passivation layer contacting the first side of the metal pad;a substrate having at least a first conductive region and a second conductive region;a first conductive bump structure disposed on the first conductive region, the first conductive region being electrically connected to the semiconductor die via the first conductive bump structure, wherein the first conductive bump structure has a first area; anda second conductive bump structure disposed on the second conductive region, the second conductive region being electrically connected to the semiconductor die via the second conductive bump structure, wherein the second conductive bump structure has an second area that is larger than the first area.2. The semiconductor package of claim 1 , wherein the first passivation layer comprises a material selected from the group consisting of oxide claim 1 , nitride and oxynitride.3. The semiconductor package of claim 1 , wherein the second passivation layer comprises a polymer.4. The semiconductor package of claim 3 , wherein the polymer comprises polyimide.5. The semiconductor package of claim 1 , wherein the first conductive bump structure contacts the second passivation layer.6. The semiconductor package of claim 1 , further comprising an under bump metallurgy layer contacting the first side of the metal pad claim 1 , the second passivation ...

SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE RESISTANT TO PLASMA DAMAGE AND METNOD FOR FORMING SAME

A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices. 1. A method for forming a semiconductor device , said method comprising:forming a semiconductor device with at least one metal layer including a top metal layer;forming a dielectric material over said top metal layer;depositing a first material layer using a deposition process including a first power, process gases and further deposition parameters;depositing a barrier layer having a lower density than said first material, over said first material layer using a further deposition process using said process gases and said further deposition parameters and a higher power than said first power; anddepositing an aluminum-containing connective layer over said barrier layer.2. The method as in claim 1 , further comprising forming an opening through said dielectric material prior to depositing said first material layer and wherein at least said aluminum containing connective layer is coupled to said top metal layer through a conductive structure within said opening and wherein said deposition process includes a higher pressure than said further deposition process.3. The method as in claim 1 , wherein said step of depositing said first material layer includes depositing a first material having a thickness of about 25-100 angstroms and a surface roughness less than about 5 nm and said step of depositing said barrier layer includes depositing said first material ...

PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME

A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated.

Semiconductor Structure With Sacrificial Anode and Method for Forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9 a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11 a on the pad electrode 9 a ; a base metal film UM formed on the base insulating film 11 ; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11 , and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure

A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal. 1. A semiconductor device comprising:a semiconductor die that comprises a conductive structure;a metal structure electrically connected to the conductive structure and containing a first metal; andan auxiliary layer stack sandwiched between the conductive structure and the metal structure and comprising an adhesion layer containing a second metal and a metal diffusion barrier layer between the adhesion layer and the conductive structure, wherein the adhesion layer contains the first metal and a second metal.2. The semiconductor device of claim 1 , further comprising a dielectric passivation layer between the metal structure and the conductive structure claim 1 , wherein the metal structure is electrically connected to the conductive structure through an opening in the dielectric passivation layer.3. The semiconductor device of claim 1 , wherein the semiconductor die comprises a semiconductor portion comprising a doped region forming the conductive structure.4. The semiconductor device of claim 1 , wherein the semiconductor die comprises a semiconductor portion and a wiring line electrically connected to a doped region formed in the semiconductor portion claim 1 , the wiring line forming the conductive structure.5. The semiconductor device of claim 1 , wherein the auxiliary layer stack comprises an auxiliary barrier layer between the metal structure and the adhesion layer.6. The semiconductor device of claim 1 , wherein the metal ...

SHEET MOLDING PROCESS FOR WAFER LEVEL PACKAGING

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate. 1. A device comprising:a substrate;electrical interconnect circuitry in the substrate;redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry;a conductive bump electrically connected to the RDL circuitry, the conductive bump forming a direct interface with the RDL circuitry through a flux; anda molding material over the substrate wherein the molding material is a backside coating film.2. The device of claim 1 , further comprising:patterned passivation material on portions of the RDL circuitry and portions of the substrate between the molding material and the substrate.3. The device of claim 2 , wherein the molding material is a planarized molding material.4. The device of claim 3 , wherein the molding material includes first holes therethrough claim 3 , the passivation material includes second holes therethrough claim 3 , the first holes and the second holes are at least partially aligned claim 3 , and the conductive bump is situated in the aligned first and second holes claim 3 , in direct contact with the RDL circuitry claim 3 , and does not include an under bump metallization (UBM).5. The device of claim 4 , wherein the first holes are laser ablated leaving burn marks on the molding material on an exposed surface of the molding material and abutting the conductive bump.6. The device of claim 1 , wherein the RDL circuitry includes one or more pads formed thereon claim 1 , the one or more pads including copper or aluminum claim ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer. 2. The semiconductor structure of claim 1 , wherein the first silicon oxide layer is in contact with the first insulating layer and the portion of the top surface of the connecting pad.3. The semiconductor structure of claim 2 , wherein a thickness of the first silicon oxide layer over the first insulating layer and a thickness of the first silicon oxide layer over the portion of the top surface of the connecting pad are the same.5. The semiconductor structure of claim 4 , wherein the connecting via penetrates a portion of the first insulating layer and a portion of the second insulating layer claim 4 , and the connecting via is electrically connected to the connecting layer.6. The semiconductor structure of claim 4 , wherein the MIM capacitor is electrically connected to the connecting layer by the connecting via.8. The semiconductor structure of claim 7 , wherein the external conductor penetrates the ONON stack.10. The semiconductor structure of claim 9 , wherein the ONON stack comprises a first silicon oxide layer claim 9 , a first silicon nitride layer claim 9 , a second silicon oxide layer and a second silicon nitride layer upwardly disposed ...

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Bond pad having ruthenium directly on passivation sidewall

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion. 1. A semiconductor package comprising:a semiconductor chip including an edge pad portion and a bonding pad portion, wherein an edge of edge pad portion is aligned with an edge of the semiconductor chip;a package substrate on which the semiconductor chip is disposed, wherein the package substrate includes a bond finger; anda bonding wire connecting the bonding pad portion to the bond finger, a semiconductor substrate; and', 'a polymer pattern formed on the semiconductor substrate to reveal edge portions of the semiconductor chip, a portion of the edge pad portion adjacent to an edge of the semiconductor chip, and the bonding pad portion, and, 'wherein the semiconductor chip includeswherein a portion of the bonding wire is physically supported by an edge of the polymer pattern such that the bonding wire is spaced apart from the edge pad portion, andwherein the edge of the polymer pattern is in direct contact with the revealed portions of the edge pad portions.2. The semiconductor package of claim 1 , wherein the semiconductor substrate includes:a first pad disposed in a chip region; anda second ...

用于凸块下金属结构的套环及相关联的系统及方法

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Collar for under-bump metal structures and related systems and methods

본 기술은 다이-다이 및/또는 패키지-패키지 간의 인터커넥트 및 관련 시스템을 위한 언더-범프 금속(UBM) 구조체용 칼라의 제조에 관한 것이다. 반도체 다이는 반도체 고체 상태 구성요소를 가진 반도체 재료와, 반도체 재료를 통해 적어도 부분적으로 연장되는 인터커넥트를 포함한다. 언더-범프 금속(UBM) 구조체는 반도체 재료 위에 형성되고 대응하는 인터커넥트에 전기적으로 결합된다. 칼라는 UBM 구조체의 측면의 적어도 일부를 둘러싸고, 솔더 재료는 UBM 구조체의 상부면 위에 배치된다. The present technology relates to the manufacture of collars for under-bump metal (UBM) structures for interconnect and related systems between die-die and/or package-package. The semiconductor die includes a semiconductor material having a semiconductor solid state component and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to a corresponding interconnect. The collar surrounds at least a portion of the side of the UBM structure, and the solder material is disposed over the top surface of the UBM structure.

Semiconductor package, and method for manufacturing semiconductor package

The present invention provides a semiconductor package on which a semiconductor substrate is mounted, wherein the heat resistance of the semiconductor substrate is reduced.　This semiconductor package comprises a semiconductor substrate, an insulation layer, a metal layer, an interposer substrate, a mounting substrate, a signal-transmitting solder ball, and a solder member. A pad is provided to one surface of the semiconductor substrate. The other surface of the semiconductor substrate is covered by the insulation layer. The metal layer covers the insulation layer. Wiring connecting to the pad is formed on the interposer substrate. The signal-transmitting solder ball is joined to the wiring and the mounting substrate and transmits a prescribed electrical signal. The solder member is joined to the metal layer and the mounting substrate.

Package substrate and method for fabricating the same

一种封装基板及其制法，该制法包括提供一具有相对的第一表面与第二表面的基板本体，该第一表面上形成有多个第一电性连接垫，并于该等第一电性连接垫上接置一金属板，再图案化该金属板，以于各该第一电性连接垫上对应定义出一金属柱。本发明能有效改善金属柱的毛边问题及金属柱的高度不一问题。

Semiconductor device

Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Collar for under bump metal structure and associated systems and methods

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Power semiconductor module and power conversion device

功率半导体模块(1)具备电路基板(10)、包含半导体基板(20)的功率半导体元件(19)以及至少一个接合部(5)。至少一个接合部(5)包含远离半导体基板(20)的第1金属构件(12)、靠近半导体基板(20)的第2金属构件(23)以及将第1金属构件(12)和第2金属构件(23)互相接合的接合层(15)。在同一温度下，第1金属构件(12)的0.2％屈服强度比第2金属构件(23)的0.2％屈服强度更小，并且比接合层(15)的剪切强度更小。

Semiconductor device and manufacturing method for same

Conductive buffer layers for semiconductor die assemblies and associated systems and methods

반도체 다이 어셈블리를 위한 전도성 버퍼층 및 관련 시스템 및 방법이 개시된다. 실시예에서, 반도체 다이 어셈블리는 서로 직접 접합된 제1 및 제2 반도체 다이들을 포함한다. 제1 반도체 다이는 제1 구리 패드를 포함하고, 제2 반도체 다이는 제2 구리 패드를 포함한다. 제1 및 제2 구리 패드들은 제1 반도체 다이와 제2 반도체 다이 사이의 인터커넥트를 형성하고, 인터커넥트는 제1 구리 패드와 제2 구리 패드 사이에 전도성 버퍼 물질을 포함하며, 전도성 버퍼 물질은 전도성 입자들의 집합체들을 포함한다. 일부 실시예들에서, 제1 및 제2 구리 패드들은 연접하지 않고, 전도성 버퍼 물질을 통해 서로 전기적으로 연결된다. 일부 실시예들에서, 전도성 버퍼 물질은 전도성 입자들의 집합체들이 전도성 버퍼층에 가해지는 압력에 반응하여 함께 압축되도록 다공성일 수 있다.

Oxidation and corrosion protection in semiconductor devices and semiconductor device assemblies

本申请案涉及半导体装置及半导体装置组合件中的氧化及腐蚀防护。在一些方面中，本文中所描述的技术涉及一种电子装置，其包含：衬底；金属化层，所述金属化层具有：第一表面，其安置于所述衬底上；第二表面，其与所述第一表面相对；及腐蚀防护植入层，其安置于所述金属化层中，所述腐蚀防护植入层在所述金属化层中从所述第二表面延伸到距所述第二表面一定深度，所述深度小于所述金属化层的厚度；以及电连接器，其与所述第二表面耦合。

Semiconductor structure and manufacturing method thereof

本发明公开了一种半导体结构及其制造方法，半导体结构包括接合的第一部件及第二部件。第一部件包括第一介电层、第一导电结构及第一填充材料层。第一导电结构位于第一介电层中且包括第一导电线及其上的第一导电衬垫。第一填充材料层位于第一导电线上且围绕第一导电衬垫。第二部件包括第二介电层、第二导电结构及第二填充材料层。将第二介电层接合至第一介电层。第二导电结构位于第二介电层中，且包括接合至第一导电衬垫的第二导电衬垫。第二填充材料层围绕第二导电衬垫且与第二导电衬垫上的第二导电线接触。本发明的半导体结构的填充材料层围绕导电衬垫，能吸收来自导电结构膨胀而产生的应力。

Semiconductor device and method for manufacturing semiconductor device

【課題】樹脂材料部分の収縮による影響を抑制するのに適した半導体装置、および半導体装置の製造方法を提供する。【解決手段】第１および第２絶縁層３１，３３を形成する工程を備え、第１絶縁層３１を形成する工程では、第１電極２１の周縁部２１１と主面とに跨って配置された第１環状部３１０を形成し、第２絶縁層３３を形成する工程は、第１環状部３１０と重なる環状をなし、かつ樹脂材料からなる第２環状部３３０を配置するステップと、第２環状部３３０を加熱するステップと、を含み、第１環状部３１０の外端境界線３１１と第２環状部３３０の外端境界線３３１との方向ｙにおける距離Ｄ１は、方向ｘの中央よりも外端境界線３３２寄りの端部において大とされ、第１環状部３１０の外端境界線３１２と第２環状部３３０の外端境界線３３２との方向ｘにおける距離Ｄ２は、方向ｙの中央よりも外端境界線３３１寄りの端部において大とされる。【選択図】図１７

Flip-chip connection of two microelectronic components using a uv anneal

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Flip chip

本发明一实施例的倒装芯片，其特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。本发明的倒装芯片能够防止超声波焊接时焊盘上产生裂纹。

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Semiconductor device and method for manufacturing the same

本发明的实施方式涉及一种半导体装置及其制造方法。实施方式的半导体装置具备：第1芯片，设置有存储单元阵列；及第2芯片，与该第1芯片接合，且设置有控制存储单元阵列的控制电路。第1芯片具有衬底、焊垫、第1构造体、及第2构造体。衬底配置于第2芯片的接合面的相反侧，且包含：第1面，与对向的接合面之间设置有存储单元阵列；第2面，与该第1面为相反侧；及开口部，在第1区域中从第2面到达第1面。焊垫设置于开口部内。第1构造体设置于第1面与接合面之间，且与焊垫电连接。第2构造体在第1区域中设置于第1面与接合面之间。

Semiconductor structure with sacrificial anode and passivation layer and method for forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Load terminal of power semiconductor element

Solder bump confinement system for an integrated circuit package

A solder bump confinement system is provided includes a substrate; a contact material patterned on the substrate; an inner passivation layer deposited over the contact material and the substrate; an under bump material pad over the contact material; an under bump material defining layer, having a bump opening contained therein, directly on the under bump material pad in which the under bump material defining layer has a thickness in the range of 200 Angstrom to 1500 Angstrom; and a system interconnect formed over the contact material and coupled to the under bump material defining layer and the under bump material pad through the bump opening.

Semiconductor package

本发明提供一种半导体封装。上述半导体封装包括半导体芯片；第一导电凸块和第二导电凸块，分别设置于上述半导体芯片上，其中上述第一导电凸块和上述第二导电凸块的上视面积比值大于1且小于或等于3。本发明提出的半导体封装因导电凸块的面积不同而提高热传导率并降低电阻性，从而改善半导体封装的热电特性。

Power semiconductor module and power conversion apparatus

A power semiconductor module includes a circuit substrate, a power semiconductor device including a semiconductor substrate, and at least one bonding portion. The at least one bonding portion includes a first metal member distal to the semiconductor substrate, a second metal member proximal to the semiconductor substrate, and a bonding layer that bonds the first metal member and the second metal member to each other. At an identical temperature, 0.2% offset yield strength of the first metal member is smaller than the 0.2% offset yield strength of the second metal member and is smaller than shear strength of the bonding layer.

Semiconductor Device and Methods of Manufacturing Semiconductor Devices

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

Semiconductor device including vertical bond pad

本发明题为“包括垂直接合焊盘的半导体器件”。本技术涉及半导体器件，该半导体器件包括半导体管芯，该半导体管芯在管芯的边缘上形成有垂直管芯接合焊盘。在晶片制造期间，垂直接合焊盘块形成在晶片的划线中并且电耦接到半导体管芯的管芯接合焊盘。垂直接合焊盘块在晶片切片期间被切穿，从而使较大垂直取向的焊盘暴露在每个半导体管芯的垂直边缘上。

Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same

A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.

Diffusion barrier collar for interconnects

접합된 기판들의 절연 또는 유전체 재료 안으로의 전도성 재료 확산을 감소 또는 방지하는 데 기술들 및 디바이스들의 대표적인 구현예들이 사용된다. 오정렬된 전도성 구조물들은, 특히 직접 접합 기술을 이용하는 동안 중첩으로 인해 기판들의 유전체 부분과 직접 접촉하게 될 수 있다. 확산을 억제할 수 있는 배리어 계면이 일반적으로 전도성 재료와 유전체 사이에 중첩부에서 배치된다.

Top cap structure for isolated capacitor

隔离电容器结构通过将隔离电容器的顶板物理地再成形为或分成两段来降低钝化层的击穿的可能性。这样，电场被向下驱动并远离钝化表面。一个实施例利用由电容器的顶部金属板和位于顶部金属板上的附加“顶帽”板形成的串联电容器，该串联电容器将电场再定向到主隔离电容器中。可以包括位于顶帽板和顶部金属板之间的通路。另一种方法是使顶板再成形以具有一体形成的顶帽结构，并获得将电荷向下引导并远离钝化层表面的击穿路径的类似结果。

Semiconductor device with a plurality of semiconductor chips

在半导体装置中，第1金属层(22)形成在半导体衬底(21)的一面上。第1保护膜(23)在第1金属层上具有开口部(23a)，以将第1金属层的端部覆盖的方式形成。在开口部(23a)中，在第1金属层上形成有第2金属层(24)，在第2金属层上形成有防氧化层(25)。第2保护膜(26)具有开口部(26a)，以将防氧化层的端部及第1保护膜覆盖的方式形成。并且，与防氧化层相比对第2保护膜的密接性高的密接部(27)与第2保护膜中的开口周缘部(26c)的下表面的一部分密接。

Bonded assemblies comprising dielectric bonding pattern defining layers and methods of forming the same

접합된 조립체 및 접합된 조립체를 형성하는 방법은, 제1 기판, 제1 반도체 디바이스들, 및 제1 반도체 디바이스들의 각자의 노드에 전기적으로 연결된 제1 접합 패드들을 포함하는 제1 반도체 다이를 제공하는 단계, 제2 기판, 제2 반도체 디바이스들, 및 제2 반도체 디바이스들의 각자의 노드에 전기적으로 연결된 제2 접합 패드들을 포함하는 제2 반도체 다이를 제공하는 단계, 제2 접합 패드들에 걸쳐 관통하는 접합 패턴 정의 개구들을 포함하는 유전체 접합 패턴 정의 층을 형성하는 단계, 및 제2 접합 패드들을 제1 접합 패드들에 접합시키는 단계를 포함하고, 제1 금속 패드들은 접합 패턴 정의 개구들을 통해 확장되고 제2 접합 패드들 중 각자의 하나에 접합된다. A bonded assembly and a method of forming the bonded assembly include providing a first semiconductor die including a first substrate, first semiconductor devices, and first bond pads electrically connected to respective nodes of the first semiconductor devices. providing a second semiconductor die comprising a second substrate, second semiconductor devices, and second bond pads electrically connected to respective nodes of the second semiconductor devices, penetrating across the second bond pads; forming a dielectric bonding pattern defining layer including bonding pattern defining openings, and bonding second bonding pads to the first bonding pads, wherein the first metal pads extend through the bonding pattern defining openings and the first bonding pads extend through the bonding pattern defining openings; It is bonded to a respective one of the 2 bonding pads.

Semiconductor device

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.

Bond pads of semiconductor devices

A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

隔离器

实施方式的隔离器具备第一电极、第二电极、导电体和第一绝缘层。所述第二电极设置于所述第一电极之上，与所述第一电极分离。所述导电体沿着与从所述第一电极朝向所述第二电极的第一方向垂直的第一面，设置于所述第一电极及所述第二电极的周围。所述第一绝缘层设置于所述第二电极之上，包含硅、碳及氮。

Power semiconductor module and power conversion apparatus

A power semiconductor module includes a circuit substrate, a power semiconductor device including a semiconductor substrate, and at least one bonding portion. The at least one bonding portion includes a first metal member distal to the semiconductor substrate, a second metal member proximal to the semiconductor substrate, and a bonding layer that bonds the first metal member and the second metal member to each other. At an identical temperature, 0.2% offset yield strength of the first metal member is smaller than the 0.2% offset yield strength of the second metal member and is smaller than shear strength of the bonding layer.

Method for fabricating semiconductor device with stress relief structure

The present application discloses a method for fabricating semiconductor device with a stress relief structure. The method includes providing a substrate, forming an intrinsically conductive pad above the substrate, and forming a stress relief structure above the substrate and distant from the intrinsically conductive pad.

半导体结构

本发明公开一种半导体结构，包括基底、介电层、第一导电层与保护层。介电层设置在基底上。第一导电层设置在介电层上。保护层设置在第一导电层与介电层上。保护层包括第一上表面与第二上表面。第一上表面位于第一导电层的顶面上方。第二上表面位于第一导电层的一侧。第一上表面的高度高于第二上表面的高度。第二上表面的高度低于或等于位于介电层的顶面与第一导电层之间的第一导电层的下表面的高度。

칩 패키지 구조 및 그 칩

칩 패키지 구조는 마이크로 칩을 기판에 전기적으로 연결시키기 위한 것으로, 특히 LED에 응용되고, 상기 칩 패키지 구조의 칩은 본체 및 적어도 하나의 전극을 포함하며, 상기 전극은 상기 본체의 표면에 설치되며, 또한 상기 표면으로부터 노출되고, 상기 전극은 위치한정 홈 및 상기 위치한정 홈의 주변에 위치하는 위치한정 벽을 구비하며, 상기 위치한정 벽은 접착제 중의 적어도 하나의 도전성 입자를 상기 위치한정 홈에 위치 한정시키며, 또한 상기 칩은 상기 위치한정 홈에 위치한 상기 도전성 입자를 통해 상기 전극과 기판의 접속패드를 전기적으로 연결시킨다.

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ウェハ接合のための犠牲アライメントリング及び自己はんだ付けビア

第１の基板を第２の基板に接合する方法であって、第１の基板は、第１の基板の上面上に第１の電気接点を含み、第２の基板は、第２の基板の底面上に第２の電気接点を含む、方法。この方法は、第１の基板の上面上にポリイミドのブロックを形成するステップであって、ポリイミドのブロックは、丸みを帯びた上角部を有する、ステップと、第１の電気接点が第２の電気接点に当接するまで、第１の基板の上面及び第２の基板の底面を互いに向かって垂直に移動させるステップであって、移動中、第２の基板は、ポリイミドの丸みを帯びた上角部と接触して、第１及び第２の基板を互いに対して横方向に移動させる、ステップと、を含む。【選択図】図１２

Sacrificial alignment ring and self-soldering vias for wafer bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.