In-street integrated circuit wafer via

Semiconductor package, semiconductor device, electronic device and production method for semiconductor package

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR PACKAGE

An insulation layer (3) is formed on an Si wafer (1), and a rewiring layer (2) is formed after an opening is formed in the insulation layer (3). Then, a resin layer (4) is formed on the rewiring layer (2), and it is cured and used to bond the rewiring layer (2) with Cu foils (5). Then, an annular opening (4a) is formed in the resin layer (4), and a Cu plated layer (8) is formed in the opening (4a).

Semiconductor device and manufacturing method thereof

Backside metal treatment of semiconductor chips

An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.

Method of manufacturing a semiconductor device

The present invention discloses a method for manufacturing semiconductor device, wherein, an internal connecting terminal 12 is formed on electrode pads 23 of a plurality of semiconductor chips 11 formed on a semiconductor substrate 35, and there is formed a resin member 13 having a resin member body 13-1 and a protruded portion 13-2 and covering the semiconductor chips 11 on which the internal connecting terminal 12 is formed, a metal layer 39 is formed on the resin member body 13-1 and the protruded portion 13-2 is used as an alignment mark to form a resist film 48 covering the metal layer 39 in a part corresponding to a region in which a wiring pattern 14 is formed and to then carry out etching over the metal layer 39 by using the resist layer 48 as a mask, thereby forming the wiring pattern 14 which is electrically connected to the internal connecting terminal 12.

Semiconductor device and a method of manufacturing the semiconductor device

A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Semiconductor device and manufacturing method thereof

Wafer level chip scale package manufacture comprises use of mold or complex stencil to make stress relaxing insulation layer for front face of wafer

L'invention concerne un procédé de réalisation d'un boîtier à la taille d'une puce électronique et réalisé à l'échelle du substrat, le substrat comportant au moins une puce et ladite au moins une puce possédant des plots d'entrée-sortie sur une face du substrat dite face avant, le procédé comprenant les étapes suivantes : a) formation, au moyen d'un moule ou d'un pochoir complexe, d'une couche isolante de relaxation de contraintes sur ladite face avant, ladite couche de relaxation recouvrant la face avant du substrat avec un relief présentant des puits d'accès au niveau des plots d'entrée-sortie, et ailleurs, des parties en saillie destinées à relaxer les contraintes, chaque partie en saillie ayant une forme étagée comprenant au moins une zone proéminente et au moins une zone, en retrait par rapport à ladite zone proéminente, destinée à supporter un plot de connection électrique, b) formation de pistes électriquement conductrices sur la couche de relaxation pour connecter les plots d'entrée ...

Redistributed Wafer Level Chip Size Package Having Concave Pattern In Bump Pad And Method For Manufacturing The Same

CHIP SCALE SURFACE MOUNT PACKAGES FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME

PURPOSE: A chip scale surface-mounting semiconductor device package is provided to have a footprint of the same side as a semiconductor die. CONSTITUTION: The method for fabricating a package for a semiconductor device comprises the steps of bringing dies into contact with connecting pads on a surface of the dies while the dies are parts of a wafer, forming a first metal layer extended into a scribe line between the die and its adjacent die, forming a nonconductive layer on a lower surface of the water, and covering the nonconductive layer with a second metal layer. In this case, the second layer is extended into the scribe line brought into contact with the first metal layer through an opening of the nonconductive layer. © KIPO 2002 ...

PACKAGE WITH UBM AND FORMING METHOD

Disclosed are a package structure and a method of forming package structures. The package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer. COPYRIGHT KIPO 2016 ...

BALL GRID ARRAY PACKAGING METHOD AND BALL GRID ARRAY PACKAGE

PURPOSE: A ball grid array(BGA) packaging method is provided to reduce process time and cost by eliminating the necessity of a back-end rerouting step used in a conventional BGA chip scale packaging technology. CONSTITUTION: A semiconductor die having metal conductors thereon is provided. The metal conductors are covered with an insulation layer. An etch process is performed through the insulation layer so as to provide one or more openings to the metal conductors. A compliant material layer is deposited. An etch process is performed through the compliant material layer so as to provide on or more openings to the metal conductors. The conductive layer is patterned so as to bring at least one of the metal conductors in electrical contact with one or more pads, each pad comprising a portion of the conductive layer disposed upon the compliant material. Solder balls(2) are disposed upon the pads. © KIPO 2004 ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To prevent a α-ray soft error of a semiconductor device wherein a solder bump is connected to a Cu wiring formed on an Al wiring. CONSTITUTION: A bump-land 6 connecting with the solder bump 10A and the Cu wiring 10 formed together with it in one-piece, consists of a stacked-layer film of a Cu film and a Ni film formed on its upper portion. The film thickness of the stacked-layer film is larger than film thickness of each of a photosensitive polyimide resin film 11 formed on the lower layers of the Cu wiring 10 and the bump-land 10A, an inorganic passivation film 26, a third Al wiring 25, the bump-pad BP, and a second inter-layer insulating film 24. That is, the bump-land 10A is constructed by film thickness larger than those of an insulating component and wiring component which are interposed between a MISFET (n- channel-type MISFETQn and p-channel-type MISFETQp) and the bump-land 10A. © KIPO & JPO 2003 ...

반도체 패키지 및 그 제조 방법

... 하부 절연층들을 포함하는 하부 패키지 기판; 상기 하부 패키지 기판 상에 실장된 제1 반도체 장치; 상기 제1 반도체 장치로부터 측방으로 이격되어 상기 하부 패키지 기판 상에 배치되고, 코어 기판, 상기 코어 기판을 관통하는 코어 비아, 및 상기 코어 비아를 연결하는 코어 패턴을 포함하는 코어층; 상기 제1 반도체 장치를 둘러 싸고, 상기 코어층의 상부을 덮는 봉지재; 및 제1 상부 절연층, 상기 제1 상부 절연층에 배치된 제1 상부 재배선 패턴을 포함하고 상기 봉지재 상에 배치되는 제1 상부 재배선층, 및 상기 제1 상부 절연층의 상부에 배치된 제2 상부 절연층, 상기 제2 상부 절연층에 배치된 제2 상부 재배선 패턴을 포함하는 제2 상부 재배선층을 포함하는 상부 패키지 기판;을 포함하고, 상기 제1 상부 재배선 패턴이 포함하는 제1 미세 패턴의 제1 선폭 및 제1 선간격이 상기 제2 상부 재배선 패턴이 포함하는 제2 미세 패턴의 대응되는 제2 선폭 및 제2 선간격과 같거나 보다 큰 것을 특징으로 하는 반도체 패키지를 제공한다.

Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument

A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.

Device and method for an integrated ultra-high-density device

A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Methods of forming integrated fan-out package

An embodiment method includes attaching a die to a carrier that comprises a recess, wherein the die is at least partially disposed in the recess. The method further includes forming a molding compound over the carrier and around at least a portion of the die, forming fan-out redistribution layers over the molding compound and electrically connected to the die, and removing the carrier.

Package substrate and its fabrication method

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device having a plurality of first terminals on its top surface and disposed in the molding compound body; a plurality of first conductive vias formed in the molding compound body and connected to the first terminals; a second circuit device having a plurality of second terminals on its top surface and disposed in the molding compound body; a plurality of second conductive vias formed in the molding compound body and connected to the second terminals; and a redistribution layer formed on the molding compound body and having at least one conductive wire which connects the first conductive vias and the second conductive vias; wherein the first terminals have a first depth in the molding compound body, the second terminals have a second depth in the molding compound body, and the first depth is not equal to the second depth.

Package structures

A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Package structure and manufacture method thereof

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. A manufacturing method of the package structure is also provided.

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion protrudes from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Semiconductor device and method

Method for producing a semiconductor device and corresponding semiconductor device

The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level (11, 12) to a semiconductor substrate (10); structuring the interconnect level (12); and applying a solder layer (13) on the structured interconnect level (11, 12) in such a way that the solder layer ...

Fan-out semiconductor package

METHOD OF FORMING SEMICONDUCTOR DEVICE

Light-emitting device, light-emitting element and method of manufacturing same

WAFER-LEVEL FABRICATION OF LIDDED CHIPS WITH ELECTRODEPOSITED DIELECTRIC COATING

A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310) exposed thereat which are insulated from the semiconductive or conductive material. By electrodeposition, an insulative layer (304) is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts (308) and a plurality of conductive traces (306) are formed overlying the electrodeposited insulative layer (304) which connect the conductive features (310) to the conductive contacts (308). An optical sensor unit (10) can be incorporated in a camera module (1030) having an optical element (1058) in registration with an imaging area (1026) of the semiconductor element (1000).

METHODS OF PROCESSING THICK ILD LAYERS USING SPRAY COATING OR LAMINATION FOR C4 WAFER LEVEL THICK METAL INTEGRATED FLOW

A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Circuit elements constituting a circuit, a wiring, and a first electrode electrically connected to the circuit are provided on a major surface of a semiconductor substrate. An organic insulating film is formed on the circuit except the opening made in the surface of the first electrode. First and second external connection electrodes are provided on the organic insulating film. A conductive layer for connection between the first and second external connection electrodes and the first electrode is deposited on the organic insulating film.

SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND METHOD OF FORMING THE SAME

A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer.

NEW DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate. 1. An insulated gate bipolar transistor (IGBT) device comprises:a semiconductor substrate comprising an epitaxial layer of a first conductivity type supported on a bottom layer of a second conductivity type electrically contacting a collector electrode disposed on a bottom surface of the semiconductor substrate;a body region of the second conductivity type disposed near a top surface of the semiconductor substrate encompassing a source region of the first conductivity type below a top surface of the semiconductor substrate;a first trench on a first side of the source region etching into the epitaxial layer through the body region, a dielectric layer lining a bottom and side walls of the first trench insulating a lower trench electrode and an upper trench electrode disposed inside the first trench from the epitaxial layer, the upper trench electrode being separated from the lower trench electrode by an inter-segment dielectric layer;a planar insulated gate disposed above the top surface of the semiconductor substrate, the planar insulated gate extending from the first trench to overlaying a portion of the source region.2. The IGBT device of wherein:the ...

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component ...

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

SEMICONDUCTOR CHIP HAVING BOND PADS

In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Micromachined chip scale package

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Mask repattern process

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Method of making flip chip

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

Microelectronics package with vertically stacked dies

The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Package structure and manufacturing method thereof

A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.

Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

Supporting InFO Packages to Reduce Warpage

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Millimeter wave antenna and EMI shielding integrated with fan-out package

Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

Fabrication method of semiconductor structure

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Semiconductor device

For preventing alpha-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.

STRUCTURES AND METHODS FOR RELIABLE PACKAGES

A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Method for establishing and closing a trench of a semiconductor component

A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

Pad configurations for an electronic package assembly

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Radio frequency device packages and methods of formation thereof

A semiconductor device package includes an integrated circuit chip comprising a radio frequency device. The radio frequency device includes active circuitry at a first surface of the integrate circuit chip. An antenna substrate is disposed over the first surface of the integrated circuit. The antenna substrate includes a first conductive layer disposed over the first surface of the integrated circuit chip. The first conductive layer includes a first transmission line electrically coupled to the integrated circuit chip. A first laminate layer is disposed over the first conductive layer. The first laminate layer overlaps a first part of the first transmission line. A second conductive layer is disposed over the first laminate layer. The second conductive layer includes a first opening overlapping a second part of the first transmission line. A second laminate layer is disposed over the second conductive layer. A first antenna is disposed over the second laminate layer and overlaps the first ...

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Semiconductor Packages and Methods of Forming the Same

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis ...

Semiconductor chip having alignment mark and method of manufacturing the same

Disclosed is a semiconductor chip having an alignment mark which is formed on the surface of the semiconductor chip where no external connection bump is formed, and which has the position information of the external connection bump. A method of manufacturing the semiconductor chip having an alignment mark is also provided. Because the semiconductor chip includes the alignment mark having the position information of the external connection bump, the external connection bump is matched with a via which is formed in the external circuit layer of a printed circuit board including the semiconductor chip, thus improving electrical connection with the printed circuit board, and increasing the reliability of the printed circuit board including the semiconductor chip.

Semiconductor device and method of producing the same

A method of producing a semiconductor device includes the steps of forming a protrusion electrode on a semiconductor chip; and sealing the protrusion electrode and a semiconductor substrate with a resin layer. The method further includes the steps of polishing the resin layer until an upper surface of the protrusion electrode is exposed; polishing the exposed upper surface of the protrusion electrode; and forming a solder terminal on the polished upper surface of the protrusion electrode.

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Wafer backside structures having copper pillars

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

PHOTONIC INTEGRATED PACKAGE AND METHOD FORMING SAME

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME

A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.

Semiconductor device and method of manufacturing the same, semiconductor wafer, circuit board and electronic instrument

The present invention may improve the reliability of a semiconductor device and method of manufacture thereof, a semiconductor wafer, a circuit board, and an electronic instrument. A resin layer (20) is formed on a semiconductor substrate (10) in which a plurality of integrated circuits (12) are formed. In the surface of the resin layer (20), a plurality of recesses (22) are formed. On the resin layer (20), an interconnecting line (40) is formed to pass along any of the recesses (22). The semiconductor substrate (10) is cut into a plurality of semiconductor chips. Each recess (22) is formed to have an opening width less than the thickness of the interconnecting line (40), and a depth of at least 1 µ m.

Buffer-less de-skewing for symbol combination in a CDMA demodulator

A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor device and production thereof, with which a package can be miniaturized and handling or performance test and the like can be simplified by using no rewiring board while attaining cost reduction. SOLUTION: For the production of this semiconductor device, the semiconductor device provided with a semiconductor chip 11 to connect electrodes corresponding to the plural electrodes of a wiring board to the respective electrodes is produced. In this production, plural metal bumps 12 corresponding to the electrode patterns of the semiconductor chip 11 are formed at least on one of the semiconductor chip 11 and a temporary board 13 having a size corresponding to this semiconductor chip 11, the semiconductor chip 11 and the temporary board 13 are mutually fixed via the metal bumps 12, a protective layer 14 is formed by filling the gaps between the semiconductor chip 11 and the temporary board 13 and mutually between the metal bumps 12 with underfill ...

HALBLEITERANORDNUNG

Halbleitervorrichtung mit Nachpassivierung-Zwischenverbindungsstruktur und Verfahren zu ihrer Bildung

Halbleitervorrichtung mit Nachpassivierungs-Zwischenverbindungsstruktur, umfassend: – eine auf einem Halbleitersubstrat (10) ausgebildete Schaltungsanordnung (12) mit elektrische Vorrichtungen überlagernden dielektrischen Schichten und dazwischenliegend ausgebildeten Metallschichten; – eine dielektrische Zwischenschicht (14) aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung mit mehreren dielektrischen Schichten und darin ausgebildeten Kontakten zum Kontaktieren der Schaltungsanordnung (12); – mehrere dielektrische Zwischenmetallschichten (16) aufgetragen durch chemische Gasphasenabscheidung mit hochdichtem Plasma mit zugeordneten Metallisierungsschichten, die der dielektrischen Zwischenschicht (14) überlagert sind, wobei die Metallisierungsschichten mittels Ätzprozess unter Verwendung von Ätzstoppschichten aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung Metallleitungen (18) und Durchkontakte (19) zum Zusammenschalten der Schaltungsanordnung (12) schaffen ...

Elektronische Komponente und Verfahren

In einer Ausführungsform umfasst eine elektronische Komponente eine erste dielektrische Schicht, die eine organische Komponente mit einer Zersetzungstemperatur von mindestens 180°C aufweist, ein in die erste dielektrische Schicht eingebettetes Halbleiter-Die, eine zweite dielektrische Schicht, die auf einer ersten Oberfläche der ersten dielektrischen Schicht angeordnet ist, wobei die zweite dielektrische Schicht eine photodefinierbare Polymerzusammensetzung aufweist und zwei oder mehr abgegrenzte Öffnungen mit leitfähigem Material definiert, und ein erstes Substrat, das auf der zweiten dielektrischen Schicht und auf dem leitfähigen Material angeordnet ist. Ein oder mehrere Kontaktpads sind auf einer äußersten Oberfläche des ersten Substrats angeordnet.

Method of making a structure with improved material properties by moderate heat treatment of a metal deposit

Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment

Semiconductor device and manufacturing method for the same

To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10 ); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.

Microelectronic assemblies having compliancy

MODULATE POWER FOR MOTOR VEHICLE

L'invention concerne un module de puissance (10), de préférence pour un véhicule, notamment électrique, caractérisé en ce qu'il comprend deux pastilles semiconductrices (12, 14) superposées, chaque pastille comportant une première face (20, 22), destinée à être connectée à un substrat de dissipation de chaleur (24, 26) et une deuxième face (28, 30), distincte de la première, sur laquelle est agencée au moins un composant électronique (38a-44b), le module étant agencé de sorte que les deuxièmes faces des pastilles sont disposées en vis-à-vis.

TREATMENT OF AUTOIMMUNE DISEASES BY THE AND INFLAMMATORY COMPOUNDS AND/OR ARSENIC AS203 AS205 ADMINISTERED TOPICALLY

L'invention concerne le domaine des maladies auto-immunes et/ou inflammatoires humaines, plus précisément l'utilisation de composés de l'arsenic pour la préparation de médicament destinés au traitement et/ou à la prévention des lésions cutanées associées à des maladies auto-immunes et/ou inflammatoires chez un sujet humain. L'invention a pour objet un composé de l'arsenic As2O5 pour utilisation dans le traitement et/ou la prévention des lésions cutanées associées à des maladies autoimmunes et/ou inflammatoires chez un sujet humain, une composition pharmaceutique comprenant un composé de l'arsenic As2O5, préférentiellement pour le traitement et/ou la prévention des lésions cutanées associées à des maladies auto-immunes chez un sujet humain, ainsi que des produits contenant un composé de l'arsenic As2O5 et un composé de l'arsenic As2O3 comme produit de combinaison pour une utilisation simultanée, séparée ou étalée dans le temps dans le traitement et/ ou la prévention des lésions cutanées ...

Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate

SYSTEM IN PACKAGE AND METHOD FOR FABRICATING THE SAME

CHIP TO PACKAGE INTERFACE

... 본 발명의 일 실시예에 따르면, 반도체 패키지(50)가, 봉지재 내에 배치된 반도체 칩(100), 및 반도체 칩(100) 내에 배치된 제1 코일(30)을 포함한다. 유전층(230)이 봉지재와 반도체 칩(100) 위에 배치되어 있다. 제2 코일(40)은 유전층(230) 위에 배치되어 있다. 제1 코일(30)은 제2 코일(40)에 자기적으로 접속되어 있다.

WIRING STRUCTURE ON SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME

REDISTRIBUTION WAFER LEVEL CHIP SIZE PACKAGE AND MANUFACTURING METHOD THEREOF

PURPOSE: A redistribution wafer level chip size package and a manufacturing method thereof are provided to enhance adhesive strength between a copper redistribution layer and an overlying polymer layer. CONSTITUTION: For the package and the method, a wafer having a plurality of chip pads(44) formed on a semiconductor substrate(42) is provided. A passivation layer(46) covers the substrate(42) except the chip pads(44). The first polymer layer(48) is formed on the passivation layer(46), and then the first UBM layer(50) is formed on the chip pads(44) and the first polymer layer(48). Next, the copper redistribution layer(52) is formed on the first UBM layer(50) and patterned. A barrier metal(54) is then plated on the copper redistribution layer(52), and the first UBM layer(50) exposed out of the copper redistribution layer(52) is removed. Thereafter, the second polymer layer(56) is formed over the first polymer layer(48) and the copper redistribution layer(52). Then, an external electrode(62 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

패키지 구조물 및 형성 방법

... 패키지의 형성 방법 및 구조물이 여기에서 설명된다. 실시예에서, 방법은 후면 재배선 구조물을 형성하는 단계, 및 후면 재배선 구조물을 형성한 후에, 후면 재배선 구조물에 제1 집적 회로 다이를 접착하는 단계를 포함한다. 방법은, 후면 재배선 구조물 상의 제1 집적 회로 다이를 봉지재로 봉지하는 단계, 봉지재 상에 전면 재배선 구조물을 형성하는 단계, 및 제2 집적 회로 다이를 제1 집적 회로 다이에 전기적으로 연결하는 단계를 더 포함한다. 제2 집적 회로 다이는 전면 재배선 구조물에 기계적으로 부착된 제1 외부 전기적 커넥터를 통해 제1 집적 회로 다이에 전기적으로 연결된다.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

PURPOSE: A manufacturing method of semiconductor device is provided to be capable of simplifying manufacturing process and reducing manufacturing cost. CONSTITUTION: Metal pads(2a,2b) are formed on a Si substrate(1) through a first oxide film(3). The Si substrate(1) is bonded to a holding substrate(8) through a bonding film(7). An opening is formed by etching the Si substrate. A second oxide film(10) is formed on the back surface of the Si substrate and in the opening. A wiring(12) is connected to the metal pads after etching the second oxide film(10). A conductive terminal(14) is formed on the wiring(12). Dicing is performed from the back surface of the Si substrate to the bonding film(7). The Si substrate is separated from the holding substrate(8). © KIPO 2004 ...

BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE TO INCREASE SURFACE AREA OF WIRING, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING THE SAME

PURPOSE: A bump with multiple vias for a semiconductor package, a fabricating method thereof, and a semiconductor package using the same are provided to increase a surface area of a wiring by forming a polymer layer having the multiple vias on an electrode pad. CONSTITUTION: An electrode pad(115) is formed on a semiconductor chip(110), and a polymer layer(130) having plural vias(135) is formed on the electrode pad. An under bump metal layer(170) having plural vias is formed on the polymer layer. A metal bump(180) is bonded on the under bump metal layer. The electrode pad is redistributed from a first region to a second region. A stress relaxation layer(160) is formed on the polymer layer having the vias. The under bump metal layer includes at least one of an adhesion layer, a diffusion-barrier layer, and a wetting layer. © KIPO 2007 ...

Image sensor package and fabrication method thereof

An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

Method for forming a double embossing structure

The present invention provides a method for forming a PI-capped double embossing structure. The method includes (a) providing an IC substrate; (b) forming a thin metal film over said IC substrate; (c) forming a plurality of metal traces on said thin metal film; (d) selecting a target metal trace from a plurality of said metal traces to form a metal structure on said target metal trace; (e) removing said thin metal film without covering; and (f) forming a (polyimide) PI cap.

Semiconductor package

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Semiconductor structure and method of manufacturing thereof

"method and device to interconnect packaged integrated circuit dies"

BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Semiconductor device and mounting structure of a semiconductor device

A mounting structure is provided for mounting a semiconductor device having an electrode on a mounting substrate having a conductive pad. A metallic bump electrically connects the electrode of the semiconductor device to the conductive pad. A first eutectic solder is used for soldering between the metallic bump and the electrode of the semiconductor device. A second eutectic solder is used for soldering between the metallic bump and the conductive pad of the substrate. A melting point of the metallic bump is higher than those of the eutectic solders and a resistance to fatigue of the first eutectic solder is higher than that of the second eutectic solder. The first eutectic solder is composed of a Sn component of 63% by mass, a Pb component of 34.3% by mass, an In component of 1% by mass, a Sb component of 0.7% by mass, and an Ag component of 1% by mass.

Chip package and manufacturing method thereof

Method of making a wafer level chip scale package

A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

Integrated fan-out package structures with recesses in molding compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Segregated power and ground design for yield improvement

A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Integrated circuit and method of making

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Semiconductor device having wafer-level chip size package

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

Chip package and method for forming the same

An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Microelectronic packages having trench vias and methods for the manufacture thereof

Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

3D Chip-On-Wafer-On-Substrate Structure With Via Last Process

Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate. 1. A package comprising:a first redistribution layer (RDL) disposed on a first semiconductor substrate;a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL;an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate;a first conductive element disposed in the first RDL;a via extending from a top surface of the insulating film, through the first semiconductor substrate to the first conductive element; anda first spacer disposed between the first semiconductor substrate and the via, wherein the first spacer extends through the first semiconductor substrate.2. The package of claim 1 , wherein a first sidewall of the first spacer is aligned with a sidewall of the insulating film claim 1 , and wherein a second sidewall of the first spacer opposite the first sidewall contacts the first semiconductor substrate.3. The package of claim 1 , wherein top surfaces of the first spacer and the first semiconductor substrate are substantially level claim 1 , and wherein bottom surfaces of the first spacer and the first semiconductor substrate are substantially level.4. The package of further comprising a second spacer disposed between the via and the first spacer.5. The package of claim 4 , wherein the second ...

Stacked Semiconductor Devices and Methods of Forming Same

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. 113-. (canceled)14. A method comprising:forming contact pads on a die;blanket depositing a passivation layer over the contact pads;patterning the passivation layer to form first openings, the first openings exposing the contact pads;blanket depositing a buffer layer over the passivation layer and the contact pads;patterning the buffer layer to form second openings, the second openings exposing a first set of the contact pads;forming first conductive pillars in the second openings, topmost surfaces of the first conductive pillars being above a topmost surface of the buffer layer;simultaneously with forming the first conductive pillars, forming conductive lines over the buffer layer, ends of the conductive lines terminating with the first conductive pillars; andforming an external connector structure over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.15. The method of claim 14 , wherein forming the external connector structure ...

UNDER BUMP METALLURGY (UBM) AND METHODS OF FORMING SAME

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die. 1. A device package comprises:a die;fan-out redistribution layers (RDLs) over the die; a conductive pad portion; and', 'a trench encircling the conductive pad portion; and, 'an under bump metallurgy (UBM) over the fan-out RDLs, wherein the UBM comprisesa connector disposed on the conductive pad portion of the UBM, wherein the fan-out RDLs electrically connect the connector and the UBM to the die.2. The device package of claim 1 , wherein the UBM further comprises a retaining wall portion encircling the trench.3. The device package of claim 2 , wherein a width of the retaining wall portion is about 10 μm to about 20 μm.4. The device package of claim 2 , wherein the connector is not disposed on the retaining wall portion of the UBM.5. The device package of claim 1 , wherein a width of the trench is between about 10 μm to about 20 μm.6. The device package of claim 1 , wherein the fan-out RDLs comprise a conductive line claim 1 , wherein the UBM is formed on a top surface of the conductive line claim 1 , and wherein the trench exposes a portion of the conductive line.7. The device package of claim 6 , wherein the fan-out RDLs comprise a polymer layer extending over a top surface of the conductive line.8. The device package of claim 7 , wherein an entirety of the UBM is disposed in an opening in the polymer layer.9. The device package of claim 7 , wherein the polymer layer covers edge portions of the UBM.10. The device package of claim 7 , wherein the polymer layer is at least partially disposed in the trench.11. A device package comprising:a device die;a conductive ...

PACKAGING STRUCTURAL MEMBER

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. 1. A method of assembling devices comprising:providing a temporary carrier substrate with first and second surfaces, the first surface is prepared with an adhesive; a package region comprises a die attach region surrounded by a peripheral region, and', 'the through-vias extend from the first to the second major surface of the structural member, wherein the through-vias comprise a conductive material; and, 'mating a structural member having first and second major surfaces on the temporary carrier substrate, the structural member comprises a plurality of die package regions and through-vias disposed in the package regions, wherein'}attaching dies in the die attach regions of the structural member.2. The method of wherein the conductive material of the through-vias comprises top and bottom surfaces which are coplanar with the first and second major surfaces of the structural member.3. The method of wherein:the die attach regions comprise openings extending through the first and second major surfaces of the structural member;attaching dies comprises disposing dies in the openings for temporary attachment to the temporary carrier substrate, wherein gaps exist between the dies and sidewalls of the openings; andthe ...

Fan-Out Package and Methods of Forming Thereof

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. 1. A package comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip;a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad;a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound;a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; anda second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.2. The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.3. The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.4. The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.5. The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.6. The package ...

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. 1. A method for manufacturing an integrated device , the method comprising:forming a first reconstitution wafer comprising first components;forming a second reconstitution wafer comprising second components;dicing the second reconstitution wafer into second packaged components, the second packaged components comprising the second components;placing the second packaged components on a first main surface of the first reconstitution wafer; anddicing the first reconstitution wafer into integrated devices, each integrated device comprising a first packaged component and a second packaged component.2. The method of claim 1 , further comprising:placing an integrated device on a carrier;bonding the integrated device to the carrier; andencapsulating the integrated device.3. The method of claim 1 , further comprising disposing a first redistribution layer (RDL) on the first main surface of the first reconstitution wafer.4. The method of claim 3 , further comprising claim 3 , before dicing the second reconstitution wafer claim 3 , disposing a second RDL on a first main surface of the second reconstitution wafer claim 3 , wherein placing the second packaged components on the first main surface of the first reconstitution wafer comprises placing the second packaged components with second RDL regions facing ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view. 1. A semiconductor device , including:a first pad;an insulating film covering the first pad;a first opening exposing part of a surface of the first pad from the insulating film;a first polyimide film having a second opening in communication with the first opening;a first interconnection filling the first opening and the second opening, and provided on the first polyimide film;a second polyimide film covering the first interconnection; anda third opening exposing part of the first interconnection from the second polyimide film,wherein the first polyimide film is provided only in a region that is planarly superposed on the first interconnection.2. The semiconductor device according to claim 1 , wherein when an interconnection length direction of the first interconnection is defined as first direction claim 1 , and an interconnection width direction claim 1 , intersecting with the first direction claim 1 , of the first interconnection is defined as second direction claim 1 , width in the second direction of the first polyimide film is equal to width in the second direction of the first interconnection.3. A method of manufacturing a semiconductor device claim 1 , the method comprising:(a) forming an insulating film covering a first pad;(b) forming a first opening in the insulating film, the first opening exposing part of a surface of the first pad;(c) forming a first polyimide film over the insulating film;(d) forming a second opening in the first polyimide film, the ...

INTEGRATED CIRCUIT PACKAGE STACK

Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package. 1. An integrated circuit (IC) package stack , comprising: a first die;', 'a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side;', 'a first set of vias that communicatively couples the contacts on the first side of the first IC package to the first redistribution layer; and', 'a second set of vias that communicatively couples the first redistribution layer to the contacts on the second side of the first IC package, wherein the first set of vias are formed within a substrate of the first IC package and the second set of vias are formed within a molded layer of the first IC package; and, 'a first IC package, a first side of the first IC package to be mounted to a circuit board, the first IC package includes a second die;', 'a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package., 'a second ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

Photonic Integrated Package and Method Forming Same

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die. 1. A method comprising:placing an electronic die and a photonic die over a carrier;encapsulating the electronic die and the photonic die in an encapsulant;planarizing the encapsulant until the electronic die and the photonic die are revealed;forming redistribution lines over the encapsulant, the electronic die and the photonic die, wherein the redistribution lines electrically connect at least the electronic die; andattaching an optical coupler to the photonic die, wherein an optical fiber attached to the optical coupler is configured to optically couple to the photonic die.2. The method of further comprising:removing a sacrificial material of the photonic die to reveal an opening extending from a front surface and an edge of the photonic die into the photonic die, wherein a waveguide in the photonic die is revealed to the opening, and the optical coupler comprises an edge coupler having a portion extending into the opening, and the optical fiber has a portion extending into a groove in the photonic die, with the groove being a part of the opening.3. The method of further comprising claim 2 , before placing the photonic die over the carrier:forming the opening in the photonic die; andfilling the sacrificial material into the opening.4. The method of claim 1 , ...

Cross-Wafer RDLs in Constructed Wafers

A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer. 1. A method of forming a semiconductor device , the method comprising:placing a plurality of package components over a carrier;encapsulating the plurality of package components in an encapsulant;forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant;exposing the light-sensitive dielectric layer using a first lithography mask;developing the light-sensitive dielectric layer to form a plurality of openings, wherein conductive features of the plurality of package components are exposed through the plurality of openings; andforming redistribution lines extending into the openings, wherein one of the redistribution lines has a length greater than about 26 mm, and the redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.2. The method of claim 1 , wherein the first lithography mask is large enough to cover all package components over the carrier.3. The method of claim 1 , wherein the forming the redistribution lines comprises:coating a plating mask;patterning the plating mask using a second lithography mask large enough to cover all package components over the carrier; andplating the ...

Method of Fabricating Redistribution Circuit Structure

A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via. 1. A method of fabricating a semiconductor device , the method comprising:forming a conductive via;forming a photosensitive dielectric layer to cover the conductive via;thinning the photosensitive dielectric layer to reveal the conductive via, thinning the photosensitive dielectric layer being performed at least through an exposure and development process; andafter thinning the photosensitive dielectric layer, forming a redistribution wiring on the photosensitive dielectric layer and the conductive via.2. The method as claimed in further comprising:after thinning the photosensitive dielectric layer, partially removing the conductive via such that an upper surface of the conductive via is lower than an upper surface of the photosensitive dielectric layer by a first distance; andafter partially removing the conductive via, partially removing the photosensitive dielectric layer to reduce the first distance.3. The method as claimed in claim 2 , wherein partially removing the photosensitive dielectric layer is performed at least in part by an etch process.4. The method as claimed in claim 1 , wherein thinning the photosensitive dielectric layer to reveal the conductive via comprises:performing the exposure and development process to remove a first portion of the photosensitive dielectric layer;after performing the exposure and development process, curing remaining portions of the photosensitive dielectric layer; andafter curing the remaining portions of the photosensitive dielectric layer, removing a second portion of the ...

BONDING SUPPORT STRUCTURE (AND RELATED PROCESS) FOR WAFER STACKING

In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC. 1. A method for bonding semiconductor wafers , the method comprising:forming a first integrated circuit (IC) over a central region of a first semiconductor wafer;forming a first ring-shaped bonding support structure over a ring-shaped peripheral region of the first semiconductor wafer, wherein the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer; andbonding a second semiconductor wafer to the first semiconductor wafer, such that a second IC disposed on the second semiconductor wafer is electrically coupled to the first IC.2. The method of claim 1 , wherein forming the first IC comprises:forming an etch stop layer over an interconnect structure, wherein the interconnect structure is disposed over the first semiconductor wafer; andforming a dielectric layer over the interconnect structure and over the first ring-shaped bonding support structure, wherein the first ring-shaped bonding support structure is formed after the etch stop layer.3. The method of claim 2 , wherein forming the first IC further comprises:performing a first planarization process on the dielectric layer to form a redistribution dielectric layer.4. The method of claim 3 , wherein the redistribution dielectric layer contacts both the etch stop layer and the first ring-shaped bonding support structure.5. The ...

CHIP PACKAGE AND METHOD OF FABRICATING THE SAME

A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. 1. A method of fabricating a chip package , the method comprising:attaching an integrated circuit component on a carrier through a first thermal paste, wherein thermal conductivity of the first thermal paste ranges from about 10 W/mK to about 250 W/mK;forming an insulating encapsulant to encapsulate the integrated circuit component attached on the carrier; andforming a redistribution circuit structure on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.2. The method as claimed in further comprising:forming a plurality of conductive through vias on the carrier before forming the insulating encapsulant such that the conductive through vias are encapsulated by the insulating encapsulant,wherein the conductive through vias are electrically connected to the integrated circuit component through the redistribution circuit structure after forming the redistribution circuit structure.3. The method as claimed in further comprising:after forming the redistribution circuit structure, de-bonding the first thermal paste and the ...

Semiconductor Device and Method of Manufacture

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate. 1. A method of forming a semiconductor device , the method comprising:arranging a plurality of interconnect structures on a carrier substrate to form a reconstructed wafer;encapsulating the plurality of interconnect structures in a first encapsulant;electrically coupling at least one semiconductor component of each of a plurality of semiconductor dies to one or more of the plurality of interconnect structures;encasing the plurality of semiconductor dies and portions of the first encapsulant in a second encapsulant to form a wafer level package;removing the carrier substrate from the plurality of interconnect structures; andbonding a plurality of external contacts to first sides of the plurality of interconnect structures.2. The method of claim 1 , further comprising:exposing a plurality of first contact areas on second sides of each of the plurality of interconnect structures, the second sides of the plurality of interconnect structures being opposite the first sides of the plurality of interconnect structures.3. The method of claim 2 , wherein the electrically coupling the at least one semiconductor component of each of the plurality of semiconductor dies to one or more of the plurality of interconnect structures includes placing at least one semiconductor die of the plurality of semiconductor ...

DEVICE CONTAINING AND METHOD OF PROVIDING CARBON COVERED COPPER LAYER

A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer. 1. A device comprising:a substrate comprising at least one of a semiconductor or mold compound;a first dielectric disposed on substrate;a copper layer plated in an opening in the first dielectric;a solder resist layer above the copper layer;a solder ball in an opening in the solder resist layer, the solder ball in conductive contact with the copper layer; anda non-conductive carbon layer on the substrate, the non-conductive carbon layer formed from carbon rather than a carbon compound and configured to act as a diffusion barrier to moisture for the copper layer.2. The device of claim 1 , wherein the carbon layer is disposed on the substrate below the first dielectric.3. The device of claim 1 , wherein the carbon layer is disposed between the solder resist layer and the first dielectric.4. The device of claim 1 , wherein the carbon layer is disposed on the solder resist layer.5. The device of claim 4 , wherein the carbon layer is further disposed on at least one of the solder ball or an interconnect element.6. The device of claim 4 , wherein the carbon layer is adjacent to the solder ball and the solder ball is free from the carbon layer.7. The device of claim 1 , further comprising:a ...

CHIP ENCAPSULATING METHOD AND CHIP ENCAPSULATING STRUCTURE

A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method. 1. A chip encapsulating method , comprising:fixing a plurality of wafers to a first panel level substrate, the wafer comprising a plurality of chips;forming a re-distribution layer on the wafer for each of the chips;forming each individual chip and the re-distribution layer connected to the chip by cutting;fixing the chip and the re-distribution layer connected to the chip to a second panel level substrate; andencapsulating the chip to form an encapsulating layer.2. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:removing the second panel level substrate;fixing the encapsulating layer to a third panel level substrate, and forming a solder ball on one side of the re-distribution layer.3. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:cutting the encapsulating layer, to form each individual chip encapsulating body; andforming a solder ball for each of the chip encapsulating ...

PHOTONIC SEMICONDUCTOR DEVICE AND METHOD

A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove. 1. A method comprising:forming a plurality of openings through a photonic substrate, wherein the photonic substrate comprises a groove configured to receive an optical fiber, wherein the groove is formed in a top surface of the photonic substrate;forming a plurality of through-vias over and electrically connected to a first redistribution structure;placing the photonic substrate over the first redistribution structure, wherein the plurality of through-vias extend through the plurality of openings in the photonic substrate;forming a sacrificial material in the groove;forming a molding compound within the plurality of openings in the photonic substrate, wherein the molding compound surrounds the plurality of through-vias;forming a second redistribution structure over the top surface of the photonic substrate, wherein the second redistribution structure is electrically connected to the plurality of through-vias and the photonic substrate;removing a portion of the second redistribution structure to expose the sacrificial material;removing the sacrificial material to expose the groove; andmounting an optical fiber within the groove.2. The method of claim 1 , further comprising performing a planarizing process on the molding compound to expose the ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. 1. A semiconductor package , comprising:an insulating encapsulation;an integrated circuit component, encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component; andconductive elements, located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through a portion of the at least one through silicon via protruding from the integrated circuit component.2. The semiconductor package as claimed in claim 1 , further comprising a plurality of conductive pillars arranged aside the integrated circuit component claim 1 , wherein the plurality of conductive pillars is electrically connected to the conductive elements claim 1 , respectively.3. The semiconductor package as claimed in claim 2 , further comprising a glue material covering a sidewall of the integrated circuit component and encapsulated in the insulating encapsulation claim 2 ,wherein an interface is between the glue material and the insulating encapsulation, and the plurality of conductive pillars penetrates and is in contact with the glue material, and the plurality of conductive pillars and ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

Package Structures and Methods of Forming

Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure. 1. A structure comprising: a first integrated circuit die having an active side and a back side opposite from the active side,', 'an encapsulant laterally encapsulating the first integrated circuit die, a first surface of the encapsulant being coplanar with a surface of a die connector on an active side of the first integrated circuit die, a second surface of the encapsulant being opposite from the first surface of the encapsulant,', 'a first redistribution structure on the first surface of the of the encapsulant,', 'a second redistribution structure on the second surface of the encapsulant, and', 'a through via extending through the encapsulant, a first end of the through via extending into the second redistribution structure, the through via extending over a surface of the second redistribution structure facing the first redistribution structure; and, 'a first package comprisinga second integrated circuit die electrically coupled to the first integrated circuit die through first external electrical connectors, the first external electrical connectors being mechanically attached to the first redistribution structure.2. The structure of claim 1 , further comprising second external ...

MICROFABRICATED ULTRASONIC TRANSDUCERS AND RELATED APPARATUS AND METHODS

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature. 1. A method of bonding an engineered substrate having first and second wafers bonded together , the first wafer having an isolation trench isolating an electrode region of the first wafer , the method comprising:forming a redistribution layer on an integrated circuit (IC) wafer having an IC;forming a solder bump array on the redistribution layer; andsolder bump bonding the engineered substrate with the IC wafer such that the first wafer of the engineered substrate is between the IC wafer and the second wafer of the engineered substrate,wherein a first solder bump of the solder bump array electrically contacts the electrode region of the first wafer.2. The method of claim 1 , wherein the first wafer includes a first side proximate the second wafer and a second side distal the second wafer claim 1 , and wherein the method further comprises claim 1 , prior to solder bump bonding the engineered substrate with the IC wafer claim 1 , forming a redistribution layer on the second side of the first wafer.3. The method of claim 1 , wherein the engineered substrate comprises a plurality of cavities in the first wafer or second wafer claim 1 , wherein a first cavity of the plurality of cavities is aligned with the electrode region.4. The method of claim 1 , wherein solder bump bonding the engineered substrate with the IC wafer is performed in a wafer-scale packaging foundry.5. The method of claim 1 , further comprising dicing the engineered substrate and IC wafer subsequent to solder bump bonding the engineered ...

SEMICONDUCTOR PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening. 1. A method of manufacturing a semiconductor device , comprising:providing a die;forming a pad on the die;disposing a first polymer over the die;patterning the first polymer with an opening over the pad;disposing a sacrificial layer over the patterned first polymer;disposing a molding surrounding the die;removing a portion of the molding thereby exposing the sacrificial layer;removing the sacrificial layer thereby exposing the pad and the first polymer;disposing a second polymer an the first polymer;patterning the second polymer with the opening over the pad; anddisposing a conductive material on the pad within the opening.2. The method of claim 1 , wherein the first polymer is surrounded by the molding.3. The method of claim 1 , wherein a portion of the pad is exposed from the first polymer.4. method of claim 1 , wherein the opening is disposed between the sacrificial layer and the pad.5. method of claim 1 , wherein the sacrificial layer includes a polymeric material.6. The method of claim 1 , wherein the molding is disposed over the sacrificial layer.7. The method of claim 1 , wherein the patterning the first polymer is performed by photolithography and etching operations.8. The method of claim 1 , wherein the removing the sacrificial layer is performed by etching operations.9. The method of claim 1 , wherein the removing the portion of the ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME

The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed. 1. A semiconductor package structure , comprising:an insulating substrate in the absence of metal members, comprising a front side and a back side;a first insulating layer disposed on the front side of the substrate; anda die disposed on the first insulating layer;wherein the die comprises a first die pad and a second die pad, the first die pad is coupled to a first portion of a metal layer, the second die pad is coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer are spaced apart by a second insulating layer.2. The semiconductor package structure of claim 1 , further comprising a protection layer disposed on the back side of the substrate.3. The semiconductor package structure of claim 1 , wherein the metal layer is selected from at least one of palladium claim 1 , aluminum claim 1 , chromium claim 1 , nickel claim 1 , titanium claim 1 , gold claim 1 , copper and platinum.4. The semiconductor package structure of claim 1 , wherein the first insulating layer and the second insulating layer are photosensitive dry films comprising constituents selected from at least one of polyimide claim 1 , epoxy resin claim 1 , benzocyclobutene resin and polymer.5. The semiconductor package structure of claim 1 , wherein at least a portion of the ...

Integrated Fan-Out Package Structures with Recesses in Molding Compound

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface. 1. A method comprising:encapsulating a first die and a second die in an encapsulating material;planarizing the encapsulating material;after the planarizing, recessing a first portion of the encapsulating material, wherein a second portion of the encapsulating material is not recessed; andforming redistribution lines over and electrically coupled to the first die and the second die.2. The method of claim 1 , wherein the recessing is performed through laser drilling.3. The method of claim 1 , wherein the second portion forms a ring encircling the first portion.4. The method of claim 3 , wherein the second portion further encircles the first die and the second die.5. The method of claim 1 , wherein after the recessing claim 1 , a portion of the encapsulating material directly underlying the recessed first portion is left un-removed.6. The method of claim 1 , wherein the first die and the second die comprise a first protection film and a second protection film claim 1 , respectively claim 1 , wherein the planarizing is stopped when the first protection film and the second protection film are exposed claim 1 , and wherein the method further comprises:after the planarizing, removing the first protection film and a second protection film to expose the first die and the second die, respectively, wherein metal pads of ...

Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed. 1. A method of packaging a semiconductor device , the method comprising:forming a dam structure on a plurality of dies proximate edge regions of the plurality of dies;disposing a molding material around the plurality of dies; andremoving a top portion of the molding material and a top portion of the dam structure.2. The method according to claim 1 , wherein removing the top portion of the molding material and the top portion of the dam structure comprises a grinding process or a chemical-mechanical polishing (CMP) process.3. The method according to claim 1 , wherein removing the top portion of the molding material comprises removing a portion of the molding material proximate the dam structure.4. The method according to claim 1 , further comprising forming an interconnect structure over the plurality of dies and the molding material.5. The method according to claim 4 , further comprising coupling a plurality of connectors to the interconnect structure.6. The method according to claim 4 , wherein forming the interconnect structure comprises forming fan-out regions.7. The method according to claim 4 , wherein forming the interconnect structure comprises forming a post-passivation interconnect (PPI) structure or a redistribution layer (RDL).8. A method of packaging a semiconductor device claim 4 , the method comprising:coupling a plurality of dies to a carrier;forming a dam structure on each of the plurality of dies proximate edge regions of the plurality of dies;disposing a molding material over the carrier around the plurality of dies;removing a top portion of the molding material and a top ...

RDL-FIRST PACKAGING PROCESS

A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs. 1. A method comprising:forming a first plurality of Redistribution Lines (RDLs) over a carrier;bonding a device die to the first plurality of RDLs through flip-chip bonding, wherein the device dies and the first plurality of RDLs are over the carrier;molding the device die in a molding material;after the molding, detaching the carrier from the first plurality of RDLs; andforming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.2. The method of further comprising forming a plurality of through-vias electrically coupled to the first plurality of RDLs claim 1 , wherein during the molding claim 1 , the plurality of through-vias are molded in the molding material.3. The method of further comprising claim 2 , after the forming the solder balls claim 2 , grinding the molding material to reveal the plurality of through-vias.4. The method of further comprising:before the forming the solder balls and before the detaching the carrier, grinding the molding material to reveal the plurality of through-vias; andafter the grinding the molding material and before the detaching the carrier, forming a plurality of solder regions on the plurality of through-vias.5. The method of further comprising:plating a plurality of solder regions over the plurality of through-vias, with edges of the plurality of solder ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Chip-On-Wafer Package and Method of Forming Same

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material. 1. A method comprising:bonding a die to a substrate, the substrate having a first redistribution structure disposed at a first surface of the substrate, the die having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure;forming a first isolation material over the substrate and around the die;patterning an opening in a second surface of the substrate, the second surface being opposite the substrate from the first surface;extending the opening to expose a first conductive element in the second redistribution structure, wherein extending the opening comprises using a second conductive element in the first redistribution structure as an etch mask; andfilling the opening with a conductive material, the conductive material contacting the first conductive element.2. The method of claim 1 , further comprising:after extending the opening, forming an isolation layer in the opening; andetching the isolation layer to form sidewall spacers on sidewalls of the opening.3. The method of claim 2 , wherein the sidewall ...

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die. 1. A semiconductor package comprising:a first redistribution layer;a first die disposed over the first redistribution layer and having at least one through via therein, wherein the first die comprises at least one sensor;at least one second die and at least one third die, disposed on the first redistribution layer and between the first redistribution layer and the first die;a molding compound disposed on the first redistribution layer, between the first redistribution layer and the first die, and encapsulating the at least one second die and the at least one third die,through interlayer vias (TIVs) arranged through the molding compound, aside the at least one second die and the at least one third die, and between the first redistribution layer and the first die, wherein the TIVs electrically connect the first redistribution layer and the at least one through via of the first die;a dielectric material layer disposed on the molding compound and between the molding compound, the at least one second die, the at least one third die and the first die, wherein the dielectric material layer exposes the at least one through via and the through interlayer vias;conductive elements electrically ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate. 1. A fan-out semiconductor package comprising:a support member having a through-hole;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the support member and the semiconductor chip; anda connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,wherein the support member includes a glass plate and an insulating layer connected to the glass plate.2. The fan-out semiconductor package of claim 1 , wherein the glass plate is an amorphous solid material including a glass component.3. The fan-out semiconductor package of claim 1 , wherein the insulating layer is formed of an insulating material including an insulating resin and an inorganic filler.4. The fan-out semiconductor package of claim 1 , wherein the support member includes a redistribution layer electrically connected to the connection pads.5. The fan-out semiconductor package of claim 4 , wherein the support member further includes vias penetrating through at least one of the glass plate and the insulating layer and electrically connected to the redistribution layer.6. The fan-out semiconductor ...

Semiconductor package and manufacturing method thereof

A method of forming a Fan-Out Wafer Level semiconductor device includes forming only a plurality of metal bonding pads on a glass carrier. Electrode pads of a semiconductor chip are coupled to the plurality of metal bonding pads. The semiconductor chip and the plurality of metal bonding pads are encapsulated with a molding compound. The glass carrier can then be removed to expose a surface of the FOWLP structure. A redistribution layer is then formed on the exposed surface of the FOWLP structure. At least one metal trace within the redistribution layer is in electrical contact with the plurality of metal bonding pads. Solder balls may be mounted on the redistribution layer to provide electrical contact between the solder balls and the electrode pads of the semiconductor chip. 1: A Fan-Out Wafer Level semiconductor device comprising:a plurality of metal bonding pads coplanar to each other;a passivation layer surrounding the plurality of metal bonding pads;a semiconductor chip having an active surface whereon a plurality of electrode pads are formed, the plurality of electrode pads is correspondingly coupled to and electrically connected with the plurality of metal bonding pads;a molding compound encapsulating the semiconductor chip and the plurality of metal bonding pads, the molding compound having a surface coplanar to a surface of each of the plurality of metal bonding pads, the molding compound, the passivation layer, and the plurality of metal bonding pads all disposed on a same side of the surface coplanar to the surface of each of the plurality of metal bonding pads; anda redistribution layer formed on the molding compound and electrically connected to the plurality of metal bonding pads.2: The Fan-Out Wafer Level semiconductor device of further comprising the metal bonding pads are formed on another passivation layer and surrounded by the passivation layer.3: The Fan-Out Wafer Level semiconductor device of further comprising a conductive layer formed to have ...

Embedded die package multichip module

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler. 1. A semiconductor device package , comprising:an electronic component;a first set of conductive wires electrically connected to the electronic component; andan insulation layer having a top surface and surrounding the first set of conductive wires, the top surface of the insulation layer exposing a portion of the first set of the conductive wires,wherein the insulation layer is devoid of a filler.2. The semiconductor device package of claim 1 , further comprising an encapsulant encapsulating the electronic component and the insulation layer.3. The semiconductor device package of claim 1 , further comprising a first patterned conductive layer disposed over the insulation layer and including a plurality of conductive pads claim 1 , wherein the conductive pads of the first patterned conductive layer are respectively electrically connected to the exposed portion of the first set of conductive wires.4. The semiconductor device package of claim 3 , whereinthe electronic component comprises a plurality of conductive contacts electrically connected to the first set of the conductive wires; anda pitch between at least two adjacent conductive contacts of the electronic component is less than a pitch between at least two adjacent conductive pads of the first patterned conductive layer.5. The semiconductor device package of claim 1 , further comprising a second set of conductive wires disposed on the insulation layer and electrically connected to the exposed portion of the first set of the conductive wires.6. The semiconductor device package of claim 5 , further comprising an encapsulant covering the electronic component claim 5 , the ...

PACKAGING METHOD AND PACKAGE STRUCTURE FOR FINGERPRINT RECOGNITION CHIP AND DRIVE CHIP

A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure. 1. A packaging method for a fingerprint recognition chip and a drive chip , comprising:preparing a wafer and a drive chip, wherein the wafer has a first surface and a second surface facing away from the first surface, the first surface of the wafer is provided with a fingerprint recognition chip, the drive chip has a first surface and a second surface facing away from the first surface, and the first surface of the drive chip is provided with a drive circuit and a second contact pad;forming a blind hole from the second surface of the wafer;securing the drive chip in the blind hole, with the first surface of the drive chip being flush with the second surface of the wafer; andcutting the wafer.2. The packaging method according to claim 1 , wherein the fingerprint recognition chip comprises a sensing region and a first contact pad around the sensing region claim 1 , and the blind hole is formed in a region corresponding to the sensing region of the fingerprint recognition chip.3. The packaging method according to claim 2 , wherein after the securing the drive chip in the blind hole and before the cutting the wafer claim 2 , the packaging method further comprises:forming a through hole from ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture;an electronic device having an interconnect electrically coupled to the first conductor; andan encapsulant on a top side of the substrate contacting a side of the electronic device.2. The semiconductor device of claim 1 , wherein the substrate comprises a third conductor on the top side of the dielectric claim 1 , and a fourth conductor on the bottom side of the dielectric claim 1 , wherein the dielectric has an additional aperture claim 1 , and the third conductor comprises a partial via contacting a pad of the fourth conductor through the additional aperture.3. The semiconductor device of claim 2 , further comprising a trace on the dielectric between the partial via of the first conductor and the partial via of the third conductor.4. The semiconductor device of claim 2 , wherein an end of the partial vial of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.5. The semiconductor device of claim 2 , wherein:the first conductor comprises a first trace on the top side of the dielectric and ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure. 1. A package structure , comprising:at least one semiconductor die;a redistribution circuit structure, located on and electrically connected to the at least one semiconductor die; andfirst reinforcement structures, embedded in the redistribution circuit structure,wherein a shape of the package structure comprises a polygonal shape on a vertical projection along a stacking direction of the at least one semiconductor die and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.2. The package structure of claim 1 , wherein the redistribution circuit structure comprises conductive traces claim 1 , and each conductive trace comprises a first contact pad claim 1 , a second contact pad and a conductive structure connecting the first contact pad and the second contact pad claim 1 , wherein a width of the first reinforcement structures is greater than a width of the conductive structures.3. The package structure of claim 1 , wherein the first reinforcement structures are further located on and extended along diagonal lines of the at least one semiconductor die on the vertical projection.4. The package structure ...

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A structure comprising:a device die;an encapsulant encapsulating the device die therein;a first plurality of Redistribution Lines (RDLs) overlying and electrically coupling to the device die, wherein the first plurality of RDLs have a first pitch, and the first plurality of RDLs are substantially free from undercuts; anda second plurality of RDLs overlying and electrically coupling to the device die, wherein the second plurality of RDLs have a second pitch greater than the first pitch, and the second plurality of RDLs have undercuts.2. The structure of claim 1 , wherein each of the first plurality of RDLs and the second plurality of RDLs comprises an adhesion layer and a metal region over the adhesion layer claim 1 , wherein the adhesion layers in the first plurality of RDLs are free from undercuts claim 1 , and the adhesion layers in the second plurality of RDLs have undercuts.3. The structure of claim 1 , wherein all RDLs at a same level as the first plurality of RDLs are substantially free from undercuts claim 1 , and all RDLs at a same level as the second plurality of RDLs have undercuts.4. The structure of claim 1 , wherein all RDLs at levels underlying the first plurality of RDLs and over the device die are substantially free from ...

Functional Spacer for SIP and Methods for Forming the Same

A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member. 2. The semiconductor structure of claim 1 , wherein the ferromagnetic member is entirely enclosed by the conductive bump.3. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is exposed from the conductive bump.4. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is coupled with an outer surface of the conductive bump.5. The semiconductor structure of claim 1 , wherein the conductive bump is in a spherical claim 1 , hemispherical or cylindrical shape.6. The semiconductor structure of claim 1 , wherein a width of the ferromagnetic member is substantially smaller than a length of the ferromagnetic member.7. The semiconductor structure of claim 1 , wherein the ferromagnetic member has a ratio of a width to a length of about 1:1.5 to about 1:30.9. The semiconductor structure of claim 8 , wherein a central axis of the ferromagnetic member passes through the first end and the second end.10. The semiconductor structure of claim 9 , wherein the central axis of the ferromagnetic member is substantially orthogonal to the substrate.11. The semiconductor structure of claim 8 , wherein the substrate includes a conductive trace extended within the substrate claim 8 , and the conductive bump is coupled with at least a portion of the conductive trace.12. The semiconductor structure of claim 11 , wherein the second end of the ferromagnetic member is coupled with at least a portion of the conductive trace.13. The semiconductor structure of claim 8 , wherein the conductive bump is disposed at a corner of the substrate.14. The semiconductor structure of claim 8 , wherein a cross section of the first end exposed from the conductive bump in a circular claim 8 , quadrilateral or cross shape.16. The method of ...

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present disclosure includes a board and a via. In the board, a wiring layer is embedded. The via extends in a depth direction from a main surface of the board to pierce through the wiring layer, and is connected to the wiring layer on a side peripheral surface. 1. A semiconductor device comprising:a board in which a wiring layer is embedded; anda via that extends in a depth direction from a main surface of the board to pierce through the wiring layer, and that is connected to the wiring layer on a side peripheral surface.2. The semiconductor device according to claim 1 , whereinthe via has a bottom portion in a tapered shape.3. The semiconductor device according to claim 2 , whereinthe via has the bottom portion in a bowl shape.4. The semiconductor device according to claim 2 , whereinthe via has the bottom portion in a conical shape.5. The semiconductor device according to claim 2 , whereinthe via has the bottom portion in a planar shape.6. The semiconductor device according to claim 1 , whereinthe via pierces through a plurality of the wiring layers laminated.7. The semiconductor device according to claim 1 , whereinthe via is connected to a wiring layer that is formed with a metallic material arranged on a shallowest layer out of a plurality of the wiring layers laminated.8. A semiconductor device comprising:a board in which a wiring layer is embedded; anda via that extends in a depth direction from a main surface of the board, and that is connected to a surface of the wiring layer at a part of a bottom portion in a tapered shape. The present disclosure relates to a semiconductor device.Semiconductor devices in chip size package (CSP) include a through silicon via (TSV) that connects a wiring layer in a package and a connecting terminal on a mounting board (for example, refer to Patent Literature 1).When a TSV is formed, generally, a through hole that reaches a wiring layer inside a package is formed from a rear surface of ...

ELECTRONIC DEVICE

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. 1a first wiring substrate having a first obverse surface, a first reverse surface opposite the first obverse surface, a plurality of first wirings formed in the first wiring substrate, and a plurality of external electrodes formed on the first reverse surface;a second wiring substrate arranged as an interposer having a second obverse surface, a second reverse surface opposite the second obverse surface, and a wiring layer arranged closer to the second obverse surface than the second reverse surface, the second wiring substrate disposed on the first obverse surface of the first wiring substrate such that the second reverse surface faces the first obverse surface of the first wiring substrate;a first semiconductor chip having a first main surface, a first rear surface opposite the first main surface, and a plurality of first electrodes formed on the first main surface, the first semiconductor chip mounted on the second obverse surface of the second wiring substrate such that the first main surface faces the second obverse surface of the second wiring substrate via a first underfill material; anda second semiconductor chip having a second main surface and a plurality of second electrodes formed on the second main surface, the second semiconductor chip mounted side by side with the first semiconductor chip on the second obverse surface of the second wiring substrate such ...

SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS

A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface. 1. A method for manufacturing a semiconductor device , the method comprising:providing a carrier with a non-photosensitive protection layer;forming a pattern in the non-photosensitive protection layer;providing a semiconductor die with a contact pad on a first surface;bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer;encapsulating a second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer with an encapsulant;removing the carrier and leaving the non-photosensitive protection layer bonded to the semiconductor die; andforming a redistribution layer on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.2. The method according to claim 1 , ...

METHOD OF PATTERN PLACEMENT CORRECTION

In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored. 1. A system , comprising:a processor; anda memory, wherein the memory includes an application program configured to perform an operation for correcting a pattern placement on a substrate, the operation comprising:detecting three reference points for a substrate;detecting a plurality of sets of three die location points, each set indicative of an orientation of a die, the plurality of sets include a first set associated with a first die and a second set associated with a second die;calculating a local transformation for an orientation of the first die and the second on the substrate;selecting three orientation points from the plurality of sets of three die location points wherein the orientation points are not members of the same set;calculating a first global orientation of the substrate from the selected three points from the set of points; andstoring the first global orientation and the local transformation for the substrate.2. The system of further comprising:positioning the substrate in a lithography tool;detecting the three reference points;calculating a second global transformation ...

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack. 124-. (canceled)25. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;coupling to the first IC die a first end of a first wire;anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; andcoupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.26. The method of claim 25 , wherein the stack further comprises a dummy layer claim 25 , and wherein anchoring the second end includes coupling the second end to the dummy stack.27. The method of claim 26 , ...

Interconnect structure for stacked die in a microelectronic device

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure. 1. A package structure , comprising:a first semiconductor die;a second semiconductor die disposed adjacent to the first semiconductor die;a molding compound encapsulating the first semiconductor die and the second semiconductor die;an interconnect structure disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die;a plurality of first conductive features disposed on the molding compound and electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion,a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die and the second semiconductor die, wherein the plurality of through insulator vias surrounds the interconnect structure;an insulating encapsulant ...

Substrate with embedded stacked through-silicon via die

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. 120-. (canceled)21. A semiconductor device comprising: a first interposer side;', 'a second interposer side opposite the first interposer side;', 'a first dielectric layer at the first interposer side;', 'a first conductive via that extends through at least the first dielectric layer;', 'a second conductive via at the second interposer side; and', 'a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;, 'an interposer comprising a first die side that faces away from the first interposer side;', 'a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and', 'a lateral die side that extends between the first die side and the second die side;, 'a semiconductor die comprising the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface;', 'no portion of the encapsulating material is substantially vertically higher than the ...

Integrated Circuit Structures And Methods Of Forming An Opening In A Material

In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed. 119-. (canceled)20. A method of forming an opening in a material , comprising:forming radiation-imageable material (RIM) over target material;impinging radiation onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed, the masking tool during the impinging allowing more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section;after the impinging, developing the RIM to form a RIM opening that has at least one pair of laterally-opposing ledges laterally- ...

EMI Package and Method for Making Same

An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer. 1. A method for manufacturing an integrated circuit structure , comprising:positioning a die on a first side of a substrate;forming a molding on the first side of the substrate and over the die;forming a via in the molding; anddepositing a continuous metallic layer over a top surface of the molding and in the via, wherein depositing the continuous metallic layer comprises a conformal deposition process.2. The method of claim 1 , further comprising:forming a through via through the substrate aligned with the via in the molding; andforming an electrically conductive liner in the through via in electrical contact with the metallic layer.3. The method of claim 1 , wherein the conformal deposition process comprises at least one selected from a group consisting of electroplating claim 1 , sputtering claim 1 , performing chemical-vapor deposition claim 1 , and depositing solder.4. The method of claim 1 , wherein forming the via in the molding comprises:exposing the molding to a patterned light source; andremoving a portion of the molding.5. The method of claim 1 , further comprising:forming another through via through the substrate under a contact pad of the die facing the substrate ...

Chip To Package Interface

In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil. 1. A method of forming a semiconductor package comprising:providing a semiconductor chip comprising a first coil;forming a reconstituted wafer by encapsulating the semiconductor chip with an encapsulant;forming a dielectric layer above the encapsulant and the semiconductor chip;forming a second coil disposed above the dielectric layer, the first coil being magnetically coupled to the second coil; andforming a metal line electrically coupled to the first coil in the semiconductor chip, the metal line being magnetically coupled to the second coil.2. The method of claim 1 , further comprising:forming a plurality of contact pads in the semiconductor chip;forming a plurality of external contact pads above the encapsulant; andforming a redistribution line coupling a pad of the plurality of contact pads with a pad of the plurality of external contact pads, the redistribution line and the second coil disposed in a same redistribution layer.3. The method of claim 1 , further comprising a second dielectric layer disposed within the semiconductor chip claim 1 , the second dielectric layer disposed between the dielectric layer and the first coil.4. The method of claim 1 , wherein the first coil has a first end and a second end claim 1 , the first end being coupled to a ground potential node.5. The method of claim 4 , wherein the second end is coupled to a node coupled to receiver/transmitter input/output node of an antenna.6. The method of claim 1 , wherein the second coil has a first end and a second end claim 1 , the first end being coupled to a first differential input/output node and the ...

CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF

This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer. 1. A method of manufacturing a chip scale sensing chip package , comprising the steps of:providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprises a sensing device and a plurality of conductive pads adjacent to the sensing device nearby the first top surface;providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second bottom surface of the cap wafer to the first top surface of the sensing device wafer by ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided. 1. A method for manufacturing semiconductor devices , the method comprising:forming a conductive pad and a metal protrusion pattern in a metallization layer;conformally depositing a passivation layer over the metallization layer;forming a first opening in the passivation layer to expose the conductive pad;conformally depositing a protection layer over the passivation layer;forming a second opening to expose the conductive pad through the first opening;conformally forming a post-passivation interconnect (PPI) structure on the protection layer, the PPI structure having a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad; andplacing a solder bump on the landing pad region in contact with the protrusion pattern of PPI structure.2. The method of claim 1 , wherein the protrusion pattern of PPI structure is a rectangular stud in or across the landing pad region and adjacent to the connection line.3. The method of claim 1 , wherein the PPI structure is redistribution lines (RDLs) claim 1 , power lines claim 1 , or passive components.4. The method of claim 1 , wherein conformally depositing the protection ...

3D FANOUT STACKING

Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die. 1. A package comprising:a first-first level die and a second-first level die arranged side-by-side;a first row of conductive pillars protruding from a front side of the first-first level die;a second row of conductive pillars protruding from a front side of the second-first level die;a back side of a second level active die attached to the front side of the first-first level die and the front side of the second-first level die laterally between the first and second rows of conductive pillars; anda redistribution layer (RDL) on and in electrical contact with the first and second rows of conductive pillars and a front side of the second level active die.2. The package of claim 1 , wherein a back side of the second level active die is attached to the first-first level die and the second-first level die with a die attach film.3. The package of claim 1 , wherein the second level active die and the first and second rows of conductive pillars are 30 μm-80 μm tall.4. The package of claim 1 , further comprising a second-second level die and a third-second level die laterally adjacent to opposite sides of the second level active die; wherein the RDL is on an in electrical contact with front sides of the second-second level die and the third-second level die.5. The package of claim 4 , wherein the second level active die is rectangular claim 4 , the first and second rows of conductive pillars are laterally adjacent to a first pair of laterally opposite sides of the second level active die claim 4 , and the second-second level die and the ...

Integrated Fan-Out Structure and Method of Forming

Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0. 1. A device , comprising:a first die;a second die;a molding material extending between the first die and the second die; anda redistribution layer overlying the first die and the second die, the redistribution layer including a conductor continuously extending, in a plan view, from a sidewall of the first die that is closest to the second die to a sidewall of the second die that is closest to the first die, the conductor being routed at a first angle over an edge of the first die, the first angle being measured in a plan view and with respect to a shortest line between the first die and the second die, and the first angle being greater than 0.2. The device according to claim 1 , wherein:the first die comprises a first dielectric layer on a first substrate, an edge of the first dielectric layer being offset from an edge of the first substrate; andthe second die comprises a second dielectric layer on a top surface of a second substrate, an edge of the second dielectric layer being offset from an edge of the second substrate;wherein the conductor comprises a first turning point over the first dielectric layer, the first turning point being located where the conductor is first routed at the first angle.3. The device according to claim 2 , wherein the conductor is routed at the first angle over the edge of the second dielectric layer claim 2 , and the first angle is greater than about 15 degrees.4. The ...

Under Bump Metallurgy (UBM) And Methods Of Forming Same

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die. 1. A method for forming a device package , the method comprising:forming a seed layer over a die;forming a conductive line on the seed layer;forming a first mask layer over the conductive line and the seed layer; a first opening for a conductive pad portion of an under bump metallurgy (UBM); and', 'a second opening for a retaining wall portion of the UBM, wherein the second opening forms a ring around the first opening, and wherein a portion of the first mask layer remains disposed between the first opening and the second opening;, 'patterning openings in the first mask layer, wherein the openings compriseforming the UBM in the first opening and the second opening, the UBM comprising the conductive pad portion contacting a surface of the conductive line, the UBM further comprising the retaining wall portion having a bottom-most portion physically contacting the conductive line;removing the first mask layer; andmounting a solder ball to the conductive pad portion of the UBM.2. The method of claim 1 , wherein forming the UBM comprises filling the first opening and the second opening with conductive material.3. The method of claim 2 , wherein filling the first opening and the second opening with conductive material comprises providing nucleation sites for a plating process claim 2 , wherein the nucleation sites are provided by at least one of the conductive line or the seed layer.4. The method of claim 1 , wherein forming the conductive line comprises:before forming the first mask layer, forming a second mask layer over the seed layer;patterning a third opening in ...

SEMICONDUCTOR DEVICES

A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion. 1. A semiconductor device , comprising:a first semiconductor chip having at least one electrically conductive contact at a first side of the first semiconductor chip;an extension layer extending laterally from one or more sides of the first semiconductor chip;a redistribution layer disposed on a surface of the extension layer and the first side of the first semiconductor chip, the redistribution layer being electrically coupled to the at least one electrically conductive contact of the first semiconductor chip;an interposer having at least one electrically conductive contact at a first surface of the interposer and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface of the interposer, the at least one electrically conductive contact at the first surface of the interposer being electrically coupled to the redistribution layer; anda molding material at least partially enclosing the first semiconductor chip and the redistribution layer, and in contact with the ...

Method for preparing semiconductor package structure

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

Electronic Component Package

A semiconductor package includes: a semiconductor chip; an encapsulant covering at least a portion of the semiconductor chip; a connection structure disposed on an active surface of the semiconductor chip, and including one or more redistribution layers electrically connected to a connection pad of the semiconductor chip; a surface treatment layer disposed on a surface of a lowermost redistribution layer, among one or more redistribution layers, of the connection structure; and a passivation layer disposed on the connection structure, covering at least a portion of each of the lowermost redistribution layer and the surface treatment layer, and having an opening exposing at least a portion of the surface treatment layer. A surface on which the surface treatment layer is disposed, of the lowermost redistribution layer, has a surface roughness greater than that of an opposite surface, and the surface treatment layer has irregularities along the surface roughness. 1. A semiconductor package , comprising:a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;an encapsulant covering at least a portion of the semiconductor chip;a connection structure disposed on the active surface of the semiconductor chip, and including one or more redistribution layers electrically connected to the connection pad;a surface treatment layer disposed on a surface of a lowermost redistribution layer, among the one or more redistribution layers, of the connection structure; anda passivation layer disposed on the connection structure, covering at least a portion of each of the lowermost redistribution layer and the surface treatment layer, and having an opening exposing at least a portion of the surface treatment layer,wherein a surface on which the surface treatment layer is disposed, of the lowermost redistribution layer, has a surface roughness greater than that of a surface of the lowermost redistribution ...

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer. 1. A method for fabricating a semiconductor structure , comprising:providing a semiconductor substrate with a first surface and a second surface opposite to the first surface, wherein at least one soldering pad is formed on the first surface of the semiconductor substrate;forming at least one via in the semiconductor substrate to expose each soldering pad by etching the semiconductor substrate from the second surface of the semiconductor substrate;forming a seed layer to cover a sidewall surface and a bottom surface of each via and the second surface of the semiconductor substrate;forming a redistribution metal layer to cover a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and on a portion of the second surface of the semiconductor substrate surrounding each via;performing a pre-wetting process by spraying a diluting agent onto the seed layer and the redistribution metal layer to let each via retain a portion of the diluting agent;performing a chemical etching process right after the pre-wetting process by spraying an etch solution onto the seed layer and the redistribution metal ...

PHOTOSENSITIVE RESIN COMPOSITION, METHOD FOR MANUFACTURING CURED RESIN FILM, AND SEMICONDUCTOR DEVICE

Provided is a photosensitive resin composition containing: one or more kinds of alkali-soluble from a polyimide, a polybenzoxazole, a polyimide precursor, a polybenzoxazole precursor, and a copolymer formed of two or more polymers selected from the preceding substances; and a photosensitizer. The photosensitive resin composition further contains a compound represented by general formula (1). Even when a cured film is fired at low temperature, the photosensitive resin composition exhibits superior adhesion properties with metallic materials, particularly copper, and also exhibits high chemical resistance. 2. The photosensitive resin composition according to claim 1 , comprising 0.1 to 5.0 parts by weight of the compound represented by the general formula (1) relative to 100 parts by weight of the alkali-soluble resin.3. The photosensitive resin composition according to claim 1 , wherein X in the compound represented by the general formula (1) is a sulfur atom.4. The photosensitive resin composition according to claim 1 , wherein at least one of Rand Rin the compound represented by the general formula (1) is an organic group containing an alkoxysilyl group.6. The photosensitive resin composition according to claim 5 , wherein the alkali-soluble resin including the structure represented by the general formula (2) contains a phenolic hydroxyl group.7. The photosensitive resin composition according to claim 5 , wherein the alkali-soluble resin represented by the general formula (2) contains 30 mol % or more organic groups containing a fluorine atom relative to the total amount of the organic groups of both Rand Ras 100 mol %.8. The photosensitive resin composition according to claim 5 , wherein the alkali-soluble resin represented by the general formula (3) contains 30 mol % or more organic groups containing a fluorine atom relative to the total amount of the organic groups of both Rand Ras 100 mol %.9. The photosensitive resin composition according to claim 1 , wherein ...

PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. 1. An electronic package assembly comprising:a solder mask layer having one or more openings;a plurality of pads coupled to the solder mask layer, wherein each of at least two pads of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion of each of the at least two pads is configured to receive a package interconnect structure through the one or more openings in the solder mask layer, wherein the package interconnect structure is configured to route electrical signals between a die and an electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion of each of the at least two pads is configured to receive one or more electrical connections from the die; anda die pad configured to receive the die,wherein the plurality of pads includes (i) a first row of pads disposed adjacent to the die pad and (ii) a second row of pads disposed adjacent and parallel to the first row of ...

Methods for Controlling Warpage in Packaging

A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages. 1. A method comprising:placing a plurality of device dies over a carrier, wherein the plurality of device dies is placed into a plurality of chip areas having sizes identical to each other;placing a plurality of dummy dies over the carrier, wherein the plurality of dummy dies is placed into a plurality of partial chip areas, with each of the plurality of partial chip areas being smaller than one of the plurality of chip areas;encapsulating the plurality of dummy dies and the plurality of device dies in an encapsulating material;forming a plurality of dielectric layers over and contacting the encapsulating material and the plurality of device dies;forming redistribution lines over and electrically coupling to the plurality of device dies; andsingulating the plurality of device dies into a plurality of packages.2. The method of claim 1 , wherein the plurality of dummy dies has sizes different from sizes of the plurality of device dies.3. The method of claim 1 , wherein no dummy die is placed into the plurality of chip areas.4. The method of claim 1 , wherein no device die that is identical to the plurality of device dies is placed into the plurality of partial chip areas.5. The method of claim 1 , wherein the plurality of dummy dies is placed into a peripheral area of the carrier claim 1 , and the plurality of device dies is placed into an inner area of the carrier claim 1 , wherein the peripheral area forms a full ring encircling the inner area.6. The method of claim 1 , wherein the plurality of dummy dies comprises a first dummy die placed into a first partial chip area of ...

SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS

A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor die can be placed directly on the first surface of the single layer dielectric film. The single layer dielectric film can be cured to lock the plurality of semiconductor die in place on the single layer dielectric film. The plurality of semiconductor die can be encapsulated while directly on the single layer dielectric film with an encapsulant. The single layer dielectric film can be patterned utilizing a mask-less patterning technique to form a via hole after removing the temporary carrier substrate. A conductive layer can be formed directly on, substantially parallel to, and extending across, the second surface of the patterned single layer dielectric film, within the vial hole, and over the plurality of semiconductor die. 1. A method of making a semiconductor package , comprising:placing a single layer dielectric film comprising a first surface and a second surface opposite the first surface directly on a temporary carrier substrate, wherein the first surface and the second surface of the single layer dielectric film are substantially parallel;placing a plurality of semiconductor die face down directly on the first surface of the single layer dielectric film opposite the second surface of the dielectric film attached to the temporary carrier substrate, wherein the plurality of semiconductor die is disposed over the temporary carrier substrate;curing the single layer dielectric film after placing the plurality of semiconductor die on the first surface of the single layer dielectric film to lock the plurality of semiconductor die in place on the single layer dielectric film and render the single layer dielectric film non-photoimageable;encapsulating the plurality of semiconductor die on the cured single layer dielectric film with an encapsulant while the temporary carrier substrate supports the single layer ...