Method for manufacturing semiconductor devices having a glass substrate

Method for permanent connection of two metal surfaces

METHOD FOR PERMANENTLY CONNECTING TWO METAL SURFACES

METHODS OF FORMING CONNECTOR PAD STRUCTURES, INTERCONNECT STRUCTURES, AND STRUCTURES THEREOF

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces. 1. A process for producing a permanent , electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate wherein said process does not include a soldering process , said process comprising the following steps:conditioning first and second metal surfaces by producing near surface layers with surface defects, said surface defects produced by application of metallic nanoparticles,aligning said first metal surface relative to said second metal surface, andconnecting the first and second metal surfaces,wherein, during the conditioning, aligning, and connecting steps, a process temperature of at most 300° C. is not exceeded,wherein the connecting step produces a permanent, electrically conductive connection—produced at least primarily by substitution diffusion between similar metal ions and/or metal atoms of the two metal surfaces.2. The process according to claim 1 , wherein the first and/or second metal surfaces have a layer thickness S<5 nm.3. The process according to claim 1 , wherein the conditioning step comprises a step of optimizing a surface roughness of at least one of the metal surfaces.4. A process for producing a permanent claim 1 , electrically conductive connection between a first surface comprising metallic and non-metallic regions of a first substrate and a second surface comprising metallic and non-metallic regions of a second substrate claim 1 , the process comprising the following steps:conditioning the first and/or second surfaces in such a way that, when the surfaces are connected, a permanent, electrically conductive ...

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

HALBLEITERVORRICHTUNG MIT AUSRICHTUNGSPADS UND VERFAHREN ZU DEREN HERSTELLUNG

Halbleitervorrichtung mit einem Halbleitersubstrat, das eine Hauptoberfläche aufweist, über der eine Mehrzahl von Die-Pads und mindestens ein Ausrichtungspad zur optischen Prozesssteuerung für Halbleiterwafer-Testen angeordnet sind. Das Ausrichtungspad hat eine Härte, die kleiner ist als eine Härte der Mehrzahl von Die-Pads.

Method for permanent connection of two metal surfaces

本发明涉及用于永久连接两个金属表面的方法。本发明涉及用于在第一衬底的第一金属表面和第二衬底的第二金属表面之间制造永久的导电连接的方法，具有如下方法步骤：通过产生表面缺陷处理第一和第二金属表面，使得在连接金属表面时制造至少主要由于在两个金属表面的金属离子和/或金属原子之间的置换扩散而产生的永久的导电键合，定向和键合第一和第二金属表面，其中应用热处理，使得发生第一和第二金属表面的近表面层的构造的再组织。

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

INTEGRATED CIRCUIT BACKSIDE METALLIZATION

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING GLASS SUBSTRATE

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a glass substrate. SOLUTION: A first glass substrate having at least one of cavities and openings at a bonding surface thereof is bonded to a first surface of a semiconductor wafer that has a first surface comprising a plurality of doping regions and metal pads and a second surface opposite to the first surface, such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is then machined to thin the semiconductor wafer. At least one metalization region is formed on the machined second surface of the semiconductor wafer. Then the semiconductor wafer and the glass substrate are diced into separate semiconductor devices. COPYRIGHT: (C)2012,JPO&INPIT ...

Method for permanently connecting two metal surfaces

Method for manufacturing semiconductor devices having a glass substrate

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.

Verfahren zum Herstellen von Halbleiterbauelementen mit einem Glassubstrat

Es wird ein Verfahren zum Herstellen von Halbleiterbauelementen offenbart. Es wird ein Halbleiterwafer (10) mit einer ersten Oberfläche (11) und einer zweiten Oberfläche (12) gegenüber der ersten Oberfläche (11) bereitgestellt. Es wird ein erstes Glassubstrat (20) bereitgestellt, das Hohlräume (21) und/oder Öffnungen an einer Bondoberfläche (22) aufweist. Das erste Glassubstrat (20) wird derart an die erste Oberfläche (11) des Halbleiterwafer (10) gebondet, dass die Metallpads (14, 15) innerhalb jeweiliger Hohlräume (21) oder Öffnungen des ersten Glassubstrats (20) angeordnet werden. Die zweite Oberfläche (12) des Halbleiterwafer (10) wird maschinell bearbeitet. Mindestens ein Metallisierungsgebiet (17, 18, 19) wird auf der maschinell bearbeiteten zweiten Oberfläche (12) des Halbleiterwafer (10) ausgebildet. A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer (10) having a first surface (11) and a second surface (12) opposite the first surface (11) is provided. A first glass substrate (20) is provided which has cavities (21) and / or openings on a bonding surface (22). The first glass substrate (20) is bonded to the first surface (11) of the semiconductor wafer (10) in such a way that the metal pads (14, 15) are arranged within respective cavities (21) or openings of the first glass substrate (20). The second surface (12) of the semiconductor wafer (10) is machined. At least one metallization region (17, 18, 19) is formed on the machined second surface (12) of the semiconductor wafer (10).

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

Method for permanent connection of two metal surfaces

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Method for permanent connection of two metal surfaces

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Verfahren zur Herstellung von Halbleitervorrichtungen und entsprechende Vorrichtung

In einer Ausführungsform weist ein Verfahren zum Herstellen von Halbleitervorrichtungen, die Metallisierungen (36, 38, 40) mit peripheren Abschnitten aufweisen, wobei mindestens eine unterliegende Schicht (20, 24) Randbereiche aufweist, die sich den peripheren Abschnitten zugewandt erstrecken, auf: – Bereitstellen einer Opferschicht (26) zum Bedecken der Randbereiche der unterliegenden Schicht (20, 24), – Bereitstellen der Metallisierungen (36, 38, 40), während die Randbereiche der unterliegenden Schicht (20, 24) von der Opferschicht (26) bedeckt sind, und – Entfernen der Opferschicht (26), so dass die Randbereiche der unterliegenden Schicht (20, 24) sich den peripheren Abschnitten ohne eine Kontaktgrenzfläche dazwischen zugewandt erstrecken, wodurch thermomechanische Belastungen vermieden werden.

With sacrificial anode semiconductor structure and its forming method

Method for preparing a semiconductor device with spacer over sidewall of bonding pad

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

For permanent connection of the method of the surface of the two metal

Method for wafer-level semiconductor die attachment

A wafer-level semiconductor die attachment method includes placing a semiconductor die of a plurality of semiconductor dies at an initial placement position to overlap a sub-mount pad on a sub-mount of a pre-singulated wafer. A die pad of the semiconductor die comes in contact with a solder layer deposited over the sub-mount pad. The semiconductor die and the sub-mount include a plurality of die and sub-mount mating features, respectively. The solder layer is heated locally to temporarily hold the semiconductor die at the initial placement position. The pre-singulated wafer is reflowed, when each semiconductor die is temporarily held at the corresponding initial placement position. During reflow, each semiconductor die slides from the initial placement position and a contact is established between the corresponding plurality of die and sub-mount mating features. Thereby, each semiconductor die is permanently attached to the corresponding sub-mount.

Method for manufacturing semiconductor devices having a glass substrate

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.

Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed. 1. A semiconductor device comprising:a first redistribution layer (RDL);a metallization pad disposed over a portion of the first RDL, an entire upper surface of the metallization pad having a surface roughness, wherein the surface roughness is an average surface roughness of approximately 0.18 μm to approximately 0.25 μm;an intermetallic compound (IMC) disposed over a portion of the upper surface of the metallization pad; anda connector disposed over the IMC.2. The semiconductor device of claim 1 , further comprising an insulating layer extending over a portion of the upper surface of the metallization pad.3. The semiconductor device of claim 2 , wherein the insulating layer comprises a polymer layer.4. The semiconductor device of claim 2 , wherein the insulating layer covers all edges of the metallization pad.5. The semiconductor device of claim 2 , wherein the insulating layer extends along sidewalls of the metallization pad.6. The semiconductor device of claim 1 , further comprising:an integrated circuit die coupled to the RDL, wherein portions of the RDL are coupled to contact pads of the integrated circuit die;molding material disposed around the integrated circuit die, the RDL extending over the integrated circuit die and the molding material; andplurality of through vias disposed within the molding material.7. A semiconductor device comprising:an integrated circuit die comprising a first connector pad and a second connector pad;a first metallization pad electrically coupled to the first connector pad, the first metallization ...

METHOD FOR PREPARING A SEMICONDUCTOR DEVICE WITH SPACER OVER SIDEWALL OF BONDING PAD

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

SEMICONDUCTOR DEVICE WITH INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

Semiconductor device with interconnect structure and method for preparing the same

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

METHOD FOR PERMANENTLY CONNECTING TWO METAL SURFACES

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a pennanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,-Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

Semiconductor structure with sacrificial anode and method for forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Semiconductor Device Package and Method of the Same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. 1. A semiconductor device package , comprising:a substrate with electrical through-holes to inter-connect a first wiring circuit on a top surface of said substrate and a second wiring circuit on a bottom surface of said substrate, wherein a contact conductive bump is formed on said first wiring circuit;an adhesive layer on said top surface and said first wiring circuit of said substrate; anda die with a bump structure on the bonding pads of said die, wherein said bump structure of said die is electrically connected to said contact conductive bump of said first wiring circuit of said substrate.2. The package of claim 1 , wherein said adhesive layer is formed only under said die for adhering said die and said substrate.3. The package of claim 2 , further comprising a second contact conductive bump on said second wiring circuit.4. The package of claim 3 , wherein a material of said second contact conductive bump of said substrate includes solder bump or gold bump.5. The package of claim 1 , wherein a material of said bump structure of die includes stud bump claim 1 , solder bump or gold bump.6. The package of claim 2 , further comprising a cover layer on said top surface of said substrate and a bottom surface of said die.7. The package of claim 1 , further comprising a second substrate with a ...

ガラス基板を有する半導体デバイスの製造方法

Methods of forming connector pad structures and interconnect structures, and the structures

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

Method for permanently connecting two metal surfaces

SEMICONDUCTOR STRUCTURE WITH SACRIFICIAL ANODE AND METHOD FOR FORMING

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Semiconductor Structure With Sacrificial Anode and Method for Forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Semiconductor device having alignment pads and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

With glass substrate for manufacturing method of semiconductor device

Method for manufacturing semiconductor devices having a glass substrate

A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.

Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

INTEGRATED CIRCUIT BACKSIDE METALLIZATION

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Semiconductor device

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHODS OF FORMING CONNECTOR PAD STRUCTURES, INTERCONNECT STRUCTURES, AND STRUCTURES THEREOF

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed. 1. A semiconductor device comprising:an integrated circuit die;a metallization pad electrically connected to the integrated circuit die, an upper surface of the metallization pad having an average surface roughness of 0.18 μm to 0.25 μm;a connector on a first portion of the upper surface of the metallization pad;a polymer layer on a second portion of the upper surface of the metallization pad and a sidewall of the metallization pad; andan intermetallic compound (IMC) between the first portion of the upper surface of the metallization pad and the connector.2. The semiconductor device of claim 1 , wherein the metallization pad is in a dielectric layer claim 1 , and wherein the polymer layer extends between a sidewall of the metallization pad and a sidewall of the dielectric layer.3. The semiconductor device of further comprising:a first redistribution line (RDL) on a first side of the integrated circuit die and electrically connected the metallization pad, the metallization pad is on the first side of the integrated circuit die;a molding compound encapsulating the integrated circuit die;a though via extending through the molding compound;a second RDL on a second side of the integrated circuit die and electrically connected to the first RDL through the through via, the second side of the integrated circuit die being opposite the first side; anda second metallization pad electrically connected to the second RDL, the second metallization pad is on the second side of the integrated circuit die.4. The semiconductor device of claim 3 , ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a permanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD FOR MOUNTING BOARD

Disclosed herein is an electronic component that includes a mounting surface having a terminal formation area and a plurality of terminal electrodes arranged in an array in the terminal formation area. The center point of the terminal formation area is offset with respect to the center point of the mounting surface. Thus, at mounting of the electronic component on a mounting substrate, a solder paste is supplied to a land pattern, and then the mounting is performed such that the center point of a mounting area and the center point of the mounting surface coincide with each other, whereby a predetermined displacement occurs between the planar positions of the land pattern and terminal electrode. This allows a void inside the solder to be released outside without involving a layout change of the land pattern. 1. An electronic component comprising:a mounting surface having a terminal formation area; anda plurality of terminal electrodes arranged in an array in the terminal formation area,wherein a center point of the terminal formation area is offset with respect to a center point of the mounting surface.2. The electronic component as claimed in claim 1 ,wherein the mounting surface includes a chip surface of a chip main body in which an internal circuit connected to a plurality of the terminal electrodes is formed and a mold surface of a mold member surrounding the chip main body,wherein the mounting surface has mutually opposing first and second edges, andwherein a width of the mold surface on the mounting surface is different at the first edge from at the second edge.3. The electronic component as claimed in claim 2 ,wherein the mounting surface further has mutually opposing third and fourth edges that connect one ends and other ends of the first and second edges, respectively, andwherein a width of the mold surface on the mounting surface is different at the third edge from at the fourth edge.4. An electronic component comprising:a mounting surface having a ...

Integrated circuit backside metallization

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Semiconductor device package and method of the same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Semiconductor structure with sacrificial anode and passivation layer and method for forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

LED wafer bonding method

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

No Available Figure] ...

For permanent connection of the two metal surface method

Integrated circuit backside metallization

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

SEMICONDUCTOR DEVICE AND A CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

SEMICONDUCTOR DEVICE WITH SPACER OVER SIDEWALL OF BONDING PAD AND METHOD FOR PREPARING THE SAME

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

SEMICONDUCTOR DEVICE HAVING ALIGNMENT PADS AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a permanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

Method for permanent connection of two metal surfaces

Method for permanent connection of two metal surfaces

Method for manufacturing semiconductor devices having a glass substrate

A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Semiconductor device with interconnect structure and method for preparing the same

本揭露提供一種半導體元件，包括一導電圖案以及一內連接結構，該導電圖案設置在一半導體基底上，該內連接結構設置在該導電圖案上。該半導體元件亦包括一內連接襯墊，形成在該內連接結構與該導電圖案之間，並圍繞該內連接結構設置。該內連接襯墊的多個內側壁表面直接接觸該內連接結構，且在該內連接襯墊的各外側壁表面之間的一最大距離大於該導電圖案的一寬度。該半導體元件還包括一半導體晶粒，接合到該半導體基底。該半導體晶粒具有一導電墊，面對該內連接結構設置，其中該導電墊電性連接到該導電圖案。

Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

LED Wafer bonding method

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for permanent connection of two metal surfaces

Method for permanent connection of two metal surfaces

Method for permanent connection of two metal surfaces

Method of manufacturing semiconductor devices and corresponding device

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

Method for permanently connecting two metal surfaces

VIA STRUCTURE, SUBSTRATE STRUCTURE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME

A via structure includes a base material, a first dielectric layer and a second dielectric layer. The base material includes a first surface and a second surface opposite to the first surface, and defines at least one through hole. The first dielectric layer is disposed on the first surface of the base material and includes a gradient surface exposed in the through hole of the base material. The second dielectric layer is disposed on the gradient surface of first dielectric layer. 1. A via structure , comprising:a base material including a first surface and a second surface opposite to the first surface, and defining at least one through hole;a first dielectric layer disposed on the first surface of the base material and including a gradient surface extending from a sidewall of the through hole of the base material downward toward a center of the through hole; anda second dielectric layer disposed on the gradient surface of first dielectric layer.2. The via structure of claim 1 , wherein the base material includes a semiconductor material.3. The via structure of claim 1 , wherein the second dielectric layer includes a first portion disposed on the sidewall of the through hole of the base material and on the gradient surface of the first dielectric layer claim 1 , and a second portion disposed on the second surface of the base material.4. The via structure of claim 3 , wherein a thickness of the first portion of the second dielectric layer is greater than a thickness of the second portion of the second dielectric layer.5. The via structure of claim 4 , wherein the thickness of the second portion is about 15% to about 50% of the thickness of the first portion.6. The via structure of claim 1 , wherein a thickness of the first dielectric layer decreases from the sidewall of the through hole of the base material to the center of the through hole.7. The via structure of claim 1 , wherein a material of the second dielectric layer includes a cured photo sensitive material.8 ...

Method for permanently connecting two metal surfaces

Die Erfindung betrifft ein Verfahren zur Herstellung einer permanenten, elektrisch leitfähigen Verbindung zwischen einer ersten, metallische und nichtmetallische Regionen aufweisenden Oberfläche eines ersten Substrats und einer zweiten, metallische und nichtmetallische Regionen aufweisenden Oberfläche eines zweiten Substrats mit folgenden Verfahrensschritten: - Bearbeitung der ersten und zweiten Oberfläche derart, dass bei einer Verbindung der Oberflächen eine permanente, zumindest überwiegend durch Substitutionsdiffusion zwischen Metallionen und/oder Metallatomen der metallischen Regionen der Oberflächen erzeugte, elektrisch leitfähige Verbindung hergestellt wird, - Ausrichtung und Verbindung der ersten und zweiten Oberfläche, wobei während der Bearbeitung, Ausrichtung und Verbindung eine Prozesstemperatur von maximal 300°C nicht überschritten wird. The invention relates to a method for producing a permanent, electrically conductive connection between a first, metallic and non-metallic regions surface of a first substrate and a second, metallic and non-metallic regions having surface of a second substrate with the following process steps: Processing of the first and second surfaces in such a way that, upon connection of the surfaces, a permanent, electrically conductive connection is produced, at least predominantly by substitution diffusion between metal ions and / or metal atoms of the metallic regions of the surfaces; - Alignment and connection of the first and second surface, wherein a maximum process temperature of 300 ° C is not exceeded during machining, alignment and connection.

Method for permanently connecting two metal surfaces

Method for permanently connecting two metal surfaces

The method involves processing metal surfaces of two respective substrates by production of adjacent-surface layers with defects. The adjacent-surface layers are produced by implanting ions of gas and/or deposition of an inferior metal layer and/or application of metallic nanoparticles. A permanent, electrically conductive connection is produced predominantly by substitution diffusion between metal ions and/or metal atoms of the metal surfaces during a connection of the metal surfaces. The metal surfaces are oriented and connected at maximum process temperature of 300 degree Celsius.

Method for permanently connecting two metal surfaces

Die Erfindung betrifft ein Verfahren zur Herstellung einer permanenten, elektrisch leitfähigen Verbindung zwischen einer ersten Metalloberfläche eines ersten Substrats und einer zweiten Metalloberfläche eines zweiten Substrats mit folgenden Verfahrensschritten, insbesondere Verfahrensablauf: - Bearbeitung der ersten und zweiten Metalloberfläche derart, dass bei einer Verbindung der Metalloberflächen, insbesondere in einem Zeitraum von wenigen Minuten nach der Bearbeitung, eine permanente, zumindest überwiegend durch Substitutionsdiffusion zwischen, insbesondere gleichartigen, vorzugsweise gleichen, Metallionen und/oder Metallatomen der beiden Metalloberflächen erzeugte, elektrisch leitfähige Verbindung herstellbar ist, - Ausrichtung und Verbindung der ersten und zweiten Metalloberfläche, wobei während der Bearbeitung, Ausrichtung und Verbindung eine Prozesstemperatur von maximal 300°C, insbesondere maximal 260°C, vorzugsweise 230°C, noch bevorzugter 200°C, besonders bevorzugt maximal 180°C, idealerweise maximal 160°C, nicht überschritten wird.

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

集成电路背面金属化

本申请公开集成电路背面金属化。一种用于背面金属化的方法包括在硅晶片(200)的第一表面(204)上喷墨印刷纳米银导电墨水(210)的图案。硅晶片(200)包括多个晶粒。该图案包括沿晶粒之间的划线的间隙区域(212)。激光通过晶片的第二表面(202)聚焦在硅晶片的第一表面(204)和硅晶片(200)的第二表面(202)之间的点处。第二表面(202)与第一表面(204)相反。沿划线分离晶粒。

密封的键合结构及其形成方法

公开了一种键合结构。键合结构包括第一元件，该第一元件具有前侧和与前侧相对的背侧。第一元件在第一元件的前侧处具有第一导电焊盘和第一非导电场区。键合结构还包括第二元件，该第二元件具有在第二元件的前侧处的第二导电焊盘和第二非导电场区。第二导电焊盘沿着界面结构被键合到第一导电焊盘。键合结构还包括集成器件，该集成器件与第一元件或第二元件耦合或与第一元件或第二元件一起形成。键合结构还包括从第一元件的背侧延伸到界面结构的细长导电结构。细长导电结构在集成器件周围提供有效闭合轮廓。

具有內連接結構的半導體元件及其製備方法

本揭露提供一種半導體元件，包括一導電圖案以及一內連接結構，該導電圖案設置在一半導體基底上，該內連接結構設置在該導電圖案上。該半導體元件亦包括一內連接襯墊，形成在該內連接結構與該導電圖案之間，並圍繞該內連接結構設置。該內連接襯墊的多個內側壁表面直接接觸該內連接結構，且在該內連接襯墊的各外側壁表面之間的一最大距離大於該導電圖案的一寬度。該半導體元件還包括一半導體晶粒，接合到該半導體基底。該半導體晶粒具有一導電墊，面對該內連接結構設置，其中該導電墊電性連接到該導電圖案。

스크라이브 라인 피처의 레이아웃

본 개시는 더미 패드 패턴을 생성하는 방법을 제공한다. 본 개시의 실시예에 따른 방법은, 스크라이브 라인 영역에 배치된 디바이스 영역을 포함하는 설계 레이아웃을 수용하는 단계, 상기 디바이스 영역을 둘러싸는 상기 스크라이브 라인 영역의 중심 부분 및 상기 중심 부분을 둘러싸는 에지 부분을 식별하는 단계, 상기 에지 부분을 복수의 직사각형 영역들로 분할하는 단계, 상기 복수의 직사각형 영역들 각각에 더미 패턴을 중첩 배치하여 에지 더미 패턴을 얻는 단계, 상기 중심 부분에 더미 패턴을 중첩 배치하여 중심 더미 패턴을 얻는 단계, 상기 디바이스 영역에 대응하는 상기 더미 패턴의 부분을 상기 중심 더미 패턴으로부터 깍아내어 순 중심 더미 패턴을 얻는 단계, 상기 에지 더미 패턴 및 상기 순 중심 더미 패턴에 기초하여 스크라이브 라인 더미 패턴을 생성하는 단계, 및 상기 스크라이브 라인 더미 패턴을 포함하는 제1 포토마스크를 제조하는 단계를 포함한다.

制造半导体器件的方法和对应的器件

本申请涉及制造半导体器件的方法和对应的器件。在一个实施例中，一种方法制造半导体器件，该半导体器件包括具有外围部分的金属化结构，该外围部分具有一个或多个下覆层，该下覆层具有面向外围部分延伸的边缘区域。方法包括：提供牺牲层以覆盖下覆层的边缘区域，在由牺牲层覆盖下覆层的边缘区域的同时提供金属化结构，以及移除牺牲层以使得下覆层的边缘区域面向外围部分延伸而在两者之间没有接触界面，由此避免热机械应力。

Layout of scribe line features

The present disclosure provides method to generate a dummy pad pattern. A method according to embodiment of the present disclosure includes receiving a design layout that includes a device region disposed in a scribe line region, identifying a center portion of the scribe line region surrounding the device region and an edge portion surrounding the center portion, dividing the edge portion into a plurality of rectangular areas, super-positioning a dummy pattern on each of the plurality of rectangular areas to obtain edge dummy patterns, super-positioning the dummy pattern on the center portion to obtain center dummy patterns, carving out a portion of the dummy pattern corresponding to the device region from the center dummy patterns to obtain net center dummy patterns, generating a scribe line dummy pattern based on the edge dummy patterns and the net center dummy patterns, and fabricating a first photomask including the scribe line dummy pattern.

Fine-pitch joining pad structure

A semiconductor device includes two integrated circuit (IC) chips. The first IC chip includes substrate, a spacer connected to the substrate and including holes, wherein at least one of the holes has a first shape, and solder bumps positioned in the holes, respectively. The second IC chip includes a substrate, electrode pads extending from the substrate and connected to the solder bumps, respectively. At least one of the electrode pads that corresponds to the at least one of the solder bumps has a second shape, and the first shape and the second shape are non-coextensive such that there is at least one gap between the first shape and the second shape when projected on each other.

Layout von ritzgrabenelementen

Die vorliegende Offenbarung stellt ein Verfahren zum Erzeugen eine Dummy-Padstruktur bereit. Ein Verfahren gemäß einer Ausführungsform der vorliegenden Offenbarung umfasst Folgendes: Empfangen eines Designlayouts, das einen Vorrichtungsbereich aufweist, der in einem Ritzgrabenbereich angeordnet ist; Identifizieren eines Mittelteils des Ritzgrabenbereichs, der den Vorrichtungsbereich umschließt, und eines Randteils, der den Mittelteil umschließt; Unterteilen des Randteils in eine Mehrzahl von rechteckigen Bereichen; Superponieren einer Dummy-Struktur auf jeden der Mehrzahl von rechteckigen Bereichen, um Dummy-Randstrukturen zu erhalten; Superponieren der Dummy-Struktur auf den Mittelteil, um Dummy-Mittelstrukturen zu erhalten; Herausschneiden eines Teils der Dummy-Struktur, der dem Vorrichtungsbereich entspricht, aus den Dummy-Mittelstrukturen, um Dummy-Netzmittelstrukturen zu erhalten; Erzeugen einer Dummy-Ritzgrabenstruktur auf der Basis der Dummy-Randstrukturen und der Dummy-Netzmittelstrukturen; und Herstellen einer ersten Fotomaske, die die Dummy-Ritzgrabenstruktur aufweist.

半导体结构的键合方法和半导体设备

本公开公布了一种半导体结构的键合方法和半导体设备，涉及半导体技术领域，该半导体结构的键合方法包括：提供具有相对设置的第一面和第二面第一半导体结构；对第一面或第二面进行处理，形成具有第一键合面的至少一个第一单体；对第一半导体结构进行扩片处理；提供具有第二键合面的第二半导体结构；整体翻转第一半导体结构；对第一键合面与第二键合面进行对准处理；完成键合操作。

Method for manufacturing semiconductor devices having a glass substrate

A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallisation region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallisation region.

Method for wafer-level semiconductor die attachment

A wafer-level semiconductor die attachment method includes placing a semiconductor die of a plurality of semiconductor dies at an initial placement position to overlap a sub-mount pad on a sub-mount of a pre-singulated wafer. A die pad of the semiconductor die comes in contact with a solder layer deposited over the sub-mount pad. The semiconductor die and the sub-mount include a plurality of die and sub-mount mating features, respectively. The solder layer is heated locally to temporarily hold the semiconductor die at the initial placement position. The pre-singulated wafer is reflowed, when each semiconductor die is temporarily held at the corresponding initial placement position. During reflow, each semiconductor die slides from the initial placement position and a contact is established between the corresponding plurality of die and sub-mount mating features. Thereby, each semiconductor die is permanently attached to the corresponding sub-mount.

Fine-pitch joining pad structure

A semiconductor device includes two integrated circuit (IC) chips. The first IC chip includes substrate, a spacer connected to the substrate and including holes, wherein at least one of the holes has a first shape, and solder bumps positioned in the holes, respectively. The second IC chip includes a substrate, electrode pads extending from the substrate and connected to the solder bumps, respectively. At least one of the electrode pads that corresponds to the at least one of the solder bumps has a second shape, and the first shape and the second shape are non-coextensive such that there is at least one gap between the first shape and the second shape when projected on each other.

Sealed bonded structures and methods for forming the same

A bonded structure is disclosed. The bonded structure includes a first element that has a front side and a back side that is opposite the front side. The first element has a first conductive pad and a first nonconductive field region at the front side of the first element. The bonded structure also includes a second element that has a second conductive pad and a second nonconductive field region at a front side of the second element. The second conductive pad is bonded to the first conductive pad along an interface structure. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The bonded structure further includes an elongate conductive structure that extends from the back side of the first element to the interface structure. The elongate conductive structure provides an effectively closed profile around the integrated device.

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

具有内连接结构的半导体元件及其制备方法

本公开提供一种具有内连接结构的半导体元件及其制备方法，该半导体元件包括一导电图案以及一内连接结构，该导电图案设置在一半导体基底上，该内连接结构设置在该导电图案上。该半导体元件亦包括一内连接衬垫，形成在该内连接结构与该导电图案之间，并围绕该内连接结构设置。该内连接衬垫的多个内侧壁表面直接接触该内连接结构，且在该内连接衬垫的各外侧壁表面之间的一最大距离大于该导电图案的一宽度。该半导体元件还包括一半导体晶粒，接合到该半导体基底。该半导体晶粒具有一导电垫，面对该内连接结构设置，其中该导电垫电性连接到该导电图案。

电子部件及其制造方法、和安装基板的制造方法

本发明的技术问题在于，提供一种表面安装型的电子部件，不用改变焊盘图案的布局，就能够减少残留于焊料的空隙。本发明的电子部件(1)具备：具有端子形成区域(A)的安装面(11)；和在端子形成区域(A)阵列状地排列的多个端子电极(12)。端子形成区域(A)的中心点(C2)相对于安装面(11)的中心点(C1)偏移。由此，在安装至安装基板(20)时，在向焊盘图案供给焊膏后，如果以搭载区域(1a)的中心点(C0)与安装面(11)的中心点(C1)一致的方式安装，则在焊盘图案(22)与端子电极(12)的平面位置产生规定的错位。因此，不用改变焊盘图案(22)的布局，就能够将焊料内部的空气释放至外部。

半导体结构的键合方法和半导体设备

本公开提供了一种半导体结构的键合方法和半导体设备，涉及半导体技术领域，该半导体结构的键合方法包括：提供具有相对设置的第一面和第二面第一半导体结构；对第一面或第二面进行处理，形成具有第一键合面的至少一个第一单体；对第一半导体结构进行扩片处理；提供具有第二键合面的第二半导体结构；整体翻转第一半导体结构；对第一键合面与第二键合面进行对准处理；完成键合操作。本公开通过将具有至少一个第一单体的第一半导体结构进行整体翻转，而后再进行键合过程，大大减少了半导体结构键合过程中的翻转次数，避免了因多次翻转而导致的半导体结构的表面污染问题，从而有效提高了半导体结构的键合质量和键合效率。

密封的键合结构及其形成方法

公开了一种键合结构。键合结构包括第一元件，该第一元件具有前侧和与前侧相对的背侧。第一元件在第一元件的前侧处具有第一导电焊盘和第一非导电场区。键合结构还包括第二元件，该第二元件具有在第二元件的前侧处的第二导电焊盘和第二非导电场区。第二导电焊盘沿着界面结构被键合到第一导电焊盘。键合结构还包括集成器件，该集成器件与第一元件或第二元件耦合或与第一元件或第二元件一起形成。键合结构还包括从第一元件的背侧延伸到界面结构的细长导电结构。细长导电结构在集成器件周围提供有效闭合轮廓。

具有对准焊盘的半导体器件以及制造该半导体器件的方法

公开了具有对准焊盘的半导体器件以及制造该半导体器件的方法。半导体器件包括半导体衬底，半导体衬底包括在其上布置有多个管芯焊盘和至少一个对准焊盘的主表面，至少一个对准焊盘用于针对半导体晶片探测的光学处理控制。对准焊盘具有比多个管芯焊盘的硬度小的硬度。

具有内连接结构的半导体元件及其制备方法

本公开提供一种具有内连接结构的半导体元件及其制备方法，该半导体元件包括一导电图案以及一内连接结构，该导电图案设置在一半导体基底上，该内连接结构设置在该导电图案上。该半导体元件亦包括一内连接衬垫，形成在该内连接结构与该导电图案之间，并围绕该内连接结构设置。该内连接衬垫的多个内侧壁表面直接接触该内连接结构，且在该内连接衬垫的各外侧壁表面之间的一最大距离大于该导电图案的一宽度。该半导体元件还包括一半导体晶粒，接合到该半导体基底。该半导体晶粒具有一导电垫，面对该内连接结构设置，其中该导电垫电性连接到该导电图案。

具有位在接合垫侧壁上的间隙子的半导体元件及制备方法

本公开提供一种具有位在接合垫侧壁上的间隙子的半导体元件及制备方法。该半导体元件具有一接合垫以及一第一间隙子，该接合垫设置在一半导体基底上，该第一间隙子设置在该接合垫的一侧壁上。该半导体元件亦包括一第一钝化层以及一导电凸块，该第一钝化层覆盖该接合垫与该第一间隙子设置，该导电凸块设置在该第一钝化层上。该导电凸块经由该接合垫而电性连接到位在该半导体基底中的一源极/漏极区。

集成电路背面金属化

本申请公开集成电路背面金属化。一种用于背面金属化的方法包括在硅晶片(200)的第一表面(204)上喷墨印刷纳米银导电墨水(210)的图案。硅晶片(200)包括多个晶粒。该图案包括沿晶粒之间的划线的间隙区域(212)。激光通过晶片的第二表面(202)聚焦在硅晶片的第一表面(204)和硅晶片(200)的第二表面(202)之间的点处。第二表面(202)与第一表面(204)相反。沿划线分离晶粒。