Electronic device including electrical connections on an encapsulation block

Semiconductor package and manufacturing method thereof

멀티플 비아를 포함하는 비아 연결 구조 및 이를 포함하는 기판

... 비아의 연결구조가 제공된다. 상기 연결구조는 절연층 내에 배치되고, 상하 방향으로 전기적 신호를 연결하는 멀티플 비아를 포함한다. 멀티플 비아는 제1비아와 제1비아를 포함하고, 이들은 서로 수직 적층된 관계로 배치되고, 동일한 면에서 접하고, 상기 제2비아와 상기 제1비아는 서로 다른 개수로 배치된다.

Uniplanar (single layer) passive circuitry

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into contact with the passivation film; a resin layer formed on the first metal layer; a wiring formed so as to be electrically coupled to the electrode and reach an upper surface of the resin layer; and a second metal layer formed so as to be in contact with the first metal layer and reach the upper surface of the resin layer.

Semiconductor package having a redistribution line structure

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

Semiconductor device having low dielectric insulating film and manufacturing method of the same

A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.

Method for establishing and closing a trench of a semiconductor component

A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

PACKAGE FÜR INTEGRIERTE SCHALTUNGEN UND VERFAHREN

In einer Ausführungsform weist eine Vorrichtung auf: einen integrierten Schaltungs-Die; eine Verkapselung, die den integrierten Schaltungs-Die zumindest teilweise umgibt, wobei das Verkapselungsmaterial Füllstoffe mit einem mittleren Durchmesser aufweist; eine Durchkontaktierung, die sich durch die Verkapselung erstreckt, wobei die Durchkontaktierung einen unteren Abschnitt einer konstanten Breite und einen oberen Abschnitt einer stetig abnehmenden Breite aufweist, wobei eine Dicke des oberen Abschnitts größer als der mittlere Durchmesser der Füllstoffe ist; und eine Umverteilungsstruktur mit: einer dielektrischen Schicht auf der Durchkontaktierung, der Verkapselung und dem integrierten Schaltungs-Die; und einer Metallisierungsstruktur mit einem Durchkontaktierungsabschnitt, der sich durch die dielektrische Schicht erstreckt, und einem Leitungsabschnitt, der sich entlang der dielektrischen Schicht erstreckt, wobei die Metallisierungsstruktur elektrisch mit der Durchkontaktierung und dem ...

Elektronische Komponente und Verfahren

In einer Ausführungsform umfasst eine elektronische Komponente eine erste dielektrische Schicht, die eine organische Komponente mit einer Zersetzungstemperatur von mindestens 180°C aufweist, ein in die erste dielektrische Schicht eingebettetes Halbleiter-Die, eine zweite dielektrische Schicht, die auf einer ersten Oberfläche der ersten dielektrischen Schicht angeordnet ist, wobei die zweite dielektrische Schicht eine photodefinierbare Polymerzusammensetzung aufweist und zwei oder mehr abgegrenzte Öffnungen mit leitfähigem Material definiert, und ein erstes Substrat, das auf der zweiten dielektrischen Schicht und auf dem leitfähigen Material angeordnet ist. Ein oder mehrere Kontaktpads sind auf einer äußersten Oberfläche des ersten Substrats angeordnet.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Microelectronic assemblies having compliancy

MODULATE POWER FOR MOTOR VEHICLE

L'invention concerne un module de puissance (10), de préférence pour un véhicule, notamment électrique, caractérisé en ce qu'il comprend deux pastilles semiconductrices (12, 14) superposées, chaque pastille comportant une première face (20, 22), destinée à être connectée à un substrat de dissipation de chaleur (24, 26) et une deuxième face (28, 30), distincte de la première, sur laquelle est agencée au moins un composant électronique (38a-44b), le module étant agencé de sorte que les deuxièmes faces des pastilles sont disposées en vis-à-vis.

Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE TO INCREASE SURFACE AREA OF WIRING, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING THE SAME

PURPOSE: A bump with multiple vias for a semiconductor package, a fabricating method thereof, and a semiconductor package using the same are provided to increase a surface area of a wiring by forming a polymer layer having the multiple vias on an electrode pad. CONSTITUTION: An electrode pad(115) is formed on a semiconductor chip(110), and a polymer layer(130) having plural vias(135) is formed on the electrode pad. An under bump metal layer(170) having plural vias is formed on the polymer layer. A metal bump(180) is bonded on the under bump metal layer. The electrode pad is redistributed from a first region to a second region. A stress relaxation layer(160) is formed on the polymer layer having the vias. The under bump metal layer includes at least one of an adhesion layer, a diffusion-barrier layer, and a wetting layer. © KIPO 2007 ...

BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Chip package and manufacturing method thereof

Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

Semiconductor package, semiconductor module, and method for fabricating the semiconductor package

Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

Wafer level chip scale packaging structure and method of fabricating the same

A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Chip scale package and method for manufacturing the same using a redistribution substrate

A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnetion bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

Method of routing an electrical connection on a semiconductor device and structure therefor

In one embodiment, conductors of a semiconductor device are routed to a contact platform of the semiconductor device by using electroless plating and screen-printing techniques.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Semiconductor device and manufacturing method

Semiconductor device having low dielectric insulating film and manufacturing method of the same

A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines. An insulating film is provided on an upper side of thelaminated structure portion. Connection pad portions for electrodes are arranged on the insulating film to be electrically connected to the connection pad portions of uppermost wiring lines of the laminated structure portion. Bump electrodes for external connection are provided on the connection pad portions for the electrodes. A sealing film is provided on the insulating film and on the peripheral portion of the semiconductor substrate. Side surfaces of the laminated structure portions are covered with the insulating film or the sealing film.

MODULATE POWER FOR MOTOR VEHICLE

SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines. An insulating film is provided on an upper side of the laminated structure portion. Connection pad portions for electrodes are arranged on the insulating film to be electrically connected to the connection pad portions of uppermost wiring lines of the laminated structure portion. Bump electrodes for external connection are provided on the connection pad portions for the electrodes. A sealing film is provided on the insulating film and on the peripheral portion of the semiconductor substrate. Side surfaces of the laminated structure portions are covered with the insulating film or the sealing film. © KIPO & WIPO 2009 ...

SEMICONDUCTOR DEVICE

POWER MODULE FOR AN AUTOMOBILE

The invention relates to a power module (10), preferably for a vehicle, in particular an electric vehicle, characterised in that said module includes two vertically adjacent semiconducting chips (12, 14), each chip having a first surface (20, 22) to be connected to a heat sink substrate (24, 26), and a second surface (28, 30) separate from the first and on which at least one electronic component (38a-44b) is arranged, the module being arranged such that the second surfaces of the chips are arranged opposite one another.

SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor substrate (1) on which a structure portion (3) is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films (4) and wiring lines (5), the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400°C or higher. An insulating film (9) is formed on the structure portion (3). A connection pad portion is arranged on the insulating film (9) and connected to an uppermost wiring line (5) of the laminated structure portion (3). A bump electrode (13) is provided on the connection pad portion. A sealing film (14) made of an organic resin is provided on a part of the insulating film (9) which surrounds the bump electrode (13). Side surfaces of the laminated structure portion (3) are covered with the insulating film (9) and/or the sealing film (14).

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

STACKED DIE PACKAGE INCLUDING A FIRST DIE COUPLED TO A SUBSTRATE THROUGH DIRECT CHIP ATTACHMENT AND A SECOND DIE COUPLED TO THE SUBSTRATE THROUGH WIRE BONDING, AND RELATED METHODS, DEVICES AND APPARATUSES

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME

SEMICONDUCTOR PACKAGE, AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To provide the manufacture of a wafer-level chip scale package, using a rewiring board. SOLUTION: This manufacture includes a stage of providing a rewiring board 130 which has a board foundation layer, a plurality of terminal pads 116 provided on that board foundation layer, a plurality of junction bumps 128, and a metallic wiring layer 122 for severally connecting the junction bumps 128 to the terminal pads 116, a step of joining a semiconductor wafer 100 provided with a plurality of integrated circuits and a plurality of chip bands 104 to the rewiring board 130, such that the junction bumps 128 of the rewiring board 130 contact with the chip pads 104 of the semiconductor wafer 100, a step of forming a plurality of external connection terminals 136 at each terminal pad 116 of the rewiring board 130, and a step of cutting the semiconductor wafer 100 and the rewiring board 130 so as to get individual semiconductor packages. COPYRIGHT: (C)2001,JPO ...

PACKAGES MIT VERGRÖSSERTEN DURCHKONTAKTIERUNGEN IN VERKAPSELUNG

Ein Package umfasst einen Vorrichtungsdie, eine Verkapselung, die den Vorrichtungsdie in sich verkapselt, eine erste Mehrzahl von Durchkontaktierungen, die durch die Verkapselung dringt, eine zweite Mehrzahl von Durchkontaktierungen die durch die Verkapselung dringt, und Umverteilungsleitungen über und in elektrischer Verbindung mit der ersten Mehrzahl von Durchkontaktierungen. Die erste Mehrzahl von Durchkontaktierungen umfasst ein Array. Die zweite Mehrzahl von Durchkontaktierungen befindet sich außerhalb des ersten Arrays und die zweite Mehrzahl von Durchkontaktierungen ist größer als die erste Mehrzahl von Durchkontaktierungen.

Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method

Integrated circuit chip using top post-passivation technology and bottom structure technology

Semiconductor device structure and method for forming the same

Semiconductor device and manufacturing method thereof

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

An interposer film for IC packaging is disclosed. The interposer film comprises a substrate that supports a plurality of electrically conductive domains. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

THERMALLY AND DIMENSIONALLY STABLE POLYIMIDE FILMS AND METHODS RELATING THERETO

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)

A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Semiconductor package having redistribution pattern and passivation patterns and method of fabricating the same

A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

SUBSTRATE MODULE, METHOD FOR MANUFACTURING SUBSTRATE MODULE, AND ELECTRONIC DEVICE

In a substrate module of the present invention, a connection electrode is provided on a first surface of a substrate, and a first penetrating hole portion is running through the substrate in a thickness direction thereof so as to reach a reverse surface of the connection electrode, with a penetrating electrode being provided inside the first penetrating hole portion. The penetrating electrode defines a depression in a position opposing the reverse surface of the connection electrode, and an upper portion of the penetrating electrode is thicker than a side portion of the penetrating electrode. The penetrating electrode is present also on a second surface of the substrate, and is connected to a wiring electrode on the second surface.

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

Electronic device, and manufacturing method of electronic device

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Package structure

A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

METHOD AND APPARATUS FOR FORMING BACKSIDE DIE PLANAR DEVICES AND SAW FILTER

Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Component carrier with included electrically conductive base structure and method of manufacturing

A component carrier having a base structure consisting of an electrically conductive material, an electronic component arranged on the base structure and a surrounding structure on the base structure, where the surrounding structure at least partially surrounds the electronic component laterally.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes a semiconductor substrate, a wiring layer including an electrode pad, the wiring layer formed on a first surface of the semiconductor substrate, a redistribution layer including wiring electrically connected to the electrode pad via a via, the redistribution layer formed on a second surface side opposite to the first surface of the semiconductor substrate, a protective film formed on a surface on a side opposite to the semiconductor substrate in the redistribution layer, and a partition formed by an insulating material, the partition arranged between pieces of wiring in the redistribution layer, in which the partition and a void are alternately formed between the pieces of wiring in a direction in which the wiring extends.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

RESIN-SEALED SEMICONDUCTOR PACKAGE AND FABRICATION THEREOF

PURPOSE: To miniaturize a semiconductor package and improve electrical characteristics of the same by providing a first conductor portion having a flat upper surface on a bonding pad on a principal surface of a semiconductor chip, and further providing sealing resin for exposing only the upper surface of the first conductor portion and sealing the semiconductor chip and a lump- shaped second conductor portion on the upper surface of the first conductor portion. CONSTITUTION: A bonding pad 4 is formed on a principal surface of a semiconductor chip 3, on which pad 4 an insulating layer 11 is formed so as to possess an opening portion. A buffer coated film 13 is formed on the insulating layer 11 so as to ride on a peripheral edge on which a ground metal layer 12 is formed. A connection layer 8 is formed on the ground metal layer 12, on which connection layer a first conductor portion 9 is formed. Sealing resin 1 is formed so as to expose only the upper surface of the first conductor portion ...

Contacts for semiconductor packages

A chip size package is disclosed herein, as well as a method for fabricating the same. A recess is formed in a surface of semiconductor chip. Bonding pads are formed on a bottom center of the recess and insulating pads 30 are formed on both lateral sides of the recess. The respective pads are connected to each other with metal wires. An epoxy compound is filled in the recess. Herein, midway portions of the metal wires are exposed from the epoxy compound. Bumps are formed on the midway portions of the metal wires being exposed from the epoxy compound and solder balls are mounted on the bumps. Therefore, the epoxy compound is not protruded from the semiconductor chip, thickness of the package is equal to that of the semiconductor chip. The thickness of package is minimized.

A routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Semiconductor device having low dielectric insulating film and manufacturing method of the same

A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines. An insulating film is provided on an upper side of the laminated structure portion. Connection pad portions for electrodes are arranged on the insulating film to be electrically connected to the connection pad portions of uppermost wiring lines of the laminated structure portion. Bump electrodes for external connection are provided on the connection pad portions for the electrodes. A sealing film is provided on the insulating film and on the peripheral portion of the semiconductor substrate. Side surfaces of the laminated structure portions are covered with the insulating film or the sealing film.

MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY

Wafer level package and method of manufacturing the same

SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME

반도체 장치 및 그 제조 방법

... 반도체 장치(1)는 관통공(7)이 형성된 반도체 기판(2)과, 반도체 기판(2)의 제1 표면(2a)에 마련된 제1 배선(3)과, 관통공(7)의 내면(7c) 및 반도체 기판(2)의 제2 표면(2b)에 마련된 절연층(10)과, 절연층(10)의 표면(10b)에 마련되고, 개구(10a)에 있어서 제1 배선(3)에 전기적으로 접속된 제2 배선(8)을 구비한다. 절연층(10)의 표면(10b)은 제1 영역(11)과, 제2 영역(12)과, 제3 영역(13)과, 제1 영역(11)과 제2 영역(12)을 연속적으로 접속하도록 만곡된 제4 영역(14)과, 제2 영역(12)과 제3 영역(13)을 연속적으로 접속하도록 만곡된 제5 영역(15)을 포함한다. 제2 영역(12)의 평균 경사 각도는, 제1 영역(11)의 평균 경사 각도보다도 작고, 또한 내면(7c)의 평균 경사 각도보다도 작다.

Sensor packages and manufactuirng methods thereof

Electronic device having a redistribution area

An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

Packages formed using RDL—last process

A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

CONDUCTIVE PATHS THROUGH DIELECTRIC WITH A HIGH ASPECT RATIO FOR SEMICONDUCTOR DEVICES

Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate. A post is formed on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is formed over the semiconductor substrate including over the connection pads and the posts. Holes are formed by removing the dielectric layer directly over the posts. The formed holes are filled with a conductive material and a connector is formed over each filled hole.

SEMICONDUCTOR PACKAGE HAVING REDISTRIBUTION PATTERN AND PASSIVATION PATTERNS AND METHOD OF FABRICATING THE SAME

A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

Chipträger und Halbleitervorrichtung mit Umverteilungsstrukturen sowie Verfahren zur Herstellung einer Umverteilungsstruktur

Chipträger, umfassend eine Umverteilungsstruktur (500), wobei die Umverteilungsstruktur (500) umfasst:eine dielektrische Schicht (12), welche sich in einer horizontalen Richtung erstreckt;eine erste elektrisch leitfähige Schicht (16A), welche über der dielektrischen Schicht (12) angeordnet ist und sich in der horizontalen Richtung erstreckt;eine zweite elektrisch leitfähige Schicht (16B), welche sich in der horizontalen Richtung erstreckt und elektrisch mit der ersten elektrisch leitfähigen Schicht (16A) gekoppelt ist, wobei die dielektrische Schicht (12) zwischen der ersten elektrisch leitfähigen Schicht (16A) und der zweiten elektrisch leitfähigen Schicht (16B) angeordnet ist, wobei die erste elektrisch leitfähige Schicht (16A) und die zweite elektrisch leitfähige Schicht (16B) ausgelegt sind, um elektrische Ströme in einer gleichen horizontalen Richtung zu leiten;einen Graben (18), welcher in der dielektrischen Schicht (12) angeordnet ist und sich in der horizontalen Richtung erstreckt ...

Flip-chip type semiconductor device with stress absorbing laYer made of resin

A flip-chip type semiconductor device, or method of manufacturing such a device, wherein the device comprises; an insulating stress absorbing resin layer 14, 34 made of thermosetting resin film on a semiconductor substrate 11, 31. The thermosetting resin has openings corresponding to pad electrodes 12, 32 formed on the substrate. A plurality of flexible conductive members 16, 38 fills each one of the openings. A plurality of metal bumps 17 are formed on the flexible conductive members. Alternatively, the plurality of metal bumps (39, Figure 14Q) may each be formed on a plurality of conductive members 35, 37. The conductive members may be formed on a second photosensitive insulating stress absorbing resin layer (34' , Figure 14Q) which may be formed on a first insulating stress absorbing resin layer (34, Figure 14Q). The thermosetting resin may be for example, epoxy resin, silicone resin, polymide resin, polyolefin resin, cyanate-ester resin, phenol resin, naphthalene resin and fluorene ...

SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

Chip package and manufacturing method thereof

Face-up fan-out electronic package with passive components using a support

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes: (1) a die having an active surface, a back surface opposite to the active surface and a lateral surface extending between the active surface and the back surface; (2) a first conductive pillar disposed on the active surface of the die and electrically connected to the die, the first conductive pillar having a top surface facing away from the die and a lateral surface substantially perpendicular to the top surface of the first conductive pillar; (3) a dielectric layer disposed on the active surface of the die and fully covering the lateral surface of the first conductive pillar; and (4) a package body encapsulating the back surface and the lateral surface of the die.

SEMICONDUCTOR PACKAGE

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area

A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

Under land routing

Semiconductor package, semiconductor module, electronic component and method for manufacturing semiconductor package and semiconductor module

반도체 장치

... 관통 공(7)은 수직 구멍이다. 관통 공(7)의 중심선 CL을 포함한 평면에 대해 중심선 CL의 양측 영역의 각각에 주목한 경우에 있어서, 절연층(10)의 개구(10a)의 가장자리에 대응하는 제1 점 X1과 제2 개구(7b)의 가장자리에 대응하는 제2 점 X2를 연결하는 선분을 제1 선분 S1로 하고, 제2 점 X2와 제2 개구(7b)와 절연층(10)의 표면(10b)이 교차하는 점에 대응하는 제3 점 X3을 연결하는 선분을 제2 선분 S2로 하며, 제3 점 X3과 제1 점 X1을 연결하는 선분을 제3 선분 S3으로 한다. 이 때, 제1 선분 S1에 대해 한쪽 측에 위치하는 절연층(10)의 제1 면적 A1은, 제1 선분 S1, 제2 선분 S2, 및 제3 선분 S3에 의해 둘러싸이는 절연층(10)의 제2 면적 A2와, 제3 선분 S3에 대해 다른쪽 측에 위치하는 절연층(10)의 제3 면적 A3의 합보다 크다.

Semiconductor device

A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are separated in the horizontal direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure there beneath in the vertical direction.

Semiconductor package structure

Semiconductor package structure is provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer. FIG. 5B ...

COVERLAY COMPOSITIONS AND METHODS RELATING THERETO

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydhde, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

Formation of circuitry with modification of feature height

A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Redistribution layer structures for integrated circuit package

A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

WAFER-LEVEL DIE ATTACH METALLIZATION

Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries ...

Electronic Component and Method

In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.

Semiconductor device

Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same

A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.

THROUGH-SUBSTRATE CONDUCTOR SUPPORT

In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film is formed over each side surface of a copper redistribution line. The barrier film includes, for example, a manganese oxide film. The barrier film is also in contact with each end surface of a barrier metal film that is located in the position receding inward from the side surface of the copper redistribution line. A redistribution portion is formed by the copper redistribution line, the barrier film, and the barrier metal film.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device improving the strength of the adhesion of a chip side land to a solder ball, and suppressing the growth of solder ball cracks due to a temperature stress. SOLUTION: This is a BGA package semiconductor device equipped with a wiring layer 1B arranged through an insulating layer 1A on a semiconductor chip 1, and a solder ball 2 arranged in an input and output area (chip side land 1C) formed in each wiring layer 1B. In this case, plural land projecting parts 3 are formed so as to be projected corresponding to the single solder ball 2 at each wiring layer 1B of the chip side land 1C. COPYRIGHT: (C)2001,JPO ...

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Chip package and method for forming the same

An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Novel three dimensional integrated circuits stacking approach

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. 1. A semiconductor device comprising:a contact pad over a substrate;a redistribution layer in electrical connection with the contact pad;a passivation layer over the redistribution layer;an underbump metallization extending through the passivation layer to be in physical contact with a surface of the redistribution layer facing away from the substrate; anda solder ball in physical contact with the underbump metallization, wherein the solder ball is laterally separated from the redistribution layer in a direction parallel with a major surface of the substrate.2. The semiconductor device of claim 1 , wherein the underbump metallization comprises a reflowable material along a top surface of the underbump metallization.3. The semiconductor device of claim 1 , wherein the underbump metallization extends through the passivation layer at two or more locations.4. The semiconductor device of claim 1 , wherein the redistribution layer comprises a plurality of sub-layers.5. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of sub-layers.6. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of connection branches.7. The semiconductor device of claim 1 , wherein a sidewall of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view. 1. A semiconductor device , including:a first pad;an insulating film covering the first pad;a first opening exposing part of a surface of the first pad from the insulating film;a first polyimide film having a second opening in communication with the first opening;a first interconnection filling the first opening and the second opening, and provided on the first polyimide film;a second polyimide film covering the first interconnection; anda third opening exposing part of the first interconnection from the second polyimide film,wherein the first polyimide film is provided only in a region that is planarly superposed on the first interconnection.2. The semiconductor device according to claim 1 , wherein when an interconnection length direction of the first interconnection is defined as first direction claim 1 , and an interconnection width direction claim 1 , intersecting with the first direction claim 1 , of the first interconnection is defined as second direction claim 1 , width in the second direction of the first polyimide film is equal to width in the second direction of the first interconnection.3. A method of manufacturing a semiconductor device claim 1 , the method comprising:(a) forming an insulating film covering a first pad;(b) forming a first opening in the insulating film, the first opening exposing part of a surface of the first pad;(c) forming a first polyimide film over the insulating film;(d) forming a second opening in the first polyimide film, the ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Process Control for Package Formation

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Semiconductor Package and Method

In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die. 1. A device comprising:a first redistribution structure comprising a first dielectric layer;a die adhered to a first side of the first redistribution structure;an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds;a through via extending through the encapsulant; andfirst conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.2. The device of claim 1 , wherein the encapsulant comprises a molding compound and a nucleophile.3. The device of claim 2 , wherein the nucleophile is ethylene glycol claim 2 , 2-ethoxyethanol claim 2 , or ethanolamine hydrochloride.4. The device of claim 2 , further comprising:an adhesive adhering the die to the first dielectric layer, the adhesive being bonded to the first dielectric layer with second covalent bonds.5. The device of claim 4 , wherein the adhesive comprises an epoxy and the nucleophile.6. The device of claim 1 , wherein each respective conductive connector of the subset of the first conductive connectors has a width claim 1 , wherein at least one quarter of the width of each respective conductive connector is disposed over the die claim 1 , wherein at least one quarter of the width of each respective conductive connector is disposed over the ...

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Package Systems Having Interposers

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. 1. A method comprising:providing a first substrate;forming a first interconnect layer on the first substrate;attaching the first interconnect layer to a second substrate;removing the first substrate;forming electrical connections on the first interconnect layer;forming a molding compound over the first interconnect layer, the molding compound encircling each of the electrical connections;forming a second interconnect layer on the molding compound; andremoving the second substrate.2. The method of claim 1 , wherein the forming the electrical connections on the first interconnect layer comprises:forming a patterned layer over the first interconnect layer, the patterned layer having openings;forming a conductive material in the openings; andremoving the patterned layer.3. The method of claim 2 , further comprising forming a conductive seed layer over the first interconnect layer prior to the forming the patterned layer claim 2 , and further comprising removing exposed portions of the conductive seed layer after the removing the patterned layer.4. The method of claim 1 , further comprising attaching a semiconductor substrate between adjacent ones of the electrical connections prior to the forming the molding compound.5. The method of claim 4 , wherein the molding compound extends over the semiconductor substrate.6. The method of claim 1 , further comprising forming external electrical connectors on the first interconnect layer prior to attaching to ...

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a chip, an isolation layer on the bottom surface and the sidewall, a redistribution layer that is on the isolation layer and in electrical contact with a side surface of the conductive pad, and a passivation layer. The chip has a sensor, at least one conductive pad, a top surface, a bottom surface, and a sidewall. The sensor is located on the top surface. The conductive pad is located on an edge of the top surface. The redistribution layer at least partially protrudes from the conductive pad so as to be exposed. The passivation layer is located on the isolation layer and the redistribution layer, such that the redistribution layer not protruding from the conductive pad is between the passivation layer and the isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer. 1. A chip package , comprising:a chip having a sensor, at least one conductive pad, a top surface, a bottom surface that is opposite the top surface, and a sidewall adjacent to the top surface and the bottom surface, wherein the sensor is located on the top surface, and the conductive pad is located on an edge of the top surface;a first isolation layer located on the bottom surface and the sidewall of the chip;a redistribution layer located on the first isolation layer, and is in electrical contact with a side surface of the conductive pad, wherein the redistribution layer at least partially protrudes from the conductive pad so as to be exposed; anda passivation layer located on the first isolation layer and the redistribution layer, wherein the redistribution layer not protruding from the conductive pad is located between the passivation layer and the first isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer.2. The chip package of claim 1 , wherein an orthogonal projection of the redistribution layer that protrudes from the conductive pad on the passivation ...

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die. 1. A semiconductor package comprising:a first redistribution layer;a first die disposed over the first redistribution layer and having at least one through via therein, wherein the first die comprises at least one sensor;at least one second die and at least one third die, disposed on the first redistribution layer and between the first redistribution layer and the first die;a molding compound disposed on the first redistribution layer, between the first redistribution layer and the first die, and encapsulating the at least one second die and the at least one third die,through interlayer vias (TIVs) arranged through the molding compound, aside the at least one second die and the at least one third die, and between the first redistribution layer and the first die, wherein the TIVs electrically connect the first redistribution layer and the at least one through via of the first die;a dielectric material layer disposed on the molding compound and between the molding compound, the at least one second die, the at least one third die and the first die, wherein the dielectric material layer exposes the at least one through via and the through interlayer vias;conductive elements electrically ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate. 1. A fan-out semiconductor package comprising:a support member having a through-hole;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the support member and the semiconductor chip; anda connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,wherein the support member includes a glass plate and an insulating layer connected to the glass plate.2. The fan-out semiconductor package of claim 1 , wherein the glass plate is an amorphous solid material including a glass component.3. The fan-out semiconductor package of claim 1 , wherein the insulating layer is formed of an insulating material including an insulating resin and an inorganic filler.4. The fan-out semiconductor package of claim 1 , wherein the support member includes a redistribution layer electrically connected to the connection pads.5. The fan-out semiconductor package of claim 4 , wherein the support member further includes vias penetrating through at least one of the glass plate and the insulating layer and electrically connected to the redistribution layer.6. The fan-out semiconductor ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler. 1. A semiconductor device package , comprising:an electronic component;a first set of conductive wires electrically connected to the electronic component; andan insulation layer having a top surface and surrounding the first set of conductive wires, the top surface of the insulation layer exposing a portion of the first set of the conductive wires,wherein the insulation layer is devoid of a filler.2. The semiconductor device package of claim 1 , further comprising an encapsulant encapsulating the electronic component and the insulation layer.3. The semiconductor device package of claim 1 , further comprising a first patterned conductive layer disposed over the insulation layer and including a plurality of conductive pads claim 1 , wherein the conductive pads of the first patterned conductive layer are respectively electrically connected to the exposed portion of the first set of conductive wires.4. The semiconductor device package of claim 3 , whereinthe electronic component comprises a plurality of conductive contacts electrically connected to the first set of the conductive wires; anda pitch between at least two adjacent conductive contacts of the electronic component is less than a pitch between at least two adjacent conductive pads of the first patterned conductive layer.5. The semiconductor device package of claim 1 , further comprising a second set of conductive wires disposed on the insulation layer and electrically connected to the exposed portion of the first set of the conductive wires.6. The semiconductor device package of claim 5 , further comprising an encapsulant covering the electronic component claim 5 , the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture;an electronic device having an interconnect electrically coupled to the first conductor; andan encapsulant on a top side of the substrate contacting a side of the electronic device.2. The semiconductor device of claim 1 , wherein the substrate comprises a third conductor on the top side of the dielectric claim 1 , and a fourth conductor on the bottom side of the dielectric claim 1 , wherein the dielectric has an additional aperture claim 1 , and the third conductor comprises a partial via contacting a pad of the fourth conductor through the additional aperture.3. The semiconductor device of claim 2 , further comprising a trace on the dielectric between the partial via of the first conductor and the partial via of the third conductor.4. The semiconductor device of claim 2 , wherein an end of the partial vial of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.5. The semiconductor device of claim 2 , wherein:the first conductor comprises a first trace on the top side of the dielectric and ...

Semiconductor device with thin redistribution layers

A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

METHOD OF MANUFACTURING 3DIC STRUCTURE

A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film. 1. A method of manufacturing a 3DIC structure , comprising:bonding a die to a wafer;forming a first dielectric layer on the wafer and laterally aside the die;forming a second dielectric material layer on the die and the first dielectric layer;selectively removing a portion of the second dielectric material layer over a non-edge region of the wafer to form a protruding portion over an edge region of the wafer; andplanarizing the second dielectric material layer to form a second dielectric layer on the first dielectric layer and the die.2. The method of claim 1 , where the selectively removing the portion of the second dielectric material layer comprises:forming a mask layer on the second dielectric material layer;pattering the mask layer to form a patterned mask layer having an opening, wherein the patterned mask layer covers the second dielectric material layer on the edge region of the wafer, and the opening exposes the portion of the second dielectric material layer over the non-edge region of the wafer;etching the portion of the second dielectric material layer exposed by the opening, wherein the second dielectric material layer covered by the patterned mask layer form the protruding portion; andremoving the patterned mask layer.3. The method of claim 1 , wherein the planarizing the second ...

SEMICONDUCTOR PACKAGE INCLUDING PLURALITY OF SEMICONDUCTOR CHIPS ON COMMON CONNECTION STRUCTURE

The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer. 1. A semiconductor package , comprising:a first semiconductor chip having a first surface and a second surface opposing the first surface, and including first connection pads and second connection pads disposed on the first surface and the second surface, respectively, and through-vias connected to the second connection pads;a connection structure disposed on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads of the first semiconductor chip;a second redistribution layer disposed on the second surface of the first semiconductor chip and electrically connected to the second connection pads of the first semiconductor chip;a second semiconductor chip disposed on a third surface of the connection structure opposing a fourth surface of the connection structure on which the first semiconductor chip is disposed; anda third semiconductor chip disposed on the third surface of the connection structure and spaced apart from the second semiconductor chip,wherein the second semiconductor chip and the third semiconductor chip are respectively disposed to partially vertically overlap with the first semiconductor chip,wherein in the first semiconductor ...

ELECTRONIC DEVICE

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. 1a first wiring substrate having a first obverse surface, a first reverse surface opposite the first obverse surface, a plurality of first wirings formed in the first wiring substrate, and a plurality of external electrodes formed on the first reverse surface;a second wiring substrate arranged as an interposer having a second obverse surface, a second reverse surface opposite the second obverse surface, and a wiring layer arranged closer to the second obverse surface than the second reverse surface, the second wiring substrate disposed on the first obverse surface of the first wiring substrate such that the second reverse surface faces the first obverse surface of the first wiring substrate;a first semiconductor chip having a first main surface, a first rear surface opposite the first main surface, and a plurality of first electrodes formed on the first main surface, the first semiconductor chip mounted on the second obverse surface of the second wiring substrate such that the first main surface faces the second obverse surface of the second wiring substrate via a first underfill material; anda second semiconductor chip having a second main surface and a plurality of second electrodes formed on the second main surface, the second semiconductor chip mounted side by side with the first semiconductor chip on the second obverse surface of the second wiring substrate such ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. 1. A packaging device comprising:a contact pad over a circuit region of a substrate, the substrate comprising a seal ring proximate a perimeter of the circuit region;a passivation layer over the substrate and over a first portion of the contact pad;a post passivation interconnect (PPI) structure over the passivation layer, wherein the PPI structure is coupled to a second portion of the contact pad;a conductive ball coupled to the PPI structure; anda molding material around the conductive ball, over the PPI structure, and over the passivation layer, wherein the molding material comprises a first thickness directly over the seal ring and a second thickness proximate the conductive ball, the second thickness being greater than the first thickness.2. The package device of claim 1 , wherein the molding material comprises:a first upper surface directly over the seal ring;a second upper surface proximate the conductive ball; anda slanted sidewall connecting the first upper surface and the second upper surface.3. The package device of claim 1 , wherein the conductive ball extends above an uppermost surface of the molding material.4. The package device of claim 1 , wherein the first thickness is about 30 μm or less.5. The package device of claim 1 , wherein the seal ring extends from a first surface of the passivation layer distal the substrate to a second surface of the passivation layer opposing the first surface.6. The package device of claim 5 , wherein the seal ring further extends into the substrate.7. The package ...

ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE

An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer. 1. An electronic device comprising:a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, and a first wiring layer that constitutes a first transmission line that has a predetermined characteristic impedance with the first grounded layer;a mold resin arranged on a side of the semiconductor device;an insulating layer arranged over the semiconductor device and the mold resin;a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer;a second wiring layer formed over the insulating layer and includesa first area disposed at a part overlapping with the second grounded layer anda second area disposed on a side of an end part of the second grounded layer, the first area including a first line width and constituting a second transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the second grounded layer, the second area including a second line width smaller than the first line ...

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. 1. A package comprising:a chip and a molding compound adjacent to each other;a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;a first interconnect structure between the first and second polymer layers;a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; anda conductive bump in an opening defined by the isolation coating and level with the capacitor.2. The ...

Interconnect structure for stacked die in a microelectronic device

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. 120-. (canceled)21. A semiconductor device comprising: a first interposer side;', 'a second interposer side opposite the first interposer side;', 'a first dielectric layer at the first interposer side;', 'a first conductive via that extends through at least the first dielectric layer;', 'a second conductive via at the second interposer side; and', 'a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;, 'an interposer comprising a first die side that faces away from the first interposer side;', 'a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and', 'a lateral die side that extends between the first die side and the second die side;, 'a semiconductor die comprising the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface;', 'no portion of the encapsulating material is substantially vertically higher than the ...

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF

This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer. 1. A method of manufacturing a chip scale sensing chip package , comprising the steps of:providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprises a sensing device and a plurality of conductive pads adjacent to the sensing device nearby the first top surface;providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second bottom surface of the cap wafer to the first top surface of the sensing device wafer by ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided. 1. A method for manufacturing semiconductor devices , the method comprising:forming a conductive pad and a metal protrusion pattern in a metallization layer;conformally depositing a passivation layer over the metallization layer;forming a first opening in the passivation layer to expose the conductive pad;conformally depositing a protection layer over the passivation layer;forming a second opening to expose the conductive pad through the first opening;conformally forming a post-passivation interconnect (PPI) structure on the protection layer, the PPI structure having a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad; andplacing a solder bump on the landing pad region in contact with the protrusion pattern of PPI structure.2. The method of claim 1 , wherein the protrusion pattern of PPI structure is a rectangular stud in or across the landing pad region and adjacent to the connection line.3. The method of claim 1 , wherein the PPI structure is redistribution lines (RDLs) claim 1 , power lines claim 1 , or passive components.4. The method of claim 1 , wherein conformally depositing the protection ...

SEMICONDUCTOR DEVICE WITH FINE PITCH REDISTRIBUTION LAYERS

A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening. 1. A semiconductor device comprising:a semiconductor die comprising a bond pad;a first passivation layer covering a first surface of the semiconductor die, the first passivation layer comprising an opening above the bond pad;a redistribution layer (RDL) on the first passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region;a second passivation layer on the RDL and on a portion of the first passivation layer, the second passivation layer comprising an opening for the connection region of the RDL;an under bump metal (UBM) on the connection region of the RDL and a portion of the second passivation layer; anda bump contact on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer.2. The semiconductor device according to claim 1 , wherein the width of the RDL is constant from the bond pad through at least a portion of the opening.3. The semiconductor device according to claim 1 , wherein the UBM is on a portion of the first passivation layer.4. The semiconductor device according to claim 1 , wherein the connection region comprises a region of the ...

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

Package-on-Package Devices with Upper RDL of WLPS and Methods Therefor

Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region with reference to the first integrated circuit, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located below a first redistribution layer respectively thereof; anda third and a fourth integrated circuit die respectively surface mount coupled over the first and the second wafer-level ...

Semiconductor package and method of fabricating the same

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

FAN-OUT SEMICONDUCTOR PACKAGE AND PACKAGE SUBSTRATE COMPRISING THE SAME

A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate. 1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; andrigid patterns disposed on at least one of the first surface and the second surface of the reinforcing plate.2. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate has an elastic modulus greater than that of the encapsulant.3. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate includes a glass fiber claim 1 , an inorganic filler claim 1 , and an insulating resin.4. The fan-out semiconductor package of claim 3 , further comprising a resin layer disposed on the second surface of the reinforcing plate claim 3 ,wherein the resin layer includes ...

Semiconductor Package and Method of Forming the Same

A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

Embedded Metal Insulator Metal Structure

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors. 1. A method , comprising:depositing a polymer layer on a carrier substrate; forming a first redistribution layer comprising metal lines on a portion of the polymer layer;', 'depositing a photoresist layer on the first redistribution layer;', 'etching the photoresist layer to form spaced apart first and second through interposer via (TIV) openings in the photoresist layer that expose respective portions of a metal line of the redistribution layer, wherein the first TIV opening is wider than the second TIV opening;', 'depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line;', 'removing the photoresist layer;', 'forming a high-k dielectric on a top surface of the first and second TIV structures; and', 'depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors; and, 'forming first and second capacitor structures on the polymer layer, wherein forming the first and second capacitor structures comprisesforming a second redistribution layer on the first and second capacitors.2. The method ...

SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR MODULES INCLUDING THE SEMICONDUCTOR PACKAGES

A semiconductor package includes a semiconductor chip including a chip pad and an external bump pad electrically connected to the chip pad of the semiconductor chip. The external bump pad may include a trench portion extending from a perimeter surface of the external bump pad toward a center of the external bump pad. The semiconductor package includes an external connector on the external bump pad, with the external connector including a portion that is in the trench portion of the external bump pad. 1. A semiconductor package comprising:a semiconductor chip including a chip pad;an external bump pad electrically connected to the chip pad of the semiconductor chip and including a trench portion extending from a perimeter surface of the external bump pad toward a center of the external bump pad; andan external connector on the external bump pad, the external connector including a portion within the trench portion of the external bump pad.2. The semiconductor package of claim 1 , wherein the external connector covers the perimeter surface of the external bump pad.3. The semiconductor package of claim 1 , wherein the trench portion is a first trench portion of a plurality of trench portions claim 1 , and wherein the plurality of trench portions are spaced apart from each other by a uniform distance along a perimeter of the external bump pad.4. The semiconductor package of claim 3 , wherein a distance between adjacent trench portions along the perimeter of the external bump pad is about one to two times a width of the first trench portion.5. The semiconductor package of claim 1 , wherein the external connector covers a portion of the perimeter surface of the external bump pad adjacent to the trench portion claim 1 , and wherein another portion of the perimeter surface of the external bump pad is free from coverage of the external connector.6. The semiconductor package of claim 1 , further comprising an insulating layer on the semiconductor chip claim 1 ,wherein the ...

SEMICONDUCTOR PACKAGES

A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via. 1. A semiconductor package comprising:a package substrate;an external connection terminal electrically connected to the package substrate;a first semiconductor device on the package substrate, the first semiconductor device comprising a through silicon via;a lower redistribution structure between the first semiconductor device and the package substrate, the lower redistribution structure comprising a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via;a package connection terminal between the lower redistribution structure and the package substrate, the package connection terminal being configured to electrically connect the lower redistribution pattern to the package substrate;an upper redistribution structure on the first semiconductor device, the upper redistribution structure comprising an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via;a conductive via in contact with the upper redistribution pattern, the ...

FAN-OUT PACKAGES AND METHODS OF FORMING SAME

An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer. 1. A device package comprising:a semiconductor die;a molding compound extending along sidewalls of the semiconductor die, wherein the molding compound comprises first fillers;a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die, wherein the planarizing polymer layer comprises second fillers smaller than the first fillers, an average thickness of the planarizing polymer layer being no more than about twenty percent of an average thickness of the molding compound; andone or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.2. The device package of claim 1 , wherein the first fillers and the second fillers comprise silicon oxide claim 1 , aluminum oxide claim 1 , boron nitride claim 1 , or a combination thereof.3. The device package of further comprising a through-intervia (TIV) extending through the molding compound and the planarizing polymer layer claim 1 , wherein the TIV is electrically connected to the one or more fan-out RDLs.4. The device package of claim 1 , wherein the first fillers comprise an average diameter of about 25 μm or less claim 1 , and wherein the second fillers comprise an ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance. 1. A method of forming a packaging device , the method comprising:forming a contact pad over a substrate;forming a passivation layer over the substrate and a first portion of the contact pad yet leaving a second portion of the contact pad exposed;forming a post passivation interconnect (PPI) line and a PPI pad over the passivation layer, the PPI line being coupled to the second portion of the contact pad, the PPI pad being coupled to the PPI line;depositing a first insulating material over the PPI line, the PPI pad, and the passivation layer; andpatterning the first insulating material to expose the PPI pad, wherein after the patterning, the first insulating material has a first sidewall spaced apart from a second sidewall of the PPI pad by a predetermined distance, the first sidewall of the first insulating material extending below a top surface of the PPI pad.2. The method of further comprising:forming a conductive material on the PPI pad.3. The method of further comprising:depositing a second insulating material over the first insulating material and surrounding at least a lower portion of the conductive material, the second insulating material being interposed between the first sidewall of the first insulating material and the second sidewall ...

Multi-chip package having encapsulation body to replace substrate core

A multi-chip package having no substrate is presented. The multi-chip package includes a chip stacked assembly, a first redistribution layer, a plurality of wire bonds, a plurality of metal pillars, an encapsulation, a second redistribution layer, and a plurality of vertical interposers. The first redistribution layer and the second redistribution layer are used in place of a substrate to reduce the thickness of the multi-chip package. In this way, a package-on-package device formed using the multi-chip package has a reduced thickness.

Package Structures and Method of Forming the Same

An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND METHOD OF FORMING THE SAME

A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer. 1. A semiconductor device comprising:a first passivation layer over an interconnect structure;a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure, wherein the first RDL via comprises a first conductive material;an RDL over the first passivation layer and electrically connected to the first RDL via, wherein the RDL comprises a second conductive material different from the first conductive material, and the RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer; anda second passivation layer over the RDL, wherein a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to the top surface of the first passivation layer.2. The semiconductor device of claim 1 , wherein a top surface of the RDL over the first RDL via is substantially flat.3. The semiconductor device of claim 1 , wherein a top surface of the second passivation layer over the RDL is substantially flat.4. The semiconductor device of claim 1 , wherein the second passivation layer over the RDL is free of voids.5. The semiconductor device of claim 1 , wherein the first RDL via comprises copper and the RDL comprises aluminum.6. The semiconductor ...

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer. 1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; anda second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip,wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad,the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad,the redistribution layer of the second interconnection member is connected to the connection pad through a via, andthe via lies over at ...

Methods Of Forming Microvias With Reduced Diameter

A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer. 1. A method of forming a microvia , the method comprising:depositing a conductive seed layer on a substrate;depositing a first conductive layer on the conductive seed layer;patterning the first conductive layer to form first conductive lines or capture pads;depositing a first dielectric layer;patterning the first dielectric layer to form at least one via having a diameter;depositing a conductive material into the at least one via to form at least one conductive pillar with a height;removing the first dielectric layer and the conductive seed layer from the substrate; anddepositing a second dielectric layer around the at least one conductive pillar.2. (canceled)3. The method of claim 1 , further comprising performing an ashing process after removing the first dielectric layer and the conductive seed layer.4. The method of claim 1 , further comprising:depositing the second dielectric layer with a thickness greater than the height of the at least one conductive pillar; andplanarizing the second dielectric layer to expose a top of the at least one conductive pillar.5. The method of claim 1 , further comprising:depositing a second conductive layer on the second dielectric layer and the at least one conductive pillar; andpatterning the second conductive layer to form second conductive lines or capture pads.6. The method of claim 1 , wherein the conductive seed layer and the conductive material comprise copper.7. The method of claim 1 , wherein the first dielectric layer comprises a photosensitive dielectric and patterning at least one via into the first dielectric layer comprises a photolithography process.8. The method of claim 7 , wherein the ...

WAFER-LEVEL CHIP SCALE PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer. 1. A method for preparing a wafer-level chip scale packaging structure , comprising:placing a first chip on a first supporting substrate;forming a first packaging layer on the first chip, wherein the first packaging layer comprises a first surface and a second surface opposing to each other, wherein the first chip is in contact of the first surface;separating the first packaging layer and the first chip from the first supporting substrate at the first surface of the first packaging layer;attaching the second surface of the first packaging layer to a second supporting substrate;disposing a second packaging layer on the first surface of the first packaging layer;forming a rewiring layer on the second packing layer, wherein the rewiring layer is electrically connected to the first chip; andattaching a second chip to the rewiring layer, wherein the second chip is electrically connected to the rewiring layer.2. The method for preparing a wafer-level chip scale packaging structure according to claim 1 , further comprising:before placing the first chip on the first supporting substrate, coating a release layer on the first ...

SEMICONDUCTOR DEVICE AND A CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A semiconductor device includes a passivation layer, an interconnection metallization having a peripheral portion over the passivation layer, and an outer surface coating on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating. 1. A semiconductor device comprising:a dielectric layer;a passivation layer over the dielectric layer;a via through said passivation layer and said dielectric layer;an interconnection metallization arranged over said via and having a metallization body and a peripheral portion on the passivation layer, an outer surface coating that coats said metallization body; anda diffusion barrier layer, separating the peripheral portion of the interconnection metallization from the passivation layer, said diffusion barrier layer comprises an inner planar portion deposited on the passivation layer and a peripheral portion, having a thickness substantially equal to the inner planar portion and extending along a plane at a vertical height higher than a surface of the passivation layer on which the inner planar portion of the barrier layer extends, so that said peripheral portion of the diffusion barrier layer forms with said inner portion a step in said diffusion barrier layer, wherein:said outer surface coating has a vertical wall with a foot that is adjacent to said peripheral portion of the diffusion barrier layer and is positioned at said ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer. 1. A semiconductor device , comprising:a semiconductor substrate comprising a chip region and an edge region;a lower dielectric layer on the semiconductor substrate;a chip pad on the lower dielectric layer of the chip region;an upper dielectric layer on the lower dielectric layer, the upper dielectric layer comprising a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region; anda redistribution pad connected to the chip pad, the redistribution pad comprising a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.2. The semiconductor device of claim 1 , wherein the lower dielectric layer comprises a dielectric material whose dielectric constant is less than that of the upper dielectric layer.3. (canceled)4. The semiconductor device of claim 1 , wherein claim 1 , on the edge region claim 1 , the lower dielectric layer comprises a first segment having a first thickness and a second segment having a second thickness less than the first thickness.5. The semiconductor device of claim 1 , wherein the lower dielectric layer has a first thickness on the chip region and a portion of the lower dielectric layer on the edge region has a second thickness claim 1 , the second thickness being less than the first thickness.6. (canceled) ...

Semicondcutor device and semicondcutor package

A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads. 1. A package comprising: a first die having a first active side and a first back-side, the first active side comprising a first bond pad and a first insulating layer;', 'a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side comprising a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds; and', 'a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads., 'a first package structure comprising2. The package of claim 1 , wherein the first insulating layer is bonded to the second insulating layer with respective bonds comprising O—H bonds.3. The package of claim 1 , wherein the first bond pad is recessed into the first insulating layer.4. The package of claim 1 , wherein the first insulating layer and the second insulating layer are both made of a polymer.5. The ...

LTHC as Charging Barrier in InFO Package Formation

A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post. 1. A method comprising:forming a release film over a carrier;forming a polymer buffer layer over the release film;forming a metal post on the polymer buffer layer;encapsulating the metal post in an encapsulating material;performing a planarization on the encapsulating material to expose the metal post;forming a redistribution structure over the encapsulating material and the metal post;decomposing a first portion of the release film, wherein a second portion of the release film remains after the decomposing; andforming an opening in the polymer buffer layer to expose the metal post.2. The method of further comprising:bonding a package component to the metal post; anddispensing an underfill between the package component and the second portion of the release film.3. The method of claim 1 , wherein the decomposing the first portion of the release film is performed by projecting a laser beam on the release film.4. The method of claim 1 , wherein the release film comprises a polymer base material and carbon black particles.5. The method of further comprising removing the second portion of the release film before the opening is formed in the polymer buffer layer.6. The method of claim 1 , wherein the opening extends into both the polymer buffer layer and the second portion of the release film.7. The method of claim 1 , wherein the first portion of the release film has a first thickness before the ...

HETEROGENEOUS FAN-OUT STRUCTURE AND METHOD OF MANUFACTURE

A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device. 1. A method comprising:attaching an integrated circuit die to a carrier, the integrated circuit die having a first thickness;attaching an interposer to the carrier, the interposer comprising a substrate and a conductive pillar in physical contact with the substrate, the substrate having a second thickness less than the first thickness, a bottommost surface of the substrate being level with a bottommost surface of the integrated circuit die, the bottommost surface of the substrate and the bottommost surface of the integrated circuit die facing the carrier; andforming an encapsulant in physical contact with a sidewall of the substrate, a sidewall of the conductive pillar, and a sidewall of the integrated circuit die, wherein a topmost surface of the conductive pillar is level with a topmost surface of the encapsulant, and wherein the topmost surface of the conductive pillar and the topmost surface of the encapsulant face away from the carrier.2. The method of claim 1 , further comprising forming a first redistribution layer over and in electrical contact with the interposer and the integrated circuit die.3. The method of claim 1 , wherein the interposer comprises an annular structure claim 1 , and wherein the integrated circuit die is disposed within the annular structure.4. The method of claim 1 , further comprising forming the interposer claim 1 , wherein forming the interposer comprises:forming conductive routing within the substrate;plating conductive pillars onto the substrate and in electrical contact with the conductive routing; andforming a hole in ...

Structure and formation method of package structure with stacked semiconductor dies

A structure and a formation method of a package structure are provided. The method includes disposing a first semiconductor die over a carrier substrate and forming a first protective layer to surround the first semiconductor die. The method also includes forming a dielectric layer over the first protective layer and the first semiconductor die. The method further includes patterning the dielectric layer to form an opening partially exposing the first semiconductor die and the first protective layer. In addition, the method includes bonding a second semiconductor die to the first semiconductor die after the opening is formed. The method includes forming a second protective layer to surround the second semiconductor die.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure. 1. A semiconductor device package , comprising:a first semiconductor device having a first conductive terminal and a second conductive terminal;a first redistribution layer (RDL) structure covering the first conductive terminal; anda second RDL structure covering the second conductive terminal and separated from the first RDL structure.2. The semiconductor device package of claim 1 , further comprising a first conductive layer covering a first surface of the first conductive terminal.3. The semiconductor device package of claim 2 , wherein the first conductive layer covers a second surface of the first conductive terminal claim 2 , and wherein the second surface of the first conductive terminal is different from the first surface and lateral to the first surface.4. The semiconductor device package of claim 1 , further comprising:a first interconnection structure electrically connected to the first RDL structure;a second interconnection structure electrically connected to the first interconnection structure; anda first anti-oxidation structure disposed between the first interconnection structure and the second interconnection structure.5. The semiconductor device package of claim 4 , wherein the first anti-oxidation structure has a first width and the first interconnection structure has a second width claim 4 , and wherein the first width is equal to or greater than the second width.6. The semiconductor device package of claim 4 , wherein the first anti-oxidation structure has a first width and the second interconnection structure has a second width claim 4 , ...

Semiconductor device and method of manufacturing semiconductor device

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film. 1. A method of manufacturing a semiconductor device , comprising:defining an element formation region and a scribe region in a semiconductor substrate;forming a semiconductor element in the element formation region;forming a plurality of wiring layers above the semiconductor element;forming, with one of uppermost wiring layers of the wiring layers as a first pad electrode, a first insulating film so as to cover the first pad electrode therewith;forming, in the first insulating film, a first opening portion from which the first pad electrode is exposed;forming a rewiring over the first insulating film so as to couple the rewiring to the first pad electrode via the first opening portion;forming a second insulating film that covers the rewiring and has a second opening portion communicated with the rewiring;forming a barrier film over at least a portion of the surface of the rewiring at which the second opening portion is present;after formation of the barrier film, testing the semiconductor element while heat treating; andcoupling, to the barrier film, a coupling member for electrical coupling to the outside, 'forming at least a film having any one of materials selected from the group comprised of palladium (Pd), ruthenium (Ru), rhodium (Rh), platinum (Pt), and iridium (Ir),', 'wherein ...

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. 1. A method comprising:forming a dielectric layer on a surface of a substrate, the dielectric layer having a first opening exposing a contact pad;forming a seed layer over the dielectric layer, the seed layer extending into the first opening to the contact pad;forming a first mask layer over the seed layer, the first mask layer having a second opening exposing the seed layer;forming a second mask layer in the second opening;forming a third mask layer over the second mask layer, the third mask layer having a third opening exposing the second mask layer;removing the second mask layer, thereby forming a fourth opening; andforming a conductive material in the fourth opening.2. The method of claim 1 , wherein the third mask layer does not extend over an upper surface of the first mask layer.3. The method of claim 1 , wherein a first slope a sidewall of the second opening is different than a second slope of a sidewall of the fourth opening.4. The method of claim 1 , further comprising removing the first mask layer and the second mask layer claim 1 , wherein the conductive material comprises an indent extending between a first sidewall adjacent the seed layer and second sidewall extending to an uppermost surface of the conductive material.5. The method of claim 4 , wherein the second sidewall is non-perpendicular.6. ...

Semiconductor package, semiconductor device using the same and manufacturing method thereof

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation. 1. A semiconductor structure , comprising:a substrate including a first surface and a second surface opposite to the first surface;a pad disposed over the first surface;a first passivation disposed over the first surface and partially covering the pad; anda redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line;wherein the conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, the land portion includes a plurality of first protrusions protruded away from the first passivation.2. The semiconductor structure of claim 1 , wherein the plurality of first protrusions are exposed from the second passivation.3. The semiconductor structure of claim 1 , further comprising a conductive member disposed between the substrate and the land portion of the conductive line.4. The semiconductor structure of claim 1 , wherein the land portion includes a plurality of second protrusions protruded towards the substrate and surrounded by the first passivation.5. The semiconductor structure of claim 4 , wherein ...

Semiconductor structure and method of manufacturing thereof

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS

A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units. 1. A semiconductor chip comprising:a first to a fourth bump areas that are provided on a surface of the semiconductor chip;a first to a fourth conductive lines that are provided on the surface and are connected to the first to the fourth bump areas, respectively; anda first and a second conductive rings that are provided inside the semiconductor chip,wherein the first conductive line and the first conductive ring are electrically connected to each other through a first internal interconnection line provided at a first point of a first row of the surface,wherein the second conductive line and the second conductive ring are electrically connected to each other through a second internal interconnection line provided at a second point of a second row of the surface,wherein the third conductive line and the first conductive ring are electrically connected to each other through a third internal interconnection line provided at a third point of a third row of the surface, andwherein the fourth conductive line and the second conductive ring are electrically connected to each other through a fourth internal interconnection line ...

Semicondcutor package and manufacturing method thereof

A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure. 1. A semiconductor package , comprising:a die;a dummy cube, disposed beside the die;a stress relaxation layer, covering a top surface of the dummy cube;an encapsulant encapsulating the die and the dummy cube; anda redistribution structure disposed over the encapsulant and electrically connected to the die,wherein the stress relaxation layer is interposed between the dummy cube and the redistribution structure.2. The semiconductor package of claim 1 , wherein the dummy cube is electrically isolated from the redistribution structure.3. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a portion of the encapsulant.4. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer claim 1 , and the polymeric layer is not in physical contact with the redistribution structure.5. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a first polymeric layer and a second polymeric layer claim 1 , and a material of the first polymeric layer is different from a material of the second polymeric layer.6. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer extending from the top surface of the dummy cube to the redistribution structure.7. The semiconductor package of claim 6 , wherein a material of the polymeric layer comprises polyimide claim 6 , polybenzooxazole claim 6 ...

SEMICONDUCTOR DEVICE WITH CONDUCTIVE FILM SHIELDING

A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die. 1. A method of assembling a plurality of semiconductor devices , comprising:attaching a plurality of wafer level semiconductor devices to a carrier, wherein active sides of the devices are attached to the carrier, and passive sides of the devices are face-up; andcovering the passive sides of the devices with a conductive film, wherein the conductive film also covers lateral sides of the devices.2. The method of claim 1 , wherein the conductive film is laminated to the passive and lateral sides of the devices.3. The method of claim 1 , herein the semiconductor devices comprise wafer-level chip scale packages (WLCSP) that include conductive balls on the active sides.4. The method of claim 3 , wherein the wafer-level chip scale packages include a redistribution layer formed between semiconductor dies thereof and the conductive balls.5. The method of claim 1 , wherein the conductive film comprises a die attach film with an inner metal filler.6. The method of claim 5 , wherein the wafer-level chip scale packages include a redistribution layer formed between semiconductor dies thereof and the conductive balls claim 5 , and the conductive film is electrically connected to the redistribution layer.7. The method of claim 1 , further comprising:attaching a metal carrier to a top, exposed surface of the conductive film.8. The method of claim 7 , wherein the metal carrier is attached to the conductive film with an adhesive.9. The method of claim 1 , further comprising:separating adjacent ones of the film-covered devices from each other to provide individual shielded devices.10. A packaged semiconductor device assembled ...

Anisotropic Carrier for High Aspect Ratio Fanout

A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

PACKAGE STRUCTURE AND BONDING METHOD THEREOF

A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package structure is also provided. 1. A package structure , comprising: a plurality of vias; and', 'a plurality of pads, disposed on the first substrate, and filling in the vias;, 'a first substrate, comprisinga second substrate, disposed opposite to the first substrate;a plurality of conductive pillars, each of the conductive pillars electrically connecting each of the pads and the second substrate, each of the conductive pillars filling in each of the vias; andan adhesive layer, disposed between the first substrate and the second substrate, the adhesive layer filling in gaps between the conductive pillars.2. The package structure according to claim 1 , wherein each of the pads is conformal with each of the vias.3. The package structure according to claim 1 , wherein each of the pads has a dimple claim 1 , and each of the conductive pillars electrically connects each of the dimples.4. The package structure according to claim 1 , wherein the adhesive layer comprises one of a non-photosensitive adhesive or a photosensitive adhesive.5. The package structure according to claim 4 , further comprising:a planarization layer, disposed on the second substrate, the planarization layer being located between the second substrate and the conductive pillars; anda macromolecular adhesive layer, disposed on the adhesive layer, the macromolecular adhesive layer filling in the gaps between the conductive pillars.6. A bonding method of a package structure claim 4 , comprising: ...

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

PAD STRUCTURE AND MANUFACTURING METHOD THEREOF IN SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region. 1. A method of manufacturing a semiconductor device , comprising:forming a conductive pad region over a substrate;depositing a dielectric layer over the conductive pad region;forming a first passivation layer over the dielectric layer;etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region;forming a second passivation layer over the first area of the conductive pad region; andremoving portions of the second passivation layer to expose a second area of the conductive pad region.2. The method according to claim 1 , wherein removing portions of the second passivation layer comprises etching the second passivation layer using a self-aligned scheme.3. The method according to claim 1 , wherein etching the first passivation layer through the dielectric layer comprises exposing a sidewall of the dielectric layer claim 1 , and wherein forming a second passivation layer over the first area of the conductive pad region comprises forming the second passivation layer covering the sidewall of the dielectric layer.4. The method according to claim 1 , wherein removing portions of the second passivation layer comprises exposing a horizontal portion of the first passivation layer.5. The method according to claim 1 , wherein removing portions of the second passivation layer comprises etching a portion of the first passivation layer.6. The method according to claim 5 , wherein ...

COMPOSITE BOND STRUCTURE IN STACKED SEMICONDUCTOR STRUCTURE

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer. 1. A semiconductor device , comprising:a substrate;a dielectric structure disposed on the substrate;a top metal layer disposed in the dielectric structure; anda bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:a silicon oxide layer disposed on the dielectric structure;a silicon oxy-nitride layer covering the silicon oxide layer and physically contacting the silicon oxide layer;a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; anda barrier layer covering a sidewall and a bottom of the conductive bonding layer.2. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second elevation ranges from substantially −50 angstroms to substantially 100 angstroms.3. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads. 1. A fan-out semiconductor package comprising:a rigid member having a through-hole;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface;a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip;a connection member disposed on the rigid member, the dummy chip, and the active surface of the semiconductor chip; andan encapsulant encapsulating at least portions of the rigid member, the dummy chip, and the inactive surface of the semiconductor chip,wherein the connection member includes a redistribution layer electrically connected to the connection pads.2. The fan-out semiconductor package of claim 1 , wherein the dummy chip is electrically insulated from the semiconductor chip.3. The fan-out semiconductor package of claim 1 , wherein the dummy chip decreases a warpage generated through disposition of the semiconductor chip.4. The fan-out semiconductor package of claim 1 , wherein the rigid member includes a first redistribution layer exposed to a first surface thereof and contacting the connection member claim 1 , and a second ...

SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS AND METHOD FOR FABRICATING THE SAME

The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor Substrate, an integrated device ort the semiconductor substrate, a first redistribution layer on the semiconductor substrate, the first redistribution layer having first conductive patterns electrically connected to the integrated device, a second redistribution layer on the first redistribution layer, the second redistribution layer having second conductive patterns connected to the first conductive patterns, and third conductive patterns on a top surface of the second redistribution layer. The third conductive patterns include pads connected to the second conductive patterns, under-bump pads spaced apart from the pads, a grouping pattern between the pads and an outer edge of the second redistribution layer, and wiring lines that connect the under-bump pads to the pads and connect the pads to the grouping pattern.

BONDING STRUCTURE AND METHOD OF FORMING SAME

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads 1. A method comprising:forming an insulating layer over an interconnect structure;forming a conductive element over the insulating layer, the conductive element extending through the insulating layer to electrically connect to the interconnect structure;forming a first stop layer extending over the insulating layer and extending over sidewalls and a top surface of the conductive element;forming a second insulating layer over the first stop layer;forming a second stop layer over the first stop layer, wherein the second stop layer physically contacts a top surface of the second insulating layer and physically contacts a top surface of the first stop layer;forming a bonding layer over the second stop layer; andforming a first bonding pad in the bonding layer.2. The method of further comprising performing a planarization process on the second insulating layer using the first stop layer as a planarization stop layer.3. The method of claim 2 , wherein after performing the planarization process claim 2 , a first thickness of the first stop layer over the insulating layer is greater than a second thickness of the first stop layer over the conductive element.4. The method of claim 1 , wherein forming a first bonding pad in the bonding layer comprises:etching an opening in the bonding layer using the second stop layer as an etch stop; andetching an opening in the first stop layer to expose the conductive element.5. The method of claim 1 , wherein forming the first bonding pad in the bonding layer comprises ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE

Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

PHOTOSENSITIVE RESIN COMPOSITION AND ELECTRONIC COMPONENT

Provided is a resin which has high elongation, low stress, high sensitivity and high film retention ratio if used in a photosensitive resin composition. A photosensitive resin composition that contains a resin which has a structure represented by general formula (1) and/or general formula (2), and which is characterized in that (a) 10-80% by mole of an organic group having an alicyclic structure and 4-40 carbon atoms is contained as the Rmoiety of general formulae (1) and (2), and (b) 10-80% by mole of an organic group having a polyether structure with 20-100 carbon atoms is contained as the Rmoiety of general formulae (1) and (2). (In general formulae (1) and (2), Rrepresents a tetravalent organic group having a monocyclic or condensed polycyclic alicyclic structure and 4-40 carbon atoms; Rrepresents a divalent organic group having a polyether structure with 20-100 carbon atoms; Rrepresents a hydrogen atom or an organic group having 1-20 carbon atoms; each of n1 and n2 represents a number within the range of 10-100,000; and p and q represents integers satisfying 0≦p+q≦6.) 4. The photosensitive resin composition according to claim 1 , wherein the resin having a structure represented by the general formula(e) (1) and/or (2) further comprises an organic group as Rat 20 to 90 mol % claim 1 , the organic group containing a fluorine atom.5. The photosensitive resin composition according to claim 1 , further comprising a photo acid generator.6. The photosensitive resin composition according to claim 5 , further comprising a multifunctional acrylate compound.7. A photosensitive sheet formed of the photosensitive resin composition according to .8. A method for producing a photosensitive sheet claim 1 , comprising the step of coating a base material with the photosensitive resin composition according to and drying the composition.9. A cured film obtained by curing the photosensitive resin composition according to .10. A cured film obtained by curing the photosensitive sheet ...

WAFER LEVEL PACKAGE (WLP) INTEGRATED DEVICE COMPRISING ELECTROMAGNETIC (EM) PASSIVE DEVICE IN REDISTRIBUTION PORTION, AND RADIO FREQUENCY (RF) SHIELD

Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal. 1. An integrated device comprising:a substrate;a plurality of lower level metal layers;a plurality of lower level dielectric layers; and a first dielectric layer comprising a first dielectric thickness; and', 'an electromagnetic (EM) passive device comprising a first redistribution interconnect, wherein the first redistribution interconnect comprises a first redistribution thickness, the first dielectric thickness being at least about 2 times (2×) greater than the first redistribution thickness., 'a redistribution portion comprising2. The integrated device of further comprises a radio frequency (RF) shield.3. The integrated device of claim 2 , wherein the RF shield is located between a passivation layer and the plurality of lower level dielectric layers.4. The integrated device of claim 2 , wherein the RF shield is located between the EM passive device and the plurality of lower level dielectric layers.5. The integrated device of claim 2 , wherein the RF shield is coupled ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a die, a molding surrounding the die, an interconnect structure disposed over the die and the molding, and a first seal ring. The interconnect structure includes a dielectric layer and a conductive member disposed within the dielectric layer. The first seal ring is disposed within the dielectric layer and disposed over the molding. 1. A semiconductor structure , comprising:a die;a molding surrounding the die;an interconnect structure disposed over the die and the molding, and including a dielectric layer and a conductive member disposed within the dielectric layer; anda first seal ring is disposed within the dielectric layer and disposed over the molding.2. The semiconductor structure of claim 1 , wherein the first seal ring is disposed adjacent to an edge of the dielectric layer.3. The semiconductor structure of claim 1 , wherein the first seal ring is electrically connected to the conductive member.4. The semiconductor structure of claim 1 , wherein the first seal ring is connected to an electrical ground through a conductive bump.5. The semiconductor structure of claim 1 , wherein the first seal ring surrounds the conductive member.6. The semiconductor structure of claim 1 , wherein a portion of the dielectric layer is disposed between the first seal ring and the molding.7. The semiconductor structure of claim 1 , further comprising a second seal ring vertically extended within the die claim 1 , wherein the second seal ring is disposed adjacent to the edge of the die or the molding.8. The semiconductor structure of claim 7 , wherein a width of the first seal ring is substantially greater than a width of the second seal ring.9. The semiconductor structure of claim 1 , further comprising a via disposed within and extended through the molding.10. The semiconductor structure of claim 9 , wherein the first seal ring is electrically isolated from the via.11. The semiconductor structure of claim 9 , further comprising a conductive bump ...

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals. 1. A manufacturing method of a semiconductor package structure , comprising:forming at least one package structure, wherein the at least one package structure comprises at least one die having a plurality of first conductive terminals thereon, a first encapsulant encapsulating the at least one die and exposing at least part of the first conductive terminals, a redistribution layer over the first encapsulant and electrically connected to the first conductive terminals, and a plurality of second conductive terminals over the redistribution layer;coupling the at least one package structure to a first surface of a redistribution structure, wherein the redistribution structure further has a second surface opposite to the first surface, and the second conductive terminals of the at least one package structure are electrically connected to between the redistribution layer and the redistribution structure; andencapsulating the at least one package structure by a second ...

Pre-bumped redistribution layer structure and semiconductor package incorporating such pre-bumped redistribution layer structure

A pre-bumped redistribution layer (RDL) structure is disclosed. The pre-bumped RDL structure includes at least a dielectric layer, a first metal layer on the first surface, a second metal layer on the second surface, and a via layer electrically connecting the first metal layer and the second metal layer. At least a bump pad is formed in the first metal layer. A bump is disposed on the bump pad. The bump comprises a copper layer with its lower end directly jointed to a top surface of the bump pad.

BONDING STRUCTURE AND METHOD OF FORMING SAME

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads 1. A device comprising:an interconnect structure over a substrate;a plurality of first conductive pads over and connected to the interconnect structure;a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the plurality of first conductive pads;a surface dielectric layer extending over the planarization stop layer; anda plurality of first bonding pads within the surface dielectric layer and connected to the plurality of first conductive pads.2. The device of claim 1 , further comprising an etch stop layer extending over the planarization stop layer claim 1 , the surface dielectric layer on the etch stop layer.3. The device of claim 2 , further comprising a first dielectric layer between the planarization stop layer and the etch stop layer.4. The device of claim 2 , wherein the plurality of first bonding pads extend through the planarization stop layer and the etch stop layer.5. The device of claim 1 , wherein the planarization stop layer comprises silicon carbide.6. The device of claim 1 , wherein the surface dielectric layer has a thickness between 6 μm and 8 μm.7. The device of claim 1 , further comprising a second dielectric layer between the interconnect structure and the plurality of first conductive pads claim 1 , wherein the planarization stop layer extends over a top surface of the second dielectric layer.8. The device of claim 1 , further comprising a plurality of second conductive pads over the interconnect structure and further comprising ...

ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA

An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion. 1. An electronic device comprising:an upper insulating layer on a substrate;an upper redistribution structure embedded in the upper insulating layer, wherein the upper redistribution structure comprises an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion;a passivation layer on the upper insulating layer and the upper redistribution structure; andan upper opening configured to pass through the passivation layer and expose the upper pad portion,wherein vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.2. The electronic device of claim 1 , wherein:the upper insulating layer has an upper contact opening, an upper line recess, and an upper pad opening;the upper contact opening and the upper pad opening pass through the upper insulating layer; andthe upper line recess connects an upper portion of the upper contact opening to an upper portion of the upper pad opening.3. The electronic device of claim 2 , wherein:the upper contact portion is in the upper contact opening;the upper pad portion is in the upper pad opening; andthe upper line portion is in the upper line portion.4. The electronic device of claim 1 , wherein the upper redistribution structure ...

SEMICONDUCTOR PACKAGE

An embodiment method includes providing a fan-out package structure having cavities to confine semiconductor dies by applying adhesive material which has similar coefficient of thermal expansion (CTE) with semiconductor dies in the gap between the edges of dies and the edges of cavities. The method further includes forming a molding compound over a fan-out package structure with semiconductor dies, building fan-out redistribution layers over a fan-out package structure with semiconductor dies and electrically connected to the semiconductor dies. 1. A semiconductor package , comprising:a fan-out package structure having a first cavity formed thereon;a first die disposed in the first cavity of the fan-out package structure;an adhesive hardened in the first cavity of the fan-out package structure, the adhesive surrounding the first die to fix the first die in the first cavity of the fan-out package structure; anda molding compound formed over the fan-out package structure.2. The semiconductor package as claimed in claim 1 , further comprising:a redistribution layer disposed under the fan-out package structure;metal pads disposed between the first die and the redistribution layer, wherein the metal pads are electrically connected to the first die and the redistribution layer; andsolder balls disposed under the redistribution layer.3. The semiconductor package as claimed in claim 2 , wherein the fan-out package structure further has a second cavity formed thereon claim 2 , the semiconductor package further comprising:a second die disposed in the second cavity of the fan-out package structure and electrically connected to the redistribution layer by metal pads.4. The semiconductor package as claimed in claim 1 , further comprising:a redistribution layer disposed under the fan-out package structure; andthrough-package interconnections formed around the first die, wherein the through-package interconnections penetrate the molding compound and the fan-out package structure ...