Substrate comprising embedded elongated capacitor

A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

Power distribution improvement using pseudo-ESR control of an embedded passive capacitor

A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

INTEGRATED DEVICE PACKAGE COMPRISING CONDUCTIVE SHEET CONFIGURED AS AN INDUCTOR IN AN ENCAPSULATION LAYER

An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet. 1. An integrated device package comprising:a package substrate;a die coupled to the package substrate;an encapsulation layer encapsulating the die; andat least one sheet of electrically conductive material configured to operate as an inductor, wherein the at least one sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer.2. The integrated device package of claim 1 , wherein the at least one sheet of electrically conductive material is configured to operate as a solenoid inductor.3. The integrated device package of claim 1 , further comprising a via in the encapsulation layer claim 1 , wherein the via is coupled to the package substrate and the at least one sheet of electrically conductive material.4. The integrated device package of claim 1 , wherein the at least one sheet of electrically conductive material comprises:a first sheet portion;a second sheet portion coupled to the first sheet portion, wherein the first sheet portion and the second sheet portion form a first winding of the inductor;a ...

Embedded package substrate capacitor

A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE

Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

Integrated device package comprising an electromagnetic (EM) passive device in an encapsulation layer, and an EM shield

Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield.

Integrated device package comprising conductive sheet configured as an inductor in an encapsulation layer

An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

INTEGRATED DEVICE PACKAGE COMPRISING AN ELECTROMAGNETIC (EM) PASSIVE DEVICE IN AN ENCAPSULATION LAYER, AND AN EM SHIELD

Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield. 120-. (canceled)21. A method for fabricating an integrated device package , comprising:providing a die;providing an electromagnetic (EM) passive device;forming an encapsulation layer around the die and the EM passive device; andforming a redistribution portion that couples the die and the EM passive device.22. The method of claim 21 , wherein the EM passive device includes an electromagnetic (EM) passive component.23. The method of claim 22 , wherein the EM passive component comprises an inductor claim 22 , a coupler and/or a transformer.24. The method of claim 21 , wherein providing the EM passive device comprises:forming a base layer;forming a via that traverses the base layer;forming a pad that couples the via; andforming at least one redistribution layer configured to operate as an electromagnetic (EM) passive component, wherein the redistribution layer is formed such that the redistribution layer is coupled to the pad.25. The method of claim 21 , wherein forming at least one redistribution portion includes forming at least one redistribution layer that is configured to ...

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Package substrate comprising capacitor, redistribution layer and discrete coaxial connection

A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

KNOWN GOOD DIE TESTING FOR HIGH FREQUENCY APPLICATIONS

Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Embedded package substrate capacitor with configurable/controllable equivalent series resistance

Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Known good die testing for high frequency applications

Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal

Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Embedded sheet capacitor

A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

PACKAGE-ON-PACKAGE (POP) STRUCTURE

A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package. 1. A method for forming a package-on-package (POP) structure , the method comprising:placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package, wherein the post is placed at a distance from a die along a particular axis of the die, wherein the particular axis is substantially parallel to the second surface, and wherein the first IC package includes the die; andforming a conductive path between a second IC package and the first IC package via the post and a solder bump, wherein the solder bump is disposed between the post and the second IC package.2. The method of claim 1 , wherein a diameter of the post is greater than or equal to approximately 75 micrometers.3. The method of claim 1 , wherein a diameter of the post is less than or equal to approximately 100 micrometers.4. The method of claim 1 , wherein the post comprises copper.5. The method of claim 1 , wherein the solder coating comprises tin claim 1 , gold claim 1 , or both.6. The method of claim 1 , wherein forming the conductive path comprises depositing a dielectric layer on the first IC package subsequent to placing the post on the first IC package.7. The method of claim 6 , wherein forming the conductive path ...

Capacitor structure for wideband resonance suppression in power delivery networks

Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Package on package (PoP) device comprising a high performance inter package connection

A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

Integrated device package and/or system comprising configurable directional optical transmitter

Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

Embedded multi-terminal capacitor

An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

INTEGRATED DEVICE COMPRISING COAXIAL INTERCONNECT

Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device. 1. An integrated device comprising:a substrate;a first interconnect coupled to the substrate; anda second interconnect surrounding the first interconnect, the second interconnect configured to provide an electrical connection to ground.2. The integrated device of claim 1 , wherein the second interconnect comprises a plate.3. The integrated device of claim 1 , further comprising a dielectric material between the first interconnect and the second interconnect.4. The integrated device of claim 1 , further comprising a mold surrounding the second interconnect.5. The integrated device of claim 1 , wherein the first interconnect is configured to provide an electrical path for a power signal in a first direction.6. The integrated device of claim 5 , wherein the second interconnect is configured to provide an electrical path for a grounding signal in a second direction.7. The integrated device of claim 1 , wherein the first interconnect is one of at least a plated interconnect and/or wire bond.8. The ...

PRECISION RESISTOR TUNING AND TESTING BY INKJET TECHNOLOGY

A method of additive tuning a resistor includes measuring resistance across a recessed area of the resistor using at least two terminals, depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance, and ceasing the depositing upon obtaining a measurement of a resistance threshold value. 1. A method of additive tuning a resistor , comprising:measuring resistance across a recessed area of a resistor device using at least two terminals;depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance; andceasing the depositing upon obtaining a measurement of a resistance threshold value.2. The method of claim 1 , further comprising controlling droplet size from the ink jet to increase resolution of the measured resistance as the measured resistance approaches the resistance threshold value.3. The method of claim 1 , further comprising controlling a spray pattern during the depositing.4. The method of claim 1 , further comprising controlling continuity of spray during the depositing.5. The method of claim 1 , further comprising controlling the ink jet spray to apply finer strips of resistance material as the measured resistance approaches the resistance threshold value.6. The method of claim 1 , further comprising controlling spray throughput of the ink jet claim 1 , wherein the spray throughput is reduced as the measured resistance approaches the resistance threshold value.7. The method of claim 1 , further comprising controlling speed of motion for the ink jet during the applying of the material.8. The method of claim 1 , wherein the measuring comprises using a four point Kelvin probing device.9. The method of claim 1 , wherein the ceasing occurs with the ink jet having deposited at least one strip of resistance material only partially spanning the recessed area.10. A resistor claim 1 , comprising:a substrate;a frame on ...

High impedance surface (his) enhanced by discrete passives

In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

METHODS OF MANUFACTURING A HIGH IMPEDANCE SURFACE (HIS) ENHANCED BY DISCRETE PASSIVES

In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors. 1. A method of manufacturing a high impedance surface (HIS) apparatus , wherein the method comprises:patterning a first conducting layer on a core to form a first set of conducting pads;patterning a second conducting layer on the core to form a second set of conducting pads;drilling cavities that run through the first set of conducting pads, the core, and the second set of conducting pads;forming a via in each of the cavities;plating a surface of each of the conducting pads of the first set of conducting pads and the second set of conducting pads;applying solder paste to each of the conducting pads of the second set of conducting pads;placing chip capacitors on the solder paste on the second set of conducting pads;reflowing the solder paste on the second set of conducting pads;applying underfill between the chip capacitors;applying solder paste to each of the conducting pads of the first set of conducting pads;placing chip inductors on the solder paste on the first set of conducting pads;reflowing the solder paste on the first set of conducting pads; andapplying underfill between ...

SEMICONDUCTOR PACKAGE ON PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure. 1. A packaged semiconductor device , comprising:a first package having a first semiconductor die and a bonding pad;a second package having a second semiconductor die; anda frame connected to the bonding pad and the second package at an interconnect, wherein the interconnect is offset from the bonding pad.2. The device of claim 1 , further comprising a non-conductive layer between the first and second packages.3. The device of claim 2 , wherein the frame is composed of lead.4. The device of claim 3 , wherein the frame forms an interconnect pattern offset from the bonding pads.5. The device of claim 4 , wherein the first package comprises an organic interposer.6. The device of claim 5 , wherein the first semiconductor die is a logic die and the second semiconductor die is a memory.7. A semiconductor package on package structure formed by the method of .8. A method of forming a package on package structure claim 8 , comprising the steps of:forming a first package, wherein forming a first package further comprises forming a substrate, forming a first semiconductor die on a top of the substrate, and forming bonding pads on the top of the substrate; ...

INTEGRATED DEVICE COMPRISING A HEAT-DISSIPATION LAYER PROVIDING AN ELECTRICAL PATH FOR A GROUND SIGNAL

Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer. 1. An integrated device comprising:a substrate;a die;a heat-dissipation layer disposed on a surface of the substrate and located between the substrate and the die;a first interconnect configured to couple the die to the heat-dissipation layer, wherein the heat-dissipation layer is configured to provide an electrical path for a ground signal and the heat-dissipation layer is adjacent to the first interconnect; anda second interconnect configured to couple the die to the substrate, wherein the second interconnect is electrically isolated from the heat-dissipation layer by a solder-resist layer.2. The integrated device of claim 1 , wherein the first interconnect is further configured to conduct heat from the die to the heat-dissipation layer.3. (canceled)4. The integrated device of claim 1 , wherein the second interconnect is configured to conduct a power signal between the die and the substrate.5. The integrated device of claim 1 , wherein the second interconnect is configured to couple the die to the substrate through an opening in the heat-dissipation layer.6. The integrated device of claim 1 , further comprising:a dielectric ...

Fishbone lc component and method of making the same

A semiconductor structure according to some examples may include an LC component for use in PMIC applications. The semiconductor structure may have a first conductive coil mounted on an upper surface of a substrate, the first conductive coil surrounding a magnetic core; an output located on a surface of the first conductive coil and coupled to the coil; a dielectric layer located on a surface of the output; and an upper conductive element located on a surface of the dielectric layer, wherein the upper conductive element, the dielectric layer, and the output form a capacitor; and the first conductive coil and the magnetic core form an inductor. The semiconductor structure may also include a second conductive coil located in a same horizontal plane as the first conductive coil, the second conductive coil surrounding a magnetic core where the first conductive coil and the second conductive coil form a fishbone pattern.

PACKAGE SUBSTRATES INCLUDING EMBEDDED CAPACITORS

Integrated devices include a substrate, and a capacitor embedded within the substrate. The capacitor is configured to include a first electrode disposed on a first surface, a second electrode disposed on an opposing second surface, and a plurality of capacitor plates extending transverse between the first electrode and the second electrode. Each capacitor plate is electrically coupled to one of the first electrode or the second electrode. A plurality of vias are positioned to extend through the substrate to one of the first electrode or the second electrode. Other aspects, embodiments, and features are also included. 1. A substrate comprising:a dielectric layer; a first electrode disposed on a first surface;', 'a second electrode disposed on an opposing second surface; and', 'a plurality of capacitor plates positioned between the first electrode and the second electrode and extending transverse to the first and second electrodes, wherein each capacitor plate is electrically coupled to one of the first electrode or the second electrode; and, 'a capacitor embedded within the dielectric layer, wherein the capacitor comprisesa plurality of vias extending through the dielectric, wherein at least one via is electrically coupled to the first electrode of the capacitor, and wherein at least one via is electrically coupled to the second electrode of the capacitor.2. The substrate of claim 1 , wherein the capacitor comprises a multi-layer ceramic capacitor (MLCC).3. The substrate of claim 1 , further comprising a resistive layer disposed over the first electrode and the second electrode of the capacitor.4. The substrate of claim 1 , wherein the capacitor and vias are part of a power distribution network.5. The substrate of claim 1 , wherein the capacitor is configured with a length substantially twice as long as the width.6. The substrate of claim 1 , wherein the dielectric layer comprises several dielectric layers.7. A method of fabricating a substrate claim 1 , comprising: ...

WAFER LEVEL PACKAGE (WLP) INTEGRATED DEVICE COMPRISING ELECTROMAGNETIC (EM) PASSIVE DEVICE IN REDISTRIBUTION PORTION, AND RADIO FREQUENCY (RF) SHIELD

Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal. 1. An integrated device comprising:a substrate;a plurality of lower level metal layers;a plurality of lower level dielectric layers; and a first dielectric layer comprising a first dielectric thickness; and', 'an electromagnetic (EM) passive device comprising a first redistribution interconnect, wherein the first redistribution interconnect comprises a first redistribution thickness, the first dielectric thickness being at least about 2 times (2×) greater than the first redistribution thickness., 'a redistribution portion comprising2. The integrated device of further comprises a radio frequency (RF) shield.3. The integrated device of claim 2 , wherein the RF shield is located between a passivation layer and the plurality of lower level dielectric layers.4. The integrated device of claim 2 , wherein the RF shield is located between the EM passive device and the plurality of lower level dielectric layers.5. The integrated device of claim 2 , wherein the RF shield is coupled ...

RECONFIGURABLE ELECTRIC FIELD PROBE

Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe. 1. An electromagnetic compatibility (EMC) probe , comprising:a center conductor extending along an axis of the EMC probe and having a probe tip at one end;a shield coaxially aligned with the axial conductor and configured to provide electromagnetic screening for the probe tip; andat least one actuator configured to axially translate the probe tip or the shield and thereby change the position of the probe tip relative to the shield.2. The EMC probe of claim 1 , wherein the at least one actuator moves the probe tip along the axis such that a first distance measured between the probe tip and a device under test (DUT) is changed while a second distance measured between the shield and the DUT remains unchanged.3. The EMC probe of claim 1 , wherein the at least one actuator moves the shield in a direction parallel to the axial conductor without moving the probe tip such that a first distance measured between the shield and a DUT is changed.4. The EMC probe of claim 1 , wherein the at least one actuator comprises one or more of:an actuator operative to move the probe tip along the axis such that a first distance measured between the probe tip and the DUT is increased or decreased; andan actuator that moves the shield in a direction parallel to the axial conductor such that a second distance measured between the shield and a DUT is changed.5. The EMC probe of claim 4 , wherein the probe tip is adapted to detect an electric field proximate to an area of interest on a surface of the DUT.6. The EMC probe of claim 5 ...

INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE

Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate. 1. A method for manufacturing an integrated circuit package comprising:providing a substrate having a plurality of build-up layers;providing a vertical capacitor;attaching a first electrode of the vertical capacitor to a first substrate pad embedded in a first layer of the plurality of build-up layers of the substrate;forming a conductive layer on a portion of the first layer of the plurality of build-up layers of the substrate and on a second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor; andattaching an integrated circuit die to a first plurality of substrate pads embedded in the first layer of the substrate.2. The method of claim 1 , wherein the first and second electrodes of the vertical capacitor are perpendicularly located to a planar surface of the substrate.3. The method of claim 1 , wherein the substrate has a thickness range of 160-190 microns.4. The method of claim 1 , wherein the substrate has a thickness of 176 microns.5. The method of claim 1 , wherein the vertical capacitor has a width of 0.5 millimeter and a thickness range of 0.1-0.2 ...

Capacitor structure for wideband resonance suppression in power delivery networks

Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

THIN FILM RESISTOR HAVING SURFACE MOUNTED TRIMMING BRIDGES FOR INCREMENTALLY TUNING RESISTANCE

A resistor assembly is disclosed and comprises a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a thin film resistor electrically coupled to the first conductive trace. The first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly. The plurality of trimming bridges are each removable to increase a resistance of the thin film resistor. 1. A resistor assembly , comprising:a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace; anda thin film resistor electrically coupled to the first conductive trace, wherein the first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly, and wherein the plurality of trimming bridges are each removable to increase a resistance of the thin film resistor.2. The resistor assembly of claim 1 , further comprising an electrical trace that is part of the surface mounted layer claim 1 , wherein the electrical trace electrically couples the thin film resistor to the first conductive trace.3. The resistor assembly of claim 1 , wherein the plurality of trimming bridges are spaced at equal distances from one another claim 1 , and wherein spacing the plurality of trimming bridges at equal distances from one another results in a linear increase in the resistance of the thin film resistor as each trimming bridge is removed.4. The resistor assembly of claim 1 , wherein the first conductive trace and the second conductive trace are arranged concentrically with respect to one another.5. The resistor assembly of claim 4 , wherein the first ...

Adjustable magnetic probe for efficient near field scanning

A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

CURRENT SOURCE DRIVEN MEASUREMENT AND MODELING

A method and apparatus for testing integrated circuit resistors includes applying a variable source current to a resistive device under test (DUT), measuring the resistance of the resistive DUT as a function of the source current, and fitting the measured resistance to parameters of a polynomial parametric equation, wherein the parametric equation comprises a constant resistance at zero current bias plus a second order current coefficient of resistance multiplied by the square of the current. 1. A method of testing integrated circuit resistors comprising:applying a variable source current to a resistive device under test (DUT);measuring the resistance of the resistive DUT as a function of the source current; andfitting the measured resistance to parameters of a polynomial parametric equation, wherein the parametric equation comprises a constant resistance at zero current bias plus a second order current coefficient of resistance times the square of the current.2. The method of claim 1 , further comprising determining the constant resistance at zero current and the second order current coefficient of resistance from the measurements by linear regression.3. The method of claim 1 , further comprising measuring the resistance as a function of the variable current at a constant temperature.4. The method of claim 1 , further comprising measuring the resistance at a constant current as a function of an applied variable temperature claim 1 , whereinthe parametric equation further comprises a temperature dependency cofactor, the cofactor including a unity constant at a fixed reference temperature added to a first order temperature coefficient times a change in temperature added to a second order temperature coefficient multiplied by the square of the change in temperature.5. The method of claim 4 , further comprising determining the first order temperature coefficient and the second order temperature coefficient from the measurements by linear regression.6. The method of ...

Stiffener with embedded passive components

Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

LOW PARASITIC PACKAGE SUBSTRATE HAVING EMBEDDED PASSIVE SUBSTRATE DISCRETE COMPONENTS AND METHOD FOR MAKING SAME

One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer. 1. A multi-layer package substrate of an integrated circuit package , comprising:a discrete circuit component (DCC) having at least one electrode, the DCC embedded at least partially within an insulator layer;a first via coupling component electrically coupled to the electrode, a first portion of the first via coupling component extending beyond a first edge of the electrode; anda plurality of vias each having a first end coupled to the first via coupling component, at least a first via of the plurality of vias coupled to the first portion of the first via coupling component extending beyond the first edge of the electrode.2. The multi-layer package substrate of claim 1 , wherein the first via coupling component increases an available surface area to which the first ends of the plurality of vias are coupled to.3. The multi-layer package substrate of claim 1 , wherein the plurality of vias includes three (3) or more vias.4. The multi-layer package substrate of claim 1 , wherein the plurality of vias each have a second end that are electrically coupled to a first outer metal layer claim 1 , and at least a second portion of the first via ...

FLEXIBLE FILM ELECTRICAL-TEST SUBSTRATES WITH CONDUCTIVE COUPLING POST(S) FOR INTEGRATED CIRCUIT (IC) BUMP(S) ELECTRICAL TESTING, AND RELATED METHODS AND TESTING APPARATUSES

Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC. 1. An electrical-test substrate for providing electrical contact to bumps in an integrated circuit (IC) during electrical testing of the IC , comprising:a backside structure comprising a flexible dielectric film structure;at least one conductive pad formed over a front side of the flexible dielectric film structure;at least one opening formed over the at least one conductive pad at a first pitch; andat least one conductive coupling post positioned within the at least one opening to provide a second pitch of the at least one conductive coupling post at substantially the first pitch, the at least one conductive coupling post configured for coupling with at least one bump of an IC during electrical testing of the IC.2. The electrical-test substrate of claim 1 , wherein the backside structure is comprised entirely of the flexible dielectric film structure.3. The electrical-test substrate of claim 1 , further comprising at least one conductive end pad disposed on the backside structure of the at least one conductive end pad coupled with the at least one ...

SEMICONDUCTOR PACKAGE INTERCONNECTIONS AND METHOD OF MAKING THE SAME

A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers. 1. A semiconductor package , comprising:a base having a first side and a second side opposite the first side;a first redistribution layer on the first side of the base, the first redistribution layer configured to couple the base with an external device;a first die attached to the second side of the base with an active side of the first die facing away from the base;a second die attached to the second side of the base adjacent the first die with an active side of the second die facing away from the base;an interposer attached to the active side of the first die and the active side of the second die;an encapsulation layer encapsulating the second side of the base, the first die, the second die, and the interposer;a first plurality of vias coupled to the first die;a second plurality of vias coupled to the second die, the first plurality of vias and the second plurality of vias extending partially through the encapsulation layer; anda third plurality of vias extending through the encapsulation layer and the base.2. The semiconductor package of claim 1 , wherein the interposer is less than 30 um in thickness.3. The semiconductor package of claim 1 , wherein the encapsulation layer comprises a photo-patternable material.4. The semiconductor package of claim 1 , further comprising a second redistribution layer on a surface of ...

Embedded sheet capacitor

A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER

An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge. 1. An integrated device package base comprising: a photo imageable layer;', 'a bridge, at least partially embedded in the photo imageable layer, configured to provide an electrical path between a first die and a second die, the bridge comprising a first set of interconnects comprising a first density of interconnection; and', 'a set of vias, in the photo imageable layer, comprising a second density of interconnection; and, 'a base portion comprising at least one dielectric layer;', 'a second set of interconnects coupled to the first set of interconnects; and', 'a third set of interconnects coupled to the set of vias., 'a redistribution portion coupled to the base portion and the redistribution portion comprising2. The integrated device package base of claim 1 , wherein the first density of interconnection of the first set of interconnects is less than the second density of interconnection of the set of vias.3. The integrated device package base of claim 1 , wherein the first density of interconnection of the first set of interconnects comprises a width of about 2 microns (μm) or less claim 1 ...

Integrated device package comprising an electromagnetic (em) passive device in an encapsulation layer, and an em shield

Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield.

Integrated device package and/or system comprising configurable directional optical transmitter

Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

MULTILAYER CERAMIC CAPACITOR INCLUDING AT LEAST ONE SLOT

An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer. 1. An apparatus comprising: 'a conductive layer, wherein the conductive layer includes at least one slot.', 'a two-terminal multilayer ceramic capacitor (MLCC) comprising2. The apparatus of claim 1 , wherein the two-terminal MLCC includes a single positive terminal and a single negative terminal.3. The apparatus of claim 1 , wherein the at least one slot decreases an equivalent series resistance (ESR) of the two-terminal MLCC as compared to the conductive layer not including the at least one slot.4. The apparatus of claim 3 , wherein the decrease in the ESR of the two-terminal MLCC increases a quality factor (Q factor) of the two-terminal MLCC.5. The apparatus of claim 1 , wherein the at least one slot includes a plurality of first slots that are perpendicular to a current flow direction of the two-terminal MLCC and at least one second slot that is parallel to the current flow direction.6. The apparatus of claim 5 , wherein the plurality of first slots includes two slots.7. The apparatus of claim 5 , wherein the at least one second slot connects a pair of first slots.8. The apparatus of claim 5 , wherein the at least one second slot includes two slots.9. The apparatus of claim 1 , wherein the at least one ...

Fire suppressing device

A fire suppressing device including a torus container with a main body defining an interior chamber and a discharge port, the interior chamber configured to receive and retain metal organic framework materials. The fire suppressing device also includes an inductor coil extending through the interior chamber of the torus container and surrounding the metal organic framework materials. The inductor coil is configured to heat the metal organic framework materials to form a fire suppressing substance that is conveyed through the discharge port.

PACKAGE SUBSTRATE COMPRISING CAPACITOR, REDISTRIBUTION LAYER AND DISCRETE COAXIAL CONNECTION

A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects. 1. A package substrate comprising: a first dielectric layer;', 'a first set of metal layers in the dielectric layer;', 'a first via in the dielectric layer, the first via coupled to the first set of metal layers, wherein the first via and the first set of metal layers are configured to provide a first electrical path for a ground signal;', 'a second set of metal layers in the dielectric layer; and', 'a second via in the dielectric layer, the second via coupled to the second set of metal layers, wherein the second via and the second set of metal layers are configured to provide a second electrical path for a power signal; and, 'a first portion configured to operate as a capacitor, the first portion comprising a second dielectric layer; and', 'a set of interconnects., 'a redistribution portion coupled to the first portion, the redistribution portion comprising2. The package substrate of claim 1 , wherein the first portion further comprises a third via claim 1 , wherein a combination of the third via and at least a portion of the first set of metal layers is configured as a discrete coaxial connection in the first portion.3. The package substrate of claim ...

Package on package (pop) device comprising a high performance inter package connection

A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

LOW PROFILE REINFORCED PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE

The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity. 1. A package-on-package (PoP) semiconductor device , comprising: an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction;', 'a first semiconductor device arranged in the central cavity of the anodized metal lid structure;', 'a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity; and', 'solder material arranged in the at least one perimeter cavity; and, 'a first semiconductor package, the first semiconductor package comprisinga second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive ...

ELECTROMAGNETIC INTERFERENCE ENCLOSURE FOR RADIO FREQUENCY MULTI-CHIP INTEGRATED CIRCUIT PACKAGES

One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

THERMAL DESIGN AND ELECTRICAL ROUTING FOR MULTIPLE STACKED PACKAGES USING THROUGH VIA INSERT (TVI)

Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

BANDPASS FILTER IMPLEMENTATION ON A SINGLE LAYER USING SPIRAL CAPACITORS

A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines. 1. A planar capacitor comprising:a first metal line formed on an insulating layer and including a first end, said first metal line forming spiral-shaped loops around the first end of the first metal line, said first metal line forming a first plate of the planar capacitor; anda second metal line formed on the insulating layer, said second metal line forming spiral-shaped loops around a first end of the second metal line, the loops of the second metal line being formed between the loops of the first metal line, said second metal line forming a second plate of the planar capacitor.2. The planar capacitor of wherein a width of each of the first and second metal lines is greater than a spacing between the first and second metal lines.3. The planar capacitor of wherein said insulating layer is formed above a semiconductor substrate.4. The planar capacitor of wherein said insulating layer is formed on a printed circuit board.5. A filter comprising:a first metal line formed on an insulating layer, said first metal line forming spiral-shaped loops around a first end of the first metal line, said first metal line comprising a first metal plate forming ...

SUBSTRATE COMPRISING EMBEDDED ELONGATED CAPACITOR

A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal. 1. A substrate comprising:a first dielectric layer; and a first terminal;', 'a second terminal;', 'a third terminal, wherein the second terminal is laterally located between the first terminal and the third terminal;', 'a second dielectric layer;', 'a first metal layer in the second dielectric layer, the first metal layer coupled to the first and third terminals, the first metal layer, the first terminal, and the third terminal configured to provide a first electrical path for a first signal; and', 'a second metal layer in the second dielectric layer, the second metal layer coupled to the second terminal, the second metal layer and the second terminal configured to provide a second electrical path for a second signal., 'a capacitor embedded in the first dielectric layer, the capacitor comprising2. The substrate of claim 1 , wherein the capacitor further comprises:a fourth terminal;a fifth terminal;a third metal layer in the second dielectric layer, the third metal layer coupled to the fourth terminal; anda fourth metal layer in the second dielectric layer, the fourth metal layer coupled to the fifth terminal, wherein the third and fourth metal layers are configured to change an equivalent series resistance (ESR) of the ...

SUBSTRATE COMPRISING AN EMBEDDED CAPACITOR

A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a base portion, a first terminal and a second terminal. The first terminal is located on a first surface of the base portion, where the first terminal is the only terminal on the first surface of the base portion. The second terminal is located on a second surface of the base portion. The second surface is opposite to the first surface. The second terminal is the only terminal on the second surface of the base portion. In some implementations, the capacitor further includes a first base metal layer located between the first surface of the base portion and the first terminal. In some implementations, the capacitor also includes a second base metal layer located between the second surface of the base portion and the second terminal. 1. A substrate comprising:a first dielectric layer; and a base portion;', 'a first terminal located on a first surface of the base portion, wherein the first terminal is the only terminal on the first surface of the base portion; and', 'a second terminal located on a second surface of the base portion, the second surface opposite to the first surface, wherein the second terminal is the only terminal on the second surface of the base portion., 'a capacitor embedded in the first dielectric layer, the capacitor comprising2. The substrate of claim 1 , wherein the capacitor further comprises:a first base metal layer located between the first surface of the base portion and the first terminal; anda second base metal layer located between the second surface of the base portion and the second terminal.3. The substrate of claim 1 , further comprising:a first terminal interconnect coupled to the first terminal of the capacitor; anda second terminal interconnect coupled to the second terminal of the capacitor.4. The substrate of claim 3 , wherein the first terminal interconnect is coupled to the first terminal such that a ...

Techniques for controlling equivalent series resistance of a capacitor

Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

LOW COST CONNECTOR FOR HIGH SPEED, HIGH DENSITY SIGNAL DELIVERY

A high-speed, high-density Input/Output bridge couples dies on a substrate to each other using a flexible connector that is attached to the substrate using solder balls disposed in openings in the substrate. Thus, the bulky, male-to-female connectors and/or silicon bridges are eliminated while still permitting dies disposed on the substrate to be coupled together. 1. A flexible connector for delivery of high speed , high density signals to a device , the flexible connector comprising:an insulating material; andinterconnects disposed in the insulating material, wherein the interconnects are configured to mate the flexible connector in openings disposed in a substrate using solder balls.2. The flexible connector of claim 1 , wherein the interconnects are further configured to align the flexible connector to circuitry disposed in the substrate.3. The flexible connector of claim 1 , wherein the interconnects comprise copper.4. The flexible connector of claim 1 , further comprising an input/output (I/O) signal path disposed in the insulating material.5. The flexible connector of claim 1 , further comprising at least one of a power path in the substrate and a ground path in the substrate.6. A semiconductor device assembly claim 1 , comprising: an insulating material; and', 'interconnects disposed in the insulating material; and, 'a flexible connector havinga substrate coupled to the flexible connector, wherein the substrate includes solder balls disposed therein, and wherein the interconnects are configured to mate the flexible connector with openings disposed in the substrate using solder balls.7. The semiconductor device assembly of claim 6 , further comprising a first die disposed on the substrate and a second die disposed on the substrate claim 6 , wherein the interconnects are configured to couple the first die with the second die.8. The semiconductor device assembly of claim 6 , further comprising an input/output (I/O) signal path disposed in the insulating material ...

Method for high-intensity radiated field (hirf) and electromagnetic pulse (emp) analysis of a vehicle

A method for modeling electromagnetic characteristics of a vehicle having electrical components comprising generating a parallel plate waveguide model and inserting a vehicle model for the vehicle within the parallel plate waveguide model. The vehicle model has a plurality of lumped ports corresponding to on-board electrical components. The method executes an electromagnetic field solver on a first and second waveguide ports and the lumped ports and determines a scaling factor between a first power level configured to excite the first and/or second waveguide ports and a second power level configured to excite the lumped ports. The electromagnetic field solver runs on the first and second waveguide and lumped ports, producing a first output data and the method produces a scattering parameter (S-parameter) model for the vehicle from the first output data that includes a plurality of S-parameter ports.

EMBEDDED MULTI-TERMINAL CAPACITOR

An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network. 1. A device , comprising:a substrate having a cavity;a multi-terminal capacitor embedded within the cavity, the multi-terminal capacitor including a plurality of positive terminals; anda capacitor metal layer adjacent a surface of the multi-terminal capacitor, the capacitor metal layer being configured to form a capacitor power network electrically coupled to the plurality of positive terminals.2. The device of claim 1 , wherein the multi-terminal capacitor further includes a plurality of ground terminals claim 1 , and wherein the capacitor metal layer is further configured to form a capacitor ground network electrically coupled to the plurality of ground terminals.3. The device of claim 2 , wherein the multi-terminal capacitor includes a die-facing surface claim 2 , and an opposing surface claim 2 , and wherein the plurality of positive terminals and the plurality of ground terminals are distributed on side walls of the multi-terminal capacitor extending between the die-facing surface and the opposing surface.4. The device of claim 2 , wherein the capacitor metal layer comprises a first capacitor metal layer arranged into a plurality of first power rails and a plurality of first ground rails.5. The device of claim 1 , wherein the substrate includes a plurality of metal layers claim 1 , and wherein the capacitor metal layer is substantially aligned with an intermediate one of the substrate metal layers.6. The device of claim 4 , further comprising a die having an internal power network electrically coupled to the first power rails through a plurality of first die interconnects.7. The device of claim 6 , wherein the substrate includes a plurality of metal layers configured to form an external power network claim 6 , and wherein the die includes ...

POWER DISTRIBUTION IMPROVEMENT USING PSEUDO-ESR CONTROL OF AN EMBEDDED PASSIVE CAPACITOR

A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern. 1. A power delivery network , comprising:a fan-out wafer level package structure comprising a multilayer redistribution layer (RDL) configured to couple with terminals of an embedded capacitor, the multilayer RDL comprising sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.2. The power delivery network of claim 1 , further comprising a semiconductor die supported by the fan-out wafer level package structure.3. The power delivery network of claim 1 , in which the multilayer RDL comprises a post passivation interconnect including a seed layer claim 1 , a coupling layer on the seed layer and a plating layer on the coupling layer.4. The power delivery network of claim 3 , in which predetermined portions of the post passivation interconnect include only the seed layer to control the ESR of the embedded capacitor and damping of the power delivery network.5. The power delivery network of claim 1 , in which the fan-out wafer level package structure comprises an embedded wafer level ball grid array (eWLB) including an embedded passive substrate.6. The power delivery network of claim 1 , in which portions of an RDL layer within the multilayer RDL are exposed according to a selected ESR control pattern.7. The power delivery network of claim 1 , incorporated into at least one of a music player claim 1 , a video player claim 1 , an entertainment unit claim 1 , a navigation device claim 1 , a communications device claim 1 , a personal digital assistant (PDA) claim 1 , a fixed location data unit claim 1 , and a computer.8. A method for a ...

CERAMIC INTERPOSER CAPACITOR

A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface. 2. The ceramic capacitor of claim 1 , wherein the substrate comprises a package substrate or a die substrate.3. The ceramic capacitor of claim 1 , wherein the ceramic capacitor comprises a high-K ceramic material.4. The ceramic capacitor of claim 3 , wherein the high-K ceramic material comprises a ceramic material having a dielectric constant greater than 3000.5. The ceramic capacitor of claim 1 , wherein the metal plates comprise nickel.6. The ceramic capacitor of claim 1 , wherein the metal plates are staggered to each other.7. The ceramic capacitor of claim 1 , wherein the ceramic capacitor has a thickness of about 100 μm.8. The ceramic capacitor of claim 1 , wherein the metal plates are capable of being soldered to the pads of the die and the pads of the substrate.9. The ceramic capacitor of claim 1 , wherein the pads of the die and the pads of the substrate comprise power pads and/or ground pads.10. The ceramic capacitor of claim 1 , wherein the ceramic capacitor is incorporated into at least one of a cellphone claim 1 , a laptop claim 1 , a tablet claim 1 , a music player claim 1 , a communication device claim 1 , a computer claim 1 , and a video player.11. A method comprising:providing a die comprising a plurality of conductive pads on a die surface;providing a substrate comprising a plurality of conductive pads on a substrate surface;forming a ceramic capacitor having metal plates ...

Pattern between pattern for low profile substrate

An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Embedded sheet capacitor

A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

EMBEDDED PACKAGE SUBSTRATE CAPACITOR WITH CONFIGURABLE/CONTROLLABLE EQUIVALENT SERIES RESISTANCE

Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates. 1. A capacitor comprising:a first electrode having a first surface and an opposing second surface;a second electrode having a third surface and an opposing fourth surface;a first dielectric layer coupled to and separating the first and second electrodes; and a second dielectric layer coupled to the first surface of the first electrode;', 'a first metal layer coupled to a first surface of the second dielectric layer; and', 'a first set of pillars embedded in the second dielectric material and extending between the first electrode and the first metal layer., 'a first equivalent series resistance (ESR) structure coupled to the first electrode, the first ESR control structure comprising2. The capacitor of claim 1 , further comprising a second ESR control structure coupled to the first electrode claim 1 , the second ESR control structure comprising:a third dielectric layer coupled to the second surface of the first electrode;a second metal layer coupled to a first surface of the third dielectric layer; anda second set of pillars embedded in the third dielectric layer and extending between the first electrode and the second metal layer.3. The capacitor of claim 2 , wherein the first surface of the ...

EMBEDDED PACKAGE SUBSTRATE CAPACITOR

A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate. 1. A package substrate , comprising:a substrate comprising a first side;a capacitor embedded in the substrate, the capacitor comprises a first electrode and a second electrode;a first metal plate extending laterally in the substrate, wherein the first metal plate is disposed directly on the first electrode of the capacitor from a first side of the substrate; anda first via extending perpendicular to the first metal plate and connected to the first metal plate from the first side of the substrate.2. The package substrate of claim 1 , wherein the first via is offset from an area of the first metal plate covering the first electrode of the capacitor.3. The package substrate of claim 1 , further comprising a plurality of vias extending perpendicular to the first metal plate and connected to the first metal plate from the first side of the substrate.4. The package substrate of claim 1 , further comprising a second metal plate extending laterally in the substrate claim 1 , wherein the second power supply metal plate is disposed on and covers the first electrode of the capacitor from a second side of the substrate opposite from the first side of the substrate.5. The package substrate of claim 4 , wherein the first metal plate and the second metal plate are connected by a second via extending in the substrate between the first and the second power ...

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Capacitor structure for power delivery applications

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

ELECTRICAL MODULE ASSEMBLY WITH EMBEDDED DIES

An electrical module assembly is provided. The electrical module assembly includes a circuit board with a first circuit-board surface and a second circuit-board surface defining a cavity, and an antenna disposed on the first circuit-board surface. The electrical module assembly also includes a wafer-level packaged (WLP) die embedded in the cavity. The WLP die has a first WLP die surface and a second WLP die surface. The second WLP die surface has electrical contacts thereon. The circuit board includes vias that extend from the antenna through the circuit board to the first WLP die surface to interconnect the antenna and the WLP die. The electrical module assembly further includes a second circuit board coupled to the second circuit-board surface, and coupled to the WLP die at the electrical contacts on the second WLP die surface of the WLP die. 1. An electrical module assembly comprising:a circuit board with opposing major surfaces including a first circuit-board surface and a second circuit-board surface, the second circuit-board surface defining a cavity in the circuit board;an antenna disposed on the first circuit-board surface of the circuit board;a wafer-level packaged die embedded in the cavity defined by the second circuit-board surface of the circuit board, the wafer-level packaged die with opposing major surfaces including a first wafer-level packaged die surface and a second wafer-level packaged die surface, the second wafer-level packaged die surface having electrical contacts thereon, the circuit board including vias that extend from the antenna through the circuit board to the first wafer-level packaged die surface to interconnect the antenna and the wafer-level packaged die; anda second circuit board coupled to the second circuit-board surface, and coupled to the wafer-level packaged die at the electrical contacts on the second wafer-level packaged die surface of the wafer-level packaged die.2. The electrical module assembly of claim 1 , wherein the ...

Semiconductor package interconnections and method of making the same

A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Variable radio frequency attenuator

A variable RF attenuator includes a substrate, a first microstrip trace, a first thin film resistor, a second microstrip trace, and a wire bond. The substrate includes a dielectric layer. The first thin film resistor is disposed on the substrate. The first microstrip trace is disposed on the substrate and the first thin film resistor. The second microstrip trace is disposed on the substrate and is uncoupled from the first microstrip trace. The wire bond extends from the second microstrip trace to a position on the first microstrip trace. The position is selected to tune RF attenuation over a conductive path defined by the first microstrip trace, the wire bond, and the second microstrip trace.

Thermal design and electrical routing for multiple stacked packages using through via insert (TVI)

Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Thin film resistor having surface mounted trimming bridges for incrementally tuning resistance

A resistor assembly is disclosed and comprises a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a thin film resistor electrically coupled to the first conductive trace. The first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly. The plurality of trimming bridges are each removable to increase a resistance of the thin film resistor.

Pattern between pattern for low profile substrate

An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages

一種特徵涉及多晶片封裝，該多晶片封裝包括基板以及耦合至基板的電磁干擾(EMI)遮罩。至少一個積體電路被耦合至基板的第一表面。EMI遮罩包括配置成遮罩封裝不受射頻輻射影響的金屬殼、耦合至金屬殼的內表面的至少一部分的介電層、以及複數條信號線。這些信號線被耦合至介電層並經由介電層與金屬殼電絕緣。至少一個其他積體電路被耦合至EMI遮罩的內表面，並且EMI遮罩的內表面的至少一部分面對基板的第一表面。這些信號線被配置成將電信號提供給第二電路元件。

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Estrutura de pacote sobre pacote, método de formação de estrutura de pacote sobre pacote e memória legível por computador

INTERMEDIÁRIO PARA UMA ESTRUTURA DE PACOTE SOBRE PACOTE. Trata-se de uma estrutura de pacote sobre pacote (PoP) que inclui uma primeira matriz, uma segunda matriz e um dispositivo de memória eletricamente acoplado à primeira matriz e à segunda matriz por um intermediário entre a primeira matriz e a segunda matriz. O intermediário inclui vias preenchidas com cobre formadas em um molde.

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Capacitor structure with asymmetric terminals

A passive discrete device (400) includes a first asymmetric terminal (410A) and a second asymmetric terminal (410B). The passive discrete device (400) further includes first internal electrodes (420A) extended to electrically couple to a first side and a second side of the first asymmetric terminal (410A). The passive discrete device (400) also includes second internal electrodes (420B) extended to electrically couple to a first side and a second side of the second asymmetric terminal (420B).

Techniques for controlling equivalent series resistance of a capacitor

Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Embedded package substrate capacitor

A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Integrated device package comprising silicon bridge in photo imageable layer

An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to the base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Integrated device comprising coaxial interconnect

Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Integrated device package comprising conductive sheet configured as an inductor in an encapsulation layer

An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Stiffener with embedded passive components

Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package (200). A continuous or uninterrupted stiffener structure (208) is designed with a recessed groove (208b), such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate (202) using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices (204) that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Capacitor structure with asymmetric terminals

A passive discrete device (400) includes a first asymmetric terminal (410A) and a second asymmetric terminal (410B). The passive discrete device (400) further includes first internal electrodes (420A) extended to electrically couple to a first side and a second side of the first asymmetric terminal (410A). The passive discrete device (400) also includes second internal electrodes (420B) extended to electrically couple to a first side and a second side of the second asymmetric terminal (420B).

Dispositivo integrado que compreende interconexão coaxial

Alguns recursos inovadores se referem a um dispositivo integrado que inclui um substrato, uma primeira interconexão acoplada ao substrato e uma segunda interconexão que circunda a primeira interconexão. A segunda interconexão pode ser configurada para fornecer uma conexão elétrica para aterramento. Em algumas implantações, a segunda interconexão inclui uma placa. Em algumas implantações, o dispositivo integrado também inclui um material dielétrico entre a primeira interconexão e a segunda interconexão. Em algumas implantações, o dispositivo integrado também inclui um molde que circunda a segunda interconexão. Em algumas implantações, a primeira interconexão é configurada para conduzir um sinal de energia em uma primeira direção. Em algumas implantações, a segunda interconexão é configurada para conduzir um sinal de aterramento em uma segunda direção. Em algumas implantações, a segunda direção é diferente da primeira direção. Em algumas implantações, o dispositivo integrado pode ser um dispositivo de pacote em pacote (PoP).

dispositivo integrado que compreende interconexão coaxial

alguns recursos inovadores se referem a um dispositivo integrado que inclui um substrato, uma primeira interconexão acoplada ao substrato e uma segunda interconexão que circunda a primeira interconexão. a segunda interconexão pode ser configurada para fornecer uma conexão elétrica para aterramento. em algumas implantações, a segunda interconexão inclui uma placa. em algumas implantações, o dispositivo integrado também inclui um material dielétrico entre a primeira interconexão e a segunda interconexão. em algumas implantações, o dispositivo integrado também inclui um molde que circunda a segunda interconexão. em algumas implantações, a primeira interconexão é configurada para conduzir um sinal de energia em uma primeira direção. em algumas implantações, a segunda interconexão é configurada para conduzir um sinal de aterramento em uma segunda direção. em algumas implantações, a segunda direção é diferente da primeira direção. em algumas implantações, o dispositivo integrado pode ser um dispositivo de pacote em pacote (pop).

Flexible film electrical-test substrates with conductive coupling post(s) for integrated circuit (ic) bump(s) electrical testing, and related methods and testing apparatuses

Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.

Stiffener with embedded passive components

Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package (200). A continuous or uninterrupted stiffener structure (208) is designed with a recessed groove (208b), such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate (202) using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices (204) that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Integrated device package and/or system comprising configurable directional optical transmitter

Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

RF filter device for aircraft nacelle access door gap

An assembly for electromagnetic interference (EMI) shielding to prevent incident radiation from penetrating through a gap to an interior of an aircraft includes an electromagnetic band gap (EBG) structure. The EBG structure has a patch-and-via array connected to a ground layer. The EMI shielding includes a conductive adhesive and is flexible for conforming attachment to curved aircraft surfaces. The shielding may be located on a deflector plate that is parallel to an adjacent aircraft surface, on the airframe surface opposite to the deflector plate, or in both locations. The assembly filters out penetrating electromagnetic energy and prevents highly resonant cavity mode build-ups of electromagnetic energy inside a nacelle or other enclosure effectively protecting electrical equipment in the interior.

Power distribution improvement using pseudo-esr control of an embedded passive capacitor

A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Low profile reinforced package-on-package semiconductor device

The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages

One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Multilayer ceramic capacitor including at least one slot

An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.

Capacitor structure for wideband resonance suppression in power delivery networks

Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a nonoverlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The nonconductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Embedded package substrate capacitor

Pattern between pattern for low profile substrate

An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Pattern between pattern for low profile substrate

An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Pattern between pattern for low profile substrate

An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Pattern between pattern for low profile substrate

Multilayer ceramic capacitor including at least one slot

An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.