Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

Structure and method for bond pads of copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1x10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 mum. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1x10E-14 cm2/s at 250° C. and a thickness of less than 1.5 mum. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost ...

GaN power device with solderable back metal

A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING PROCESSES

STRUCTURE AND METHOD FOR CONTACT PADS HAVING AN OVERCOAT-PROTECTED BONDABLE METAL PLUG OVER COPPER-METALLIZED INTEGRATED CIRCUITS

A metal structure for a contact pad of an integrated circuit (IC), which has copper interconnecting metallization (311). A portion (301) of this metallization is exposed to provide a contact pad to the IC. A conductive barrier layer (330) is positioned on the exposed portion of the copper metallization. A plug (350) of bondable metal, preferably aluminum between about 0.4 and 1.4 µm thick, is positioned on the barrier layer. A protective overcoat layer (320) surrounds the plug and has a thickness (320b) so that the exposed surface (322) of the plug lies at or below the exposed surface (320a) of the overcoat layer. Optionally, a portion (321) of the overcoat layer between about 0.1 and 0.3µm wide may overlap the perimeter of the plug.

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

Semiconductor device and method of manufacturing the same

A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device

A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin.

CONTACTING STRUCTURE OF AN INTEGRATED ACHIEVEMENT CIRCUIT

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

Wire bonding process for copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

SEMICONDUCTOR DEVICE

A semiconductor device which is provided with enhanced reliability and capable of preventing cracking of a layer below an interconnection layer and separation of the interconnection layer and a bonding pad electrode layer. The semiconductor device includes: an interconnection layer including a conductive material formed on a silicon substrate; an intermediate layer formed in contact with interconnection layer and including a titanium layer and a titanium nitride layer; and a bonding pad electrode layer which is in contact with the intermediate layer.

Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder ...

SEMICONDUCTOR CHIP, AND FABRICATION AND PACKAGING METHODS THEREOF

A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.

Light emitting diode module for surface mount technology and method of manufacturing the same

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Kontaktierungsstruktur einer integrierten Leistungsschaltung

Improvement of Electrode Structure in a Semiconductor Device.

... 1,196,834. Semi-conductor devices. HITACHI Ltd. 26 March, 1968 [29 March, 1967], Nov., 14541/68. Heading H1K. An electrode applied to a surface of a semiconductor wafer 22 having an insulating covering 32 comprises an Al layer 34 contacting the substrate surface and extending across the insulation 32, a layer 38 of a refractory metal; i.e. Mo, Cr, Ti, W or Ta; also extending across the insulation 32 and contacting the A1 layer 34, and a further metal layer 42; e.g. of Ag. Au, Ni or Cu: in contact with the layer 38. The refractory metal layer 38 is, in general, less finely shaped than the A1 layer 34, since it is less easily etched into detailed configurations. Thus in the Si transistor shown the A1 layer 34 forms a comb-like base electrode interdigitated with a similar comb-like A1 emitter electrode 36 connected to a series of strip-like emitter regions and on which are provided a relatively large-area rectangular refractory metal layer 40 and a further metal layer 44. The layer 38 is similarly ...

Ball limiting metalization process for interconnection

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder ...

Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal

This invention relates generally to structure and method for preventing metal diffusion between a noble metal layer and an adjoining non-noble metal layer, and more specifically to new structures and methods for providing a superbarrier structure between copper and an adjoining noble metal layer. This is achieved by sequentially deposited a layer of non-noble metal, a layer of titanium, a layer of molybdenum, and a layer of noble or relatively less noble metal as the interconnecting metallurgy. This invention also relates to an improved multilayer metallurgical pad or metallurgical structure for mating at least a portion of a pin or a connector or a wire to a substrate.

Organic light emitting display device and method of manufacturing the same

Discussed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device according to an embodiment includes a substrate including an active area and a pad area, a thin film transistor (TFT) in the active area of the substrate, an anode electrode on the TFT, an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, an auxiliary electrode connected to the cathode electrode and disposed on the same layer as the anode electrode, a signal pad in the pad area of the substrate, and a pad electrode connected to the signal pad to cover a top of the signal pad for preventing the top of the signal pad from being corroded. The TFT includes a gate electrode. The signal pad is disposed on the same layer as the gate electrode.

METAL BUMP STRUCTURE AND MANUFACTURING METHOD THEREOF AND DRIVING SUBSTRATE

A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

HALBLEITERVORRICHTUNG MIT METALLISIERUNGSSTRUKTUR UND HERSTELLUNGSVERFAHREN FÜR DIESE

Eine Halbleitervorrichtung (100) beinhaltet ein Halbleitersubstrat (110) mit einer ersten Seite (101) und einer zweiten Seite (102) und wenigstens ein Dotierungsgebiet (111, 112), das an der ersten Seite (101) des Halbleitersubstrats (110) gebildet ist. Die Halbleitervorrichtung (100) beinhaltet ferner eine erste Metallisierungsstruktur (120) an der ersten Seite (101) des Halbleitersubstrats (110) und auf und in Kontakt mit dem wenigstens einen Dotierungsgebiet (111, 112) und eine zweite Metallisierungsstruktur (130) an der zweiten Seite (102) des Halbleitersubstrats (110). Die zweite Metallisierungsstruktur (130) bildet ein Silicidgrenzflächengebiet (135) mit dem Halbleitersubstrat (110) und ein Nichtsilicidgrenzflächengebiet (136) mit dem Halbleitersubstrat (110).

Verfahren zum Drahtbonden

METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS USING MASKLESS BACK SIDE ALIGNMENT TO CONDUCTIVE VIAS

INTEGRATED ELECTRONIC DEVICE WITH A REDISTRIBUTION REGION AND A HIGH RESILIENCE TO MECHANICAL STRESSES AND METHOD FOR ITS PREPARATION

An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Discussed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device according to an embodiment includes a substrate including an active area and a pad area, a thin film transistor (TFT) in the active area of the substrate, an anode electrode on the TFT, an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, an auxiliary electrode connected to the cathode electrode and disposed on the same layer as the anode electrode, a signal pad in the pad area of the substrate, and a pad electrode connected to the signal pad to cover a top of the signal pad for preventing the top of the signal pad from being corroded. The TFT includes a gate electrode. The signal pad is disposed on the same layer as the gate electrode.

Verbindungsstruktur mit Begrenzungsschicht

Es werden eine Verbindungsstruktur sowie ein Verfahren für die Bereitstellung einer Verbindungsstruktur, die leitfähige Elemente mit verringerten topografischen Schwankungen aufweist, offenbart. Die Verbindungsstruktur umfasst ein Kontaktpad, das über einem Substrat angeordnet ist. Das Kontaktpad umfasst eine erste Schicht auf einem ersten leitfähigen Material sowie eine zweite Schicht aus einem zweiten leitfähigen Material über der ersten Schicht. Das erste leitfähige Material und das zweite leitfähige Material bestehen im Wesentlichen aus demselben Material und sie weisen eine erste mittlere Korngröße und eine zweite mittlere Korngröße, die kleiner als die erste mittlere Korngröße ist, auf. Die Verbindungsstruktur umfasst weiterhin eine Passivierungsschicht, welche das Substrat und das Kontaktpad bedeckt, wobei die Passivierungsschicht eine Öffnung aufweist, welche das Kontaktpad freilegt.

Verfahren zum Drahtbonden

Robuste Intermetallische-Verbindung-Schicht-Grenzfläche für ein Gehäuse in einer Gehäuseeinbettung

Ausführungsformen können ein eingebettetes Gehäuse mit einer Diffusionsbarriereschicht betreffen, die zwischen einem Kupfer(Cu)-Pad und einer Lötkugel innerhalb des eingebetteten Gehäuses platziert ist. Während des Lotaufschmelzprozesses wird eine Intermetallische-Verbindung(IMC)-Schicht erzeugt, die nicht mit dem Cu in Kontakt kommt, so dass anschließende hohe Temperaturen, die auf das eingebettete Gehäuse angewandt werden, möglicherweise nicht bewirken, dass das Cu durch Diffusion verbraucht wird. Andere Ausführungsformen können beschrieben und/oder beansprucht werden.

METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS USING MASKLESS BACK SIDE ALIGNMENT TO CONDUCTIVE VIAS

CONDUCTIVE PARTICLES

System and method for dual-region singulation

A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.

Semiconductor Device with Metallization Structure and Method for Manufacturing Thereof

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT

Semiconductor devices and methods for manufacturing the same

Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors

A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.

SEMICONDUCTOR DEVICE AND POWER AMPLIFIER MODULE

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Process for the metallization of the semiconductors and semiconductor forms by this process

WIRE BONDING PROCESS FOR COPPER-METALLIZED INTEGRATED CIRCUITS

Process for protecting solder joints and structure for alleviating electromigration and joule heating in solder joints

This invention provides a process for protecting solder joints, comprising forming an UBM or pad metallurgy in solder joints and then further forming a small solder bump on UBM or pad metallurgy between substrate and chip. Wherein a material of high electric resistance is coated at the ends of UBM or pad metallurgy where substrate is connected to chip, as to equalize the current distribution of solder bump, therefore the electromigration resistance of solder joints is improved by suppressing the current crowding and joule heating phenomenon.

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

LIGHT EMITTING DIODE HAVING MULTILAYER BONDING PAD

A light-emitting diode having a multilayer bonding pad includes: a P1 layer disposed under a light-emitting structure and configured to improve ohmic contact and adhesion; a P3 layer disposed under the P1 layer and configured to prevent diffusion; a Sn-based metal layer disposed under the P1 layer and configured to enhance soldering weldability and prevent oxidation; a Cu-based P5 layer disposed on the Sn-based metal layer and configured to prevent the diffusion of Sn; and a P4 layer disposed between the P3 layer and the P5 layer and configured to suppress the reaction between the P5 layer and other layers.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

To restrict the deterioration of properties in a semiconductor device due to hydrogen, provided is a semiconductor device including a semiconductor substrate; a hydrogen absorbing layer that is provided above a top surface of the semiconductor substrate and formed of a first metal having a hydrogen absorbing property; a nitride layer that is provided above the hydrogen absorbing layer and formed of a nitride of the first metal; an alloy layer that is provided above the nitride layer and formed of an alloy of aluminum and a second metal; and an electrode layer that is provided above the alloy layer and formed of aluminum. A pure metal layer of the second metal is not provided between the electrode layer and the nitride layer.

Display panel, manufacturing method of display panel, and display device

A display panel, a manufacturing method thereof, and a display device are disclosed. The display panel includes: a base substrate, provided with a terminal and a terminal protection layer pattern; the terminal protection layer pattern includes a first shielding region and a first opening region, an orthographic projection of the first shielding region on the base substrate and an orthographic projection of the terminal on the base substrate have an overlapping region, the overlapping region is located at an edge of the orthographic projection of the terminal on the base substrate, and an orthographic projection of the first opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device which uses an apparatus for manufacturing the semiconductor device including: a chamber, a support structure provided inside the chamber, and configured to support a bonding structure that comprises a first substrate structure, a second substrate structure, and a bonding metal layer provided between the first substrate structure and the second substrate structure, and a laser device which is provided above the chamber, the semiconductor device manufacturing method comprising: irradiating a laser beam to the bonding structure using the laser device.

Semiconductor device has an interlayer of titanium, molybdenum, tungsten or silicides or nitrides between and in contact with a connection layer and a connection pad electrode layer

Semiconductor device has an interlayer (9, 10) of titanium, molybdenum, tungsten or their silicides or nitrides between and in contact with a connection layer (3) and a connection pad electrode layer (6). Preferred Features: The interlayer consists of a Ti layer (9) and a TiN layer (10). The connection layer (3) and the connection pad electrode layer (6) consist of Al.

Method for fabricating semiconductor components using maskless back side alignment to conductive vias

CONDUCTIVE PARTICLES AND METHOD AND DEVICE FOR MANUFACTURING THE SAME, ANISOTROPIC CONDUCTIVE ADHESIVE AND CONDUCTIVE CONNECTION STRUCTURE, AND ELECTRONIC CIRCUIT COMPONENTS AND METHOD OF MANUFACTURING THE SAME

An electrical connection is formed by using a double laminated conductive fine particle provided with a conductive metal layer on the surface of a spherical elastic base particle by electroless plating and electroplating and a layer of a low-melting-point metal on the surface of the conductive metal layer and wherein the conductive metal layer comprises a plurality of metal layers.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.

ELECTRONIC DEVICE

An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Elektronisches Bauteil und Verfahren zum Herstellen

Erläutert wird unter anderem ein elektronisches Bauteil (400), umfassend: - ein integriertes Bauelement (10) mit einer ersten Schicht (44), die aus Kupfer oder einer Kupferlegierung besteht oder die Kupfer oder eine Kupferlegierung enthält, und mit ederen Material sich von dem Material der ersten Schicht (44) unterscheidet, - und eine Verbindungsvorrichtung (60), die an der ersten Schicht (44) und an der zweiten Schicht (52) angeordnet ist.

HÖCKERSTRUKTUR UND HERSTELLUNGSVERFAHREN EINER HÖCKERSTRUKTUR

Ein Verfahren zur Herstellung einer Höckerstruktur umfasst das Bilden einer Passivierungsschicht über einem Substrat. Eine Metallpadstruktur wird über dem Substrat gebildet, wobei die Passivierungsschicht die Metallpadstruktur umgibt. Eine Polyimidschicht, die ein Polyimid enthält, wird über der Passivierungsschicht und der Metallpadstruktur gebildet. Ein Metallhöcker wird über der Metallpadstruktur und der Polyimidschicht gebildet. Das Polyimid ist ein Reaktionsprodukt eines Dianhydrids und eines Diamins, wobei mindestens eines von Dianhydrid und Diamin eines aus der folgenden Gruppe enthält: ein Cycloalkan, ein kondensierter Ring, ein Bicycloalkan, ein Tricycloalkan, ein Bicycloalken, ein Tricycloalken, ein Spiroalkan und ein heterocyclischer Ring.

Leistungshalbleiterkontaktstruktur mit Bondbuffer sowie Verfahren zu dessen Herstellung

Es wird eine Leistungshalbleiterkontaktstruktur für Leistungshalbleitermodule beschrieben, welche zumindest ein Substrat 1 und einen Metallformkörper 2 als Elektrode aufweisen, welche mittels einer im Wesentlichen geschlossenen Sinterschicht 3a mit Bereichen variierender Dicke aufeinandergesintert sind. Der Metallformkörper 2 ist dabei in Form einer flexiblen Kontaktierungsfolie 5 mit einer derartigen Dicke ausgebildet, dass diese mit ihrer der Sinterschicht 3a zugewandten Seite 4 im Wesentlichen vollständig an die Bereiche variierender Dicke der Sinterschicht angesintert ist. Des Weiteren wird ein Verfahren beschrieben zum Ausbilden einer Leistungshalbleiterkontaktstruktur in einem Leistungshalbleitermodul, welches ein Substrat und einen Metallformkörper aufweist. Das Ausbilden der Leistungshalbleiterkontaktstruktur erfolgt zunächst durch Aufbringen einer Schicht aus Sintermaterial mit lokal variierender Dicke auf entweder den Metallformkörper 2 oder das Substrat, gefolgt von einem Zusammensintern ...

Semiconductor device

A highly reliable semiconductor device, which is capable of preventing from cracking of a layer below an interconnection layer and peeling between the interconnection layer and a bonding-pad electrode layer, is provided in the present invention. The invented semiconductor device is provided with the followings: an interconnection layer 3, which is composed of conductive material and is formed on a silicon substrate 1; an intermediate layer, which is formed in contact with the interconnection layer 3 and is composed of a titanium layer 9 and a titanium nitride layer 10; and a bonding-pad electrode layer 6, which is in contact with the intermediate layer.

CHIP HAVING SIDE PAD, METHOD OF FABRICATING THE SAME AND PACKAGE USING THE SAME

A semiconductor device includes a first chip having a top surface, a bottom surface and a side surface connected to the top and bottom surfaces. The first chip includes a chip substrate; a lower conductive pattern over the chip substrate; an interlayer dielectric layer over the lower conductive pattern; and an upper conductive pattern over the interlayer dielectric layer. At least a portion of the lower conductive pattern and at least a portion of the upper conductive pattern are exposed on the side surface of the first chip to collectively form a side pad.

Pad structure and display device having the same

A display device includes a plurality of signal lines arranged in a display area of a substrate and a pad structure located at a non-active area and connected with the signal lines. The pad structure includes a plurality of metal layers and two or more insulating layers located between the metal layers and having one or more contact hole which makes two metal layers among the metal layers contacted with each other, and the contact holes respectively located in the insulating layers are not overlapped with each other.

Halbleiterelement, Halbleitervorrichtung und Verfahren zum Herstellen eines Halbleiterelemts

Es wird ein Halbleiterelement mit einer Elektrode angegeben, wobei das Halbleiterelement und eine Metall-Nanopartikel aufweisende gesinterte Schicht in stabiler Weise für eine ausreichend lange Zeitdauer haftend miteinander verbunden sind, selbst wenn das Halbleiterelement bei einer hohen Temperatur, insbesondere einer Temperatur von 175°C oder mehr, betrieben wird. Das Halbleiterelement besitzt eine Elektrode, die folgendes aufweist: eine Nickel enthaltende Metallschicht (4), die auf einer Seite von mindestens einer Oberfläche des Halbleiterelement-Ausbildungsteils gebildet ist; eine Nickelbarrieren-Metallschicht (5), die an einer Außenseite der Nickel enthaltenden Metallschicht (4) gegenüber von der Seite zu dem Halbleiterelement-Ausbildungsteil hin gebildet ist; und eine Oberflächen-Metallschicht (6), die an einer Außenseite der Nickelbarrieren-Metallschicht (5) gegenüber von der Seite zu dem Halbleiterelement-Ausbildungsteil hin gebildet ist und mit der Metall-Nanopartikel gesinterten ...

Schichtstapel und Integrierter-Schaltkreis-Anordnungen

In verschiedenen Ausführungsformen wird ein Schichtstapel bereitgestellt. Der Schichtstapel kann aufweisen: einen Träger; ein erstes Metall, das auf oder über dem Träger angeordnet ist; ein zweites Metall, das auf oder über dem ersten Metall angeordnet ist; und ein Lötmaterial, das auf oder über dem zweiten Metall angeordnet ist, oder ein Material, das einen Kontakt bereitstellt zu einem Lötmaterial, das von einer externen Quelle zugeführt wird. Das zweite Metall kann eine Schmelztemperatur von mindestens 1800°C haben und ist während eines Lötprozesses und/oder nach dem Lötprozess nicht oder im Wesentlichen nicht in dem Lötmaterial gelöst.

SEMICONDUCTOR DEVICE

PURPOSE: A semiconductor device is provided which prevents the generation of a crack in a lower layer of an interconnection layer and thus improves the reliability of the semiconductor device. CONSTITUTION: A semiconductor device prevents the crack of a lower layer of an interconnection layer(3) and also prevents the delamination between the interconnection layer and a bonding pad electrode layer(6). The semiconductor device comprises: the interconnection layer formed with a conductive material on a silicon substrate(1); a medium layer formed with a titan layer(9) and a titan nitride layer(10) to be contacted with the interconnection layer; and the bonding pad electrode layer contacted with the medium layer. COPYRIGHT 2000 KIPO ...

SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor component having plate and stacked dice

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Metal bump structure and manufacturing method thereof and driving substrate

A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

Semiconductor device and method of manufacturing the same

A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Multi-dice chip scale semiconductor components

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Chip having side pad, method of fabricating the same and package using the same

A semiconductor device includes a first chip having a top surface, a bottom surface and a side surface connected to the top and bottom surfaces. The first chip includes a chip substrate; a lower conductive pattern over the chip substrate; an interlayer dielectric layer over the lower conductive pattern; and an upper conductive pattern over the interlayer dielectric layer. At least a portion of the lower conductive pattern and at least a portion of the upper conductive pattern are exposed on the side surface of the first chip to collectively form a side pad.

Interconnection Structure with Confinement Layer

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Wire welding tech. for copper metallized integrated circuit

Semiconductor device and method of manufacturing the same

A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Leistungshalbleiterkontaktstruktur mit Bondbuffer sowie Verfahren zu dessen Herstellung

Leistungshalbleiterkontaktstruktur für Leistungshalbleitermodule mit zumindest einem Substrat (1) und einem Metallformkörper (2) als Elektrode, welche mittels einer geschlossenen Sinterschicht (3a) mit Bereichen variierender Dicke aufeinandergesintert sind, wobei der Metallformkörper (2) in Form einer flexiblen Kontaktierungsfolie (5) mit einer derartigen Dicke ausgebildet ist, dass dieser mit seiner der Sinterschicht (3a) zugewandten Seite (4) vollständig an die Bereiche variierender Dicke der wellig ausgeprägten Sinterschicht angesintert ist und auch an seiner der Sinterschicht abgewandten Seite die bewusst erzeugte wellige Struktur aufweist, wobei an der Höhen und Tiefen aufweisenden, den Bereichen variierender Dicke angepassten Kontaktierungsfolie (5) Kontaktdraht oder-bändchen derart metallisch verbunden sind, dass der Kontaktdraht oder das -bändchen zumindest zwei Höhen mit einer Tiefe dazwischen überdeckt.

Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelementes

Ein Verfahren zum Herstellen eines Halbleiterbauelementes weist das Abscheiden einer Sperrschicht auf einer ersten Oberfläche eines Halbleiterkörpers, welcher aktive Gebiete eines Halbleiterbauelementes aufweist, das Ausbilden einer Kontaktschicht derart, dass diese die Sperrschicht zumindest teilweise bedeckt, wobei die Sperrschicht dazu ausgebildet ist ein Material der Kontaktschicht daran zu hindern in den Halbleiterkörper hineinzudiffundieren, das Ausbilden einer ersten Passivierungsschicht auf der Kontaktschicht und auf freiliegenden Oberflächen der Sperrschicht, in einem ersten Ätzschritt das Entfernen der ersten Passivierungsschicht von oberhalb der Sperrschicht um Bereiche der Sperrschicht freizulegen, und in einem zweiten Ätzschritt, das Entfernen wenigstens einiger Bereiche der Sperrschicht auf, welche durch den ersten Ätzschritt freigelegt wurden.

System and method for dual-region singulation

Method for fabricating semiconductor components using maskless back side alignment to conductive vias

A method for fabricating semiconductor components (90) includes the steps of: providing a semiconductor substrate (52) having a circuit side (54), a back side (56) and conductive vias (58); removing portions of the substrate (52) from the back side (56) to expose terminal portions (76) of the conductive vias (58); depositing a polymer layer (78) on the back side (56) encapsulating the terminal portions (76); and then planarizing the polymer layer (78) and ends of the terminal portions (76) to form self aligned conductors embedded in the polymer layer (78). Additional back side elements, such as terminal contacts (86) and back side redistribution conductors (88), can also be formed in electrical contact with the conductive vias (58). A semiconductor component (90) includes the semiconductor substrate (52), the conductive vias (58), and the back side conductors embedded in the polymer layer (78). A stacked semiconductor component (96) includes a plurality of components (90-1, 90-2, 90-3) ...

Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same

A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

Semiconductor element, semiconductor device and method for manufacturing semiconductor element

The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a Ni-barrier metal layer formed outwardly on a side of the Ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the Ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the Ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer.

Power semiconductor contact structure and production method thereof

SEMICONDUCTOR DEVICE

밀폐층을 갖는 배선 구조

... 토포그래피 변화가 감소된 전도성 특징부를 포함하는 배선 구조 및 방법이 개시된다. 배선 구조는 기판 위에 배치된 컨택 패드를 포함한다. 컨택 패드는 제1 도전 재료의 제1 층과, 상기 제1 층 위에 제2 도전 재료의 제2 층을 포함한다. 제1 도전 재료와 제2 도전 재료는 실질적으로 동일한 재료로 이루어지며, 제1 도전 재료는 제1 평균 입자 크기를 가지고, 상기 제2 도전 재료는 상기 제1 평균 입자 크기보다 작은 제2 평균 입자 크기를 가진다. 배선 구조는 또한, 기판과 컨택 패드를 피복하며, 컨택 패드를 노출시키는 개구를 갖는 패시베이션층을 포함한다.

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device

A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

SEMICONDUCTOR DEVICE

PURPOSE: To improve the high frequency characteristics of a semiconductor device by forming a contacting part of a molybdenum layer and an aluminum layer directly under a wiring terminal, thereby reducing the contacting resistance of molybdenum and aluminum. CONSTITUTION: An Mo layer 3 is formed through a thin gate insulating film 2 on an Si substrate 1. Part of the layer 3 is extended as Mo wirings on a thick insulating film 4, and a wiring terminal is widely formed. An aluminum layer 8 is contacted through a through hole 6 of large diameter of the second insulating film (phosphorus silicate glass or the like) thereon, and Au wirings 9 are bonded as a bonding pad. The Au and the Mo are approached or contacted through the aluminum layer by the bonding of the Au wirings 9, thereby reducing the contacting resistance. COPYRIGHT: (C)1983,JPO&Japio ...

Kontaktierungsstruktur einer integrierten Leistungsschaltung

Individualized low parasitic power distribution lines deposited over active integrated circuits

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mOmega/. and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

Light emitting device and method of manufacturing light emitting device

A method of manufacturing a light emitting device includes preparing wafer with a plurality of light emitting elements arrayed on a growth substrate, on a first side of a semiconductor stacked layer body, forming a resin layer which includes metal wires respectively connected to a p-side electrode and an n-side electrode, forming a groove by removing at least portion of the resin layer from an upper surface side in a boundary region between the light emitting elements and exposing end surfaces of metal wires which are internal conductive members on an inner side surface defining a groove, forming electrodes for external connection respectively connecting to exposed end surfaces of metal wires, and singulating the wafer into a plurality of singulated light emitting elements.

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION CAP

A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection ...

System and Method for Dual-Region Singulation

A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.

SEMICONDUCTOR DEVICE

PURPOSE: To obtain a semiconductor device having leads of high moisture resistance and weld strength and proper hardness by using an Mo electrode attached with a copper clad iron wire. COPYRIGHT: (C)1977,JPO&Japio ...

Verfahren zum Bilden eines Bondpads und Bondpad

Verschiedene Ausführungsformen schaffen ein Verfahren zum Bilden eines Bondpads, wobei das Verfahren das Bereitstellen eines rohen Bondpads und das Bilden einer Aussparungsstruktur an einer Kontaktfläche des rohen Bondpads umfasst, wobei die Aussparungsstruktur Seitenwände umfasst, die in Bezug auf die Kontaktfläche geneigt sind.

Composite material, material for light-emitting element, light-emitting element, light-emitting device and electronic device

BONDING STRUCTURE FOR A MICROELECTRONIC ASSEMBLY COMPRISING A HIGH MELTING POINT ALLOY FORMED BY BONDING TWO BOND COMPONENTS EACH COMPRISING A NON-LOW MELTING POINT MATERIAL LAYER COVERING A LOW MELTING POINT MATERIAL LAYER AND CORRESPONDING MANUFACTURING METHOD

A microelectronic assembly (10, 110, 210, 310, 410) includes a first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) having a first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a second substrate (14, 114, 214, 314, 414) having a second conductive element (26, 126, 226, 326, 426). The assembly further includes an electrically conductive alloy mass (16, 116) joined to the first and second conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022), including a first, a second and a third material. First and second materials of the alloy mass (16, 116) each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) to a relatively lower amount toward the second conductive element (26, 126, 226, 326, 426), and a concentration ...

Structure and method for bond pads of copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1x10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 mum. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1x10E-14 cm2/s at 250° C. and a thickness of less than 1.5 mum. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost ...

Semiconductor element, semiconductor device, and method for manufacturing semiconductor element

The purpose of the present invention is to achieve a semiconductor element which has an electrode that enables stable close adhesion between the semiconductor element and a metal nanoparticle sintered layer for a sufficiently long period of time even in cases where the semiconductor element operates at high temperatures, especially at 175 DEG C or higher. The semiconductor element comprises an electrode that is provided with: an Ni-containing metal layer (4) which is formed on at least one surface of a semiconductor element structure portion and contains Ni; an Ni barrier metal layer (5) which is formed outside a surface of the Ni-containing metal layer (4), said surface being on the reverse side of the semiconductor element structure portion-side surface thereof; and a surface metal layer (6) which is formed outside a surface of the Ni barrier metal layer (5), said surface being on the reverse side of the semiconductor element structure portion-side surface thereof, and connected to a ...

ELECTRONIC CIRCUIT COMPONENTS

Bond pad structure

A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second oxide layer is formed over the plurality of adhesion structures and the first oxide layer. Each one of a plurality of contact openings formed within a surface region of the second oxide layer includes one or more sides and is aligned over at least a portion of a top surface of a corresponding one of the plurality of adhesion structures. A barrier layer is formed within the surface region that is over the second oxide layer and within the plurality of contact openings and over the at least a portion of the top surface of the corresponding ones of the plurality of adhesion structures. A metal layer is formed over the barrier layer.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Redistribution layers for microfeature workpieces, and associated systems and methods

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Sealed surface acoustic wave element package

An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Stacked Integrated Chips and Methods of Fabrication Thereof

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Fluorine depleted adhesion layer for metal interconnect structure

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

SEMICONDUCTOR STRUCTURE CONTAINING PRE-POLYMERIZED PROTECTIVE LAYER AND METHOD OF MAKING THEREOF

A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer. 1. A method of forming a semiconductor structure , comprising:providing a semiconductor wafer including a plurality of semiconductor dies;providing a polymerized material layer;attaching the polymerized material layer to the semiconductor wafer, wherein the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer;applying and patterning an etch mask layer over the polymerized material layer, wherein openings are formed through the etch mask layer;etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process; andremoving the etch mask layer selective to the polymerized material layer.2. The method of claim 1 , wherein the semiconductor wafer comprises:bonding pads located within the plurality of semiconductor dies; anda passivation dielectric layer covering peripheral portions of the bonding pads and covering dielectric material layers of the ...

Semiconductor Package System and Method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. 1. A semiconductor device comprising:a semiconductor die with a first sidewall;a first protective layer over the semiconductor die, wherein a second sidewall of the first protective layer is recessed from the first sidewall of the semiconductor die;an opening through the first protective layer;an encapsulant covering the first sidewall and the second sidewall, wherein the encapsulant has a top surface that is planar with the first protective layer; anda conductive material filling the opening and extending over the encapsulant.2. The semiconductor device of claim 1 , further comprising a second protective layer over the conductive material.3. The semiconductor device of claim 2 , further comprising an underbump metallization extending through the second protective layer to make electrical contact with the conductive material.4. The semiconductor device of claim 2 , wherein the second protective layer has a third sidewall aligned with a fourth sidewall of the encapsulant.5. The semiconductor device of claim 1 , further comprising a through via extending through the encapsulant and in electrical connection with the conductive material.6. The semiconductor device of claim 1 , wherein the conductive material is in physical contact with the encapsulant.7. The semiconductor device of claim 6 , wherein the conductive material is copper.8. A semiconductor device comprising:a protective material overlying a first surface of a semiconductor die, the protective material having a second surface facing away from the first surface;an encapsulant encapsulating the ...

PROCESS FLOW FOR FABRICATION OF CAP METAL OVER TOP METAL WITH SINTER BEFORE PROTECTIVE DIELECTRIC ETCH

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer. 1. A method of forming a semiconductor device , comprising:providing a device substrate containing the semiconductor device, the device substrate including a semiconductor material;forming an active component extending into the semiconductor material;forming an interconnect region on the semiconductor material; andforming a top metal layer in the interconnect region;forming a protective dielectric layer on the top metal layer, the protective dielectric layer being at least 1 micron thick;heating the semiconductor device in a sintering operation while the protective dielectric layer covers the top metal layer;after the sintering operation, removing the protective dielectric layer from a bond pad opening in the protective dielectric layer to expose a portion of the top metal layer; andforming a bond pad cap on the top metal layer in the bond pad opening.2. The method of claim 1 , wherein the sintering operation has a sinter thermal profile sufficient to passivate the active component.3. The method of claim 2 , wherein the sinter thermal profile includes heating the semiconductor device to a sinter temperature for a sinter time claim 2 , wherein a product of the sinter time claim 2 , in minutes claim 2 , and an Arrhenius factor of the sinter temperature is greater than 0.0027 minutes claim 2 , the Arrhenius factor of the sinter temperature being determined by the expression:{'br': None, 'i': E', 'k', '+T, 'sub': A ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;a foundation layer formed on the first face of the semiconductor substrate;a first electrode formed on the foundation layer;a second electrode formed on the foundation layer;an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face of the semiconductor substrate, and the integrated circuit being electrically connected to the first electrode and the second electrode;a groove portion formed through the semiconductor substrate;an insulating film formed on a side wall of the groove portion;a conductive portion formed inside the groove portion on the insulating film and electrically connected to the second electrode;a first insulation layer formed on the foundation layer;a first interconnection formed on the first insulation layer, the first interconnection being electrically connected to the first electrode;a second insulation layer formed on the first interconnection and the first insulation layer;a second interconnection formed on the second insulation layer, the second interconnection being electrically connected to the first interconnection; anda third insulation layer formed on the second interconnection and the second insulation layer; ...

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

SELF-ALIGNED UNDER BUMP METAL

An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers. 1. A method of forming an integrated circuit , comprising;forming an interconnect region;forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad;forming a dielectric layer over the top interconnect level;forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad;forming an under bump metal layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, such that the under bump metal layer contacts the connection opening sidewall;selectively removing material from the under bump metal layer over the dielectric layer so as to form a self-aligned under bump metal pad, such that the self-aligned under bump metal pad contacts the connection opening sidewall, and such that the self-aligned under bump metal pad does not contact a top surface of the dielectric layer; andforming a solder ball on a top surface of the self ...

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing an organic light emitting display device, the method includes forming a thin film transistor (TFT) in an active area of a substrate and forming a signal pad and a first pad electrode, connected to the signal pad, in a pad area of the substrate, forming a passivation layer on the TFT and the first pad electrode, forming a planarization layer on the passivation layer, removing a certain region of the passivation layer to simultaneously form an area, through which the TFT is exposed to the outside, and an area through which the first pad electrode is exposed to the outside, forming a first anode electrode connected to the TFT, a first auxiliary electrode spaced apart from the first anode electrode, and a second pad electrode that is connected to the first pad electrode and covers the exposed first pad electrode; and forming a second anode electrode, covering a top and a side surface of the first anode electrode, and a second auxiliary electrode covering a top and a side surface of the first auxiliary electrode. 1. A method of manufacturing an organic light emitting display device , the method comprising:forming a thin film transistor (TFT) in an active area of a substrate and forming a signal pad and a first pad electrode, connected to the signal pad, in a pad area of the substrate;forming a passivation layer on the TFT and the first pad electrode;forming a planarization layer on the passivation layer;removing a certain region of the passivation layer to simultaneously form an area, through which the TFT is exposed to the outside, and an area through which the first pad electrode is exposed to the outside;forming a first anode electrode connected to the TFT, a first auxiliary electrode spaced apart from the first anode electrode, and a second pad electrode that is connected to the first pad electrode and covers the exposed first pad electrode; andforming a second anode electrode, covering a top and a side surface of the first anode electrode, ...

Al bond pad clean method

Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor.

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Semiconductor Die Singulation and Structures Formed Thereby

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. 1. A method comprising:receiving a wafer comprising:a first integrated circuit die;a second integrated circuit die; anda scribe line region between the first integrated circuit die and the second integrated circuit die; andforming a kerf in the scribe line region, wherein the kerf extends through a plurality of dielectric layers into a semiconductor substrate, and wherein the kerf comprises:a first width at an interface between the plurality of dielectric layers and the semiconductor substrate; anda second width at a surface of the plurality of dielectric layers opposite the semiconductor substrate, wherein a ratio of the first width to the second width is at least about 0.6.2. The method of claim 1 , wherein an angle between a bottom surface of the kerf and a sidewall of the kerf is about 90° to about 135°.3. The method of further comprising after forming the kerf claim 1 , using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die.4. The method of claim 3 , wherein the mechanical sawing process comprises using a saw blade having a third width claim 3 , wherein the third width is less than the first width.5. The method of claim 1 , wherein forming the kerf in the scribe line region comprises a laser ablation process.6. The method of claim 5 , wherein the laser ablation process further forms a recast region on a sidewall of the plurality of dielectric layers and a sidewall ...

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector. 1. A structure comprising:a first die;a molding compound at least laterally encapsulating the first die;a first redistribution structure comprising metallization patterns extending over the first die and the molding compound;a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure; andan integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.2. The structure of claim 1 , wherein a solder layer of the micro bump bonding joint contacts the first metallization pattern of the first redistribution structure claim 1 , and wherein the under bump metallization of the first conductive connector contacts a second metallization pattern in the first redistribution structure.3. The structure of claim 2 , wherein the first metallization pattern is at a same level in the first redistribution structure as the second metallization pattern.4. The structure of further comprising:a substrate bonded to the first redistribution structure using the first conductive connector.5. The structure of claim 4 , wherein the integrated passive device is interposed between the first redistribution structure and the substrate.6. The structure of further comprising:an electrical connector ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CURVED IMAGE SENSOR

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor die including a base semiconductor material comprising a first surface and a second surface opposite the first surface, wherein the second surface includes an image sensor area;applying a masking layer over the first surface of the base semiconductor material, wherein the masking layer includes openings of varying width;removing a portion of the first surface of the base semiconductor material to form a first curved surface; andmoving the base semiconductor material to change orientation of the second surface with the image sensor area into a second curved surface.2. The method of claim 1 , further including utilizing plasma etching to remove the portion of the first surface of the base semiconductor material.3. The method of claim 1 , further including disposing the semiconductor die on a substrate with the first curved surface oriented toward the substrate.4. The method of claim 1 , further including:providing a substrate;disposing the semiconductor die over the substrate with the first curved surface oriented toward the substrate; ...

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

SEMICONDUCTOR DEVICE PRODUCTION METHOD

A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4. 1. A semiconductor device production method comprising:forming a first recess portion in a first insulating film formed on a first substrate;forming a first conductive layer on a front surface of the first insulating film located both inside and outside the first recess portion;forming, in the first recess portion, a first pad having a width of 3 μm or less and including the first conductive layer by performing a first process of polishing the first conductive layer at a first polishing rate and, after the first process, a second process of polishing the first conductive layer at a second polishing rate which is lower than the first polishing rate, wherein the second process is performed such that a selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4; andjoining the first pad of the first substrate and a second pad of a second substrate together by annealing the first substrate and the second substrate.2. The semiconductor device production method according to claim 1 , wherein the first conductive layer contains copper.3. The semiconductor device production method according to ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor. 2. The method of claim 1 , wherein the disposing of the oxide layer is prior to or after the disposing of the nitride layer.3. The method of claim 1 , wherein the disposing of the oxide layer and the disposing of the nitride layer are alternately performed.4. The method of claim 1 , wherein the oxide layer and the nitride layer are disposed by chemical vapor deposition (CVD).5. The method of claim 1 , wherein the disposing of the third dielectric layer is performed after the formation of the capacitor.6. The method of claim 1 , wherein the oxide layer includes PEOX or USG.7. The method of claim 1 , wherein the nitride layer includes silicon nitride.8. The method of claim 1 , wherein the formation of the conductive via includes removing a portion of the oxide layer claim 1 , a portion of the nitride layer and a portion of the capacitor to form an opening surrounded by the oxide layer claim 1 , the nitride layer and the capacitor.9. The method of claim 8 , wherein a portion of the conductive member is exposed by the opening.10. The method of claim 8 , wherein the opening extends through the ...

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

INTERCHIP BACKSIDE CONNECTION

A multi-chip module structure (MCM) having improved heat dissipation includes a plurality of semiconductor chips having a front side mounted on a packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips further includes a through-substrate vias located at a backside of each semiconductor chip of the plurality of semiconductor chips. A plurality of wire bonds is present that provides interconnect between each semiconductor chip of the plurality of semiconductor chips and is located at the backside of each semiconductor chip of the plurality of semiconductor chips. A heat sink is located above a gap containing the plurality of wire bonds, and a cooling element is located on a surface of the heat sink. 1. A multi-chip module structure comprising:a plurality of semiconductor chips having a front side mounted by a controlled collapse chip connection (C4) on a packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips further comprises a plurality of through-substrate vias located at a backside of each semiconductor chip of the plurality of semiconductor chips;a plurality of wire bonds interconnecting each semiconductor chip of the plurality of semiconductor chips and located at the backside of each semiconductor chip of the plurality of semiconductor chips;a heat sink located above a gap containing the plurality of wire bonds; anda cooling element located on a surface of the heat sink.2. The multi-chip module structure of claim 1 , wherein the gap is completely filled with a thermal paste.3. The multi-chip module structure of claim 1 , wherein the gap is partially filled with a thermal paste.4. The multi-chip module structure of claim 1 , wherein the cooling element is a fan.5. The multi-chip module structure of claim 1 , wherein each semiconductor chip of the plurality of semiconductor chips comprises a dielectric material on the backside of the semiconductor chip claim 1 , each dielectric material ...

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLCSP

A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor substrate including a plurality of semiconductor die with a saw street between the semiconductor die;forming a plurality of bumps over a first surface of the semiconductor die;forming an insulating layer over the first surface of the semiconductor die between the bumps;singulating the semiconductor substrate through removing substrate material through an entire thickness of the semiconductor substrate in the saw street;moving the semiconductor die to increase a space between the semiconductor die;depositing an encapsulant over the semiconductor die and into the space between the semiconductor die; andforming a channel through the encapsulant between the semiconductor die to separate the semiconductor die.2. The method of claim 1 , wherein removing the substrate material further comprises removing the substrate material using a saw blade.3. The method of claim 1 , further including depositing the encapsulant over a portion of the first surface of the ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

IMAGE SENSOR

An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate. 1. An image sensor comprising:a first substrate comprising a pixel array region comprising a plurality of pixel regions and a peripheral region around the pixel array region;a plurality of photoelectric conversion units respectively positioned in the plurality of pixel regions of the first substrate;a first connection layer disposed on the pixel array region and the peripheral region of the first substrate;a plurality of first pixel pads disposed on a portion of the first connection layer on the pixel array region of the first substrate;a plurality of first peripheral pads disposed on a portion of the first connection layer on the peripheral region of the first substrate;a plurality of second pixel pads respectively positioned on the plurality of first pixel pads;a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads;a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads;a device disposed on the second connection layer; anda ...

Semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A semiconductor device comprising:a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization over a first contact of a first package; anda second package over the first package, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with a second underbump metallization.2. The semiconductor device of claim 1 , wherein the first external conductive connector comprises a solder material.3. The semiconductor device of claim 1 , wherein the first post-contact material has a thickness of between about 10 μm and about 200 μm.4. The semiconductor device of claim 1 , wherein the second package comprises a semiconductor die.5. The semiconductor device of claim 1 , wherein the second conductive connector comprises solder.6. The semiconductor device of claim 5 , wherein the second package comprises a copper pillar is physical contact with the second conductive connector.7. A semiconductor device comprising:a post contact material located on a first set of a first plurality of package contacts on a first side of a first package;a second package with external connections bonded directly to a second set of the first plurality of package contacts, the second package comprising a first surface facing away from ...

SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS AND METHOD FOR FABRICATING THE SAME

The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene.

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Logic drive based on standardized commodity programmable logic semiconductor ic chips

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad. 1. A semiconductor device , comprising:a first semiconductor element having a first electrode;a second semiconductor element having a second electrode;a Sn-based micro-solder bump formed on the second electrode; anda concave bump pad formed on the first electrode opposite to the micro-solder bump,wherein the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.2. The semiconductor device according to claim 1 , further comprising a second metal layer and a third metal layer that are sequentially formed on the concave bump pad claim 1 , wherein the third metal layer is diffused to the micro-solder bump claim 1 , and wherein the second metal layer is made of a metal of the vanadium group.3. The semiconductor device according to claim 2 , wherein the first semiconductor element has a plurality of concave bump pads thereon claim 2 , the diameters of which are different from each other.4. The semiconductor device according to claim 3 , wherein the diameters of the concave bump pads differ depending on the use of the respective electrodes connected thereto.5. The semiconductor device according to claim 2 , wherein a diameter of the micro-solder bump corresponds to a diameter of the concave bump pad.6. The semiconductor device according to claim 2 , further comprising a first metal layer that is sequentially formed on the concave bump pad together with the second metal layer and the third metal layer claim 2 , wherein the third metal layer is ...

Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Semiconductor package with air gap

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices. 1. A method for bonding a first semiconductor device to a second semiconductor device , comprising:providing a first semiconductor device comprising a first metal pad, wherein the first metal pad has a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface;providing a second semiconductor device comprising a second metal pad, wherein the second metal pad has a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface;contacting the second metal pad to the first metal pad; andbonding the first semiconductor device to the second semiconductor device at a temperature of less than 250° C. to greater than 100° C. and at a pressure of less than 250 psi to greater than 50 psi.2. The method of claim 1 , wherein the first and second metal pad comprise copper claim 1 , aluminum claim 1 , tungsten claim 1 , nitrides thereof claim 1 , or combinations comprising at less one of the foregoing.3. The method of claim 1 , wherein bonding the first semiconductor device to the second semiconductor device at a temperature of less than 200° C. to greater than 100° C. and at a pressure of less than 200 psi to greater than 100 psi.4. The method of claim 1 , wherein bonding the first semiconductor device to the second semiconductor device at a temperature of less than 175° C. to greater than 125° C. and at a pressure of less than 150 ...

Semicondcutor packages

Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends.

CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer. 1. (canceled)2. A method comprising:forming one or more openings in a dielectric layer of a substrate, the one or more openings extending at least partially through the dielectric layer from a surface of the dielectric layer, a width of at least one of the one or more openings being at least 5 microns;forming a barrier layer over the surface of the dielectric layer and surfaces of the openings;forming a conductive structure disposed over the barrier layer and in the openings;polishing at least a portion of the conductive structure to reveal a surface of the barrier layer; andpolishing the barrier layer to reveal a planar dielectric bonding surface with a surface roughness of less than 1 nm root mean square (RMS), the conductive structure is recessed less than 25 nm from the dielectric bonding surface.3. A method according to claim 2 , wherein the substrate is a first substrate claim 2 , the method further comprising directly bonding the planar dielectric bonding surface of the first substrate to a prepared planar bonding surface of a second substrate.4. ...

PACKAGE SYSTEMS INCLUDING PASSIVE ELECTRICAL COMPONENTS

A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure. 1. A converter comprising:a plurality of active circuitry elements over a substrate;a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element of the plurality of active circuitry elements;a plurality of passive electrical components over the passivation structure, wherein each passive electrical component of the plurality of passive electrical components is selectively connectable with at least one other passive electrical component of the plurality of electrical components, and a first side of each passive electrical component of the plurality of electrical components is electrically coupled to an electrical pad of each of at least two active circuitry elements of the plurality of active circuitry elements; anda plurality of electrical connection structures, wherein a first ...

BONDING PAD STRUCTURE, SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SAME

A bonding pad structure includes a bonding pad layer, and an expansion stagnating block that is at least wrapped by the bonding pad layer partially. The expansion stagnating block is subjected to high-temperature tempering treatment. A semiconductor structure, a semiconductor package structure and a method for preparing the same are also provided. 1. A bonding pad structure , comprising a bonding pad layer , and an expansion stagnating block that is at least wrapped by the bonding pad layer partially , the expansion stagnating block being subjected to A high-temperature tempering treatment.2. The bonding pad structure of claim 1 , wherein an isolation layer is arranged between the bonding pad layer and the expansion stagnating block.3. The bonding pad structure of claim 1 , wherein the bonding pad layer comprises a bonding pad top layer and a bonding pad bottom layer that are arranged in a stacked manner claim 1 , the bonding pad top layer is arranged on a side of a bonding pad close to a bonding surface claim 1 , the bonding pad bottom layer and the bonding pad top layer are integrated as a whole claim 1 , and projection of the bonding pad bottom layer on the bonding surface is positioned in projection of the bonding pad top layer on the bonding surface.4. The bonding pad structure of claim 3 , wherein an area of an end of the bonding pad layer close to the bonding surface is greater than an area of an end of the bonding pad layer far away from the bonding surface.5. The bonding pad structure of claim 1 , wherein the bonding pad layer is a metal block.6. A semiconductor package structure comprising a semiconductor substrate provided with the bonding pad structure of .7. The semiconductor package structure of claim 6 , wherein the semiconductor substrate comprises a substrate layer far away from a bonding surface claim 6 , and a dielectric layer and a dielectric surface layer that are arranged on the substrate layer sequentially claim 6 , the bonding pad structure ...

Semiconductor device with slanted conductive layers and method for fabricating the same

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring. 1(a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode;(b) foaming a first insulating film having a first opening, for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode;(c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening;(d) forming a wiring which is electrically connected to the second pad electrode via the second opening;(e) forming a second insulating film on the first pad electrode and on the wiring;(f) forming a third opening in the second insulating film above the first pad electrode and ...

Multi-Stack Package-on-Package Structures

Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Semiconductor Die Contact Structure and Method

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact. 1. A method of manufacturing a semiconductor device , the method comprising:forming a conductive material within a first passivation layer over a semiconductor substrate, the first passivation layer having a height greater than 15,000 Å, the conductive material having a constant composition;depositing a second passivation layer on the first passivation layer, the second passivation layer covering the conductive material;patterning the second passivation layer to form a first opening extending to a top surface of the conductive material;forming a polyimide coating over the second passivation layer;patterning the polyimide coating to expose at least a portion of the conductive material; andforming an external contact in electrical contact with the conductive material, a portion of the external contact being interposed between sidewalls of the polyimide coating.2. The method of further comprising forming a conductive contact on the conductive material claim 1 , the conductive contact comprising a saddle profile in a cross section view.3. The method of further comprising forming an underbump metallization under the external contact claim 1 , the underbump metallization comprising a U shape in a cross section view.4. The method of further comprising forming the first passivation layer over the semiconductor substrate to a thickness in a range of 0.6 μm to 1.4 μm.5. The method of claim 4 , wherein forming the first passivation layer comprises a plasma enhanced chemical vapor deposition process.6. ...

MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield. 1. A semiconductor device manufacturing method , comprising:providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad;stacking the plurality of second dies on the first die, the second pads of the plurality of second dies and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped;forming a connecting hole passing through the second dies, the connecting hole exposing the first pad, and comprising a plurality of hole sections each located in one of the second dies, and each hole section exposing a portion of the second pad of the corresponding second die; andforming a conductive body filling the connecting hole and connecting the first pad and the second pads.2. The method of claim 1 , wherein the connecting hole is formed by a single perforation process.3. The method of claim 2 , wherein the forming a connecting hole passing through the second dies comprises:covering the second die farthest from the first die with a photoresist layer;exposing and developing the photoresist layer to form a developing area, ...

POST-PASSIVATION INTERCONNECT STRUCTURE

A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region. 1. A semiconductor device , comprising:a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;a passivation layer overlying the semiconductor substrate;an interconnect structure overlying and interfacing a top surface of the passivation layer,the interconnect structure comprising a landing pad conductive element and a plurality of dummy conductive elements, wherein the landing pad conductive element and the dummy conductive elements are electrically separated;a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad conductive element and a second opening exposing a portion of each of the plurality of dummy conductive elements;a metal layer comprising a first portion on a topmost surface of the protective layer and on the exposed portion of the landing pad conductive element and a plurality of second portions on the topmost surface of the protective layer and on the exposed portion of the dummy conductive element, the plurality of second portions of the metal layer being electrically separated from the semiconductor substrate and from the first portion of the metal layer; anda single bump on the first portion of the metal layer ...

Semiconductor device and a method of manufacturing the same

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE

Disclosed herein is a semiconductor device including: a first substrate provided with a first surface layer including a first electrode; an expanded second substrate provided with a second surface layer including a second electrode and directly bonded to the first substrate so that the second surface layer contacts with the first surface layer; and a through electrode running through the first or second substrate. The second surface layer is provided over an expanded second principal surface defined by a second substrate and a resin portion. The second substrate has a smaller planar size than the first substrate. The first and second electrodes are connected together and in contact with each other. 1. A semiconductor device comprisinga first substrate having a first principal surface on which circuit components are provided and over which a first surface layer, including a first electrode, is provided,an expanded second substrate including: a second substrate having a second principal surface on which circuit components are provided; a resin portion provided on a side surface of the second substrate; and a second surface layer which is provided over an expanded second principal surface defined by the second substrate and the resin portion surrounding the second substrate and which includes a second electrode, the expanded second substrate being directly bonded to the first substrate such that the second surface layer contacts with the first surface layer, anda through electrode which either is connected to the first electrode and runs through the first substrate or is connected to the second electrode and runs through the second substrate, whereinthe second substrate has a smaller planar size than the first substrate, andthe first and second electrodes are connected together and are in contact with each other.2. The semiconductor device of claim 1 , whereinthe second substrate includes a second substrate body and an interconnect layer provided between the second ...

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a redistribution layer over the semiconductor die; anddepositing an encapsulant over the semiconductor die and redistribution layer after forming the redistribution layer.2. The method of claim 1 , further including depositing the encapsulant over a side surface of the semiconductor die.3. The method of claim 1 , further including depositing the encapsulant over a back surface of the semiconductor die.4. The method of claim 1 , further including disposing a solder bump on the redistribution layer after depositing the encapsulant.5. The method of claim 1 , further including:disposing the semiconductor die on a carrier with the redistribution layer oriented toward the carrier; anddepositing the encapsulant over the semiconductor die and carrier.6. The method of claim 1 , further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH GRAPHENE LAYERS

The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene. 1. A method for fabricating a semiconductor device , comprising:providing a substrate;forming a first passivation layer above the substrate;forming a redistribution layer on the first passivation layer;forming a first adjustment layer on the redistribution layer;forming a pad layer on the first adjustment layer;forming a second adjustment layer between the pad layer and the first adjustment layer;forming a second passivation layer on the first passivation layer;wherein the first adjustment layer and the second adjustment layer are formed of graphene.2. The method for fabricating a semiconductor device of claim 1 , wherein forming the pad layer comprises: forming a lower portion on the first adjustment layer and forming an upper portion on the lower portion.3. The method for fabricating a semiconductor device of claim 2 , wherein the second adjustment layer is formed between the lower portion of the pad layer and the first adjustment layer claim 2 , on sidewalls of the lower portion of the pad layer claim 2 , and on bottom surfaces of the upper portion of the pad layer.4. The method for fabricating a semiconductor device of claim 3 , wherein the redistribution layer and the lower portion of the pad layer are formed in the second passivation layer claim 3 , and the upper portion of the pad layer is formed on the second passivation layer.5. The method for ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SLANTED CONDUCTIVE LAYERS

The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers. 1. A method for fabricating a semiconductor device , comprising:providing a substrate;forming a first insulating layer above the substrate;forming first slanted recesses along the first insulating layer; andforming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.2. The method for fabricating the semiconductor device of claim 1 , wherein the step of forming the first slanted recesses along the first insulating layer comprises:forming a first hard mask layer on the first insulating layer;forming first hard mask openings along the first hard mask layer;performing a first slanted etch process on the first insulating layer to form the first slanted recesses along the first insulating layer; andremoving the first hard mask layer;wherein the first slanted etch process uses the first hard mask layer as a pattern guide.3. The method for fabricating the semiconductor device of claim 2 , wherein an angle of incidence of the first slanted etch process is between about 5 degree and about 80 degree.4. The method for fabricating the semiconductor device of claim 3 , wherein the first hard mask layer is formed of a material having etch selectivity to the first insulating layer.5. The method for fabricating the semiconductor device of claim 3 , wherein the first hard mask layer is formed of silicon oxide claim 3 , silicon nitride claim 3 , silicon oxynitride claim 3 , silicon nitride oxide claim 3 , boron nitride claim 3 , silicon boron nitride ...

Electronic Device with Multi-Layer Contact and System

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow. 1. A semiconductor device comprising:a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface;an electrical contact layer disposed directly on the first electrode terminal, the electrical contact layer consisting essentially of Al;a functional layer directly disposed on the electrical contact layer, the functional layer consisting essentially of Ti or an alloy containing Ti;an adhesion layer directly disposed on the functional layer, the adhesion layer consisting essentially of Ni or NiV;a solder layer directly disposed on the adhesion layer, the solder layer consisting essentially of Sn; anda protection layer directly disposed on the solder layer,wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.2. The device according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm claim 1 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm claim 1 , wherein the adhesion layer has a thickness in a range from 200 nm to 2 μm claim 1 , ...

Stacked Semiconductor Structure and Method

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer;', 'a first connector embedded in the first dielectric layer, the first connector directly contacting the first connection pad; and', 'a first bonding pad embedded in the first dielectric layer, the first connector being interposed between first bonding pad and the first connection pad; and, 'a first chip comprising a semiconductor substrate', 'an interconnect structure interposed between the semiconductor substrate and the first chip;', 'an external connection pad directly on the interconnect structure, the interconnect structure being interposed between the external connection pad and the first chip;', 'a second dielectric layer interposed between the interconnect structure the first chip, the second dielectric layer being directly bonded to the first dielectric layer; and', 'a second bonding pad embedded in the second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad., 'a second chip bonded to the first chip, the second chip comprising2. The device of claim 1 , wherein a width of the first connector is less than a width of the first bonding pad and a width of the first connection pad.3. The device of claim 2 , wherein a width of the first bonding pad is less than a width of the second bonding pad.4. The device of claim 1 , ...