Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Verfahren zum Bearbeiten eines Halbleitersubstrats und Verfahren zum Bearbeiten eines Halbleiterwafers

TRANSIENT LIQUID PHASE MATERIAL BONDING AND SEALING STRUCTURES AND METHODS OF FORMING SAME

A method of forming a bonding element including a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value, and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Methods for providing a flexible structure and flexible apparatuses

WARPAGE CONTROL FOR FLEXIBLE SUBSTRATES

Power MOSFET having selectively silvered pads for clip and bond wire attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Solderless Die Attach to a Direct Bonded Aluminum Substrate

A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

HYBRID LOW METAL LOADING FLUX

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

Electronic devices with semiconductor die coupled to a thermally conductive substrate

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

NANOPARTICLE BACKSIDE DIE ADHESION LAYER

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

Method of manufacturing a silver bond pad on a semiconductor power device using silver nanopaste, as well as an assembly including said semiconductor device

A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Chip mit sinterbarem Oberflächenmaterial

Eine elektronische Komponente (100) weist einen elektronischen Chip (102) und ein sinterbares Verbindungsmaterial (104), das einem Trocknungsvorgang unterzogen wurde und das auf oder über zumindest einem Teil einer Hauptoberfläche (106) des elektronischen Chips (102) freiliegt, auf.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

플렉시블 기판에 대한 휨 제어

제 1 측 및 제 2 측을 구비한 플렉시블 기판이 제공될 수 있다. 하나 이상의 전기 접속부를 통하여 플렉시블 기판의 제 1 측에 디바이스가 전기적으로 연결될 수 있다. 휨(warpage) 제어 디바이스는 상기 플렉시블 기판의 제 2 측에 부착될 수 있다. 휨 제어 디바이스는 접착층 및 리지드(rigid)층을 포함할 수 있다. 휨 제어 디바이스는 플렉시블 기판의 제 1 측 상의 하나 이상의 전기 접속부에 대향할 수 있는 플렉시블 기판의 제 2 측의 영역 내에 형성될 수 있다. A flexible substrate having a first side and a second side can be provided. The device can be electrically connected to the first side of the flexible substrate through the one or more electrical connections. A warpage control device may be attached to the second side of the flexible substrate. The deflection control device may include an adhesive layer and a rigid layer. The flexural control device may be formed in a region of the second side of the flexible substrate that is capable of opposing one or more electrical contacts on the first side of the flexible substrate.

Power MOSFET having selectively silvered pads for clip and bond wire attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

TRANSIENT LIQUID PHASE MATERIAL BONDING AND SEALING STRUCTURES AND METHODS OF FORMING SAME

A bonding element includes a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

Method for processing a semiconductor substrate and a method for processing a semiconductor wafer

本发明涉及用于处理半导体衬底的方法和用于处理半导体晶片的方法。根据各种实施例，用于处理半导体衬底的方法可以包括：用金属覆盖半导体衬底的多个管芯区；由半导体衬底形成多个管芯，其中多个管芯中的每一个管芯覆盖有金属；以及随后，对覆盖多个管芯中的至少一个管芯的金属进行退火。

Semiconductor device and manufacturing method thereof

本發明提供了具有EMI屏蔽層及/或EMI屏蔽線的半導體裝置及其製造方法。在示例性實施例中，半導體裝置包括半導體晶粒、屏蔽半導體晶粒的EMI屏蔽層和囊封EMI屏蔽層的囊封部分。在另一個示例實施例中，半導體裝置還包括從EMI屏蔽層延伸且屏蔽半導體晶粒的EMI屏蔽線。

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

ELECTRONIC COMPONENT, ELECTRONIC COMPONENT DEVICE USING SAME, AND METHOD FOR MANUFACTURING SAME

Disclosed is an electronic component which has a connection part wherein an electrode at least whose surface is made of Al or an Al alloy and a sintered compact of metal nanoparticles are connected. Also disclosed are an electronic component device using such an electronic component and a method for manufacturing such an electronic component. Specifically disclosed is an electronic component comprising an electronic component base body and electrodes including a first electrode at least whose surface is made of Al or an Al alloy and a second electrode which is joined onto the first electrode and composed of a sintered compact of metal nanoparticles. This electronic component is characterized in that the junction interface between the first electrode and the second electrode has a multilayer structure wherein (a) a first layer mainly containing Al, (b) a second layer mainly containing an Al oxide, (c) a third layer mainly containing an alloy of Al and the constituent element of the metal ...

REDISTRIBUTION LAYER (RDL) STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Verfahren zur Herstellung einer bondbaren Metallisierung und korrespondierende bondbare Metallisierung

Die Erfindung betrifft ein Verfahren zur Herstellung einer bondbaren Metallisierung (1) auf einem Halbleitersubstrat (3) für einen Leistungshalbleiter, wobei die bondbare Metallisierung (1) eine erste Metallisierungslage (M1), welche auf das Halbleitersubstrat (3) aufgebracht ist, und eine zweite Metallisierungslage (M2) aufweist, welche auf die erste Metallisierungslage (M1) aufgebracht ist, und eine korrespondierende bondbare Metallisierung (1). Erfindungsgemäß wird zur Ausbildung der zweiten Metallisierungslage (M2) eine Paste oder Tinte mit Kupfernanopartikeln auf die erste Metallisierungslage (M1) aufgedruckt und mittels eines thermischen Prozesses zu einer Kupfermetallisierung (Cu) versintert.

Conductive connections, structures with such connections, and methods of manufacture

Electronic element that includes multilayered bonding interface between first electrode having aluminum-containing surface and second electrode composed of metal nanoparticle sintered body

An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles.

Redistribution layer (RDL) structure and method of manufacturing the same

Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Solderless die attach to a direct bonded aluminum substrate

A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

플렉시블 기판에 대한 휨 제어

... 제 1 측 및 제 2 측을 구비한 플렉시블 기판이 제공될 수 있다. 하나 이상의 전기 접속부를 통하여 플렉시블 기판의 제 1 측에 디바이스가 전기적으로 연결될 수 있다. 휨(warpage) 제어 디바이스는 상기 플렉시블 기판의 제 2 측에 부착될 수 있다. 휨 제어 디바이스는 접착층 및 리지드(rigid)층을 포함할 수 있다. 휨 제어 디바이스는 플렉시블 기판의 제 1 측 상의 하나 이상의 전기 접속부에 대향할 수 있는 플렉시블 기판의 제 2 측의 영역 내에 형성될 수 있다.

Verfahren zum Bearbeiten eines Halbleitersubstrats und Verfahren zum bearbeten eines Halbleiterwafers

Gemäß verschiedenen Ausführungsformen kann ein Verfahren (100) zum Bearbeiten eines Halbleitersubstrats Folgendes enthalten: Bedecken von mehreren Chipbereichen des Halbleitersubstrats mit einem Metall (110); Bilden von mehreren Chips aus dem Halbleitersubstrat, wobei jeder Chip aus den mehreren Chips mit dem Metall bedeckt ist (120); und nachfolgend Tempern des Metalls, das wenigstens einen Chip aus den mehreren Chips bedeckt (130).

Conductive connections, structures with such connections, and methods of manufacture

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

METHOD FOR PROCESSING A SEMICONDUCTOR SUBSTRATE AND A METHOD FOR PROCESSING A SEMICONDUCTOR WAFER

According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

반도체 패키징 및 이의 제조 방법

본 발명개시는 반도체 패키지를 제공하고, 이러한 반도체 패키지는 콘택 패드, 콘택 패드 외부의 디바이스 및 콘택 패드 상의 솔더 범프를 포함한다. 디바이스는 콘택 패드에 대응하는 전도성 콘택 패드를 갖는다. 솔더 범프는 전도성 콘택 패드와 콘택 패드를 접속한다. 솔더 범프는 솔더 범프의 상부로부터 콘택 패드까지의 높이; 및 높이에 수직인 방향에서 솔더 범프의 가장 넓은 치수인 폭을 포함한다. 콘택 패드에 근접한 솔더 범프의 접합 부분은 모래시계 모양을 포함한다.

Warpage Control for Flexible Substrates

Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

Conductive connections, structures with such connections, and methods of manufacture

本案中，藉由焊料卡固層(1210,2210)所圍繞之一種焊料連接，可凹陷進該層中的孔(1230)。該凹陷可藉由蒸發該焊接連接的可蒸發部分(1250)而獲得。另外，本案也提供其他特徵。

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Method of manufacturing a silver bond pad on a semiconductor power device using silver nanopaste, as well as an assembly including said semiconductor device

A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process

The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

ELECTRONIC COMPONENT, ELECTRONIC COMPONENT DEVICE USING SAME, AND METHOD FOR MANUFACTURING SAME

There are provided an electronic element having a connection portion at which an electrode having a surface composed of at least Al or an alloy and a metal nanoparticle sintered body is connected to each other, an electronic element device using the same, and a manufacturing method thereof. In an electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode, a bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the ...

Warpage control for flexible substrates

Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

Transient liquid phase material bonding and sealing structures and methods of forming same

A bonding element includes a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

HYBRID LOW METAL LOADING FLUX

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed. 117.-. (canceled)18. A method for coupling solder balls to a substrate , comprising:providing a substrate including a plurality of bonding pads;positioning a flux formulation on the bonding pads, the flux formulation comprising a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 weight percent of the flux formulation;positioning solder balls on the flux formulation; andapplying heat and bonding the solder balls to the bonding pads.19. The method of claim 18 , wherein the flux component comprises an acid and a solvent.20. The method of claim 19 , wherein the metal particle component includes solder particles and pure metal particles.21. The method of claim 20 , wherein the pure metal particles are selected from the group consisting of noble metals and rare earth metals.22. The method of claim 20 , wherein a plurality of the pure metal particles have a particle size in the range of 1 to 100 nm.23. The method of claim 19 , wherein the metal particle component comprises solder particles having a particle size in the range of up to 15 μm.24. The method of claim 18 , wherein the metal particle component comprises solder particles.25. The method of claim 24 , wherein the solder particles comprise at least one metal and the solder particles have a melting point of less than 250° C.26. The method of claim 19 , wherein the metal particle component comprises solder particles having a melting point less than the solder balls.27. An apparatus comprising:a bonding pad;a flux ...

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

Warpage Control for Flexible Substrates

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an EMI shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the EMI shield layer. In another example embodiment, the semiconductor device further includes EMI shielding wires extending from the EMI shield layer and shielding the semiconductor die.

Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Semiconductor package and manufacturing method thereof

Methods for providing a flexible structure and flexible apparatuses

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

Electronic element, electronic element device using the same, and manufacturing method thereof

There are provided an electronic element having a connection portion at which an electrode having a surface composed of at least Al or an alloy and a metal nanoparticle sintered body is connected to each other, an electronic element device using the same, and a manufacturing method thereof. In an electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode, a bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the ...

Method for processing a semiconductor substrate and a method for processing a semiconductor wafer

According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Silver-To-Silver Bonded IC Package Having Two Ceramic Substrates Exposed On The Outside Of The Package

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

ELECTRONIC DEVICES WITH ATTACHED DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Conductive connections, structures with such connections, and methods of manufacture

A solder connection may be surrounded by a solder locking layer ( 1210, 2210 ) and may be recessed in a hole ( 1230 ) in that layer. The recess may be obtained by evaporating a vaporizable portion ( 1250 ) of the solder connection. Other features are also provided.

Nanoparticle backside die adhesion layer

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

Solderable contact regions

A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.

Hybrid low metal loading flux

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

Solderable contact regions

A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer ( 1210, 2210 ) and may be recessed in a hole ( 1230 ) in that layer. The recess may be obtained by evaporating a vaporizable portion ( 1250 ) of the solder connection. Other features are also provided.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Solderless die attach to a direct bonded aluminum substrate

A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

SILVER-TO-SILVER BONDED IC PACKAGE HAVING TWO CERAMIC SUBSTRATES EXPOSED ON THE OUTSIDE OF THE PACKAGE

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Solar cell via thin film solder bond

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

SOLAR CELL VIA THIN FILM SOLDER BOND

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor die with an aluminium pad coated by a sintered silver structure for a clip and with an uncoated aluminium pad for a bond wire and corresponding manufacturing method

A method of manufacturing a semiconductor die comprises the steps of: forming (101) (e.g., microjetting) a plurality of separate amounts of silver nanoparticle paste on a top-side of a wafer (25) such that there is an amount of silver nanoparticle paste (29) on a first aluminum pad (28) and such that there is no silver nanoparticle paste on a second aluminum pad (27); sintering (102) the amount of silver nanoparticle paste (29) so that the amount of silver nanoparticle paste (29) becomes a sintered silver structure (31) on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver structure; and dicing (103) the wafer (25) into a plurality of dice (26), wherein one of the dice (26) is a die (26) that includes the first aluminum pad (28) that is covered with the sintered silver structure (31) and the second aluminum pad (27) that is not covered by any sintered silver structure. The step of forming (101) may include directing a stream of abrasive particles at the first aluminum pad (28) thereby removing a layer of native aluminum oxide (30) from the first aluminum pad (28). The silver nanoparticle paste (29) may include flux particles (31) that assist in penetrating the native aluminum oxide (30) on the first aluminum pad (28). The semiconductor die (26) may be a power field effect transistor die, the first aluminum pad (28) may be a source pad and the second aluminum pad (27) may be a gate pad. A clip (37, 45) may be attached, e.g. via soft solder (43), to the sintered silver structure (31) on the first aluminum pad (28) and a bond wire (39) may be attached, e.g. ultrasonically welded, to the second aluminum pad (27). The semiconductor die (26) may have a layer of silver disposed on a backside, direct silver-to-silver bonded to a sintered silver structure (36) on a plate (35) of aluminum of a direct bonded aluminum (DBA) substrate (33). A packaged power field effect transistor device (32) may include the power field ...

Semiconductor die with an aluminium pad coated by a sintered silver structure for a clip and with an uncoated aluminium pad for a bond wire and corresponding manufacturing method

A method of manufacturing a semiconductor die comprises the steps of: forming (101) (e.g., microjetting) a plurality of separate amounts of silver nanoparticle paste on a top-side of a wafer (25) such that there is an amount of silver nanoparticle paste (29) on a first aluminum pad (28) and such that there is no silver nanoparticle paste on a second aluminum pad (27); sintering (102) the amount of silver nanoparticle paste (29) so that the amount of silver nanoparticle paste (29) becomes a sintered silver structure (31) on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver structure; and dicing (103) the wafer (25) into a plurality of dice (26), wherein one of the dice (26) is a die (26) that includes the first aluminum pad (28) that is covered with the sintered silver structure (31) and the second aluminum pad (27) that is not covered by any sintered silver structure. The step of forming (101) may include directing a stream of abrasive particles at the first aluminum pad (28) thereby removing a layer of native aluminum oxide (30) from the first aluminum pad (28). The silver nanoparticle paste (29) may include flux particles (31) that assist in penetrating the native aluminum oxide (30) on the first aluminum pad (28). The semiconductor die (26) may be a power field effect transistor die, the first aluminum pad (28) may be a source pad and the second aluminum pad (27) may be a gate pad. A clip (37, 45) may be attached, e.g. via soft solder (43), to the sintered silver structure (31) on the first aluminum pad (28) and a bond wire (39) may be attached, e.g. ultrasonically welded, to the second aluminum pad (27). The semiconductor die (26) may have a layer of silver disposed on a backside, direct silver-to-silver bonded to a sintered silver structure (36) on a plate (35) of aluminum of a direct bonded aluminum (DBA) substrate (33). A packaged power field effect transistor device (32) may include the power field ...

Semiconductor device and manufacturing method thereof

EMI 차폐층 및/또는 EMI 차폐 와이어를 갖는 반도체 장치 및 그 제조 방법이 제공된다. 예시적인 실시예에서, 반도체 장치는 반도체 다이, 반도체 다이를 차폐하는 EMI 차폐층 및 EMI 차폐층을 인캡슐레이팅하는 인캡슐레이팅 부분을 포함한다. 다른 예시적인 실시예에서, 반도체 장치는 EMI 차폐층으로부터 연장되어 반도체 다이를 차폐하는 EMI 차폐 와이어를 더 포함한다.

Semiconductor device

本发明提供一种半导体装置，其包括：半导体晶粒，包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；EMI屏蔽层，其包括屏蔽所述半导体晶粒的所述第一表面的第一导电层和屏蔽所述半导体晶粒的所述第三表面的第二导电层；基板，其电连接到所述半导体晶粒的所述多个互连结构；以及囊封部分，其囊封所述EMI屏蔽层和所述基板。

Solar cell via thin film solder bond

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

Solder Ball Application for Singular Die

A method is provided. The method includes one or more of conditioning one or more die pads of a singular die, applying a nickel layer to the one or more die pads, applying a gold layer over the nickel layer, applying a solder paste over the gold layer, applying one or more solder balls to the solder paste, and mating the one or more solder balls to one or more bond pads of another die, a printed circuit board, or a substrate.

Nanoparticle backside die adhesion layer

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

반도체 장치 및 그 제조 방법

EMI 차폐층 및/또는 EMI 차폐 와이어를 갖는 반도체 장치 및 그 제조 방법이 제공된다. 예시적인 실시예에서, 반도체 장치는 반도체 다이, 반도체 다이를 차폐하는 EMI 차폐층 및 EMI 차폐층을 인캡슐레이팅하는 인캡슐레이팅 부분을 포함한다. 다른 예시적인 실시예에서, 반도체 장치는 EMI 차폐층으로부터 연장되어 반도체 다이를 차폐하는 EMI 차폐 와이어를 더 포함한다.

플렉시블 기판에 대한 휨 제어

제 1 측 및 제 2 측을 구비한 플렉시블 기판이 제공될 수 있다. 하나 이상의 전기 접속부를 통하여 플렉시블 기판의 제 1 측에 디바이스가 전기적으로 연결될 수 있다. 휨(warpage) 제어 디바이스는 상기 플렉시블 기판의 제 2 측에 부착될 수 있다. 휨 제어 디바이스는 접착층 및 리지드(rigid)층을 포함할 수 있다. 휨 제어 디바이스는 플렉시블 기판의 제 1 측 상의 하나 이상의 전기 접속부에 대향할 수 있는 플렉시블 기판의 제 2 측의 영역 내에 형성될 수 있다.

플렉시블 기판에 대한 휨 제어

제 1 측 및 제 2 측을 구비한 플렉시블 기판이 제공될 수 있다. 하나 이상의 전기 접속부를 통하여 플렉시블 기판의 제 1 측에 디바이스가 전기적으로 연결될 수 있다. 휨(warpage) 제어 디바이스는 상기 플렉시블 기판의 제 2 측에 부착될 수 있다. 휨 제어 디바이스는 접착층 및 리지드(rigid)층을 포함할 수 있다. 휨 제어 디바이스는 플렉시블 기판의 제 1 측 상의 하나 이상의 전기 접속부에 대향할 수 있는 플렉시블 기판의 제 2 측의 영역 내에 형성될 수 있다.

Hybrid low metal loading flux

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

Solder Ball Application for Singular Die

A device is provided. The device includes one or more of a singular die, one of another die, a printed circuit board, and a substrate, and one or more solder balls. The singular die includes one or more reconditioned die pads, which include die pads of the singular die with a plurality of metallic layers applied. The other die, printed circuit board, and the substrate include one or more bond pads. The one or more solder balls are between the one or more reconditioned die pads and the one or more bond pads.

Solder ball application for singular die

A device is provided. The device includes one or more of a singular die, one of another die, a printed circuit board, and a substrate, and one or more solder balls. The singular die includes one or more reconditioned die pads, which include die pads of the singular die with a plurality of metallic layers applied. The other die, printed circuit board, and the substrate include one or more bond pads. The one or more solder balls are between the one or more reconditioned die pads and the one or more bond pads.

반도체 패키징 및 이의 제조 방법

본 발명개시는 반도체 패키지를 제공하고, 이러한 반도체 패키지는 콘택 패드, 콘택 패드 외부의 디바이스 및 콘택 패드 상의 솔더 범프를 포함한다. 디바이스는 콘택 패드에 대응하는 전도성 콘택 패드를 갖는다. 솔더 범프는 전도성 콘택 패드와 콘택 패드를 접속한다. 솔더 범프는 솔더 범프의 상부로부터 콘택 패드까지의 높이; 및 높이에 수직인 방향에서 솔더 범프의 가장 넓은 치수인 폭을 포함한다. 콘택 패드에 근접한 솔더 범프의 접합 부분은 모래시계 모양을 포함한다.

Nanoparticle backside die adhesion layer

In described examples, a microelectronic device includes a microelectronic die (102) with a die attach surface (104). The microelectronic device further includes a nanoparticle layer (112) coupled to the die attach surface (104). The nanoparticle layer (112) may be in direct contact with the die attach surface (104), or may be coupled to the die attach surface (104) through an intermediate layer (110), such as an adhesion layer or a contact metal layer. The nanoparticle layer (112) includes nanoparticles (114) having adjacent nanoparticles (114) adhered to each other. The microelectronic die is attached to a package substrate (116) by a die attach material (124). The die attach material (124) extends into the nanoparticle layer (112) and contacts at least a portion of the nanoparticles (114).

플렉시블 기판에 대한 휨 제어

제 1 측 및 제 2 측을 구비한 플렉시블 기판이 제공될 수 있다. 하나 이상의 전기 접속부를 통하여 플렉시블 기판의 제 1 측에 디바이스가 전기적으로 연결될 수 있다. 휨(warpage) 제어 디바이스는 상기 플렉시블 기판의 제 2 측에 부착될 수 있다. 휨 제어 디바이스는 접착층 및 리지드(rigid)층을 포함할 수 있다. 휨 제어 디바이스는 플렉시블 기판의 제 1 측 상의 하나 이상의 전기 접속부에 대향할 수 있는 플렉시블 기판의 제 2 측의 영역 내에 형성될 수 있다.

Method of manufacturing circuit structure

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.