Herstellungsverfahren für ein Leistungshalbleiterbauelement mit Metallkontaktschicht

Verfahren zur Herstellung eines Leistungshalbleiterbauelements (10) mit einem Grundkörper und mit mindestens einer Kontaktfläche (20, 22, 24), wobei auf dieser Kontaktfläche (20, 22, 24) mindestens eine erste dünne metallische Schicht eines ersten Werkstoffs (30, 32, 34) angeordnet ist und eine weitere im Vergleich zur ersten dickeren metallische Schicht eines zweiten Werkstoffs (40, 42, 44) angeordnet ist mit den wesentlichen Schritten: Herstellung einer Mehrzahl von Leistungshalbleiterbauelementen (10) im Waferverbund; Aufbringen der ersten dünnen metallischen Schicht (30, 32, 34) auf der Kontaktfläche (20, 22, 24) der jeweiligen Leistungshalbleiterbauelemente (10); Anordnung der pastösen Schicht (40, 42, 44), aus dem zweiten Werkstoff und einem Lösungsmittel, mittels eines Schablonendruckverfahrens auf der ersten metallischen Schicht je Leistungshalbleiterbauelement (10); Bedecken der Oberfläche der pastösen Schicht (40, 42, 44) oder des gesamten Waferverbunds mit einer Folie (50); Nachfolgende ...

Power semiconductor device with metal contact layer and corresponding production method

Die Erfindung beschreibt ein Leistungshalbleiterbauelement (10) mit einem Grundkörper und mit mindestens einer Kontaktfläche (20,22,24), wobei auf dieser Kontaktfläche mindestens eine erste dünne metallische Schicht eines ersten Werkstoffs (30,32,34) angeordnet ist. Erfindungsgemäß ist eine weitere im Vergleich zur ersten dickeren metallische Schicht eines zweiten Werkstoffs (40,42,44) mittels einer Drucksinterverbindung dieses Werkstoffs hierauf angeordnet ist. Das zugehörige Verfahren weist die wesentlichen Schritte auf: Herstellung einer Mehrzahl von Leistungshalbleiterbauelementen im Waferverbund; Aufbringen mindestens einer ersten dünnen metallischen Schicht auf mindestens einer Kontaktfläche der jeweiligen Leistungshalbleiterbauelemente; Anordnung einer pastösen Schicht, aus dem zweiten Werkstoff und einem Lösungsmittel, auf mindestens einer der ersten metallischen Schichten je Leistungshalbleiterbauelement; Druckbeaufschlagung auf die pastöse Schicht; Vereinzeln der Halbleiterbauelemente ...

Package and method

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Package and method of conducting heat in package

PROCEEDED Of ASSEMBLY Of an ELEMENT CHIP HAS MICRO-ELECTRONIC ON a TELEGRAPHIC ELEMENT, INSTALLATION MAKING IT POSSIBLE TO CARRY out the ASSEMBLY

Le procédé d'assemblage comprend le étapes suivantes : prévoir un système de défilement de l'élément filaire (6) entre un dispositif d'alimentation (16) en élément filaire vers un dispositif de stockage (18) dudit élément filaire ; tendre l'élément filaire entre le dispositif d'alimentation (16) et le dispositif de stockage (18) par un dispositif de mise sous tension (16, 18) ; prévoir (E1) un réservoir (7) d'éléments à puce (1) individualisés et désolidarisés, chaque élément à puce (1) comprenant une borne de connexion (3), la borne de connexion (3) de chaque élément à puce (1) comprenant un sommet libre d'accès en regard duquel aucune partie de l'élément à puce (1) n'est présente ; amener (E2) un élément à puce (1) à partir du réservoir (7) dans une zone d'assemblage (Z1) située entre les dispositifs d'alimentation (16) et de stockage (18) de sorte que l'élément filaire (6) soit tendu dans ladite zone d'assemblage (Z1) ; fixer (E3), dans la zone d'assemblage (Z1), l'élément filaire (6 ...

Method for assembling a microelectronic chip element on a wire element, and installation enabling assembly to be performed

Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.

METHOD FOR ASSEMBLING AN ELEMENT HAVING A MICROELECTRONIC CHIP ONTO A WIRE ELEMENT, AND EQUIPMENT FOR CARRYING OUT THE ASSEMBLY

METHOD OF ASSEMBLING A MICROELECTRONIC ELEMENT CHIP ON A WIRE ELEMENT, A PLANT FOR CARRYING OUT THE ASSEMBLY

METHOD FOR ASSEMBLING AN ELEMENT HAVING A MICROELECTRONIC CHIP ONTO A WIRE ELEMENT, AND EQUIPMENT FOR CARRYING OUT THE ASSEMBLY

The invention relates to an assembly method, including the following steps: providing a system for moving the wire element (6) from a wire-element supply system (16) to a device (18) for storing said wire element; tensioning the wire element between the supply device (16) and the storage device (18) using a tensioning device (16, 18); providing (E1) a supply (7) of customized and separated chip elements (1), each chip element (1) including a connection terminal (3), the connection terminal (3) of each chip element (1) including a free top access portion, opposite which no portion of the chip element (1) is arranged; moving (E2) a chip element (1) from the supply (7) into an assembly area (Z1) located between the supply (16) and storage (18) devices such that the wire element (6) is tensioned in said assembly area (Z1); attaching (E3), in the assembly area (Z1), the electrically conductive wire element (6) to the connection terminal (3) of the chip element (1); and supplying electrically ...

Wärmeableitung durch Dichtungsringe in 3DIC-Struktur

Eine Packung enthält einen Chip, der ein Halbleitersubstrat, eine Vielzahl von Durchkontaktierungen, die durch das Halbleitersubstrat dringen, einen Dichtungsring, der die Vielzahl von Durchkontaktierungen überlappt und mit diesem verbunden ist, und eine Vielzahl elektrischer Verbindungen, die unter dem Halbleitersubstrat liegen und mit dem Dichtungsring verbunden sind, auf. Eine Zwischenschaltung liegt unter dem Chip und ist mit diesem verbunden. Die Zwischenschaltung enthält und ein Substrat und eine Vielzahl von Metallleitungen über dem Substrat. Die Vielzahl von Metallleitungen ist mit der Vielzahl elektrischer Verbindungen elektrisch verbunden. Jede der Vielzahl von Metallleitungen weist einen ersten Abschnitt auf, der von dem ersten Chip überlappt wird, und einen zweiten Abschnitt, der gegenüber dem Chip versetzt ist. Ein wärmeleitender Block umschließt den Chip und ist an der Vielzahl von Metallleitungen der Zwischenschaltung angebracht.

Wärmeableitung durch Dichtungsringe in 3DIC-Strukturen

Eine Packung, umfassend: einen ersten Chip, umfassend: ein erstes Halbleitersubstrat; eine erste Vielzahl von Durchkontaktierungen, die durch das erste Halbleitersubstrat dringen; einen ersten Dichtungsring, der eine erste Vielzahl von Durchkontaktierungen überlappt und mit diesen verbunden ist; und eine erste Vielzahl elektrischer Verbindungen, die unter dem Halbleitersubstrat liegt und mit dem ersten Dichtungsring verbunden ist; eine Zwischenschaltung, die unter dem ersten Chip liegt und mit diesem verbunden ist, wobei die Zwischenschaltung umfasst: ein Substrat; und eine Vielzahl von Metallleitungen über dem Substrat, wobei die Vielzahl von Metallleitungen mit der ersten Vielzahl elektrischer Verbindungen gekoppelt ist, und wobei jede der Vielzahl von Metallleitungen einen ersten Abschnitt umfasst, der von dem ersten Chip überlappt wird, und einen zweiten Abschnitt, der gegenüber dem ersten Chip versetzt ist; und einen wärmeleitenden Block, der den ersten Chip umschließt, wobei der wärmeleitende ...

POWER SEMICONDUCTOR ELEMENT HAVING METAL CONTACT LAYER, AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a power semiconductor element having a metal contact layer, and to provide a manufacturing method thereof. SOLUTION: The power semiconductor element has a substrate and at least one contact surface, on which at least one first thin metal layer of a first material is arranged. Another metal layer of a second material, thicker than the first layer, is arranged on the first layer by pressure sintering connection of the materials. A related process includes the following essential steps of: manufacturing a plurality of power semiconductor elements in a wafer assembly; providing at least one first thin metal layer on at least one contact surface of each power semiconductor element; arranging a paste layer formed by the second material and a solvent on at least one of the first metal layers for each power semiconductor element; applying pressure to the paste layer; and separating each of the semiconductor elements. COPYRIGHT: (C)2009,JPO&INPIT ...

Thermal dissipation through seal rings in 3DIC structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Leistungshalbleiterbauelement mit Metallkontaktschicht sowie Herstellungsverfahren hierzu

Die Erfindung beschreibt ein Leistungshalbleiterbauelement mit einem Grundkörper und mit mindestens einer Kontaktfläche, wobei auf dieser Kontaktfläche mindestens eine erste dünne metallische Schicht eines ersten Werkstoffs angeordnet ist. Erfindungsgemäß ist eine weitere, im Vergleich zur ersten dickeren, metallische Schicht eines zweiten Werkstoffs mittels einer Drucksinterverbindung dieses Werkstoffs hierauf angeordnet. Das zugehörige Verfahren weist die wesentlichen Schritte auf: Herstellung einer Mehrzahl von Leistungshalbleiterbauelementen im Waferverbund; Aufbringen mindestens einer ersten dünnen metallischen Schicht auf mindestens einer Kontaktfläche der jeweiligen Leistungshalbleiterbauelemente; Anordnung einer pastösen Schicht aus dem zweiten Werkstoff und einem Lösungsmittel auf mindestens einer der ersten metallischen Schichten je Leistungshalbleiterbauelement; Druckbeaufschlagung auf die pastöse Schicht; Vereinzeln der Halbleiterbauelemente.

Power semiconductor device with metal contact layer and corresponding production method

The invention relates to a power semiconductor element comprising a base body and at least one contact surface having at least one thin first metal layer of a first material arranged thereon. Another metal thicker of a second material according to the invention, compared to a first metal layer is connected via sintering thereon by means of the pressure of the material. The provided method includes the steps of fabricating a plurality of power semiconductor elements in a wafer matrix; coating the at least one thin first metal layer on at least one contact surface of each power semiconductor element; arranging the second material and a solvent-made mushy layer on the at least one first metal layer of each power semiconductor element; loading pressure on the mushy layer; separating each semiconductor element.

Power semiconductor device with metal contact layer and corresponding production method

Die Erfindung beschreibt ein Leistungshalbleiterbauelement (10) mit einem Grundkörper und mit mindestens einer Kontaktfläche (20,22,24), wobei auf dieser Kontaktfläche mindestens eine erste dünne metallische Schicht eines ersten Werkstoffs (30,32,34) angeordnet ist. Erfindungsgemäß ist eine weitere im Vergleich zur ersten dickeren metallische Schicht eines zweiten Werkstoffs (40,42,44) mittels einer Drucksinterverbindung dieses Werkstoffs hierauf angeordnet ist. Das zugehörige Verfahren weist die wesentlichen Schritte auf: Herstellung einer Mehrzahl von Leistungshalbleiterbauelementen im Waferverbund; Aufbringen mindestens einer ersten dünnen metallischen Schicht auf mindestens einer Kontaktfläche der jeweiligen Leistungshalbleiterbauelemente; Anordnung einer pastösen Schicht, aus dem zweiten Werkstoff und einem Lösungsmittel, auf mindestens einer der ersten metallischen Schichten je Leistungshalbleiterbauelement; Druckbeaufschlagung auf die pastöse Schicht; Vereinzeln der Halbleiterbauelemente ...

Power semiconductor component with metal contact layer and production method therefor

A power semiconductor component having a basic body and at least one contact area. At least one first thin metallic layer of a first material is arranged on the contact area. A second metallic layerthicker than the firstof a second material is arranged on the first material by a pressure sintering connection of said material. The associated method has the following steps: producing a plurality of power semiconductor components in a wafer; applying at least one first thin metallic layer on at least one contact area of a respective power semiconductor component; arranging a pasty layer, composed of the second material and a solvent, on at least one of the first metallic layers for each power semiconductor component; pressurizing the pasty layer; and singulating the semiconductor components.

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

METHOD FOR ASSEMBLING A MICROELECTRONIC CHIP ELEMENT ON A WIRE ELEMENT, AND INSTALLATION ENABLING ASSEMBLY TO BE PERFORMED

Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.

Thermal dissipation through seal rings in 3DIC structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Thermal dissipation through seal rings in 3DIC structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Power semiconductor device with metal contact layer and corresponding production method

The invention relates to a power semiconductor element comprising a base body and at least one contact surface having at least one thin first metal layer of a first material arranged thereon. Another metal thicker of a second material according to the invention, compared to a first metal layer is connected via sintering thereon by means of the pressure of the material. The provided method includes the steps of fabricating a plurality of power semiconductor elements in a wafer matrix; coating the at least one thin first metal layer on at least one contact surface of each power semiconductor element; arranging the second material and a solvent-made mushy layer on the at least one first metal layer of each power semiconductor element; loading pressure on the mushy layer; separating each semiconductor element.

Method for assembling element having microelectronic chip onto wire element, and equipment for carrying out the assembly

The invention relates to an assembly method, including the following steps: providing a system for moving the wire element (6) from a wire-element supply system (16) to a device (18) for storing said wire element; tensioning the wire element between the supply device (16) and the storage device (18) using a tensioning device (16, 18); providing (E1) a supply (7) of customized and separated chip elements (1), each chip element (1) including a connection terminal (3), the connection terminal (3) of each chip element (1) including a free top access portion, opposite which no portion of the chip element (1) is arranged; moving (E2) a chip element (1) from the supply (7) into an assembly area (Z1) located between the supply (16) and storage (18) devices such that the wire element (6) is tensioned in said assembly area (Z1); attaching (E3), in the assembly area (Z1), the electrically conductive wire element (6) to the connection terminal (3) of the chip element (1); and supplying electrically ...

In the wiring element on the method of assembling a microelectronic chip element and so that the assembly can carry on mounting apparatus

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Chip stacked structure

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Heat conduction for chip stacks and 3-d circuits

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Semiconductor device

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Microelectronic devices having conductive through via electrodes insulated by gap regions

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Power Semiconductor Module with Embedded Chip Package

A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

Distributed semiconductor device methods, apparatus, and systems

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Back-side contact formation

In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Integrated circuit packaging system with encapsulation and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Power Module with Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

Group III-V and Group IV Composite Diode

In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.

Semiconductor package

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Backside integration of rf filters for rf front end modules and design structure

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Reducing stress in multi-die integrated circuit structures

An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Semiconductor Packages and Methods of Forming The Same

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Semiconductor device fabrication method

A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Reliable Area Joints for Power Semiconductors

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Voltage switchable dielectric for die-level electrostatic discharge (esd) protection

A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Chip package and method for forming the same

An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Semiconductor apparatus comprised of two types of transistors

A semiconductor apparatus that includes two types of transistors is disclosed. The first semiconductor chip includes the first semiconductor device of a type of GaAs-HEMT, while, the second semiconductor chip includes the second semiconductor device of another type of GaN-HEMT. The second semiconductor device is formed in a SiC substrate, and the first semiconductor chip is mounted in an inactive region of the SiC substrate.

Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board

An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Method of fabricating wafer level package

A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.

Emi shielding semiconductor element and semiconductor stack structure

A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Power device and power device module

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Charge sharing testing of through-body-vias

In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Semiconductor Device Having a Clip Contact

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Through silicon via and method of fabricating same

A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Thermally Enhanced Package-on-Package (PoP)

A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Stacked Semiconductor Device Assembly in Computer System

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device. 1. A stacked semiconductor device assembly , comprising: a master interface;', 'a channel master circuit coupled to the master interface;', 'a slave interface;', 'a channel slave circuit coupled to the slave interface;', 'a memory core coupled to the channel slave circuit; and', 'selection circuitry configured to determine whether the IC chip is to communicate data using the channel master circuit or the channel slave circuit., 'a plurality of stacked integrated circuit (IC) chips, each IC chip further comprising2. The stacked semiconductor device assembly of claim 1 , wherein for one of the plurality of stacked IC chips claim 1 , the selection circuitry receives an input claim 1 , and is configured to determine whether the one of the plurality of stacked IC chips is to communicate data using the channel master or slave circuit based on a voltage level of the input.3. The stacked semiconductor device assembly of claim 2 , wherein the one of the plurality of IC chips is physically offset from other IC chips in the stacked semiconductor device assembly.4. The stacked semiconductor device assembly of claim ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

METHODS FOR FORMING SHIELDED RADIO-FREQUENCY MODULES HAVING REDUCED AREA

Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond. 1. A method for fabricating a radio-frequency module , the method comprising:forming or providing a packaging substrate configured to receive a plurality of components;mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices; andforming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.2. The method of further comprising forming each of the shielding wirebonds to have a loop shape ...

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Power semiconductor device and method for manufacturing power semiconductor device

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

Semiconductor chip and stacked type semiconductor package having the same

The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.

TSV Check Circuit With Replica Path

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Electronic component device

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Power device package structure

A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad. 1. A semiconductor chip , comprising:a semiconductor substrate comprising a first surface that is an active surface and a second surface that is opposite to the first surface;a through electrode penetrating the semiconductor substrate and disposed in at least one column in a first direction in a center portion of the semiconductor substrate;an inter-mediation pad disposed in at least one column in the first direction in an edge portion of the second surface;an upper pad disposed on the second surface and connected to the through electrode; anda rewiring line disposed on the second surface and connecting the inter-mediation pad to the upper pad.2. The semiconductor chip of claim 1 ,wherein a number of the at least one column of the inter-mediation pad is equal to a number of additional semiconductor chips disposed on the semiconductor substrate,wherein a region in which the inter-mediation pad is disposed is divided into a first region and a second region in the first direction,a region in which the upper pad is disposed is divided into a third region corresponding to the first region and a fourth region corresponding to the second region in the first direction,wherein the inter-mediation pad in the first region ...

MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures. 1. A semiconductor package , comprising:a substrate;a main stacked dies (MSD) structure comprising a substantially horizontal arrangement of semiconductor dies interconnected to the substrate; anda vertical side chip electrically coupled to a side of the MSD structure, wherein the vertical side chip comprises one or more through silicon vias (TSVs).2. The semiconductor package of claim 1 , wherein the vertical side chip is electrically coupled to the side of the MSD structure through one or more interconnections of the vertical side chip.3. The semiconductor package of claim 2 , wherein the one or more interconnections of the vertical side chip are disposed on an active side of the vertical side chip.4. The semiconductor package of claim 2 , wherein an interconnection of the one or more interconnections of the vertical side chip is coupled to the MSD structure through a die side pad (DSP) of the MSD structure.5. The semiconductor package of claim 2 , wherein an interconnection of the one or more interconnections of the vertical side chip is coupled to the MSD structure through an end of metal routing of a die in the MSD structure.6. The semiconductor package of claim 1 , wherein the vertical side chip is interconnected to the substrate.7. The semiconductor package of claim 6 , wherein the vertical side chip is interconnected to the substrate through a die side pad (DSP) of the vertical side chip.8. The ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region. 111.-. (canceled)12. A semiconductor device comprising:a semiconductor layer including a wide bandgap semiconductor, said semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of said element region when viewed two-dimensionally;a step portion formed in said outer peripheral region and surrounding said outer periphery of said element region; anda metal layer formed along said step portion,said step portion having a sidewall recessed downward from a main surface of said element region in a cross section parallel to a thickness direction of said semiconductor layer, said metal layer extending to cover at least a portion of said sidewall.13. The semiconductor device according to claim 12 , further comprising a first insulating film formed on said semiconductor layer claim 12 , whereinsaid metal layer covers an end face of said first insulating film.14. The semiconductor device according to claim 12 , whereinan inner peripheral surface including said sidewall is continuous with an outer peripheral end face of said ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF DIES OPERATING AS A PLURALITY OF CHANNELS

A semiconductor apparatus includes a substrate, a first die, and a second die. The substrate includes first and second byte pads of a first channel and first and second byte pad of a second channel. First byte pads of the first die are respectively coupled to the first byte pads of the first channel, and second byte pads of the first die are respectively coupled to the second byte pads of the first channel. The second die, as disposed, is rotated by 180° with respect to the first die. First byte pads of the second die are respectively coupled to the second byte pads of the second channel, and second byte pads of the second die are respectively coupled to the first byte pads of the second channel. 1. A semiconductor apparatus comprising:a substrate comprising first byte pads of a first channel, first byte pads of a second channel, second byte pads of the first channel, and second byte pads of the second channel, wherein the first byte pads of the first channel and the first byte pads of the second channel are sequentially disposed on a first side of the substrate, and wherein the second byte pads of the first channel and the second byte pads of the second channel are sequentially disposed on a second side of the substrate opposite the first side of the substrate;a first die comprising first byte pads of the first die and second byte pads of the first die, wherein the first byte pads of the first die are sequentially disposed on a first side of the first die and the second byte pads of the first die are sequentially disposed on a second side of the first die opposite the first side of the first die, and wherein the first byte pads of the first die are respectively coupled to the first byte pads of the first channel and the second byte pads of the first die are respectively coupled to the second byte pads of the first channel; anda second die comprising first byte pads of the second die and second byte pads of the second die, wherein the second die, as disposed, is ...

Semiconductor device and a manufacturing method thereof

A semiconductor device including: a substrate; a via which penetrates the substrate; a via insulating film formed along an inner wall of the via; and a core plug which fills the via, wherein a residual stress of the via insulating film is 60 MPa to −100 MPa.

Semiconductor Device

A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction. 1. A semiconductor device comprising:a semiconductor body,an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side,an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, andat least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction, wherein:the lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via,the lateral extent in the first lateral direction of the contact ...

Substrate with embedded stacked through-silicon via die

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME

A semiconductor package includes a package substrate, a first semiconductor device on an upper surface of the package substrate, a second semiconductor device on an upper surface of the first semiconductor device, a first connection bump attached to a lower surface of the package substrate, a second connection bump interposed between and electrically connected to the package substrate and the first semiconductor device, and a third connection bump interposed between and electrically connected to the first semiconductor device and the second semiconductor device. The first semiconductor device has an edge and a step at the edge. 1. A semiconductor package comprising:a package substrate;a first semiconductor device on an upper surface of the package substrate;a second semiconductor device on an upper surface of the first semiconductor device;a first connection bump attached to a lower surface of the package substrate;a second connection bump interposed between and electrically connected to the package substrate and the first semiconductor device; anda third connection bump interposed between and electrically connected to the first semiconductor device and the second semiconductor device,wherein a step in the first semiconductor device is defined at an edge of the first semiconductor device.2. The semiconductor package of claim 1 , wherein the edge of the first semiconductor device has a modified region.3. The semiconductor package of claim 2 , wherein a density of the modified region of the first semiconductor device is less than a density of a central region of the first semiconductor device.4. The semiconductor package of claim 3 , wherein the package substrate comprises a third semiconductor device having a semiconductor substrate and a first through electrode extending through the semiconductor substrate and electrically connected to the first semiconductor device claim 3 , andthe first semiconductor device comprises a second semiconductor substrate and a second ...

Semiconductor device

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

Semiconductor Package Including Conductive Carrier Coupled Power Switches

In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.

Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device

A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

Chip arrangement and a method for forming a chip arrangement

A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via 1. A semiconductor package , comprising:a first power device having a first surface, a second surface opposite to the first surface, and a first terminal adjacent to the first surface of the first power device;a second power device having a first surface, a second surface opposite to the first surface, and a second terminal adjacent to the first surface of the second power device;a control device having a first surface, a second surface opposite to the first surface, and control device terminals adjacent to the first surface of the control device;a first lower wiring adjacent to the second surface of the first power device;a second lower wiring adjacent to the second surface of the second power device;a third lower wiring adjacent to the second surface of the control device;a first insulating layer covering the first power device, the second power device, the control device, the first lower wiring, the second lower wiring, and third lower wiring, the first insulating layer comprising first openings extending from a first surface of the first insulating layer to the first terminal, the second terminal, and the control device terminals;a first conductive layer over the first terminal and the second terminal but not over the control device terminals; the second conductive layer is ...