Semiconductor Packages and Methods of Forming the Same

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine- containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Semiconductor packages and methods of forming the same

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis ...

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

SEMICONDUCTOR PACKAGE

A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

Electronic device having a redistribution area

An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

Semiconductor device with an anti-pad peeling structure and associated method

BOND PAD HAVING A TRENCH AND METHOD FOR FORMING

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Semiconductor device and semiconductor device manufacturing method

According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

Integrated circuit system with recessed through silicon via pads and method of manufacture thereof

A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.

Mehrfachaufprallprozess zum Bonden

Verfahren mit den folgenden Schritten:Durchführen eines ersten Aufprallprozesses zum Schlagen eines Metallkontakthügels einer ersten Package-Komponente gegen eine Metall-Kontaktstelle einer zweiten Package-Komponente, wobei der Metallkontakthügel oder die Metall-Kontaktstelle Kupfer aufweist und der/die jeweils andere des Metallkontakthügels oder der Metall-Kontaktstelle Aluminium aufweist;Durchführen eines zweiten Aufprallprozesses zum Schlagen des Metallkontakthügels gegen die Metall-Kontaktstelle undDurchführen eines Glühprozesses, um den Metallkontakthügel auf die Metall-Kontaktstelle zu bonden.

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Mehrfachaufprallprozess zum Bonden

Ein Verfahren weist das Durchführen eines ersten Aufprallprozesses zum Schlagen eines Metallkontakthügels einer ersten Package-Komponente gegen eine Metall-Kontaktstelle einer zweiten Package-Komponente auf. Ein erster Metallkontakthügel oder eine erste Metall-Kontaktstelle umfasst Kupfer. Ein zweiter Metallkontakthügel oder eine zweite Metall-Kontaktstelle umfasst Aluminium. Das Verfahren weist weiterhin das Durchführen eines zweiten Aufprallprozesses zum Schlagen des Metallkontakthügels gegen die Metall-Kontaktstelle auf. Ein Glühprozess wird durchgeführt, um den Metallkontakthügel auf die Metall-Kontaktstelle zu bonden.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

L'invention concerne un procédé de liaison consistant à utiliser une couche de liaison présentant un oxyde fluoré. Le fluor peut être introduit dans la couche de liaison par exposition à une solution contenant du fluor, à de la vapeur ou du gaz ou par implantation. La couche de liaison peut aussi être formée au moyen d'un procédé au cours duquel du fluor est introduit dans la couche pendant sa formation. La surface de la couche de liaison se termine par une espèce voulue, de préférence une espèce de NH2. Ceci est accompli par exposition de la couche de liaison à une solution de NH4OH. Un pouvoir de liaison élevé est obtenu à température ambiante. Ce procédé consiste aussi à relier deux couches de liaison ensemble et à créer une répartition de fluor présentant un pic à proximité de l'interface entre les couches de liaison. Une des couches de liaison peut comprendre deux couches d'oxyde formées l'une sur l'autre. La concentration de fluor peut également présenter un second pic au niveau de ...

Forming metal bonds with recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Semiconductor device

According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.

Method for producing structure, and structure

本發明的課題在於：即便是構件的薄膜形成面不平滑的情況，亦藉由原子擴散接合來進行接合。另外，於在構件的金屬薄膜之間存在異物的情況下，亦藉由原子擴散接合來進行接合。本發明為一種將基體（10、20）進行原子擴散接合的結構體（1）的製造方法，其包括：於基體（10）的表面塗佈液狀樹脂（11a）的步驟；藉由液狀樹脂（11a）的表面張力，使液狀樹脂（11a）的表面平滑化的步驟；將液狀樹脂（11a）硬化而形成樹脂層（11）的步驟；於樹脂層（11）的表面形成金屬薄膜（12）的步驟；於基體（20）的表面形成金屬薄膜（21）的步驟；以及將基體（10）的金屬薄膜（12）與基體（20）的金屬薄膜（21）密接而進行原子擴散接合的步驟。

Semiconductor packages and methods of forming the same

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line.

Semiconductor apparatus and method for preparing the same

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

METHOD OF ROOM TEMPERATURE COVALENT BONDINGA method of bonding includes using a bonding layer having a fluorinatedoxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also beformed using a method where fluorine is introduced into the layer during itsformation. The surface of the bonding layer is terminated with a desired species,preferably an NH[err] species. This may be accomplished by exposing the bondinglayer to an NH[err]OH solution. High bonding strength is obtained at roomtemperature. The method may also include bonding two bonding layers together andcreating a fluorine distribution having a peak in the vicinity of the interface betweenthe bonding layers. One of the bonding layers may include two oxide layers formedon each other. The fluorine concentration may also have a second peak at theinterface between the two oxide layers.Figure 1 ...

Forming metal bonds with recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH 2 species. This may be accomplished by exposing the bonding layer to an NH 4 OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Ausbilden von Metallbonds mit Aussparungen

Ein Verfahren umfasst ein Ausbilden eines ersten Vorrichtungs-Die, was ein Abscheiden einer ersten dielektrischen Schicht, und ein Ausbilden eines ersten Metallpads in der ersten dielektrischen Schicht umfasst. Das erste Metallpad umfasst eine Aussparung. Das Verfahren umfasst ferner ein Ausbilden eines zweiten Vorrichtungs-Die, der eine zweite dielektrische Schicht und ein zweites Metallpad in der zweiten dielektrischen Schicht umfasst. Der erste Vorrichtungs-Die wird an den zweiten Vorrichtungs-Die gebondet, wobei die erste dielektrische Schicht an die zweite dielektrische Schicht gebondet wird, und das erste Metallpad an das zweite Metallpad gebondet wird.

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Semiconductor device

本发明提供一种抑制接合焊盘间的短路的技术。半导体装置具有：半导体基板；第一接合焊盘，设在所述半导体基板的上表面，且由含有铝的金属构成；及第二接合焊盘，设在所述半导体基板的所述上表面。所述第一接合焊盘的上表面以越接近所述第二接合焊盘则越位于上方的方式倾斜。

INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

Halbleitervorrichtung

Eine Halbleitervorrichtung umfasst ein Halbleiterelement, ein Die-Pad, ein einkapselndes Element, und eine Mehrzahl von Anschlüssen. Das Die-Pad weist eine vordere Fläche auf, auf welcher das Halbleiterelement montiert ist. Das einkapselnde Element überdeckt und versiegelt das Halbleiterelement. Die Mehrzahl von Anschlüssen weist jeweils ein erstes Ende auf, das mit dem Halbleiterelement im Inneren des einkapselnden Elements verbunden ist und ein zweites Ende, welches aus einer Seitenfläche des einkapselnden Elements herausgeführt ist. Eine untere Fläche einer Verpackung umfassend das Halbleiterelement, das Die-Pad und das einkapselnde Element, befindet sich auf einer Seite einer rückwärtigen Fläche des Die-Pads und weist eine konvex gekrümmte Form auf.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH 2 species. This may be accomplished by exposing the bonding layer to an NH 4 OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Semiconductor device

METHOD OF ROOM TEMPERATURE COVALENT BONDING

CASTELLATION, HATCHING, AND OTHER SURFACE PATTERNS IN DIELECTRIC SURFACES FOR HYBRID BONDING WITH INCREASED SURFACE AREA, BOND STRENGTH, AND ALIGNMENT

A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface, a first layer of dielectric material over the first major surface, and a second layer of dielectric material over the second major surface. The first layer includes a plurality of recesses, and the second layer includes a plurality of protrusions. Each of the plurality of recesses are defined by a shape, and each of the plurality of protrusions are vertically aligned with a corresponding one of the plurality of recesses and are defined by the shape of the corresponding one of the plurality of recesses.

반도체 소자 및 그 형성 방법

... 유전체 위에 UBM(under-bump metallurgy)을 갖는 반도체 소자가 제공된다. UBM은 UBM의 중앙 포인트로부터 오프셋되도록 구성된 트렌치를 갖는다. 트렌치의 중앙과 UBM의 에지 간의 거리는 트렌치의 중앙과 UBM의 대향 에지 간의 거리보다 더 크다. 프로브 핀은 UBM에 접촉하고 측정 데이터를 수집하도록 구성된다.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. © KIPO & WIPO 2007 ...

Semiconductor device and method of forming the same

一種具有覆於一介電層之一凸塊下冶金層(UBM)的半導體裝置被提供。該UBM具有一溝渠，該溝渠經組態以自該UBM之一中心點偏移。介於該溝渠之一中心及該UBM之一邊緣之一距離大於介於該溝渠之該中心至該UBM之一相對邊緣的一距離。一探針經組態以接觸該UBM並收集測量資料。

WAFER BONDING STRUCTURE, WAFER BONDING METHOD AND CHIP BONDING STRUCTURE

The present invention provides a wafer bonding structure, a wafer bonding method and a chip bonding structure. A first wafer has non-metallic regions and metallic regions provided with a first metal layer. A portion of a first modification layer located above the non-metallic regions is recessed with respect to a portion of the first modification layer located above the metallic regions. A second modification layer covers the first modification layer. A chemical mechanical polishing process is performed on the second and first modification layers, which uses a polishing slurry exhibiting different polishing rates for the first and second modification layers, and as a result of which, the remaining second modification layer above the non-metallic regions is raised or recessed with respect to the remaining first modification layer above the metallic regions, resulting in the formation of first convex portions or first concave portions above the non-metallic regions. When this wafer is bonded to a wafer or dies with corresponding concavities or convexities, less gaps will be left from the bonding, improving process quality and product yield. Moreover, local concavities resulting from the CMP process can be eliminated or reduced, alleviating the problem of gaps left between bonded upper and lower wafers and achieving enhanced bonding strength and quality.

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

本揭露係關於一種半導體裝置及其製造方法，該半導體裝置具有由融熔接合技術形成之複數個接合的半導體元件。該等半導體元件具有複數個傳導部，其熱膨脹係數大於介電部的熱膨脹係數。在融熔接合技術之熱處理製程中，具有較高熱膨脹係數的傳導部的體積膨脹，可藉由凹部提供的膨脹空間予以容納。如此，藉由融熔接合技術接合該等半導體元件而形成的半導體裝置在兩個介電部之間的界面中不具有一橫向突出。因此，可以有效排除橫向突出造成的電性功能故障。

Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH₂ species. This may be accomplished by exposing the bonding layer to an NH₄OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

SOLID-STATE IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

BONDING STRUCTURE AND METHOD THEREOF

A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Forming metal bonds with recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH 2 species. This may be accomplished by exposing the bonding layer to an NH 4 OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH 2 species. This may be accomplished by exposing the bonding layer to an NH 4 OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

PACKAGE WITH BUILT-IN ELECTRONIC COMPONENTS AND ELECTRONIC DEVICE

A package with built-in electronic components that is to be soldered to an electronic circuit board includes: an insulating layer; an electronic component provided on one surface of the insulating layer; and a pad which is electrically connected to the electronic component and in which a plurality of openings that extend from a first surface of the pad in contact with a solder bump to the insulating layer are formed, wherein an area of the plurality of openings at the first surface is larger than an area of the plurality of openings at a second surface of the pad, which is an opposite surface to the first surface and is in contact with the insulating layer.

SOLID-STATE IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Semiconductor device and manufacturing method thereof

本发明提供了半导体器件及其形成方法。提供了一种具有位于介电层上方的凸块下金属层(UBM)的半导体器件。UBM具有配置为偏离UBM的中心点的沟槽。沟槽中心到UBM的边缘之间的距离大于沟槽中心到UBM的相对边缘之间的距离。探针配置为接触UBM并采集测量数据。

Semiconductor device and semiconductor device manufacturing method

若根據實施形態，則提供一種半導體裝置。半導體裝置是具備：絕緣層、電極、及溝。絕緣層是設在基板的表面。電極是被埋設於絕緣層中，一方的端面會從絕緣層露出。溝是被形成於基板表面的電極的周圍。並且，溝是以電極的外側面作為一方的側面，絕緣層的表面側被開放。被埋設於絕緣層的電極是一方的端面會從絕緣層的表面突出。

ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA

An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion. 1. An electronic device comprising:an upper insulating layer on a substrate;an upper redistribution structure embedded in the upper insulating layer, wherein the upper redistribution structure comprises an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion;a passivation layer on the upper insulating layer and the upper redistribution structure; andan upper opening configured to pass through the passivation layer and expose the upper pad portion,wherein vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.2. The electronic device of claim 1 , wherein:the upper insulating layer has an upper contact opening, an upper line recess, and an upper pad opening;the upper contact opening and the upper pad opening pass through the upper insulating layer; andthe upper line recess connects an upper portion of the upper contact opening to an upper portion of the upper pad opening.3. The electronic device of claim 2 , wherein:the upper contact portion is in the upper contact opening;the upper pad portion is in the upper pad opening; andthe upper line portion is in the upper line portion.4. The electronic device of claim 1 , wherein the upper redistribution structure ...

Semiconductor device with an anti-pad peeling structure and associated method

本揭露揭示一種具有一抗銲墊剝離結構之半導體裝置。該半導體裝置包含：一半導體基板，其包含一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且其中包含複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽；其中該銲墊延伸至該複數個凹槽，且該銲墊與導電層之間的複數個接觸點侷限於該等凹槽中，且當自一俯視觀點觀看時，該等接觸點中之每一者至少部分地在該TSV之一邊界之外。

Semiconductor device with an anti-pad peeling structure and associated method

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Semiconductor device with an anti-pad peeling structure and associated method

本揭露揭示一種具有一抗銲墊剝離結構之半導體裝置。該半導體裝置包含：一半導體基板，其包含一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且其中包含複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽；其中該銲墊延伸至該複數個凹槽，且該銲墊與導電層之間的複數個接觸點侷限於該等凹槽中，且當自一俯視觀點觀看時，該等接觸點中之每一者至少部分地在該TSV之一邊界之外。

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different ...

SEMICONDUCTOR PACKAGES

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via. 1. A semiconductor package comprising:a plurality of semiconductor chips electrically connected to each other and stacked in a first direction, a semiconductor substrate including a semiconductor layer having a first surface and a second surface that are opposite each other;', 'a passivation layer on the first surface and having a third surface that is opposite the first surface;', 'a circuit structure on the second surface;', 'a frontside pad on the circuit structure;', 'a backside pad on the third surface; and', 'a through-via in the semiconductor substrate and extending between the second surface and the third surface to be electrically connected to the backside pad and the frontside pad,, 'wherein at least one of the plurality of semiconductor chips includeswherein the backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding toward the first surface on one side of the electrode pad portion and surrounding a side surface of the through-via, andwherein the dam structure is spaced apart from the side surface of the through-via.2. The semiconductor package of claim 1 ,wherein the dam structure penetrates the third surface of the passivation layer,wherein a ratio of a height of the dam structure in the first direction to a maximum thickness of the passivation layer is within a range of about 0.5:1 to about 0.8:1,wherein the through- ...

SEMICONDUCTOR DEVICE WITH AN ANTI-PAD PEELING STRUCTURE AND ASSOCIATED METHOD

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective. 1. A semiconductor device with an anti-pad peeling structure , comprising:a semiconductor substrate comprising a Through Substrate Via (TSV) including a conductive portion;a dielectric layer on the semiconductor substrate and comprising a plurality of recesses therein; anda pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses,wherein from a top-down perspective the pad fully covers the TSV, and a distance between an edge of the pad and the outermost edge of the recesses is greater than a specified length;wherein a plural portion of the plurality of the recesses has planar boundaries that partially overlap that of the conductive portion of the TSV; and for the recesses that partially overlap the conductive portion of the TSV, an overlap ratio is less than a specified ratio of an area of the recess.2. The semiconductor device of claim 1 , further comprising:a conductive layer on the TSV;wherein the pad is extended to the conductive layer through the recesses so that the pad is electrically connected to the TSV.4. The semiconductor device of claim 2 , wherein the conductive layer comprises copper (Cu).5. The semiconductor device of claim 1 , wherein the specified length is about 2 μm.6. (canceled)7. The semiconductor device of claim 1 , wherein the ...

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Semiconductor device

According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.

Multi-Strike Process for Bonding

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH₂ species. This may be accomplished by exposing the bonding layer to an NH₄OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

METHOD FOR PRODUCING STRUCTURE, AND STRUCTURE

This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion

Interconnect structures

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Semiconductor packages

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

EXPANSION CONTROLLED STRUCTURE FOR DIRECT BONDING AND METHOD OF FORMING SAME

An element, a bonded structure including the element, and a method forming the element and the bonded structure are disclosed. The element can include a non-conductive region having a cavity. The element can include a conductive feature formed in the cavity. The conductive feature includes a center portion and an edge portion having first and second coefficients of thermal expansion respectively. The center and edge portions are recessed relative to a contact surface of the non-conductive region by a first depth and a second depth respectively. The first coefficient of thermal expansion can be at least 5% greater than the second coefficient of thermal expansion. The bonded structure can include the element and a second element having a second non-conductive region and a second conductive feature. A conductive interface between the first and second conductive features has a center region and an edge region. In a side cross-section of the bonded structure, there are more voids at or near the edge region than at or near the center region.

Semiconductor device

Embodiments provide a semiconductor device capable of properly bonding pads to each other. According to one embodiment, a semiconductor device includes: a first chip having a first plug and a first pad provided on the first plug; and a second chip having a second plug and a second pad provided under the second plug. The second chip includes: an electrode layer electrically connected to the second plug; a charge accumulation layer provided on a side surface of the electrode layer with a first insulating film interposed there between; and a semiconductor layer provided on a side surface of the charge accumulation layer with a second insulating film interposed there between. The first bonding pad and the second bonding pad are bonded to each other. The first plug and the second plug are arranged so that at least a part of the first plug and at least a part of the second plug do not overlap each other in a first direction perpendicular to the surface of the substrate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

Multi-strike process for bonding packages and the packages thereof

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Multi-strike process for bonding

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

HYBRID BONDING STRUCTURE AND HYBRID BONDING METHOD

Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric. 1. A hybrid bonding structure , comprising:a first chip; anda second chip, whereina surface of the first chip includes a first dielectric layer and a first metal layer, the first dielectric layer includes a first insulation dielectric, the first metal layer includes a first metal, and a first gap area exists between an edge of the first metal and the first insulation dielectric;a surface of the second chip includes a second dielectric layer and a second metal layer, the second dielectric layer includes a second insulation dielectric, and the second metal layer includes a second metal;a surface of the first metal is higher than a surface of the first insulation dielectric;metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area, andinsulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric.2. The hybrid bonding structure according to claim 1 , wherein a surface of the second metal is higher than a surface of the second insulation dielectric.3. The hybrid bonding structure ...

INTERCONNECT STRUCTURES

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

SEMICONDUCTOR DEVICE

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate. 1. A semiconductor device comprising: a substrate,', 'a first interconnect layer provided above the substrate,', 'a first pad provided above the first interconnect layer, and', 'a first plug extending in a first direction crossing a surface of the substrate and connecting the first interconnect layer and the first pad; and, 'a first chip including a second interconnect layer,', 'a second pad provided under the second interconnect layer,', 'a second plug extending in the first direction and connecting the second interconnect layer and the second pad, and', 'a memory cell array electrically connected to the second interconnect layer, wherein', 'the first and second plugs do not overlap with each other in the first direction,, 'a second chip includinga first portion of the first pad overlapping with the first plug in the first direction are all bonded with the second pad, anda second portion of the second pad overlapping with the second plug in the first direction are all bonded with the first pad.2. The device of claim 1 , whereina material of the first plug is identical with a material of the first pad and different from a material of the first interconnect layer, anda ...

Semiconductor device and semiconductor device manufacturing method

According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonding method comprising: depositing a first film on the first element,', 'introducing fluorine into the first film,', 'polishing the first film,', 'depositing a second film directly on the first film to define an interface between the first film and the second film,', 'introducing fluorine into the second film, and', 'polishing the second film;, 'forming a first bonding layer on a first element, wherein forming the first bonding layer comprisesforming a second bonding layer on a second element;bringing into contact a surface of the second film with a surface of the second bonding layer at about room temperature; andforming a direct bond between the second film and the second bonding layer without an intervening adhesive.3. The method of claim 2 , wherein forming the first bonding layer comprises depositing the first film and subsequently introducing fluorine into the first film; and depositing the second film and subsequently introducing fluorine into the second film.4. The method of claim 3 , wherein introducing fluorine into the first film comprises ...

Semiconductor packages and methods of forming the same

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis ...

Semiconductor device

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

SEMICONDUCTOR DEVICE

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate. 1. A semiconductor device comprising: a substrate,', 'a first interconnect layer provided above the substrate,', 'a first pad provided above the first interconnect layer; and', 'a first plug extending in a first direction crossing a surface of the substrate and connecting the first interconnect layer and the first pad; and, 'a first chip including a second interconnect layer,', 'a second pad provided under the second interconnect layer,', 'a second plug extending in the first direction and connecting the second interconnect layer and the second pad,, 'a second chip includinga memory cell array electrically connected to the second interconnect layer, anda bit line provided between the second interconnect layer and the memory cell array in the first direction and extending in a second direction crossing the first direction, whereinthe first plug does not overlap with the second plug in the first direction.the first pad has a first width in a third direction crossing the first direction and the second direction,the first plug has a second width in the third direction which is minimum width in the third direction,the first pad includes a first portion which is bonded to the ...

METHOD FOR PREPARING A SEMICONDUCTOR APPARATUS

The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

CHIP BONDING METHOD AND SEMICONDUCTOR CHIP STRUCTURE

A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

Multi-strike process for bonding

PACKAGED SEMICONDUCTOR DEVICE

A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data. 1. A semiconductor device , comprising:an under-bump metallurgy (UBM) overlying a dielectric, the UBM having a trench,wherein the trench is offset from a central point of the UBM,wherein the trench has a base portion at a center of the trench,wherein the UBM has a first skirt and a second skirt, the first skirt being greater in dimension than the second skirt, and a terminal portion of the first skirt not being contacting with a conductive material.2. The semiconductor device according to claim 1 , wherein the base portion is substantially quadrilateral.3. The semiconductor device according to claim 1 , wherein the UBM is substantially quadrilateral.4. The semiconductor device according to claim 1 , wherein a first distance from the center of the trench to an edge of the UBM is larger than a second distance between the center of the trench to an opposite edge of the UBM.5. The semiconductor device according to claim 4 , wherein a difference between the first distance and the second distance is about 50 μm and about 100 μm.6. The semiconductor device according to claim 1 , wherein the trench has a perimeter portion next to the base portion claim 1 ,wherein a distance from an outer boundary of the perimeter portion to an edge of the UBM is different from a distance from an outer boundary of the base portion to an opposite edge of the UBM.7. The semiconductor device according to claim 1 , wherein the trench has a first perimeter portion and a second perimeter portion claim 1 , and the first perimeter portion and the second perimeter portion are at opposites sides of the base ...

SEMICONDUCTOR DEVICE

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate. 1. A semiconductor device comprising:a first chip including a substrate, a first plug provided on the substrate, and a first pad provided on the first plug; anda second chip including a second plug and a second pad provided under the second plug,the second chip comprising:an electrode layer electrically connected to the second plug;a charge storage layer provided on a side face of the electrode layer via a first insulator; anda semiconductor layer provided on a side face of the charge storage layer via a second insulator,whereinthe first pad and the second pad are bonded with each other, andthe first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.2. The device of claim 1 , wherein a thickness of the first plug is equal to or greater than twice as thick as a thickness of the first pad claim 1 , and a thickness of the second plug is equal to or greater than twice as thick as a thickness of the second pad.3. The device of claim 1 , further comprising:a first interconnect that extends in a first interconnect ...

Multi-strike process for bonding

Bond pad having a trench and method for forming

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Used for jointing multi-impact process

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonded structure comprising:a first element;a first bonding layer disposed on the first element, the first bonding layer comprising a first film and a second film formed directly on the first film, wherein each of the first and the second films is planarized and includes fluorine;a second element; anda second bonding layer disposed on the second element,wherein the second film and the second bonding layer are directly bonded to one another without an intervening adhesive.3. The bonded structure of claim 2 , further comprising a fluorine concentration within the first bonding layer having a first peak in the vicinity of a bonding interface between the first and second bonding layers and a second peak in the vicinity of an internal interface between the first and second films.4. The bonded structure of claim 2 , wherein the second bonding layer comprises a third film on the second element and a fourth film on the third film.5. The bonded structure of claim 2 , wherein the second film is disposed directly on the first film without intervening layers.6. The ...

Hybrid bonding structure and hybrid bonding method

Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric.

結構體的製造方法及結構體

本發明為一種將基體(10、20)進行原子擴散接合的結構體(1)的製造方法，其包括：於基體(10)的表面塗佈液狀樹脂(11a)的步驟；藉由液狀樹脂(11a)的表面張力，使液狀樹脂(11a)的表面平滑化的步驟；將液狀樹脂(11a)硬化而形成樹脂層(11)的步驟；於樹脂層(11)的表面形成金屬薄膜(12)的步驟；於基體(20)的表面形成金屬薄膜(21)的步驟；以及將基體(10)的金屬薄膜(12)與基體(20)的金屬薄膜(21)密接而進行原子擴散接合的步驟。

SOLID-STATE IMAGING ELEMENTS, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Semiconductor device and method of forming the same

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data. 1. A semiconductor device , comprising:an interconnecta dielectric layer overlying the interconnect having an opening defined therein that exposes a portion of the interconnect; andan under-bump metallurgy (UBM) overlying a top surface of the dielectric layer, the UBM comprising a trench structure that is offset from a central point of the UBM and electrically connects the interconnect through the opening;wherein the UBM comprises a first skirt on one end and a second skirt on the other end, the first skirt having a greater dimension than that of the second skirt,wherein the trench structure comprises a partially tapered shape defined by a substantially flat base portion and only one angled perimeter portion, andwherein the only one angled perimeter portion is proximal to the first skirt.2. The semiconductor device of claim 1 , wherein the trench structure comprises a trench set having a first trench and a second trench.3. The semiconductor device of claim 2 , wherein a length between the first trench and the second trench is in a range of from about 30 μm to about 45 μm..4. The semiconductor device of claim 1 , wherein a top surface of the first skirt and a top surface of the second skirt being free of material formed directly on it.5. The semiconductor device of claim 1 , wherein a length of the first skirt is in a range of from about 50 μm to about 200 μm.6. The semiconductor device of claim 5 , wherein a length of the second skirt is in a range of from about 10 μm to about 50 μm.7. The semiconductor device of claim 2 , further comprising a bump disposed in one of the ...

Semiconductor apparatus and method for preparing the same

The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

Semiconductor device

A semiconductor device includes a semiconductor element, a die pad, an encapsulating member, and a plurality of leads. The die pad has a front surface on which the semiconductor element is mounted. The encapsulating member covers and seals the semiconductor element. The plurality of leads each have a first end connected to the semiconductor element in an inside of the encapsulating member and a second end led out from a side surface of the encapsulating member. A lower surface of a package including the semiconductor element, the die pad, and the encapsulating member is located on a back surface side of the die pad and has a convexly curved shape.

形成具有凹槽的金属接合件

一种方法包括形成第一器件管芯，其中，该形成包括沉积第一介电层，以及在第一介电层中形成第一金属焊盘。第一金属焊盘包括凹槽。该方法还包括形成第二器件管芯，其中，第二器件管芯包括第二介电层和位于第二介电层中的第二金属焊盘。将第一器件管芯接合至第二器件管芯，其中，第一介电层接合至第二介电层，并且第一金属焊盘接合至第二金属焊盘。本发明的实施例还涉及形成具有凹槽的金属接合件。

Metal joint with groove

一种方法包括形成第一器件管芯，其中，该形成包括沉积第一介电层，以及在第一介电层中形成第一金属焊盘。第一金属焊盘包括凹槽。该方法还包括形成第二器件管芯，其中，第二器件管芯包括第二介电层和位于第二介电层中的第二金属焊盘。将第一器件管芯接合至第二器件管芯，其中，第一介电层接合至第二介电层，并且第一金属焊盘接合至第二金属焊盘。本发明的实施例还涉及形成具有凹槽的金属接合件。

Electronic Device having a Redistribution Area

재배선 영역을 갖는 전자 소자가 제공될 수 있다. 상기 전자 소자는 기판 상에 배치되는 상부 절연 층을 포함한다. 상기 상부 절연 층 내에 상부 재배선 구조체가 매립된다. 상기 상부 재배선 구조체는 상부 콘택 부분, 상부 패드 부분 및 상기 상부 콘택 부분과 상기 상부 패드 부분 사이의 상부 라인 부분을 포함한다. 상기 상부 절연 층 및 상기 상부 재배선 구조체 상에 패시베이션 층이 배치된다. 상기 패시베이션 층을 관통하며 상기 상부 패드 부분을 노출시키는 상부 개구부가 배치된다. 상기 상부 패드 부분 및 상기 상부 콘택 부분의 수직 두께들은 상기 상부 라인 부분의 수직 두께 보다 크다.

Room temperature covalent bonding method

Forming metal bonds with recesses

방법은, 제1 유전체 층을 성막하는 단계 및 제1 유전체 층 내에 제1 금속 패드를 형성하는 단계를 포함하는, 제1 디바이스 다이를 형성하는 단계를 포함한다. 제1 금속 패드는 리세스를 포함한다. 상기 방법은 제2 유전체 층 및 제2 유전체 층 내의 제2 금속 패드를 포함하는 제2 디바이스 다이를 형성하는 단계를 더 포함한다. 제1 디바이스 다이는 제2 디바이스 다이에 본딩되고, 제1 유전체 층은 제2 유전체 층에 본딩되고, 제1 금속 패드는 제2 금속 패드에 본딩된다.

Semiconductor packages and forming method thereof

提供一种半导体封装，所述半导体封装包括第一装置封装，所述第一装置封装包括：第一重布线结构，包括第一重布线及第二重布线；管芯，位于第一重布线结构上；第一通孔，耦合到第一重布线的第一侧；第二通孔，耦合到第二重布线的第一侧且延伸穿过所述第二重布线；包封体，环绕管芯、第一通孔、及第二通孔；以及第二重布线结构，位于包封体之上，所述第二重布线结构电连接到管芯、第一通孔、及第二通孔。所述半导体封装还包括：第一导电连接件，耦合到第一重布线的第二侧，所述第一导电连接件沿与第一通孔的纵向轴线不同的轴线设置；第二导电连接件，耦合到第二重布线的第二侧，所述第二导电连接件沿第二通孔的纵向轴线设置。

Solid-state imaging element, the manufacture method of solid-state imaging element and electronic installation

本发明涉及一种固态成像元件以及固态成像元件的制造方法和电子装置。所述固态成像元件包括：配置且形成有光电转换部的传感器基板；形成有用于驱动所述光电转换部的电路的电路基板，所述电路基板层叠到所述传感器基板；传感器侧电极，被引出到所述传感器基板的位于电路基板侧的表面，并且形成为凸型电极和凹型电极中的一者；和电路侧电极，被引出到所述电路基板的位于传感器基板侧的表面，形成为凹型电极和凸型电极中的一者，并在所述电路侧电极与所述传感器侧电极被装配在一起的状态下接合至所述传感器侧电极。

Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic apparatus

Semiconductor package including alignment material and method for manufacturing semiconductor package

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.

semiconductor equipment

Semiconductor package

본 발명의 일 실시예는, 복수의 반도체 칩들 중 적어도 하나의 반도체 칩은, 반도체 층 및 제3 면을 갖는 패시베이션층을 포함하는 반도체 기판, 제3 면 상에 배치되는 후면 패드, 및 반도체 기판을 관통하는 관통 비아를 포함하고, 후면 패드는 제3 면 상에 배치되는 전극 패드부 및 전극 패드부의 일측에서 돌출되며 관통 비아의 측면을 둘러싸는 댐(dam) 구조를 포함하고, 댐 구조는 관통 비아의 측면과 이격되는 반도체 패키지를 제공한다.

Multi-strike process for bonding

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Hybrid bonding structure and hybrid bonding method

Semiconductor packages and methods of forming the same

A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.

Hybrid bonding structure and hybrid bonding method

一种混合键合结构及混合键合方法，该混合键合结构包括：第一芯片(10)和第二芯片(20)，第一芯片(10)的表面包括第一绝缘介质(11)和第一金属(12)，第一金属(12)和第一绝缘介质(11)之间具有第一空隙区域(13)；第二芯片(20)的表面包括第二绝缘介质(21)和第二金属(22)；第一金属(12)的表面高于第一绝缘介质(11)的表面；第一金属(22)和第二金属(22)接触后形成金属键合，在第一空隙区域(13)内，第一金属(12)发生纵向和横向的形变；第一绝缘介质(11)和第二绝缘介质(21)接触后形成绝缘介质键合。通过设置第一空隙区域(13)，保证第一金属(12)可以同时发生纵向和横向的形变，可以避免出现金属键合缺陷和介质键合缺陷，提高量产良率和器件的长期可靠性。

Hybrid bonding structure and hybrid bonding method

Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and there is a first gap area between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric. In the embodiments of this application, the first gap area is disposed to ensure that the first metal may be longitudinally deformed and transversely deformed at the same time. This may avoid a metallic bonding defect and a dielectric bonding defect, and improve a yield rate of mass production and long-term reliability of a device.

Semiconductor device

实施方式提供一种能够将焊垫彼此适当地接合的半导体装置。根据一实施方式，半导体装置具备：第1芯片，具有第1插塞、及设置在所述第1插塞上的第1焊垫；及第2芯片，具有第2插塞、及设置在所述第2插塞下的第2焊垫。所述第2芯片具备：电极层，和所述第2插塞电连接；电荷蓄积层，在所述电极层的侧面介隔第1绝缘膜而设置；及半导体层，在所述电荷蓄积层的侧面介隔第2绝缘膜而设置。而且，所述第1焊垫与所述第2焊垫接合；所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞至少一部分不相互重叠的方式配置。

Method of room temperature covalent bonding

결합 방법은 플루오르화 산화물을 갖는 결합층의 이용을 포함한다. 불소는 불소-함유 용액, 증기 또는 가스에 노출시키거나 또는 주입에 의해 결합층 중으로 도입될 수 있다. 결합층은 또한 불소가 층을 형성하는 동안 이에 도입되는 방법을 이용하여 형성될 수 있다. 결합층의 표면은 목적하는 종, 바람직하게는 NH 2 종으로 종결된다. 이러한 과정은 결합층을 NH 4 OH 용액에 노출시킴으로써 달성될 수 있다. 고 결합 강도는 실온에서 수득된다. 상기 방법은 또한 두 개의 결합층을 함께 결합시키고 결합층 간의 계면 부근에서 피크를 갖는 불소 분포를 생성시키는 단계를 포함할 수 있다. 결합층 중 하나는 서로의 위에 형성된 두 산화물층을 포함할 수 있다. 불소 농도는 또한 두 산화물층간의 계면에서 제 2 피크를 가질 수 있다. The bonding method involves the use of a bonding layer having a fluorinated oxide. Fluorine may be introduced into the binding layer by exposure to fluorine-containing solution, vapor or gas, or by injection. The bonding layer can also be formed using a method in which fluorine is introduced therein during the formation of the layer. The surface of the bonding layer is terminated with the desired species, preferably with NH 2 species. This process can be accomplished by exposing the bonding layer to NH 4 OH solution. High bond strength is obtained at room temperature. The method may also include joining two bonding layers together and generating a fluorine distribution with peaks near the interface between the bonding layers. One of the bonding layers may comprise two oxide layers formed on top of each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 결합 방법, 플루오르화 산화물, 불소, 암모늄, 웨이퍼 Bonding method, fluoride oxide, fluorine, ammonium, wafer

半导体装置

实施方式提供一种能够将焊垫彼此适当地接合的半导体装置。根据一实施方式，半导体装置具备：第1芯片，具有第1插塞、及设置在所述第1插塞上的第1焊垫；及第2芯片，具有第2插塞、及设置在所述第2插塞下的第2焊垫。所述第2芯片具备：电极层，和所述第2插塞电连接；电荷蓄积层，在所述电极层的侧面介隔第1绝缘膜而设置；及半导体层，在所述电荷蓄积层的侧面介隔第2绝缘膜而设置。而且，所述第1焊垫与所述第2焊垫接合；所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞至少一部分不相互重叠的方式配置。

在介電表面中用於增加表面積、接合強度、及對準之接合的齒型、陰影線、及其他表面圖案

本發明係關於一種半導體裝置，其包括具有一第一主表面及與該第一主表面相對之一第二主表面的一半導體基板、在該第一主表面上方之一第一介電材料層及在該第二主表面上方之一第二介電材料層。該第一層包括複數個凹部，且該第二層包括複數個突起。該複數個凹部中之每一者由一形狀界定，且該複數個突起中之每一者與該複數個凹部中之一對應一者豎直對準且由該複數個凹部中之該對應一者的形狀界定。

Semiconductor packages

A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.

Interconnect structures

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Expansion controlled structure for direct bonding and method of forming same

An element, a bonded structure including the element, and a method forming the element and the bonded structure are disclosed. The element can include a non-conductive region having a cavity. The element can include a conductive feature formed in the cavity. The conductive feature includes a center portion and an edge portion having first and second coefficients of thermal expansion respectively. The center and edge portions are recessed relative to a contact surface of the non-conductive region by a first depth and a second depth respectively. The first coefficient of thermal expansion can be at least 5% greater than the second coefficient of thermal expansion. The bonded structure can include the element and a second element having a second non-conductive region and a second conductive feature. A conductive interface between the first and second conductive features has a center region and an edge region. In a side cross-section of the bonded structure, there are more voids at or near the edge region than at or near the center region.

Semiconductor device and method of manufacturing the same

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

Semiconductor device and method of manufacturing the same

A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

用於直接接合的膨脹控制結構及其形成方法

本發明揭示一種元件、一種包括該元件之接合結構以及一種形成該元件及該接合結構之方法。該元件可包括具有空腔之不導電區。該元件可包括形成於該空腔中之導電特徵。該導電特徵包括分別具有第一熱膨脹係數之中心部分及具有第二熱膨脹係數之邊緣部分。該中心部分及該邊緣部分相對於該不導電區之接觸表面分別凹陷第一深度及第二深度。該第一熱膨脹係數可比該第二熱膨脹係數大至少5%。該接合結構可包括該元件及第二元件，該第二元件具有第二不導電區及第二導電特徵。該第一導電特徵與該第二導電特徵之間的一導電界面具有中心區及邊緣區。在該接合結構之側截面中，相比於在該中心區處或附近，在該邊緣區處或附近存在更多孔隙。

Method for producing structure, and structure

This method for producing a structure (1) wherein base materials (10, 20) are bonded by atomic diffusion comprises: a step for applying a liquid resin (11a) to the surface of the base material (10); a step for smoothing the surface of the liquid resin (11a) by means of the surface tension of the liquid resin (11a); a step for forming a resin layer (11) by curing the liquid resin (11a); a step for forming a metal thin film (12) on the surface of the resin layer (11); a step for forming a metal thin film (21) on the surface of the base material (20); and a step for bringing the metal thin film (12) of the base material (10) and the metal thin film (21) of the base material (20) into close contact with each other, thereby bonding the metal thin film (12) of the base material (10) and the metal thin film (21) of the base material (20) with each other by atomic diffusion. Consequently, the present invention enables bonding by means of atomic diffusion even in cases where the thin film formation surface of a member is not smooth.

構造体の製造方法及び構造体

基体（１０，２０）を原子拡散接合した構造体（１）の製造方法であって、基体（１０）の表面に液状樹脂（１１ａ）を塗布する工程と、液状樹脂（１１ａ）の表面張力により、液状樹脂（１１ａ）の表面を平滑化する工程と、液状樹脂（１１ａ）を硬化して樹脂層（１１）を形成する工程と、樹脂層（１１）の表面に金属薄膜（１２）を形成する工程と、基体（２０）の表面に金属薄膜（２１）を形成する工程と、基体（１０）の金属薄膜（１２）と基体（２０）の金属薄膜（２１）とを密着して原子拡散接合する工程とを含む。これにより、部材の薄膜形成面が平滑ではない場合でも、原子拡散接合による接合を行うことができる。

晶圆键合结构、晶圆键合方法及芯片键合结构

本发明提供了一种晶圆键合结构、晶圆键合方法及芯片键合结构，第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于非金属层区域的第一调整层低于位于金属层区域的所述第一调整层；第二调整层覆盖第一调整层；化学机械研磨所述第二调整层和所述第一调整层，研磨液对第一调整层和第二调整层的研磨速率不同，使在非金属层区域剩余的第二调整层高于或低于在金属层区域剩余的第一调整层，在非金属层区域形成第一凸起部或第一凹陷部，以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙，提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷，修正上下晶圆的键合空隙，提高键合强度以及质量。

晶圆键合结构、晶圆键合方法及芯片键合结构

本发明提供了一种晶圆键合结构、晶圆键合方法及芯片键合结构，第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于非金属层区域的第一调整层低于位于金属层区域的所述第一调整层；第二调整层覆盖第一调整层；化学机械研磨所述第二调整层和所述第一调整层，研磨液对第一调整层和第二调整层的研磨速率不同，使在非金属层区域剩余的第二调整层高于或低于在金属层区域剩余的第一调整层，在非金属层区域形成第一凸起部或第一凹陷部，以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙，提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷，修正上下晶圆的键合空隙，提高键合强度以及质量。

반도체 장치 및 그의 제조 방법

하부 구조체, 및 상부 구조체를 포함하는 반도체 장치를 제공하되, 상기 하부 구조체는 제 1 반도체 기판, 상기 제 1 반도체 기판 상의 제 1 패드, 및 상기 제 1 반도체 기판 상에서 상기 제 1 패드를 둘러싸는 제 1 절연막을 포함하고, 상기 상부 구조체는 제 2 반도체 기판, 상기 제 2 반도체 기판 상의 제 2 패드, 및 상기 제 2 반도체 기판 상에서 상기 제 2 패드를 둘러싸는 제 2 절연막을 포함하고, 상기 제 1 패드와 상기 제 2 패드가 서로 접하고 상기 제 1 절연막과 상기 제 2 절연막이 서로 접하도록, 상기 상부 구조체와 상기 하부 구조체가 서로 접합되고, 상기 제 1 절연막은 상기 제 1 패드와 접하는 제 1 리세스를 갖고, 상기 제 2 절연막은 상기 제 2 패드와 접하고 상기 제 1 리세스와 중첩되는 제 2 리세스를 갖고, 상기 제 1 리세스 및 상기 제 2 리세스에 의해 기공이 정의되되, 상기 기공 내에 제 1 및 제 2 패드들을 구성하는 금속 물질의 입자가 배치될 수 있다.

반도체 장치 및 이의 제조 방법

본 발명은 반도체 장치를 제공한다. 본 발명에 따른 반도체 장치는 제1 기판, 상기 제1 기판 상의 제1 패드, 및 상기 제1 패드를 둘러싸는 제1 절연막을 포함하는 하부 구조체 및 제2 기판, 상기 제2 기판 상의 제2 패드, 및 상기 제2 패드를 둘러싸는 제2 절연막을 포함하는 상부 구조체를 포함하되, 상기 제1 및 제2 패드들 각각은 제1 부분 및 상기 제1 부분 상의 제2 부분을 포함하되, 상기 제2 부분은 상기 제1 부분과 동일한 금속 물질을 포함하고, 상기 제1 패드의 상기 제2 부분과 상기 제2 패드의 상기 제2 부분이 서로 접촉하고, 상기 제1 절연막과 상기 제2 절연막이 서로 접촉한다.

Method for forming bonded semiconductor structure utilizing concave/convex profile design for bonding pads

A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.

半导体装置

实施方式提供一种能够确保各晶片间的接合强度及导通性的半导体装置。实施方式的半导体装置具有第1晶片、第1配线层、第1绝缘层、第1电极、第2晶片、第2配线层、第2绝缘层、第2电极和第1层。第1电极具有第1面、第2面、第3面及第4面。第2电极具有第5面、第6面、第7面、第2侧面及第8面。第1层设于第4面与第1绝缘层中的将第4面包围的部分之间，从第3面在第1方向上远离而设置。

芯片封装结构及其制作方法

本发明提供一种芯片封装结构及其制作方法，芯片封装结构包括基板、至少二个芯片、多个第一接垫、多个第一微凸块以及桥接元件。基板具有第一表面以及与第一表面相对的第二表面。二个芯片配置于基板的第一表面，且彼此水平相邻。各芯片具有主动表面。第一接垫配置于各芯片的主动表面。第一微凸块配置于第一接垫上且尺寸皆相同。桥接元件配置于第一微凸块上，以使其中一芯片通过第一接垫、第一微凸块以及桥接元件电性连接至另一芯片。

Semiconductor device

A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted of a metal including aluminum, and a second bonding pad provided on the upper surface of the semiconductor substrate. An upper surface of the first bonding pad may be inclined such that positions on the upper surface of the first bonding pad which are closer to the second bonding pad are positioned further above.

一种半导体封装结构及其形成方法

本公开实施例公开了一种半导体封装结构及其形成方法，其中，所述半导体封装结构包括：第一半导体芯片；所述第一半导体芯片的表面形成有多个第一接触垫；介质层，位于所述第一半导体芯片上；所述介质层内形成有多个第二接触垫；第二半导体芯片堆叠结构，位于所述介质层上；所述第二半导体芯片堆叠结构包括依次堆叠的多层第二半导体芯片；第一层第二半导体芯片的表面形成有多个第三接触垫；所述第一半导体芯片和所述第一层第二半导体芯片通过所述第一接触垫、所述第二接触垫和所述第三接触垫一一对应相互键合；其中，每一个所述第二接触垫的宽度与其相对应的第一接触垫，和/或，第三接触垫的宽度不一致。

Semiconductor structure for wafer level bonding and bonded semiconductor structure

A semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface, and a sidewall between the top surface and the bottom surface. A bottom angle between the bottom surface and sidewall of the bonding pad is smaller than 90 degrees.

반도체 패키지 및 반도체 패키지의 제조 방법

반도체 패키지는, 서로 반대하는 제1 상면 및 제1 하면을 가지며 중앙 영역 및 상기 중앙 영역 둘레의 코너 영역들을 갖는 기판, 상기 기판의 상기 중앙 영역을 관통하는 복수 개의 관통 전극들, 상기 관통 전극과 전기적으로 연결되며 상기 제1 상면으로부터 제1 높이를 갖도록 구비되는 본딩 패드, 및 상기 기판의 코너 영역들 상에서 상기 제1 상면으로부터 상기 제1 높이보다 높은 제2 높이를 갖도록 각각 연장하는 복수 개의 더미 패드들을 구비하는 제1 반도체 칩, 및 서로 반대하는 제2 상면 및 제2 하면을 갖고, 상기 제2 하면에 구비되며 상기 본딩 패드들과 전기적으로 연결되는 도전성 범프들을 통해 상기 제1 반도체 칩 상에 배치되는 제2 반도체 칩을 포함한다.

Semiconductor package

A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

Hybrid bonding for semiconductor device assemblies

A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die; a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die; and a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die, the hybrid bonding interface including a gap free metal-metal bonding region between the first and the second bond pads and a gap free dielectric-dielectric bonding region between the first and the second dielectric regions, wherein the dielectric-dielectric bonding region includes a nitrogen gradient with a concentration that increases with proximity to the metal-metal bonding region.

Package structure and manufacturing method thereof

A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Semiconductor device structure with bonding pad and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a device region and a seal ring region surrounding the device region. The semiconductor device structure includes a seal ring structure over the seal ring region. The seal ring structure surrounds the device region. The semiconductor device structure includes a bonding film over the seal ring structure and the substrate. The semiconductor device structure includes a bonding pad embedded in the bonding film. The bonding pad overlaps the seal ring structure along an axis perpendicular to a first top surface of the substrate, and a second top surface of the bonding pad is substantially level with a third top surface of the bonding film.

半导体装置

目的在于提供能够确保可靠性，并且实现引线的窄间距化及大数量化的半导体装置。半导体装置包含半导体元件、管芯焊盘、封装材料、多个引线。管芯焊盘在表面搭载有半导体元件。封装材料将半导体元件覆盖而进行封装。多个引线各自的一端在封装材料的内部与半导体元件连接，各自的另一端被从封装材料的侧面引出。包含半导体元件、管芯焊盘和封装材料的封装件的下表面位于管芯焊盘的背面侧，具有凸状的翘曲形状。

Bonded semiconductor structure utilizing concave/convex profile design for bonding pads

A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Hybrid bonding of a thin semiconductor die

When locating a semiconductor die on a substrate, the die is picked up and carried with a die-holding surface of a bonding tool having a protrusion. The protrusion of the bonding tool is configured to be movable between a retracted position within the die-holding surface and an extended position protruding from the die-holding surface. When the protrusion is located in the extended position, the die is bent when the bonding tool is carrying the die. Thereafter, the bonding tool is moved to flatten the die against the substrate while the substrate urges the protrusion to retract from the extended position towards the retracted position.

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Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.

반도체 장치 및 반도체 장치의 제조 방법

실시 형태에 따르면, 반도체 장치가 제공된다. 반도체 장치는 절연층과, 전극과, 홈을 구비한다. 절연층은 기판 표면에 형성된다. 전극은 절연층에 매설되어 한쪽 단부면이 절연층으로부터 노출된다. 홈은 기판 표면의 전극 주위에 형성된다. 또한, 홈은 전극의 외측면을 한쪽 측면으로 하여, 절연층의 표면측이 개방된다. 절연층에 매설되는 전극은 한쪽 단부면이 절연층의 표면으로부터 돌출된다.

Semiconductor device and method of manufacturing the same

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

半导体器件及其制造方法

提供了一种半导体器件及其制造方法，该半导体器件包括接合在一起的第一半导体芯片和第二半导体芯片。第一半导体芯片包括第一基板、设置在第一基板上并且具有顶表面的第一绝缘层、嵌入在第一绝缘层中并且具有与第一绝缘层的顶表面基本齐平的顶表面的第一金属焊盘、以及设置在第一绝缘层和第一金属焊盘之间的第一阻挡件。第二半导体芯片以与第一半导体芯片相似的构造包括第二基板、第二绝缘层、第二金属焊盘和第二阻挡件。第一绝缘层的顶表面和第二绝缘层的底表面被接合以提供接合界面，第一金属焊盘和第二金属焊盘被连接，并且第一绝缘层的部分与第一金属焊盘的侧部区域接触。

Semiconductor device and method of manufacturing the same

A semiconductor device (500) is provided and includes first (100) and second (200) semiconductor chips bonded together. The first chip (100) includes a first substrate (120), a first insulating layer (131) disposed on the first substrate (120) and having a top surface, a first metal pad (155) embedded in the first insulating layer (131) and having a top surface substantially planar with the top surface of the first insulating layer (131), and a first barrier (152) disposed between the first insulating layer (131) and the first metal pad (155). The second chip (200) includes a second substrate (220), a second insulating layer (231), a second metal pad (255), and a second barrier (252) with a similar configuration to the first chip (100). The top surfaces of the first and second insulating layers (131, 231) are bonded to provide a bonding interface, the first and second metal pads (155, 255) are connected, and a portion of the first insulating layer (131) is in contact with a side region of the first metal pad (155).

Semiconductor device and method of manufacturing the same

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

반도체 패키지 및 반도체 패키지의 제조 방법

반도체 패키지는 제1 반도체 칩 및 상기 제1 반도체 칩 상에 적층되는 제2 반도체 칩을 포함한다. 상기 제1 반도체 칩은 제1 기판, 상기 제1 기판을 관통하는 복수 개의 관통 전극들, 상기 제1 기판의 전면 상에 구비되는 제1 배선층, 상기 제1 배선층 상에 구비되며 상기 관통 전극들과 전기적으로 연결되는 제1 본딩 패드들, 상기 제1 배선층 상에 구비되는 제1 테스트 패드 및 상기 제1 배선층 상에 구비되며 상기 제1 본딩 패드들 및 상기 제1 테스트 패드의 적어도 일부분들을 노출시키는 제1 패시베이션 막을 포함한다. 상기 제2 반도체 칩은 제2 기판, 상기 제2 기판의 전면 상에 구비되는 제2 배선층, 상기 제2 배선층 상에 구비되는 제3 본딩 패드들, 상기 제2 배선층 상에 구비되는 제2 테스트 패드 및 상기 제2 배선층 상에 형성되며 상기 제3 본딩 패드들 및 상기 제2 테스트 패드의 적어도 일부분들을 노출시키는 제2 패시베이션 막을 포함한다. 상기 제1 본딩 패드들과 상기 제3 본딩 패드들은 서로 직접 접합된다. 상기 제1 패시베이션 막과 상기 제2 패시베이션 막을 서로 직접 접합된다.

半导体封装器件、其接合结构及其制造方法

提供了一种半导体封装器件的接合结构、半导体封装器件和用于制造半导体封装器件的方法。所述接合结构物理连接和电连接在半导体芯片与封装基底之间和/或封装基底与板之间，所述接合结构包括：焊料；主焊盘，面对焊料；以及导电支撑结构，连接在焊料与主焊盘之间，导电支撑结构包括：子焊盘，接合到焊料，子焊盘与主焊盘间隔开并且面对主焊盘；以及至少一个腿部，从子焊盘延伸到主焊盘。

半导体器件及其制造方法

提供了一种包括下结构和上结构的半导体器件。下结构包括第一衬底、第一衬底上的第一焊盘、以及围绕第一焊盘的第一绝缘层。上结构包括第二衬底、第二衬底上的第二焊盘、以及围绕第二焊盘的第二绝缘层。上结构与下结构彼此接触。第一焊盘与第二焊盘彼此接触。第一绝缘层与第二绝缘层彼此接触。第一绝缘层包括与第一焊盘相邻的第一凹陷，第二绝缘层包括与第二焊盘相邻并与第一凹陷重叠的第二凹陷，并且空腔由第一凹陷和第二凹陷限定，且构成第一焊盘和第二焊盘的金属性材料的颗粒在该空腔中。

半導體裝置

本發明提供一種半導體裝置，包含下部結構及上部結構。下部結構包含：第一基底；第一接墊；位於第一基底上；以及第一絕緣層，包圍第一接墊。上部結構包含：第二基底；第二接墊，位於第二基底上；以及第二絕緣層，包圍第二接墊。上部結構與下部結構彼此接觸。第一接墊與第二接墊彼此接觸。第一絕緣層與第二絕緣層彼此接觸。第一絕緣層包含鄰近於第一接墊的第一凹部，第二絕緣層包含鄰近於第二接墊且與第一凹部重疊的第二凹部，且空腔由第一凹部及第二凹部界定，且構成第一接墊及第二接墊的金屬材料的粒子位於空腔中。

半导体器件及其制造方法

一种半导体器件可以包括：下结构，包括第一衬底、第一衬底上的第一焊盘、以及包围第一焊盘的第一绝缘层；以及上结构，包括第二衬底、第二衬底上的第二焊盘、以及包围第二焊盘的第二绝缘层。第一焊盘和第二焊盘中的每一个可以包括第一部分和第一部分上的第二部分。第二部分可以包括与第一部分相同的金属材料。第一焊盘的第二部分可以与第二焊盘的第二部分接触，并且第一绝缘层可以与第二绝缘层接触。

Semiconductor structure for wafer level bonding and bonded semiconductor structure

A semiconductor structure for wafer level bonding includes an interconnecting layer on a substrate, a bonding dielectric layer on the interconnecting layer, and a bonding pad in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface and physically contacting a dielectric portion of the interconnecting layer, and a sidewall between the top surface and the bottom surface. A bottom angle between the sidewall and the bottom surface is smaller than 90 degrees, and the bonding pad is not electrically connected to the interconnecting layer.

Fine-pitch joining pad structure

A semiconductor device includes two integrated circuit (IC) chips. The first IC chip includes substrate, a spacer connected to the substrate and including holes, wherein at least one of the holes has a first shape, and solder bumps positioned in the holes, respectively. The second IC chip includes a substrate, electrode pads extending from the substrate and connected to the solder bumps, respectively. At least one of the electrode pads that corresponds to the at least one of the solder bumps has a second shape, and the first shape and the second shape are non-coextensive such that there is at least one gap between the first shape and the second shape when projected on each other.

반도체 소자 및 그 형성 방법

유전체 위에 UBM(under-bump metallurgy)을 갖는 반도체 소자가 제공된다. UBM은 UBM의 중앙 포인트로부터 오프셋되도록 구성된 트렌치를 갖는다. 트렌치의 중앙과 UBM의 에지 간의 거리는 트렌치의 중앙과 UBM의 대향 에지 간의 거리보다 더 크다. 프로브 핀은 UBM에 접촉하고 측정 데이터를 수집하도록 구성된다.