Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

Procédé de fabrication de plots de connexion électrique sur une face d'une plaque, comprenant : la réalisation de zones conductrices de l'électricité (6a, 6b) et de branches de connexion électrique (7) reliant ces zones; le dépôt d'une couche (8) en une matière de masque; la réalisation, dans cette couche de masque, d'ouvertures (9a, 9b) qui s'étendent au-dessus desdites zones conductrices et dont au moins certaines (9a) s'étendent au moins en partie au-delà des bords périphériques des zones conductrices sous-jacentes (6a) ; la réalisation de blocs (12a, 12b) en une matière de soudure dans lesdites ouvertures par dépôt électrolytique dans un bain; la suppression de la matière de masque; la coupure des branches de connexion (7) ; et le passage ou la mise dans un four de façon à conformer, sur les zones conductrices, lesdits blocs en des plots de connexion électrique (3a, 3b) substantiellement bombés.

INTEGRATED CIRCUIT SYSTEM WITH CARRIER CONSTRUCTION CONFIGURATION AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

INTEGRATED CIRCUIT SYSTEM WITH CARRIER CONSTRUCTION CONFIGURATION AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure. 1. A method of manufacture of a detachable carrier utilized in manufacturing an integrated circuit system comprising:providing a carrier frame portion;forming a release layer on a surface of the carrier frame portion;forming a temporary shaping structure on the release layer, the temporary shaping structure having a void exposing the release layer;applying a conductive material in the void of the temporary shaping structure and contacting the release layer; andforming a terminal structure directly on the release layer by solidifying the conductive material and removing the temporary shaping structure.2. The method as claimed in further comprising forming a terminal pod by applying a conductive connector to the end of the terminal structure opposite the release layer.3. The method as claimed in wherein removing the temporary shaping structure includes volatilizing the temporary shaping structure by a heating process.4. The method as claimed in wherein forming the terminal structure includes forming the terminal structure by a sintering process.5. The method as claimed in wherein forming the terminal structure includes forming the terminal structure having a geometric shape wherein the portion of the terminal structure attached to the release layer is smaller than the portion of the terminal structure facing away from the carrier frame portion.6. The method as claimed in wherein forming the temporary shaping structure includes forming the voids as a complementary to the geometric shape for the terminal ...

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

SOLDER CONTACTS AND METHOD FOR FORMING THE SAME

PROBLEM TO BE SOLVED: To provide a method for forming improved solder contacts into an integrated circuit. SOLUTION: A structured layer 200 includes an aperture section 3000 to the integrated circuit substrate 100 and a first region 1011 and a second region 1012 on the substrate. The first and the second regions are at least partially overlapped on the aperture section. The integrated circuit further includes a first material 100 inside zones of the first region and a second material 500 inside zones of the second region. The first material prevents soaking caused by a solder material, and the second material gives soaking caused by the solder material. COPYRIGHT: (C)2009,JPO&INPIT ...

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

ENGINEERED POLYMER-BASED ELECTRONIC MATERIALS

METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE

A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the ...

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Solder contact points prodn. on semiconductor contact layer - using structurised oxide film of e.g. silica or alumina as solder stop in simple, quick and economical technique

Application of solder contact points on a contact layer of semiconductor chips produced on a wafer involves providing the entire contact layer with a solder contact point structure. The structure of the contact points (1) is defined by an oxide layer (3), which is applied to the contact layer (3) and etched; and the solder contact points (1) are formed by dip soldering. The structurised oxide film is used as solder stop and pref. consists of Al2O3 or SiO2. A Sn-Pb-Ag alloy solder is used. USE/ADVANTAGE - For applying contact points to a contact layer of laser diode chips (claimed). It is simple, quick and economical.

The stacked interconnection layer is laminated to the liquid crystal polymer solder mask of the electronic device of the method and related apparatus

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Engineered polymer-based electronic materials

一種用於電子組裝製程的組成，組成包含分散於有機介質的填料，其中：有機介質包含聚合物；填料包含一或更多的石墨烯、官能化石墨烯、氧化石墨烯、多面體寡聚半矽氧烷、石墨、二維材料、氧化鋁、氧化鋅、氮化鋁、氮化硼、銀、奈米纖維、碳纖維、鑽石、奈米碳管、二氧化矽和金屬塗覆粒子，及組成按組成總重量計包含0.001-40重量%的填料。

Methods for Metal Bump Die Assembly

Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

Method of manufacturing micro light-emitting element array, transfer carrier, and micro light-emitting element array

A method of manufacturing micro light-emitting element array is disclosed. A transfer substrate and at least one metal bonding pad are provided, and the metal bonding pad is disposed on the transfer substrate. A growth substrate and a plurality of micro light-emitting elements are provided. The micro light-emitting elements are disposed on the growth substrate, and a surface of each of the micro light-emitting elements away from the growth substrate having at least one electrode. The metal bonding pad is molten at a heating temperature, and the electrode is connected to the metal bonding pad. Then, the growth substrate is removed.

Integrated circuit system with carrier construction configuration and method of manufacture thereof

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages

Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.

Manufacturing method of micro light-emitting element array, transfer carrier, and micro light-emitting element array

A manufacturing method of micro light-emitting element array includes the following steps. Provide a transfer substrate and metal pads disposed on the transfer substrate. Provide a growth substrate and micro light-emitting elements disposed on the growth substrate in an array. Heat the metal pad to a heating temperature and melt the metal pad to connect the metal pad and electrodes of the micro light emitting elements. Remove the growth substrate. A transfer carrier includes the transfer substrate and the plurality of metal pads which are disposed on the transfer substrate. The plurality of metal pads are separated by isolation space. A micro light-emitting element array includes the above mentioned transfer carrier and the plurality of micro light-emitting elements. Each of the micro light-emitting elements has an electrode. The electrodes of the micro light-emitting elements are connected and fixed to the transfer substrate by the metal pads.

METHOD FOR PRODUCING JOINED BODY, AND JOINING MATERIAL

... [in Formula (I), M1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M2 represents a non-volatile content in the joining material.] ...

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

Semiconductor element and forming method

Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

在一些實施方式中，一種半導體裝置之封裝基板包含一基板核心與置於基板核心上方之一材料層。封裝基板包含置於基板核心與材料層中之鍃孔開口。

METHOD FOR PRODUCING JOINED BODY, AND JOINING MATERIAL

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

A microelectronic assembly, comprising: a substrate (112); and a microelectronic component (130-1) coupled to the substrate by a solder interconnect, wherein the solder interconnect includes a first portion (106A) and a second portion (106B), the first portion is between the second portion and the substrate, and the first portion (106A) has a ground top surface.

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

A microelectronic assembly, comprising: a substrate (112); and a microelectronic component (130-1) coupled to the substrate by a solder interconnect, wherein the solder interconnect includes a first portion (106A) and a second portion (106B), the first portion is between the second portion and the substrate, and the first portion (106A) has a ground top surface.

Engineered polymer-based electronic materials

Doping minor elements into metal bumps

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

一种用于制造电子装置的方法，其包括在刚性晶片衬底上形成互连层堆叠，所述互连层堆叠具有多个经图案化的电导体层、在邻近的经图案化的电导体层之间的电介质层，和在最上的经图案化的电导体层上的至少一个焊料衬垫。形成LCP焊料掩模，所述LCP焊料掩模在其中具有可与所述至少一个焊料衬垫对准的至少一个孔隙。使所述LCP焊料掩模与所互连层堆叠对准且层叠在一起。将焊料定位于所述至少一个孔隙中。使用所述焊料将至少一个电路组件附接到所述至少一个焊料衬垫。

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Elektronische Vorrichtung

Eine elektronische Vorrichtung (100) umfasst eine Trägerplatine (1) mit einer oberen Oberfläche (11), einen elektronischen Chip (2), der auf der oberen Oberfläche der Trägerplatine befestigt ist, wobei der elektronische Chip eine Befestigungsseite (21), die zur oberen Oberfläche der Trägerplatine zeigt, eine Oberseite (22), die weg von der oberen Oberseite der Trägerplatine zeigt, und Seitenwände (23), die die Befestigungsseite mit der Oberseite verbinden, aufweist, wobei der elektronische Chip auf der Befestigungsseite gleich oder weniger als 5 Stud-Bumps (24) pro Quadratmillimeter einer Grundfläche der Befestigungsseite aufweist, und eine laminierte Polymerabdeckung (4), die zumindest teilweise die Oberseite des elektronischen Chips abdeckt und sich auf die obere Oberfläche der Trägerplatine erstreckt. An electronic device (100) comprises a support board (1) having an upper surface (11), an electronic chip (2) mounted on the upper surface of the support board, the electronic chip having a mounting side (21) facing the upper surface Surface of the carrier board, an upper side (22) facing away from the upper top of the carrier board, and side walls (23) connecting the mounting side to the top, wherein the electronic chip on the mounting side equal to or less than 5 Stud Bumps (24) per square millimeter of attachment surface footprint, and a laminated polymer cover (4) at least partially covering the top of the electronic chip and extending onto the top surface of the support board.

Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Transient interface gradient bonding for metal bonds

SELECTIVE SOLDER DEPOSITION BY SELF-ASSEMBLY OF NANO-SIZED SOLDER PARTICLES, AND METHODS OF ASSEMBLING SOLDERED PACKAGES

A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.

TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES

本发明公开了一种用于实现超薄晶片级封装（WLP）的封装体的低成本、低轮廓的焊料凸点工艺。具体而言，本文说明了用于浸焊工艺的技术，其提供了低轮廓、低成本的焊料凸点形成工艺，可以实施它以促进封装厚度缩放（例如减小总体封装厚度）。例如，本文公开的浸焊工艺可以实现超薄晶片级封装（WLP）、超薄晶片级方形扁平无引脚（WQFN）封装等。

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER

A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads.

DOPING MINOR ELEMENTS INTO METAL BUMPS, CAPABLE OF ACCURATELY CONTROLLING THE THICKNESS OF SOME ELEMENT INCLUDING LAYER

PURPOSE: Doping minor elements into metal bumps are provided to improve manufacturing costs and the property of a metal pump by adding some elements of a plurality of types. CONSTITUTION: In doping minor elements into metal bumps, a wafer including a substrate(10) is provided. A semiconductor device(14) is formed in the surface of the substrate. An interconnect structure(12) is electrically combined with the semiconductor device. The interconnect structure comprises an inter-layer dielectric and an inter-metal dielectric. A metal pad(28) is formed on the interconnect structure. COPYRIGHT KIPO 2012 ...

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Technique for wafer-level processing of QFN packages

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

DOPING MINOR ELEMENTS INTO METAL BUMPS

기판 제조 방법은 기판을 마련하는 단계와, 기판 위에 솔더 범프를 형성하는 단계를 포함한다. 소수 엘리먼트가 솔더 범프의 상면에 인접한 영역에 도입된다. 다음에 소수 엘리먼트를 솔더 범프로 도출하기 위해 솔더 범프에 대한 리플로우 공정이 수행된다.

SOLDER CONTACTS AND METHODS OF FORMING SAME

An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

Electronic Device

An electronic device is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface of the carrier board, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, and wherein a laminated polymer hood at least partly covers the top side of the electronic chip and extends onto the upper surface of the carrier board.

System for processing semiconductor devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

Solder contacts and methods of forming same

本发明涉及一种焊接触点及其形成方法。相应地还涉及一种集成电路，包括衬底和衬底上的结构层。结构层包括到衬底的开口，在衬底上具有第一范围和第二范围，其中，第一范围和第二范围至少部分地与开口重叠。集成电路还包括第一范围区域内的第一材料和第二范围区域内的第二材料。第一材料通过焊接材料阻止潮湿，以及第二材料通过焊接材料提供潮湿。

Electronic Device with Stud Bumps

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

Techniques for wafer-level processing of QFN packages

Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Transient interface gradient bonding for metal bonds

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

Verfahren zum Aufbringen von Lötkontaktstellen durch Tauchlöten auf eine Kontaktschicht eines Halbleiterchips

Lötkontakte und Verfahren zur Herstellung solcher Lötkontakte

Die vorliegende Erfindung betrifft eine integrierte Schaltung mit einem Substrat und einer strukturierten Schicht auf dem Substrat. Die strukturierte erstes Feld und ein zweites Feld auf dem Substrat, wobei das erste Feld und das zweite Feld sich zumindest teilweise mit der Öffnung überschneiden. Die integrierte Schaltung umfasst weiterhin einen ersten Werkstoff im Bereich des ersten Feldes und einen zweiten Werkstoff im Bereich des zweiten Feldes. Der erste Werkstoff verhindert ein Benetzen mit Lötwerkstoff und der zweite Werkstoff ermöglicht ein Benetzen mit Lötwerkstoff.

Techniques for wafer-level processing of QFN packages

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Bonded assembly and display device including the same

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK LAMINATED TO AN INTERCONNECT LAYER STACK AND RELATED DEVICES

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

Method for fabricating electrical bonding pads on a wafer

A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads.

Doping minor elements into metal bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Electronic device with stud bumps

An electronic device is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface of the carrier board, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, and wherein a laminated polymer hood at least partly covers the top side of the electronic chip and extends onto the upper surface of the carrier board.

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

QFN package for wafer processing technology

Engineered polymer-based electronic materials

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Solder contacts and methods of forming same

LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES

Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.

ENGINEERED POLYMER-BASED ELECTRONIC MATERIALS

Semiconductor package

A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

Tool and system for processing semiconductor device and method for processing semiconductor device

SEMICONDUCTIVE CHIP ATTACHMENT MEANS

A method for mounting a semiconductive chip on a substrate, using integral leads, and a method for making the leads. The techniques described are particularly useful in making integral leads on a semiconductive chip which can be flipped onto a complementary conductor network. The leads are preferably formed on the chip while the chip is still part of a slice. The leads are simultaneously formed on the slice by progressive solidification from a melt material, and the slice subsequently diced to form the individual leaded chips.

TRANSFER CARRIER FOR MICRO LIGHT-EMITTING ELEMENT

A transfer carrier is adapted to be connected to an electrode of a micro light-emitting element and transfer the micro light-emitting element. A transfer carrier includes a transfer substrate and a plurality of metal bonding pads. The metal bonding pads are disposed on the transfer substrate, and every two metal bonding pads that are adjacent to each other are spaced apart from each other through a gap.

Transient interface gradient bonding for metal bonds

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu—Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Semiconductor package

A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the ...

Doping minor elements into metal bumps

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

TRANSIENT INTERFACE GRADIENT BONDING FOR METAL BONDS

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

Solder contacts and methods of forming same

Package substrate

Disclosed is a package substrate, including a substrate body having a plurality of electrical contact pads, an insulating protection layer formed on the substrate body while exposing the electrical contact pads therefrom, and a plurality of conductive pillars disposed on the electrical contact pads, wherein the bottom width of the conductive pillars is larger than the top width thereof, thereby forming a cone shape structure without wings to reduce the distance between contact points and satisfying the demands for fine-pitch and multi-points.

Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles

A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.

MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Engineered polymer-based electronic materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

Techniques for wafer-level processing of QFN packages

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Methods for metal bump die assembly

Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Transfer carrier for micro light-emitting element

A transfer carrier is adapted to be connected to an electrode of a micro light-emitting element and transfer the micro light-emitting element. A transfer carrier includes a transfer substrate and a plurality of metal bonding pads. The metal bonding pads are disposed on the transfer substrate, and every two metal bonding pads that are adjacent to each other are spaced apart from each other through a gap.

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

MANUFACTURING METHOD OF MICRO LIGHT-EMITTING ELEMENT ARRAY, TRANSFER CARRIER, AND MICRO LIGHT-EMITTING ELEMENT ARRAY

MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

Solder contacts and methods of forming same

An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

Through-silicon via pillars for connecting dice and methods of assembling same

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

Bonded assembly and display device including the same

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Bonded assembly and display device comprsing the same

본 발명의 일 실시예에 따른 접합 조립체는 서로 접합되어 있는 제1 전자 부품 및 제2 전자 부품을 포함한다. 제1 전자 부품은 제1 기재, 그리고 압착 영역 내에 위치하며 제1 기재의 표면으로부터 제1 높이를 가지는 복수의 제1 전극을 포함한다. 제2 전자 부품은 제2 기재, 그리고 제2 기재의 표면으로부터 제2 높이를 가지는 복수의 제2 전극을 포함하며, 각각의 제2 전극이 대응하는 제1 전극과 마주하게 중첩하도록 제1 전자 부품 위에 위치한다. 접합 조립체는 중첩하는 제1 전극과 제2 전극 사이에 위치하며 제1 전극과 제2 전극을 접합시키는 도전 접합 부재, 그리고 제1 기재와 제2 기재 사이에서 압착 영역과 중첩하게 위치하며, 제1 높이와 제2 높이의 합보다 큰 두께를 가지는 적어도 하나의 간격재를 포함한다.

Bonded body manufacturing method and bonding material

Packaged semiconductor device and packaging method thereof

本发明提供了一种用于半导体器件的封装件衬底，该封装件衬底包括衬底核心和设置在衬底核心上方的材料层。该封装件衬底包括设置在衬底核心和材料层中的鱼眼孔径。

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Multilayer package substrate with stress buffer

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

금속 본드를 위한 임시적 인터페이스 그래디언트 본딩

전기 디바이스를 위한 금속 대 금속 본딩을 수행하는 방법과 장치 및 이에 의해 생산된 전기 디바이스. 예를 들어 제약없이, 본 개시의 다양한 양태는 구리 필러 상에 얇은 금속층을 증착하고, 그리고 나서 다른 구리 구성과 구리 필러를 합착하는 것을 포함한다. 얇은 금속층의 원자들은 예를 들어, 구리와 치환 고용체 또는 금속간 화합물을 형성할 수 있다. 농도 기울기는 얇은 금속층에 의해 도입되며, Cu-Cu 인터페이스에서 확산이 즉시 시작된다. 얇은 금속 필름 및 구리는 예를 들어, 인터페이스가 사라지거나 거의 사라질 때까지 확산할 수 있다.

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a tool for processing semiconductor devices includes a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support.

Through-silicon via pillars for connecting dice and methods of assembling same

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

半導体装置および半導体装置の製造方法

【課題】半導体チップ間からのアンダーフィル樹脂の流出が抑制される半導体装置を提供する。 【解決手段】第１の面１２と前記第１の面１２に配置された複数の第１の電極１４とを有する第１の半導体チップ４と、前記第１の面１２に対向する第２の面１６と前記第２の面１６に少なくとも一端が配置された複数の第２の電極１８と各前記第２の電極１８の前記一端を電極ごとに囲む複数の第１の突出部２０とを有する第２の半導体チップ６と、前記複数の第１の電極１４に含まれる第３の電極をそれぞれ前記複数の第２の電極１８のうち前記第３の電極に対向する電極の前記一端に接合する複数の導電性の接合材料８と、それぞれが各前記第１の突出部２０の内側に配置され、前記接合材料８を材料ごとに覆う複数の第１のアンダーフィル樹脂１０とを有すること。 【選択図】図１

접합체의 제조 방법 및 접합재

표면에 금속 필러가 마련된 제1 부재와, 표면에 전극 패드가 마련되고, 금속 필러와 전극 패드가 서로 대향하도록 배치된 제2 부재와, 금속 필러와 전극 패드 사이에 마련된, 금속 입자 및 유기 화합물을 함유하는 접합재를 구비하는 적층체를 준비하는 제1 공정과, 적층체를 가열하여, 소정의 소결 온도로 접합재를 소결시키는 제2 공정을 포함하고, 접합재는 하기 식 (I)의 조건을 만족하는 것인 접합체의 제조 방법. (M 1 -M 2 )/M 1 ×100≥1.0 (I) [식 (I) 중, M 1 은, 제2 공정에 있어서, 접합재의 온도가 소결 온도에 도달하였을 때의 접합재의 질량을 나타내고, M 2 는 접합재 중의 불휘발분량을 나타낸다.]

用于实现超薄晶片级封装（wlp）的封装体的低成本、低轮廓的焊料凸点工艺

本发明公开了一种用于实现超薄晶片级封装（WLP）的封装体的低成本、低轮廓的焊料凸点工艺。具体而言，本文说明了用于浸焊工艺的技术，其提供了低轮廓、低成本的焊料凸点形成工艺，可以实施它以促进封装厚度缩放（例如减小总体封装厚度）。例如，本文公开的浸焊工艺可以实现超薄晶片级封装（WLP）、超薄晶片级方形扁平无引脚（WQFN）封装等。

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

半导体元件及其形成方法

本发明一实施例提供一种半导体元件及其形成方法，其中半导体元件的形成方法包括：提供一基底；于该基底上形成一焊料凸块；将一少量元素导入至一区域中，该区域邻接该焊料凸块的一顶表面；以及对该焊料凸块进行一回焊工艺以驱使该少量元素进入该焊料凸块之中。采用本发明的实施例，在公知技术中不适合加进金属凸块中的许多类型的少量元素现可被添加。因此，金属凸块的性质可获显著的提升。

금속 본드를 위한 임시적 인터페이스 그래디언트 본딩

전기 디바이스를 위한 금속 대 금속 본딩을 수행하는 방법과 장치 및 이에 의해 생산된 전기 디바이스. 예를 들어 제약없이, 본 개시의 다양한 양태는 구리 필러 상에 얇은 금속층을 증착하고, 그리고 나서 다른 구리 구성과 구리 필러를 합착하는 것을 포함한다. 얇은 금속층의 원자들은 예를 들어, 구리와 치환 고용체 또는 금속간 화합물을 형성할 수 있다. 농도 기울기는 얇은 금속층에 의해 도입되며, Cu-Cu 인터페이스에서 확산이 즉시 시작된다. 얇은 금속 필름 및 구리는 예를 들어, 인터페이스가 사라지거나 거의 사라질 때까지 확산할 수 있다.

Package substrate having integrated passive device(s) between leads

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

Multilayer package substrate with stress buffer

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

금속 범프로의 소수 엘리먼트들의 도핑

기판 제조 방법은 기판을 마련하는 단계와, 기판 위에 솔더 범프를 형성하는 단계를 포함한다. 소수 엘리먼트가 솔더 범프의 상면에 인접한 영역에 도입된다. 다음에 소수 엘리먼트를 솔더 범프로 도출하기 위해 솔더 범프에 대한 리플로우 공정이 수행된다.

包括桥的微电子结构

本文公开了包括桥的微电子结构以及相关的组件和方法。在一些实施例中，微电子结构可以包括衬底和桥。

一种Cu-Sn基金属间化合物焊点及其制备方法

本发明提供一种Cu‑Sn基金属间化合物焊点及其制备方法，涉及3D封装芯片堆叠互连制造和高功率器件封装制造。选用Cu‑xNi合金为第一金属基体，纯Cu或Cu‑xNi合金为第二金属基体，纯Sn或Sn基钎料作为中间钎料层，构成Cu‑xNi/钎料/Cu或Cu‑xNi/钎料/Cu‑xNi结构组合体，随后将上述组合体在一定温度条件下进行钎焊回流反应，使钎料全部反应完并转化为以(Cu,Ni) 6 Sn 5 为主体的金属间化合物焊点，(Cu,Ni) 6 Sn 5 晶粒细小，晶粒取向杂乱、随机，且热稳定性良好。本发明具有成本低廉、工艺流程简单、与现有技术设备兼容性好，显著缩短键合时间等优点。

Microelectronic structures including bridges

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

接合体的制造方法及接合材料

本发明提供一种接合体的制造方法，其具备以下工序：第一工序，其中准备具备第一构件、第二构件和接合材料的层叠体，所述第一构件在表面设有金属柱状物，所述第二构件在表面设有电极垫，且按照金属柱状物与电极垫相互间相向的方式配置，所述接合材料设置在金属柱状物与电极垫之间，且含有金属粒子及有机化合物；第二工序，其中加热层叠体，在规定的烧结温度下使接合材料烧结，其中，接合材料满足下述式(I)的条件，(M 1 ‑M 2 )/M 1 ×100≥1.0 (I)。式(I)中，M 1 表示在第二工序中、接合材料的温度到达烧结温度时的接合材料的质量，M 2 表示接合材料中的不挥发成分量。

封装的半导体器件及其封装方法

本发明提供了一种用于半导体器件的封装件衬底，该封装件衬底包括衬底核心和设置在衬底核心上方的材料层。该封装件衬底包括设置在衬底核心和材料层中的鱼眼孔径。

处理半导体器件的工具和系统以及处理半导体器件的方法

本发明公开了用于处理半导体器件的工具和系统以及处理半导体器件的方法。在一些实施例中，用于处理半导体器件的工具包括设置在第一材料上方的第二材料以及设置在第一材料和第二材料内的多个孔。第二材料包括比第一材料更高的反射率。每个孔均被用来将封装部件保持在支撑件上方。

电子设备

本发明涉及一种电子设备（100），其包括具有上表面（11）的载体板（1）；安装在载体板的上表面上的电子芯片（2），电子芯片具有面向载体板的上表面的安装侧（21）、背离载体板的上表面的顶侧（22）、以及将安装侧连接到顶侧的侧壁（23），其中电子芯片在安装侧上具有在每平方毫米安装侧的基部区域上等于或小于5个的柱形凸起（24）；以及叠层式聚合物罩（4），其至少部分地覆盖电子芯片的顶侧并延伸到载体板的上表面上。