Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

FORMATION OF SOLDER AND COPPER INTERCONNECT STRUCTURES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed. 1providing an integrated circuit (IC) substrate; anddepositing a solderable ink on the IC substrate using an ink deposition process.. A method comprising: This application is a continuation of, and claims priority to, U.S. patent application Ser. No. 14/581,825, entitled “FORMATION OF SOLDER AND COPPER INTERCONNECT STRUCTURES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS,” filed on Dec. 23, 2014. The Specification of application Ser. No. 14/581,825 is hereby fully incorporated by reference.Embodiments of the present disclosure generally relate to the field of materials for integrated circuit (IC) assemblies, and more particularly, to formation of solder and copper interconnect structures and associated techniques and configurations.Current techniques to form solder bumps on an integrated circuit (IC) substrate such as a die, wafer, or package substrate may include, for example, plating, paste printing and/or ball placement techniques. Such solder bumping techniques are expensive and complex, particularly for solder bumps having different geometries on a same IC substrate.Current techniques to form conductive traces such as copper traces of circuits and/or devices may use multiple processes and tools that utilize subtractive processes, which may waste material, resulting in high costs, particularly for low volume production. ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

When a semiconductor element is bonded to a base plate electrode, a cushioning is used for protecting the surface of the semiconductor element. A protrusion having an outwardly cutting shape is formed around an area on the base plate electrode for bonding the semiconductor element to disperse and reduce shear force acting on the cushioning during the bonding, so that no cushioning adheres to the surface of the semiconductor element after bonding. 18-. (canceled)9. A semiconductor device comprising:a semiconductor element; andan insulating base plate including a base plate electrode on a surface of the insulating base plate,wherein the base plate electrode includes a wedge-shape protrusion along the periphery of a bonding area on the base plate electrode for mounting the semiconductor element, and an inner face of the protrusion is vertical and an outer face is inclined outwardly, to bond inside the protrusion the semiconductor element to the base plate electrode at a bottom face and side faces of the semiconductor element with a sinterable metal bond.10. The semiconductor device of claim 9 , wherein the protrusion is formed along the periphery of the bonding area to be coated with the sinterable metal bond.11. The semiconductor device of claim 9 , wherein the semiconductor element is a wide gap semiconductor made up of any one of silicon carbide claim 9 , gallium-nitride-based material claim 9 , or diamond.12. The semiconductor device of claim 9 , wherein the semiconductor element has arc-shape side faces or beveled side faces outside a constant thickness portion of the semiconductor element.13. A method of manufacturing a semiconductor device that is manufactured by implementing a semiconductor element on an insulating base plate by bonding the semiconductor element to the insulating base plate with a sinterable metal bond claim 9 , the method of manufacturing a semiconductor device comprising:coating with the sinterable metal bond an area of a base plate electrode ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor. 1. A semiconductor device , comprising:a substrate including a first surface and a second surface opposite to the first surface;a package over the substrate;a plurality of first conductors over the substrate;a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; anda passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.2. The semiconductor device of claim 1 , wherein a volume of a second conductor of the plurality of second conductors is substantially ...

Method of manufacturing electronic component module and electronic component module

A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

FORMING OF BUMP STRUCTURE

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material. 1. A method of fabricating a bump structure , the method comprising:preparing a substrate including a set of pads formed on a surface thereof, the pads comprising first conductive material;coating a metallic adhesion layer on each of the pads; andforming a bump on each of the pads by sintering conductive particles using a mold layer, the conductive particles comprising second conductive material different from the first conductive material.2. The method of claim 1 , wherein the mold layer has a set of openings each aligned with one of the pads and forming the bump on each of the pads comprises:disposing the mold layer on the substrate;filling conductive particles into the openings of the mold layer, the conductive particles filled in the openings of the mold layer being sintered to give a bump base on each of the pads; andfilling solder material into remaining space in each of the openings of the mold layer above the bump base to form a solder cap on each bump base.3. The method of claim 1 , wherein the first conductive material comprises Al and the second conductive material comprises Cu.4. The method of claim 2 , wherein the conductive particles are provided in a form of a paste and the bump base formed on each of the pads has a shape of a cup conforming to a contour of the opening of the mold layer and a bottom bonded to the pad by the metallic adhesion layer.5. The method of claim 2 , wherein the method further comprises:applying a resist layer over the surface of the substrate;patterning the resist layer to fabricate the ...

ELECTRICALLY CONDUCTIVE PILLAR, BONDING STRUCTURE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRICALLY CONDUCTIVE PILLAR

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar is composed of a sintered body of metal micro-particles disposed on a base member . The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface of the sintered body has a concave shape recessed on the base member side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu. 1. An electrically conductive pillar composed of a sintered body of metal micro-particles disposed on a base member ,wherein an average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method, andan upper surface of the sintered body has a concave shape recessed on a base member side.2. The electrically conductive pillar according to claim 1 , wherein the metal micro-particles are made of one or more metals selected from Ag and Cu.3. A bonding structure disposed between a base member and a member to be bonded claim 1 , the member to be bonded being disposed opposite to the base member claim 1 , the bonding structure comprising:an electrically conductive pillar composed of a sintered body of metal micro-particles disposed on the base member, an average particle size of the metal micro-particles being less than 1 μm as measured using a small-angle X-ray scattering method, an upper surface of the sintered body having a concave shape recessed on a base member side; anda bonding layer provided along the concave shape of the electrically conductive pillar.4. The bonding structure according to claim 3 , wherein the electrically conductive pillar has a plurality of groove sections that extend from the upper surface toward the base member and has anchoring sections made ...

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

CONDUCTIVE PASTE, ELECTRODE CONNECTION STRUCTURE, AND ELECTRODE CONNECTION STRUCTURE PRODUCTION METHOD

Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste () contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 μm or more and 0.1 μm or less and a representative length of 5 μm or more and 10 μm or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less. 1. A conductive paste usable for electrical connection between a substrate and an electronic component mounted on the substrate ,the conductive paste comprising a conductive powder and an alcoholic liquid component, the conductive paste containing no adhesives,wherein the conductive powder contains conductive particles having a thickness of 0.05 μm or more and 0.1 μm or less and a representative length of 5 μm or more and 10 μm or less, the representative length being a maximum diameter in a plane perpendicular to a direction of the thickness, anda weight percentage of the alcoholic liquid component in the conductive paste is 8% or more and 20% or less.2. An electrode connection structure claim 1 , wherein the conductive paste according to is used for electrical connection. portions that connect an electrode pad on the substrate and an electrode pad on the electronic component to each other claim 1 , andthe electrical connection portions obtained by curing the conductive paste that connects the electrode pad on the substrate and the electrode pad on the electronic component to each other have sections having substantially the same shape, the sections being taken in a direction perpendicular to a direction in which the electrode pad on the substrate and the electronic component are connected to each other, and have a variation in sectional area of 20% or less.3. A method for ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:filling conductive paste in an opening of a layer formed over an electrode pad;sintering the conductive paste in the opening to cause shrinkage of the conductive paste to form a conductive layer having a cone-shaped surface formed therein, the conductive layer covering a side wall of the opening and a surface of the electrode pad in the opening; andfilling solder in the cone-shaped surface on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.6. The method according to claim 1 , wherein a thickness of a central portion of a cross-section of the conductive layer is in a range of ⅕ to ⅔ of a depth of the opening.7. The method according to claim 1 , further comprising a step of etching a surface of the ...

System and Method for Extreme Performance Die Attach

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms. 1. A method for fabricating semiconductor die with die-attach preforms , comprising:applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material;curing the one or more die-attach preforms;performing one or more planarization processes on the one or more die-attach preforms;coupling a first surface of a semiconductor die to a handling tool; andbonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.2. The method of claim 1 , wherein the one or more die-attach preforms comprise one or more sintered silver preforms.3. The method of claim 1 , wherein bonding the second surface of the semiconductor die to at least one die-attach preform comprises:applying heat to the at least one die-attach preform with one or more heating elements disposed within the handling tool.4. The method of claim 1 , further comprising:coupling the semiconductor die to a product substrate by bonding the die-attach preform to the product substrate.5. The method of claim 4 , wherein coupling the semiconductor die to a product substrate by bonding the die-attach preform to the product substrate comprises:applying heat to the at least one die-attach preform bonded to the ...

FORMATION OF SOLDER AND COPPER INTERCONNECT STRUCTURES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed. 1. A method comprising:providing an integrated circuit (IC) substrate; anddepositing a solderable ink on the IC substrate using an ink deposition process; andreflowing the deposited solderable ink to form one or more solder bumps on the IC substrate, wherein a first solder bump of the one or more solder bumps has a size that is different than a size of a second solder bump of the one or more solder bumps.2. The method of claim 1 , wherein the solderable ink includes a solder powder mixed with a flux material.3. (canceled)4. The method of claim 1 , wherein the solderable ink includes a solder powder mixed with a stabilizing binder that is stable at room temperature and configured to decompose at an elevated temperature above the room temperature.5. The method of claim 1 , wherein:the IC substrate includes a contact;providing the IC substrate comprises providing a die, wafer, or package substrate; anddepositing the solderable ink comprises depositing the solderable material on the contact using an ink jet printer according to a computer-aided design (CAD) file.6. A method comprising:providing an integrated circuit (IC) substrate; anddepositing a solderable material on the IC substrate using a binder printing system.7. The method of claim 6 , wherein depositing the solderable material comprises:spreading solder powder on the IC ...

BUMP, METHOD FOR FORMING THE BUMP, AND METHOD FOR MOUNTING SUBSTRATE HAVING THE BUMP THEREON

A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer. 1. A method of producing bumps of a conductive metal formed in a predetermined pattern on a substrate , the bump comprising:a two-layer structure of a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on the substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is either gold or silver, formed on the first bump layer; the bulk body composing the first bump layer being formed through any of plating, sputtering, and CVD; the sintered body composing the second bump layer being formed by sintering a metal powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm; and the second bump layer having a Young's modulus 0.1 to 0.4 times that of the first bump layer; the method comprising the steps of:forming the first bump layer on the substrate through any of plating, sputtering, and CVD; and forming the second bump layer by applying a metal paste containing a powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm onto the first bump layer, drying the metal paste, and then heating the metal paste at a ...

LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer and including a first surface and a second surface; first and second contact electrodes each ohmic-contacting the first and second conductivity type semiconductor layers; and first and second electrodes disposed on the first surface of the light emitting structure, in which the first and second electrodes each include sintered metal particles and the first and second electrodes each include inclined sides of which the tangential gradients with respect to sides of vertical cross sections thereof are changing. 1. A light emitting device comprising:a semiconductor stack located between a first surface and a second surface that are on opposite sides of the semiconductor stack and including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer;an electrical contact structure formed on the first surface of the semiconductor stack and having an inclined side surface with an inclination angle changing along a direction away from the first surface of the semiconductor stack; anda wavelength conversion structure formed on the second surface of the semiconductor stack and structured to change a wavelength of light emitted from the semiconductor stack.2. The light emitting device of claim 1 , wherein the inclination angle of the inclined side surface changes with respect to an axis perpendicular to a surface of the electrical contact structure.3. The light emitting device of claim 1 , wherein the inclined side surface includes a first region in which the inclination angle increases and a second region in which the inclination angle decreases.4. The light emitting device of claim 1 , wherein the electrical contact ...

Semiconductor Device Manufacturing Method

A method for manufacturing a semiconductor includes: a Step A of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a semiconductor chip, a Step B of preparing an adherend, a Step C of pasting the chip with sheet-shaped resin composition onto the adherend so that the sheet-shaped resin composition serves as a pasting surface, a Step D of heating the sheet-shaped resin composition to semi-cure the sheet-shaped resin composition after the Step C, and a Step E of heating the sheet-shaped resin composition at a higher temperature than in the Step D to cure the sheet-shaped resin composition after the Step D. 1. A method for manufacturing a semiconductor , comprising:a Step A of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a semiconductor chip,a Step B of preparing an adherend,a Step C of pasting the chip with sheet-shaped resin composition onto the adherend so that the sheet-shaped resin composition serves as a pasting surface,a Step D of heating the sheet-shaped resin composition to semi-cure the sheet-shaped resin composition after the Step C, anda Step E of heating the sheet-shaped resin composition at a higher temperature than in the Step D to cure the sheet-shaped resin composition after the Step D.2. The method for manufacturing a semiconductor device according to claim 1 , wherein the sheet-shaped resin composition has a thermal curing rate of 10% or more after heating at 200° C. for 10 seconds.3. The method for manufacturing a semiconductor device according to claim 1 , wherein the adherend has an unevenness of 3 μm to 100 μm on a surface onto which the sheet-shaped resin composition is pasted.41. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor chip has an unevenness of 3 μm to 100 μm on a surface onto which the sheet-shaped resin composition is pasted. The present invention relates to a ...

Semiconductor device

A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.

Chip-on-chip structure and methods of manufacture

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad. 1. A method for creating a metallic pillar on a metallic base layer of a semiconductor device , comprising:depositing a photoresist layer over the metallic base layer;creating an opening in the photoresist layer having a total volume that is configured to expose the metallic base layer and is further configured to define the metallic pillar;substantially filling the total volume of the opening in the photoresist layer with a multi-element metallic paste comprising a metallic portion and a non-metallic portion;at least partially driving off the non-metallic portion of the multi-element metallic paste by heating the multi-element paste to a sintering temperature of the metallic portion of the multi-element metallic paste, whereby a bottom portion of the total volume of the opening in the photoresist layer retains the sintered metallic portion of the multi-element metallic paste and a top portion of the total volume is empty;substantially filling the empty top portion of the total volume with a solder paste;forming a solder cap by heating the solder paste to a reflow temperature of the solder paste, and;stripping away the photoresist layer.2. The method of claim 1 , wherein the multi-element metallic paste comprises metal powder as the metallic portion and one or both of a flux material and a solvent as the non-metallic portion.3. The method of claim 2 , wherein the multi-element ...

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed. 1. A device comprising:an I/O pad of a substrate;a column on the I/O pad; anda head on the column and extending on all lateral sides of the column, a portion of a surface of the head, aligned with the column in a cross-sectional view of the device, is substantially parallel to a surface of the substrate.2. The device of claim 1 , wherein a plane along the portion of a surface of the head is parallel to a plane along a surface of the head adjacent to the column.3. The device of claim 1 , wherein the head has a rounded side profile with a radius that is approximately equal to the thickness of the head.4. The device of further comprising solder on the head.5. The device of further comprising a barrier layer between the surface of the head and the solder.6. The device of claim 5 , wherein the barrier layer impacts formation of intermetallic compounds between a material of the head and solder.7. The device of claim 1 , wherein the head extends past the column on all lateral sides of the column by a lateral distance that is approximately equal to a vertical thickness of the head.8. The device of further comprising a seed layer between the column ...

LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer and including a first surface and a second surface; first and second contact electrodes each ohmic-contacting the first and second conductivity type semiconductor layers; and first and second electrodes disposed on the first surface of the light emitting structure, in which the first and second electrodes each include sintered metal particles and the first and second electrodes each include inclined sides of which the tangential gradients with respect to sides of vertical cross sections thereof are changing. 1. A light emitting device , comprising:a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the light emitting structure disposed between a first surface and a second surface opposite to the first surface;first and second contact electrodes disposed on the first surface of the light emitting structure to be in ohmic-contact with the first and second conductivity type semiconductor layers, respectively;a first electrode disposed on the first surface of the light emitting structure and electrically connected to the first contact electrode;a second electrode disposed on the first surface of the light emitting structure and electrically connected to the second contact electrode; andan insulating part covering sides of the first and second electrodes and the first surface of the light emitting structure,wherein the first and second electrodes, each including metal particles, andthe first and second electrodes, each including an inclined side having tangential gradients with respect to a ...

CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap. 1. A method , comprising:placing a powder on a substrate;sintering the powder to form a plurality of pillars directly in contact with the substrate;repeating the placing and sintering steps until the plurality of pillars reach a predetermined height;forming a solder cap on the plurality of pillars; andjoining the substrate to a board using the solder cap and a process such as thermal reflow.2. The method of claim 1 , wherein:the powder is a copper powder;the solder cap is a solder cap that is formed by a powder deposition followed by a sintering process; andthe sintering is a laser sintering process.3. The method of claim 2 , wherein the solder cap is reflowed claim 2 , prior to the joining.4. The method of claim 1 , further comprising removing any non-sintered powder from the substrate claim 1 , prior to the joining.5. The method of claim 1 , wherein the predetermined height of the plurality of pillars is greater than 75 μm.6. The method of claim 5 , wherein the predetermined height of the plurality of pillars is about 500 μm.7. The method of claim 6 , further comprising joining a chip to the substrate by a reflow process.8. The method of claim 7 , further comprising underfilling empty spaces between the chip claim 7 , the substrate and the board.9. The method of claim 1 , wherein the plurality of pillars are tapered.10. The method of claim 1 , wherein the plurality of pillars are shaped as an hourglass.11. A method claim 1 , comprising:placing a wafer in a chuck and coating the wafer with a ...

Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

Bump bond structure for enhanced electromigration performance

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

DIELECTRIC MOLDED INDIUM BUMP FORMATION AND INP PLANARIZATION

The disclosed technique may be used to electrically and physically connect semiconductor wafers to allow high density interconnects and accommodate mismatched coefficients of thermal expansion materials by having room temperature hybridization as well as to remove the bow from wafers. The wafers may utilize a thick dielectric to remove the bow and create a planar surface. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together. The small size of the columns enables wafer or chip scale hybridization with a very high interconnect density, high reliability, and the ability to accommodate mismatches in the coefficients of thermal expansion of the constituent materials. 1. A method of fabricating a semiconductor device , the method comprising:depositing a dielectric film having a thickness of greater than 2 micrometers on a semiconductor wafer;opening holes through the dielectric film;depositing indium or an alloy of indium in the holes;melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape;repeating the depositing and melting of the indium or alloy of indium until the indium columns reach a desired height; andremoving at least a portion of the dielectric film to expose a plurality of substantially uniform indium columns on a surface of the semiconductor wafer having a pitch of less than 15 micrometers.2. The method according to claim 1 , further comprising planarizing the dielectric film surface prior to opening holes through the dielectric film.3. The method according to claim 2 , further comprising forming trenches around the indium columns by removing the dielectric film immediately adjacent the indium columns as part of the ...

Dielectric-dielectric and metallization bonding via plasma activation and laser-induced heating

The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

플립 칩 실장 방법 및 범프 형성 방법

제1 전자 부품(2) 상에 땜납 분말(5a)과 수지(4)를 포함하는 땜납 수지 조성물(6)을 탑재하고, 제1 전자 부품(2)의 접속 단자(3)와 제2 전자 부품(8)의 전극 단자(7)가 대향하도록 배치하고, 제1 전자 부품(2)과 땜납 수지 조성물을 가열하여 제1 전자 부품(2)에 포함되는 가스 발생원(1)으로부터 가스를 분출시키고, 가스(9a)를 땜납 수지 조성물(6) 중에서 대류시킴으로써, 땜납 분말(5a)을 땜납 수지 조성물(6) 중에서 유동시키고, 접속 단자(3) 및 전극 단자(7) 상에 자기 집합시켜 접속 단자(3)와 전극 단자(7)를 전기적으로 접속시킨다. 이로 인해, 협(狹)피치로 배선된 반도체 칩의 전극 단자와 회로 기판의 접속 단자를 높은 접속 신뢰성으로 접속할 수 있는 플립 칩 실장 방법과 회로 기판 상에 실장하기 위한 범프 형성 방법을 제공한다.

Flip-chip mounting resin composition and bump forming resin composition

차세대 LSI의 플립 칩 실장에 적용가능한, 생산성 및 신뢰성이 높은 플립 칩 실장에 적합한 플립 칩 실장용 수지 조성물은, 수지(13)가 가열되었을 때에 비등하는 대류 첨가제(12)를 함유하고 있다. 수지(13)가 가열되었을 때, 금속 입자가 수지 중에서 용융함과 아울러, 비등한 대류 첨가제(12)가 수지 속을 대류한다. The resin composition for flip chip mounting suitable for flip chip mounting with high productivity and reliability applicable to flip chip mounting of next generation LSI contains the convection additive 12 which boils when resin 13 is heated. When the resin 13 is heated, the metal particles melt in the resin, and the boiling convection additive 12 convex in the resin. 회로 기판(10)과 반도체 칩(20)의 사이에 공급된 수지(13)를 가열하고, 수지(13) 속에서 용융한 금속 입자가, 회로 기판(10)과 반도체 칩(20)의 단자(11, 21) 사이에 자기 집합함으로써, 단자 사이를 전기적으로 접속하는 접속체(22)를 형성하고, 그 후, 수지(13)를 경화시켜서, 반도체 칩(20)을 회로 기판(10)에 고정시킴으로써 플립 칩 실장체가 얻어진다. The metal particles melted in the resin 13 by heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20 form the terminals of the circuit board 10 and the semiconductor chip 20 ( By self-assembly between 11 and 21, the connection body 22 which electrically connects between terminals is formed, after that, resin 13 is hardened and the semiconductor chip 20 is fixed to the circuit board 10. FIG. By doing so, a flip chip mounting body is obtained.

Flip chip mounting resin composition and bump forming resin composition

次世代ＬＳＩのフリップチップ実装に適用可能な、生産性及び信頼性の高いフリップチップ実装に適したフリップチップ実装用樹脂組成物は、樹脂１３が加熱されたときに沸騰する対流添加剤１２を含有している。樹脂１３が加熱されたとき、金属粒子が樹脂中で溶融するとともに、沸騰した対流添加剤１２が樹脂中を対流する。回路基板１０と半導体チップ２０との間に供給された樹脂１３を加熱し、樹脂１３中で溶融した金属粒子が、回路基板１０と半導体チップ２０の端子１１、２１間に自己集合することによって、端子間を電気的に接続する接続体２２を形成し、その後、樹脂１３を硬化させて、半導体チップ２０を回路基板１０に固定させることによって、フリップチップ実装体が得られる。 A flip chip mounting resin composition suitable for flip chip mounting with high productivity and reliability applicable to next-generation LSI flip chip mounting contains a convection additive 12 that boils when the resin 13 is heated. is doing. When the resin 13 is heated, the metal particles melt in the resin, and the boiled convective additive 12 convects in the resin. By heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20, the metal particles melted in the resin 13 are self-assembled between the terminals 11 and 21 of the circuit board 10 and the semiconductor chip 20, A connection body 22 that electrically connects the terminals is formed, and then the resin 13 is cured, and the semiconductor chip 20 is fixed to the circuit board 10 to obtain a flip chip mounting body.

Solder bump having cored structure and production method therefor

유심 구조 땜납 범프 및 그 제조 방법을 제공한다. 땜납 범프의 제조에 있어서, 미리, 범프의 중심 부분에 심용 페이스트를 인쇄 도포하고, 땜납 금속의 리플로우 처리 온도 근방 또는 그 이하에 이하의 온도에서 심용 페이스트를 소결함으로써 소결심을 형성하고, 이어서, 이 소결심의 주위에 땜납 금속을 인쇄법으로 도포하고, 이 땜납 금속을 리플로우 처리함으로써, 땜납 범프의 내부에, 수직인 방향으로 연장되는 소결심이 형성된 유심 구조 땜납 범프를 얻는다. A cored structure solder bump and a method of manufacturing the same are provided. In the production of the solder bump, a sintered core is formed by previously applying a core paste to the central portion of the bump and sintering the core paste at a temperature below or below the reflow treatment temperature of the solder metal, and then, By applying a solder metal around the sintered core by a printing method and reflowing the solder metal, a cored structure solder bump having a sintered core extending in a vertical direction is formed inside the solder bump.

Method to form solder alloy deposits on substrates

Described is a method of forming a solder alloy deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one inner layer contact pad, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a metal seed layer on the substrate surface, iv) form a structured resist layer on the metal seed layer, v) electroplate a first solder material layer containing tin onto the conductive layer, vi) electroplate a second solder material layer onto the first solder material layer, vii) remove the structured resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area and reflow the substrate and in doing so form a solder alloy deposit from the metal seed layer, the first solder material layer and the second solder material layer.

Method to form solder alloy deposits on substrates

Described is a method of forming a solder alloy deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one inner layer contact pad, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a metal seed layer on the substrate surface, iv) form a structured resist layer on the metal seed layer, v) electroplate a first solder material layer containing tin onto the conductive layer, vi) electroplate a second solder material layer onto the first solder material layer, vii) remove the structured resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area and reflow the substrate and in doing so form a solder alloy deposit from the metal seed layer, the first solder material layer and the second solder material layer.

The manufacture method of semiconductor package part

本发明提供高成品率的半导体封装件的制造方法。半导体封装件的制造方法包括如下步骤：对包含至少一种金属且具有第一面和与所述第一面对置的第二面的基材的所述第一面及位于所述第一面与所述第二面之间的侧面部进行蚀刻，且在所述第一面及所述侧面部附着与所述金属不同的其他金属；在所述基材的所述第二面配置包括外部端子的半导体装置，使得所述外部端子不与所述第二面对置；形成用于覆盖所述半导体装置的树脂绝缘层；在所述树脂绝缘层上形成第一导电层；在所述第一导电层和所述树脂绝缘层形成用于使所述半导体装置的所述外部端子露出的开口部；以及在所述基材的所述第一面和侧面部、所述第一导电层上及所述开口部内形成镀层。

ASSEMBLY COMPRISING MIXED INTERCONNECT MEANS COMPRISING INTERMEDIATE INTERCONNECTION ELEMENTS AND METAL SINTERED JOINTS AND METHOD OF MANUFACTURE

ASSEMBLY COMPRISING MIXED INTERCONNECT MEANS COMPRISING INTERMEDIATE INTERCONNECTION ELEMENTS AND METAL SINTERED JOINTS AND METHOD FOR MANUFACTURING THE SAME

L'invention a pour objet un assemblage comprenant : - au moins un premier élément (100) comprenant au moins un premier plot de connexion électrique (12) ; - au moins un second élément (200) comprenant au moins un second plot de connexion électrique (21) ; - des moyens d'interconnexion électrique et mécanique, caractérisé en ce que lesdits moyens d'interconnexion électrique et mécanique comprennent au moins : - au moins un premier élément intermédiaire métallique d'interconnexion (13), à la surface d'au moins le premier plot de connexion électrique ; - au moins un joint fritté de microparticules ou de nanoparticules métalliques empilé avec ledit premier élément intermédiaire d'interconnexion ; - la température de fusion dudit premier élément intermédiaire d'interconnexion étant supérieure à la température de frittage desdites microparticules ou de nanoparticules métalliques. L'invention a aussi pour objet un procédé de fabrication d'un assemblage de l'invention The invention relates to an assembly comprising: - at least one first element (100) comprising at least a first electrical connection pad (12); at least one second element (200) comprising at least one second electrical connection pad (21); electrical and mechanical interconnection means, characterized in that said electrical and mechanical interconnection means comprise at least: at least one first metallic intermediate interconnection element (13), on the surface of at least the first electrical connection pad; at least one sintered gasket of microparticles or metal nanoparticles stacked with said first intermediate interconnection element; - The melting temperature of said first intermediate interconnect element being greater than the sintering temperature of said microparticles or metal nanoparticles. The invention also relates to a method for manufacturing an assembly of the invention

Using underfill or flux to promote placing and parallel bonding of light emitting diodes

Embodiments relate to using flux or underfill as a trapping layer for temporarily attaching light emitting diodes (LEDs) to a substrate and heating to simultaneously bond multiple LEDs onto the substrate. The flux or underfill may be selectively coated at the ends of electrodes of the LEDs prior to placing the LEDs on the substrate. Due to adhesive properties of the flux or underfill, multiple LEDs can be placed on and attached to the substrate prior to performing the bonding process. Once LEDs are placed on the substrate, the flux or underfill facilitates formation of metallic contacts between electrodes of the LED and contacts of the substrate during the bonding process. By using the flux or underfill, the formation of metallic contacts can be performed even without applying pressure.

Light emitting device and method of fabricating the same

Provided are a light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer and including a first surface and a second surface; first and second contact electrodes each ohmic-contacting the first and second conductivity type semiconductor layers; and first and second electrodes disposed on the first surface of the light emitting structure, in which the first and second electrodes each include sintered metal particles and the first and second electrodes each include inclined sides of which the tangential gradients with respect to sides of vertical cross sections thereof are changing.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Conductive pillar and method for manufacturing same, and method for manufacturing bonded structure

Provided are a method for manufacturing a conductive pillar capable of bonding a substrate and a member to be bonded via a bonding layer with high bonding strength without use of an electroplating method, and a method for manufacturing a bonded structure using the same. A method for manufacturing a conductive pillar 1 comprises, in an order to be mentioned, a step for forming a resist layer 16 on a substrate 11 on which an electrode pad 13 is formed, the resist layer 16 having an opening 16a on the electrode pad 13, a step for sputtering or depositing Cu on a surface of the substrate 11, on which the resist layer 16 having the opening 16a is formed, to form a Cu thin film 17, a step for filling the opening 16a with a copper fine particle paste 12c, and a step for heating the substrate 11 filled with the copper fine particle paste 12c to sinter the copper fine particle paste 12c.

Method for manufacturing metal powder

一种用于制造金属粉末的方法，包括：提供碱性金属盐溶液；使该碱性金属盐溶液与还原剂接触以从其中沉淀出金属粉末；以及从溶剂中回收所沉淀的金属粉末。

Method for forming resin insulation film pattern on substrate surface and semiconductor device

In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.

Pillar bump formed using spot-laser

A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

Tin/tin alloy nanoparticle having low melting temperature and method for manufacturing same

Disclosed are a nanoparticle having a size of 1-20nm prepared by electrolyzing a tin or a tin alloy, and a method for preparing same. The nanoparticle surface-melts in a temperature range of 80-130℃. A solder ball having the nanoparticle can be sintered at or below 160℃, and can thus, first, save 22% of energy by resolving the energy consumption of 74 kW for the conventionally used reflow processing device to an energy consumption of 50 kW by enabling the heating temperature to be lowered from 240℃ to 160℃ during reflow process. Second, deformation of a PCB board can be minimized by enabling the temperature for the reflow process to be lowered, and application areas for implementation materials having a low unit cost can be created by enabling the use of low cost polymer materials such as PET having low glass transition temperature. And third, the uniformity of a solder paste on a pad can be enhance when using a nanoparticle having a size of 10 nm or smaller, and in the case of a nano-solder ink, the limitations of micro-patterning can be overcome due to the small size of the particle (Figure 4).

Methods of fabricating semiconductor chip solder structures

Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

Formation of solder and copper interconnect structures and associated techniques and configurations

Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.

Bump, method for forming the bump, and method for mounting substrate having the bump formed thereon

Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process

L'invention a pour objet un assemblage comprenant : - au moins un premier élément (100) comprenant au moins un premier plot de connexion électrique (12); - au moins un second élément (200) comprenant au moins un second plot de connexion électrique (21); - des moyens d'interconnexion électrique et mécanique, caractérisé en ce que lesdits moyens d'interconnexion électrique et mécanique comprennent au moins : - au moins un premier élément intermédiaire métallique d'interconnexion (13), à la surface d'au moins le premier plot de connexion électrique; - au moins un joint fritté de microparticules ou de nanoparticules métalliques empilé avec ledit premier élément intermédiaire métallique d'interconnexion; - la température de fusion dudit premier élément intermédiaire métallique d'interconnexion étant supérieure à la température de frittage desdites microparticules ou de nanoparticules métalliques. L'invention a aussi pour objet un procédé de fabrication d'un assemblage de l'invention.

UBM structure for strengthening solder bumps

A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon.

Bump, method for forming the bump, and method for mounting substrate having the bump formed thereon

A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt% and an average particle diameter of 0.005 µm to 1.0 µm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

Methods and structures for a vertical pillar interconnect

In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Method for mounting semiconductor device and structure thereof

A method and a structure is provided for mounting a semiconductor device by the bump technique using compound metallic ultra-fine particles each comprising a core portion consisting substantially of a metallic component, and a coating layer chemically bound to the core portion and comprising an organic substance. The method and the structure are characterized by using one of, or a combination of, the following two bump technologies: 1) Forming under bump metals from the compound metallic ultra-fine particles, and forming ordinary solder balls on the under bump metals. 2) Using paste balls comprising the compound metallic ultra-fine particles, instead of ordinary solder balls.

Method of bonding

The present invention provides a bonding method in which a bonded portion having a sufficient bonding strength can be obtained at a relatively low temperature, for example, in die bonding a semiconductor chip. A metal paste 20 was applied to a semiconductor chip 10, the metal paste 20 consisting of metal powder of one or more kinds selected from gold powder, silver powder, platinum powder, and palladium powder having a purity not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm and an organic solvent. After being applied, the metal paste 20 was dried in a vacuum in a dryer. The chip was heated at 230° C. for 30 minutes to sinter the metal paste, by which a metal powder sintered compact 21 was formed. Next, a nickel plate 30 was placed on the semiconductor chip 10, and bonded to the semiconductor chip 10 by heating and pressurization.

Compliant electrical contacts

A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

Flip chip mounting method and bump forming method

본 발명은 차세대LSI의 플립칩실장에 적용 가능한, 생산성 및 신뢰성 높은 플립칩 실장방법, 및 범프형성방법을 제공하는 것이다. The present invention is to provide a flip chip mounting method and a bump forming method with high productivity and reliability applicable to flip chip mounting of next generation LSI. 복수의 접속단자(11)를 갖는 회로기판(21)과 복수의 전극단자(12)를 갖는 반도체칩(20) 틈새에, 땜가루(16)와 기포발생제를 함유한 수지(14)를 공급한 후, 수지(14)를 가열하여, 수지(14) 중에 함유된 기포발생제로부터 기포(30)를 발생시킨다. 수지(14)는, 발생한 기포(30)가 성장함에 따라 기포 외측으로 밀려나, 접속단자(11)와 전극단자(12) 사이로 자기집합한다. 또한 수지(14)를 가열하여, 단자간에 자기집합한 수지(14) 중에 함유된 땜가루(16)를 용융시킴으로써, 단자간 접속체(22)를 형성하고 플립칩 실장체를 완성시킨다. The resin 14 containing the solder powder 16 and the bubble generator is supplied to the gap between the circuit board 21 having the plurality of connection terminals 11 and the semiconductor chip 20 having the plurality of electrode terminals 12. After that, the resin 14 is heated to generate bubbles 30 from the bubble generator contained in the resin 14. The resin 14 is pushed out of the bubble as the generated bubble 30 grows, and self-assembles between the connection terminal 11 and the electrode terminal 12. Further, the resin 14 is heated to melt the solder powder 16 contained in the resin 14 self-assembled between the terminals, thereby forming the terminal-to-terminal connecting body 22 and completing the flip chip mounting body. 플립칩 실장체, 접속체, 자기집합, 기포발생제, 땜가루 Flip chip mounting body, connector, self-assembly, bubble generator, solder powder

Flip chip mounting method and bump forming method

The invention involves mounting a solder resin composition ( 6 ) including a solder powder ( 5 a ) and a resin ( 4 ) on the first electronic component ( 2 ); arranging such that the connecting terminals ( 3 ) of the first electronic component ( 2 ) and the electrode terminals ( 7 ) of the second electronic component ( 8 ) are facing each other; ejecting a gas ( 9 a ) from a gas generation source ( 1 ) included in the first electronic component ( 2 ) by heating the first electronic component ( 2 ) and the solder resin composition; and inducing the flow of the solder powder ( 5 a ) in the solder resin composition ( 6 ) by inducing convection of the gas ( 9 a ) in the solder resin composition ( 6 ), and electrically connecting the connecting terminals ( 3 ) and the electrode terminals ( 7 ) by self-assembly on the connecting terminals ( 3 ) and the electrode terminals ( 7 ). Through this are provided a flip chip packaging method that enables connecting, with high connection reliability, electrode terminals of a semiconductor chip wired with narrow pitch and connecting terminals of a circuit board, and a bump formation method for packaging on a circuit board.

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Manufacturing method of semiconductor device

The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is supplied into the openings. The first metal is then heated to melt and coagulate it. The second metal is then supplied into the openings on the first metal. The first metal and the second metal are heated to melt and coagulate them. The resist film is finally removed. By this method, excellent solder bumps can be formed on the substrate without remnants of the resist film being left on the substrate.

Zinc-cobalt barrier for interface in solder bond applications

Solder bump having cored structure and production method therefor

本发明提供一种有芯结构焊料凸点及其制造方法。在制造焊料凸点时，预先在凸点的中心部分印刷涂布芯用浆料，并以焊料金属的回流处理温度附近或其以下的温度对芯用浆料进行烧结，由此形成烧结芯，接着以印刷法在该烧结芯周围涂布焊料金属，并对该焊料金属进行回流处理，从而得到在焊料凸点的内部形成有沿垂直方向延伸的烧结芯的有芯结构焊料凸点。

Electroplated lead-free bump deposition

A method of forming a metal feature on a workpiece with deposition is provided. The method includes providing an under bump metal layer for solder of an electronic device on the workpiece, depositing a substantially pure tin layer directly to the under bump metal layer, and depositing a tin silver alloy layer onto the substantially pure tin layer.

Electroplated lead-free bump deposition

Method of manufacturing semiconductor device

【課題】半導体装置の製造方法に関し、狭いピッチで良好なはんだバンプを形成することができるようにすることを目的とする。 【解決手段】絶縁膜１６を電極１２を有する基板１０の表面に設け、該絶縁膜の該基板の電極の位置に開口部１４を設け、該開口部内に第１の金属１８を供給し、該第１の金属を加熱して溶融させ、そして凝固させ、該開口部内に第１の金属に重ねて第２の金属２２を供給し、該第１及び第２の金属を加熱して溶融させ、そして凝固させ、該絶縁膜を除去する構成とする。 【選択図】 図１

Solder Bump Fabrication Method and Solder Bumps Formed Thereby

The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump. This lip provides extra protection for the solder bump.

Mask and method for electrokinetic deposition and patterning process on substrates

A mask for application to a substrate to facilitate electrokinetic deposition of charged particles onto the substrate, the mask comprising a conducting layer, a dielectric layer, and mask openings. A method for applying a pattern of charged particles to a substrate comprising applying the foregoing the substrate to yield a masked substrate; immersing the masked substrate in a bath containing the charged particles; and establishing an electrical potential between the conducting layer of the mask and a counter-electrode thereby electrokinetically depositing the particles through the mask openings onto areas of the substrate exposed in the mask openings. Products made by this method.

Electronic component packaging method, semiconductor module, and semiconductor device

本发明提供可实现缩小安装面积及薄形化的电子部件的安装方法、半导体模块及半导体器件。本发明的一个课题解决手段是将形成于基板上的电极和形成于电子部件上的电极进行接合的电子部件的安装方法，所述接合通过凝聚了至少一种金属粒子的金属层来进行接合。而且，所述金属粒子以平均粒径为1～50nm构成。另外，最好是构成其厚度为5～100μm的金属层。

Electronic component module manufacturing method and electronic component module

電子部品の複数の外部端子と基板の表面電極との接合部が、電子部品の側面に接触することがない、電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールを提供する。複数のバンプ６を厚さの厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成し、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子２の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子２の、電子部品の中央側と反対側に位置するように、基板の一方の面にそれぞれ形成する。形成した複数のバンプ６を変形させて複数の外部端子２を接合した複数の接合部７を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成する。 Provided are an electronic component module manufacturing method and an electronic component module manufactured by the manufacturing method, in which joint portions between a plurality of external terminals of an electronic component and a surface electrode of a substrate do not contact a side surface of the electronic component. When the plurality of bumps 6 are composed of a thick part that is a thick part and a thin part that is a thin part, and the electronic component is viewed in plan, the thick part is a corresponding external terminal. The thin-walled portion is formed on one surface of the substrate so as to be located on the opposite side of the central side of the electronic component of each corresponding external terminal 2 so as to be located on the central side of the electronic component. . The plurality of joints 7 formed by deforming the plurality of formed bumps 6 and joining the plurality of external terminals 2 are located on the opposite side of the center side of the electronic component from the height of the center side of the electronic component when the electronic component is viewed in plan view. It is formed so that the height is lower.

Method for manufacturing Sn alloy bump

Provided is a method for manufacturing an Sn alloy bump, wherein composition of the Sn alloy bump can be readily controlled. The method for manufacturing an Sn alloy bump formed of an alloy composed of Sn and other one or more types of metals has a step of forming an Sn layer on an electrode pad in a resist opening formed on a substrate by electrolytic plating; a step of laminating Sn and an alloy layer on the Sn layer by electrolytic plating; and a step of forming an Sn alloy bump by melting the Sn layer and the laminated alloy layer after removal of a resist.

Forming of bump structure

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

Manufacturing method of semiconductor device

According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Wafer with a plurality of chips

本公开涉及一种晶片。本文中描述了适用于形成集成电路芯片封装的集成电路互连。在一个示例中，集成电路互连体现在晶片中，该晶片包括其上形成有多个集成电路(IC)裸片的基板。多个IC裸片包括具有第一固态电路的第一IC裸片和具有第二固态电路的第二IC裸片。第一接触焊盘设置在基板上并且耦合到第一固态电路。第一焊球设置在第一接触焊盘上。第一焊球具有形成在其上的基本上均匀的氧化物涂层。

METHOD FOR THE PRODUCTION OF SOLDERING BUMBS AND SOLDERING BOBBIES MADE THEREOF.

Dielectric molded indium bump formation and inp planarization

The disclosed technique may be used to electrically and physically connect semiconductor wafers to allow high density interconnects and accommodate mismatched coefficients of thermal expansion materials by having room temperature hybridization as well as to remove the bow from wafers. The wafers may utilize a thick dielectric to remove the bow and create a planar surface. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together. The small size of the columns enables wafer or chip scale hybridization with a very high interconnect density, high reliability, and the ability to accommodate mismatches in the coefficients of thermal expansion of the constituent materials.

Semiconductor die terminal

A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Method of bonding

본 발명은 반도체 칩의 다이본딩 등에 있어서, 비교적 저온에서 충분한 접합강도를 갖는 접합부를 얻을 수 있는 방법을 제공한다. 반도체 칩(10)에 순도가 99.9 중량% 이상이고, 평균 입경이 0.005 ㎛~1.0 ㎛인 금분말, 은분말, 백금분말, 또는 팔라듐분말로부터 선택되는 1종 이상의 금속분말과, 유기 용제로 되는 금속 페이스트(20)를 도포하였다. 금속 페이스트(20)를 도포한 후, 이를 건조기에서 진공 건조하고, 칩을 230℃에서 30분 가열하여 금속 페이스트를 소결(sintering)하여, 분말 금속 소결체(21)로 하였다. 다음으로, Ni판(30)을 반도체 칩(10) 상에 올려놓고, 가열 및 가압하여 접합한다. The present invention provides a method for obtaining a bonded portion having sufficient bonding strength at a relatively low temperature in die bonding of a semiconductor chip. At least one metal powder selected from gold powder, silver powder, platinum powder, or palladium powder having a purity of 99.9% by weight or more and an average particle diameter of 0.005 µm to 1.0 µm in the semiconductor chip 10, and a metal which is an organic solvent Paste 20 was applied. After apply | coating the metal paste 20, it was vacuum-dried in the dryer, the chip was heated at 230 degreeC for 30 minutes, and the metal paste was sintered, and it was set as the powder metal sintered compact 21. Next, the Ni plate 30 is placed on the semiconductor chip 10, and heated and pressed to join.

Bump, method for forming the bump, and method for mounting substrate having the bump thereon

A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

Metal member bonding agent, metal member assembly manufacturing method, metal member assembly, and electric circuit connecting bump manufacturing method

Lead free alloy bump structure and fabrication method

A method includes forming a patterned resist layer comprising a resist layer opening overlying a bond pad of a substrate. The resist layer opening is at least partially filled with a first solder component layer. A second solder component layer is formed on the first solder component layer. The patterned resist layer is removed. The first solder component layer and the second solder component layer are reflowed to form a lead free binary metal alloy solder bump electrically connected to the bond pad.

Semiconductor device manufacturing method

　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、被着体を準備する工程Ｂと、被着体に、シート状樹脂組成物付きチップを、シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、工程Ｃの後に、シート状樹脂組成物を加熱して半硬化させる工程Ｄと、工程Ｄの後に、工程Ｄにおける加熱よりも高温でシート状樹脂組成物を加熱して硬化させる工程Ｅとを含む半導体装置の製造方法。

Solder bump bonding in semiconductor package using solder balls having high-temperature cores

A semiconductor die is solder bump-bonded to a leadframe or circuit board using solder balls having cores made of a material with a melting temperature higher than the melting temperature of the solder to ensure that in the finished structure the die is parallel to the leadframe or circuit hoard.

Method of forming a solder bump structure

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Methods for forming pillar bumps on semiconductor wafers

本案所含之請求標的揭示用於在半導體晶圓上的凸塊下金屬墊上形成垂直金屬柱及在該金屬柱之頂表面上施用不連續焊帽的方法，其中該金屬柱是由至少一光阻層所界定而成。該方法包括加熱多元素金屬膏，該多元素金屬膏含有可變量的金屬粉末、熔點降低劑及助焊劑，以使金屬粉末燒結成金屬柱並同時使該金屬柱附著於該凸塊下金屬墊。

Flip chip mounting method and bump forming method

A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin 14 containing a solder powder 16 and a gas bubble generating agent is supplied to a space between a circuit board 21 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 12, the resin 14 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 14. The resin 14 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof and self-assembled between the connecting terminals 11 and the electrode terminals 12. By further heating the resin 14 and melting the solder powder 16 contained in the resin 14 self-assembled between the terminals, connectors 22 are formed between the terminals to complete a flip chip mounting body.

Transfer substrate for forming metal wiring and method for forming metal wiring using the transfer substrate

【課題】転写法により被転写物に金属配線を形成するための転写用基板であって、被転写物側の加熱温度を低くすることのできるもの、及び、金属配線の形成方法を提供する 【解決手段】本発明は、基板と、前記基板上に形成された少なくとも一つの金属配線素材と、前記金属配線素材の表面上に形成された少なくとも１層の被覆層と、前記基板と前記金属配線素材との間に形成された下地金属膜と、からなり、前記金属配線素材を被転写物に転写させるための転写用基板であって、前記金属配線素材は、純度９９．９重量％以上、平均粒径０．０１μｍ〜１．０μｍである金粉等の金属粉末を焼結してなる成形体であり、前記被覆層は、金等の所定の金属又は合金であって、前記金属配線素材と相違する組成の金属又は合金からなり、かつ、その合計厚さは１μｍ以下であり、前記下地金属膜は、金等の所定の金属又合金からなる転写用基板である。 【選択図】図１ [PROBLEMS] To provide a transfer substrate for forming a metal wiring on a transfer object by a transfer method, which can reduce the heating temperature on the transfer object side, and a method of forming a metal wiring. The present invention includes a substrate, at least one metal wiring material formed on the substrate, at least one coating layer formed on a surface of the metal wiring material, the substrate and the metal wiring. A transfer substrate for transferring the metal wiring material to an object to be transferred, the metal wiring material having a purity of 99.9% by weight or more, It is a molded body formed by sintering metal powder such as gold powder having an average particle size of 0.01 μm to 1.0 μm, and the coating layer is a predetermined metal or alloy such as gold, and the metal wiring material and Made of metals or alloys of different composition, and The total thickness is 1 μm or less, and the base metal film is a transfer substrate made of a predetermined metal or alloy such as gold. [Selection] Figure 1

Electroplated lead-free bump deposition

A method of forming a metal feature on a workpiece with deposition is provided. The method includes providing an under bump metal layer for solder of an electronic device on the workpiece, depositing a substantially pure tin layer directly to the under bump metal layer, and depositing a tin silver alloy layer onto the substantially pure tin layer.

Method of forming a solder bump structure

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Flip chip packaging method and bump forming method

供给一种可能适用于下一代半导体集成电路的倒装芯片封装的、生产性及信赖性高的倒装芯片封装方法、以及衬底间连接方法。具有多个连接端子(11)的电路衬底(21)和具有多个电极端子(12)的半导体芯片(20)的间隙间，供给含有焊锡粉(16)和气泡产生剂的树脂(14)后，加热树脂(14)，使树脂(14)中含有的气泡产生剂产生气泡(30)。树脂(14)，由产生的气泡(30)的膨胀被向气泡(30)外推出，在电路衬底(10)和半导体芯片(20)的端子间自行聚合。再有，通过加热树脂(14)，熔融端子间自行聚合了的树脂(14)中含有的焊锡粉(16)，在端子间形成连接体(22)，完成倒装芯片封装体。

Electroconductive bonding material and method for bonding conductor

본 발명은 도전성 접합 재료를 기판의 전극에 공급하면서 용착시키는 도전성 접합 재료 공급 공정, 및 전자 부품의 단자에 도전성 접합 재료를 한번 용융시켜서 전사하는 전사 공정을 선택할 수 있고, 기판과 전자 부품을 150 ℃ 이하의 저온에서 효율적으로 접합할 수 있는 도전성 접합 재료 및 도체의 접합 방법, 및 반도체 장치의 제조 방법을 제공하는 것을 목적으로 한다. 융점 150 ℃ 이상의 고융점 금속 입자와, 융점 80 ℃ 이상 139 ℃ 이하의 중융점 금속 입자와, 융점 79 ℃ 이하의 저융점 금속 입자로 이루어지는 금속 성분을 함유하는 도전성 접합 재료에 있어서, 상기 금속 성분이 고융점 금속 입자 표면에, 중융점 금속 입자로 형성된 중융점 금속층과, 저융점 금속 입자로 형성된 저융점 금속층을 이 순서로 갖는 다층 금속 입자인 양태 등이 바람직하다.

Semiconductor device and method of patternning resin insulation layer on substrate of the same

In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.

Flip chip mounting method and bump forming method

在第1电子元件(2)上载置含有焊料粉(5a)和树脂(4)的焊料树脂组合物(6)，第1电子元件(2)的连接端子(3)和第2电子元件(8)的电极端子(7)相对置地配置，加热第1电子元件(2)和焊料树脂组合物以使从包含在第1电子元件(2)中的气体发生源(1)喷出气体，通过使气体(9a)在焊料树脂组合物(6)中对流，从而使焊料粉(5a)在焊料树脂组合物(6)中流动，使其自己集合在连接端子(3)及电极端子(7)上，从而使连接端子(3)及电极端子(7)电连接。由此，提供一种能够将以窄节距布线的半导体芯片的电极端子和电路基板的连接端子高连接可靠性地连接的倒装片安装方法、以及用于安装在电路基板上的凸块形成方法。

Electronic component, semiconductor package, and electronic device

In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni.

솔더 범프의 형성 방법

본원은 전극 상에 솔더(solder)를 배치하는 단계; 상기 솔더에 제 1 광을 조사하여 솔더 범프를 형성하는 단계; 및 상기 솔더 범프에 제 2 광을 조사하는 단계; 를 포함하는, 솔더 범프의 형성 방법에 대한 것이다.

焼結材料、及びそれを用いる接着方法

【課題】各種コンポーネントを接着（接合）するための方法を提供する。【解決手段】フリップチップなどのマルチチップ及び単一コンポーネントのダイ接着のための方法であって、基板の上又はダイの裏側に焼結ペーストをプリントすることを含むことができる。プリンティングは、ステンシルプリンティング、スクリーンプリンティング、又はディスペンシングプリンティングを含むことができる。ペーストは、ダイシングの前に全ウェハの裏側にプリントすることができる、又は個々のダイの裏側にプリントすることができる。また、焼結膜は、作成後、ウェハ、ダイ、又は基板に転写することができる。ポスト焼結工程は、スループットを上げることができる。【選択図】図３２

Halbleitereinheit und verfahren zum herstellen einer halbleitereinheit

Halbleitereinheit, die Folgendes aufweist:- ein Halbleiterelement (4); und- eine isolierende Basisplatte (1), die eine auf einer Oberfläche der isolierenden Basisplatte (1) ausgebildete Basisplatten-Elektrode (2) aufweist, wobei die Basisplatten-Elektrode (2) so ausgebildet ist, dass sie einen keilartigen Vorsprung (A) entlang des Umfangs eines Bonding-Bereichs auf der Basisplatten-Elektrode (2) für die Montage des Halbleiterelements (4) aufweist, und eine innere Fläche des Vorsprungs (A) vertikal ist und eine äußere Fläche nach außen geneigt ist, um innerhalb des Vorsprungs (A) das Halbleiterelement (4) an einer unteren Fläche und Seitenflächen des Halbleiterelements (4) mit einem sinterbaren Metall-Bondmaterial (3) an die Basisplatten-Elektrode (2) zu bonden.

バンプボンドのための拡張ヘッドピラー

Tsv-凸块结构、半导体装置及其形成方法

本申请涉及TSV‑凸块结构、半导体装置及其形成方法。根据本公开的一或多个实施例，提供一种穿硅通路TSV‑凸块结构。所述TSV‑凸块结构包括半导体衬底中的TSV及所述TSV上的凸块。所述凸块包含导电插塞部分及所述导电插塞部分下方的台阶结构部分。所述台阶结构经配置以将所述TSV与所述导电插塞部分彼此电耦合。

Electronics assemblies employing copper in multiple locations

Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.