Interconnection [...] structure and method

Semiconductor package and manufacturing method thereof

FLIP CHIP MOUNTING PROCESS AND FLIP CHIP ASSEMBLY

Flip chip interconnection structure and method for forming same

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension. 1. A structure comprising:a first substrate having a first pillar, a first barrier layer being on the first pillar, the first pillar being interposed between the first barrier layer and the first substrate, material of the first barrier layer being different than material of the first pillar;a second substrate having a second pillar, a second barrier layer being on the second pillar, material of the second barrier layer being different than material of the second pillar; and a first conductive region extending continuously from the first barrier layer to the second barrier layer, the first conductive region comprising a compound, the compound comprising solder, the compound having at least one common element as the material of the first barrier layer or material of the second barrier layer, and', 'a solder material extending along exterior walls of the first pillar and the second pillar, wherein the solder material extends a first distance from a plane of a sidewall of the first pillar along a line perpendicular to a sidewall of the first pillar, the first distance being greater than a distance from the first barrier layer to the second barrier layer., 'a joint structure physically and electrically connecting the first pillar to the second ...

FABRICATING PROCESS OF A CHIP PACKAGE STRUCTURE

A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Flip chip interconnection structure

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Intermetallic compound layer on a pillar between a chip and substrate

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Stud bump structure and method for manufacturing the same

A stud bump structure and method for manufacturing the same are provided. The stud bump structure includes a substrate, and a first silver alloy stud bump disposed on the substrate, wherein the first silver alloy stud bump has a weight percentage ratio of Ag:Au:Pd=60-99.98:0.01-30:0.01-10.

Device packaging with substrates having embedded lines and metal defined pads

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Semiconductor device

MANUFACTORING PROCESS OF TWO SUBSTRATES CONNECT BY AT LEAST A MECHANICAL CONNECTION AND ELECTRICALLY CONDUCTING OBTAINED

HYBRIDIZATION TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEAL UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : ▪ à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; ▪ à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; ▪ à reporter les premier et second composants (12, 14) l'un sur l'autre ; et ▪ à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en œuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre.

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

Surface mounting semiconductor component, chip scale semiconductor package assembly, and surface mounting method

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

3di solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Flip-chip device

Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

Circuit substrate

A circuit substrate that includes a substrate having a major surface, a multilayer body on the major surface, and an insulating layer that covers the major surface. The multilayer body includes a first layer and a second layer that overlies the first layer. The first layer is made of a first metal as a main material thereof, and the second layer is made of a second metal as a main material thereof. The second metal has a higher solder wettability than the first metal. As viewed perpendicular to the major surface, the insulating layer is spaced from and surrounds the surface of the second layer so as to define a recess between the multilayer body and the insulating layer.

3D-JOINING OF MICROELECTRONIC COMPONENTS WITH CONDUCTIVELY SELF-ADJUSTING ANISOTROPIC MATRIX

... 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

CIRCUIT SUBSTRATE

A circuit substrate that includes a substrate having a major surface, a multilayer body on the major surface, and an insulating layer that covers the major surface. The multilayer body includes a first layer and a second layer that overlies the first layer. The first layer is made of a first metal as a main material thereof, and the second layer is made of a second metal as a main material thereof. The second metal has a higher solder wettability than the first metal. As viewed perpendicular to the major surface, the insulating layer is spaced from and surrounds the surface of the second layer so as to define a recess between the multilayer body and the insulating layer.

3D-joining of microelectronic components with conductively self-adjusting anisotropic matrix

... 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

Semiconductor chip stack and method for manufacturing semiconductor chip stack

A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.

Chip Package Structure, Terminal Device, and Method

A chip package apparatus includes a substrate, a chip on the substrate, and a filling layer on the substrate and surrounding a portion of the chip. The filling layer is made of epoxy molding compound (EMC) and the EMC is white. An electronic device with the chip package apparatus and a method for manufacturing the chip apparatus structure are provided. 1. A chip package apparatus , comprising:a substrate;a chip on the substrate; anda filling layer on the substrate and surrounding a portion of the chip, and the filling layer being made of epoxy molding compound and the epoxy molding compound being white.2. The chip package apparatus of claim 1 , wherein the chip is coupled with the substrate through solder balls claim 1 , and the solder balls are disposed on the substrate in array.3. The chip package apparatus of claim 1 , wherein the chip is coupled with the substrate through conductive wires.4. The chip package apparatus of claim 3 , wherein the chip and the substrate are adhesively coupled through transparent optical adhesive.5. The chip package apparatus of claim 2 , wherein each solder ball has a diameter ranging from 0.22 mm to 0.3 mm or a distance between neighbor solder balls ranges from 0.46 mm to 0.55 mm.6. The chip package apparatus of claim 1 , wherein the chip package apparatus further comprises a reinforcement member disposed on the substrate to avoid the warpage of the substrate.7. The chip package apparatus of claim 6 , wherein the thermal conductivity of the reinforcement member is greater than that of the substrate.8. The chip package apparatus of claim 6 , wherein the substrate and the reinforcement member are adhesively coupled through transparent optical adhesive.9. An electronic device claim 6 , comprising:a white panel glass; anda chip package apparatus attached to the white panel glass, the chip package apparatus comprising:a substrate;a chip on the substrate; anda filling layer on the substrate and surrounding a portion of the chip, and the ...

Electronic device

An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

FLIPCHIP VERBINDUNGSSTRUKTUR AND ITS MANUFACTURING PROCESSES

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS TOGETHER, FLIP CHIP TYPE

L'invention concerne un procédé d'assemblage de type flip-chip, de deux composants microélectroniques (1,2) l'un à l'autre. Selon l'invention, on prévoit soit de dimensionner des cales (24) en sus des protubérances d'interconnexion (22) soit de sur-dimensionner ces dernières de sorte que leur déformation revienne élastique une fois le contact d'assemblage entre composants (1, 2) atteint, après avoir été plastique lors de l'insertion par des inserts (12) de connexion. Grâce à l'invention, on peut maîtriser très finement l'espacement entre les deux composants lors de leur assemblage et ceci sans ajouter d'étape supplémentaire à leur fabrication ni au process d'assemblage.

제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치

... 마이크로전자 조립체들 및 이의 제조 방법들이 본 명세서에 개시된다. 일 실시예에서, 마이크로전자 조립체의 형성 방법은 제1 및 제2 구성요소(102, 128)들의 제1 주 표면(104, 130)들이 서로 대면하고 사전결정된 간격만큼 서로 이격되도록 제1 및 제2 구성요소(102, 128)들을 조립하는 단계로서, 제1 구성요소(102)는 반대편을 향하는 제1 및 제2 주 표면(104, 106)들, 제1 주 표면(104)과 제2 주 표면(106) 사이에서 제1 방향으로 연장되는 제1 두께, 및 제1 주 표면(104)에 있는 복수의 제1 금속 접속 요소(112)들을 구비하고, 제2 구성요소(128)는 제2 구성요소(128)의 제1 주 표면(130)에 있는 복수의 제2 금속 접속 요소(132)들을 구비하는, 상기 제1 및 제2 구성요소들을 조립하는 단계; 및 이어서 각자의 제1 접속 요소(112)와 각자의 제1 접속 요소(112)의 반대편의 대응하는 제2 접속 요소(132) 사이에서 각각 제1 방향으로 연속적으로 연장되어 접속하는 복수의 금속 커넥터 영역(146)들을 도금(전기 도금 또 무전해 도금)하는 단계를 포함한다. 제1 및 제2 금속 접속 요소(112, 132)들은 구성요소(102, 128)들 내의 금속 비아(116, 134)들 또는 구성요소(102, 128)들의 표면에 있는 금속 패드(118)들을 포함할 수 있는데, 금속 비아(116, 134)들 또는 금속 패드(118)들은 도금 금속 영역(114)들에 의해 덮인다. 제1 시드 층(126)이 도금 공정 전에 제1 구성요소(102)의 주 표면 위에 놓이게 형성될 수 있는데, 여기서 금속 커넥터 영역(146)들을 도금한 후에 제1 시드 층(126)의 덮이지 않은 부분들이 제거된다. 유사하게, 제2 시드 층(144)이 제2 구성요소(128)의 주 표면 위에 놓이게 형성될 수 있다. 복수의 장벽 영역(152)들이 금속 커넥터 영역(146)들, 제1 도금 금속 영역(114)들 또는 제2 도금 금속 영역들 중 적어도 하나의 ...

도전 접속부재, 및 도전 접속부재의 제작방법

... 열사이클 특성이 우수한 금속 다공질체로 이루어지는 도전성 범프, 도전성 다이본드부 등의 도전 접속부재를 제공한다. 반도체소자의 전극 단자 또는 회로기판의 전극 단자의 접합면에 형성된 도전 접속부재로서, 상기 도전 접속부재가 평균 1차 입자직경 10∼500㎚의 금속 미립자(P)와, 유기용제(S), 또는 유기용제(S) 및 유기 바인더(R)로 이루어지는 유기 분산매(D)를 포함하는 도전성 페이스트를 가열처리하여 금속 미립자끼리가 결합되어 형성된 금속 다공질체이고, 상기 금속 다공질체의 공극률이 5∼35체적%이며, 상기 금속 다공질체를 구성하고 있는 금속 미립자의 평균입자직경이 10∼500㎚의 범위이며, 또한 상기 금속 미립자 사이에 존재하는 평균 공공직경이 1∼200㎚의 범위인 것을 특징으로 하는 도전 접속부재.

Semiconductor Packages and Methods of Fabricating the Same

Substrate, semiconductor chip, and semiconductor package having bump, and methods of fabricating the same

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

METAL BUMP JOINT STRUCTURE

Semiconductor device and production method therefor

A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.

MICROELECTRONIC ELEMENTS WITH COMPLIANT TERMINAL MOUNTINGS AND METHODS FOR MAKING THE SAME

A dielectric structure is formed by a molding process, so that a first surface (32, 432) of a dielectric structure is shaped by contact with the mold. The opposite second surface (34, 434) of the dielectric structure is applied onto the front surface of a wafer element (38, 438). The dielectric structure may include protruding bumps (30, 130, 230) and terminals (44, 144, 244) may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts (213, 413) which extend above a surrounding solder mask layer (248, 448) to facilitate engagement with a test fixture. The posts are immersed within solder joints (274) when the structure is bonded to a circuit panel.

PACKAGE WITH CONDUCTIVE UNDERFILL GROUND PLANE

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung

Das Verfahren zum Herstellen einer Halbleitereinrichtung enthält: Bilden einer Öffnung in einem Gebiet von zumindest einem von dem komplementären Metalloxidhalbleiterwafer, der einen ersten Teil enthält, und dem anderen Halbleiterwafer, der einen zweiten Teil enthält, wobei die Öffnung innerhalb des Gebiets endet und nicht das Gebiet durchdringt, wobei das Gebiet ein entsprechendes des ersten Teils und des zweiten Teils und einen äußeren peripheren Teil des entsprechenden einen des ersten Teils und des zweiten Teils enthält; Bilden eines Leitungslochs innerhalb des ersten Teils, wobei das Leitungsloch mit einem metallischen Material in dem komplementären Metalloxidhalbleiterwafer in Verbindung steht; Anbringen eines ersten Verbindungsmaterials innerhalb des Leitungslochs und auf dem ersten Teil und eines zweiten Verbindungsmaterials auf dem zweiten Teil; und Verbinden des angebrachten ersten Verbindungsmaterials und des angebrachten zweiten Verbindungsmaterials.

Can not be remove the bump non-lead package

작은 간극 내의 상호접속 구조체의 국소화된 밀봉

... 장치는 일반적으로 마이크로전자 디바이스에 관한 것이다. 그러한 장치에서, 제1 기판이 제1 표면을 갖고, 제1 표면 상에 제1 상호접속부들이 위치되며, 제2 기판이 제1 표면으로부터 이격되는 제2 표면을 갖고, 제1 표면과 제2 표면 사이에 간극이 있다. 제2 상호접속부들이 제2 표면 상에 위치된다. 제1 상호접속부들의 하부 표면들과 제2 상호접속부들의 상부 표면들이 제1 기판과 제2 기판 사이의 전기 전도성을 위해 서로 결합된다. 전도성 칼라가 제1 및 제2 상호접속부들의 측벽들 주위에 있고, 유전체 층이 전도성 칼라 주위에 있다.

Semiconductor apparatus, and method of manufacturing semiconductor apparatus

A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD

A flip chip mounting method and a bump forming method which are applicable to next generation LSI flip chip mounting and have high productivity and reliability. A resin (14) containing a solder powder (16) and an air bubble generating agent is supplied to a space between a circuit board (21) having a plurality of connecting terminals (11) and a semiconductor chip (20) having a plurality of electrode terminals (12). Then, the resin (14) is heated and air bubbles (30) are generated from the air bubble generating agent contained in the resin (14). The resin (14) is pushed to the outside of the air bubbles by growth of the generated air bubbles (30), and are self-collected between the connecting terminals (11) and the electrode terminals (12). Furthermore, by heating the resin (14) and melting the solder powder (16) contained in the self-collected resin (14) between the terminals, a connector is formed between the terminals and a flip chip mounting body is completed.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Method of manufacturing a semiconductor apparatus

A method of making a semiconductor apparatus provides a plurality of electrode pads on a main surface of a semiconductor chip, and a plurality of bump electrodes on the electrode pads. The method also provides a wired board which is allocated in a side of the main surface of the chip and is positioned in a central area of the main surface of the chip so as to be separated from an edge part of the chip by at least 50 m or more, a plurality of external terminals on the wired board and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and a sealing part between the chip and the wired board, the sealing part being made of underfill material that covers a connection part between the bump electrode and the wiring.

Chip packages with sintered interconnects formed out of pads

The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.

Localized sealing of interconnect structures in small gaps

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

SUBSTRATE ON SUBSTRATE PACKAGE

Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.

Flexible package-to-socket interposer

A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.

SURFACE MOUNTING SEMICONDUCTOR COMPONENTS

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. 1. A surface mounting semiconductor component , comprising:a semiconductor device including a plurality of die pads on a first mounting surface;a circuit board including a plurality of contact pads on a second mounting surface;a plurality of first solder bumps configured to bond the semiconductor device and the circuit board through a first type of the plurality of die pads; anda plurality of second solder bumps configured to bond the semiconductor device and the circuit board through a second type of the plurality of die pads,wherein the first type of the plurality of die pads are arranged symmetrically to a center of the first mounting surface.2. The component of claim 1 , wherein a size of each of the first type of the plurality of die pads is smaller than a size of each of the second type of the plurality of die pads.3. The component of claim 2 , wherein each of the first solder bumps comprises substantially identical volume to each of the second solder bumps.4. The component of claim 2 , wherein the first type of the plurality of die pads are arranged in a polygonal pattern on the first mounting surface.5. The component of claim 2 , wherein a first gap between adjacent first solder bumps is smaller than a second gap between adjacent second solder bumps.6. The component of claim 1 , further comprising a trace connecting at least two first type of the plurality of die pads.7. The component of claim 6 , further comprising a ...

Substrat-auf-Substrat-Package

Ausführungsformen hierin können eine PoINT(Patch on Interposer)-Architektur betreffen. Bei Ausführungsformen kann die PoINT-Architektur mehrere Lotfügestellen zwischen einem Patch und einem Interposer enthalten. Die Lotfügestellen können eine Lotkugel für eine relativ hohe Temperatur und eine Lötpaste für eine relativ niedrige Temperatur, die die Lotkugel umgibt, enthalten. Es können andere Ausführungsformen beschrieben und/oder beansprucht werden.

CHIPKARTENMODUL, CHIPKARTE, CHIPKARTENANORDNUNG, VERFAHREN ZUM AUSBILDEN EINES CHIPKARTENMODULS UND VERFAHREN ZUM AUSBILDEN EINER CHIPKARTE

Es wird ein Chipkartenmodul bereitgestellt. Das Chipkartenmodul kann Folgendes enthalten: einen Träger mit einer ersten Seite und einer gegenüberliegenden zweiten Seite; einen Chip, der über dem Träger angeordnet ist, wobei der Chip einen ersten Chipkontakt besitzt; einen ersten und einen zweiten Antennenkontakt, über der ersten Seite ausgebildet; einen metallfreien Bereich, der über der ersten Seite zwischen dem ersten Antennenkontakt und dem zweiten Antennenkontakt ausgebildet ist, wobei sich der metallfreie Bereich zwischen einem ersten Kantenabschnitt und einem zweiten Kantenabschnitt des Trägers erstreckt; und eine erste Chipverbindung, die den ersten Chipkontakt elektrisch mit dem ersten Antennenkontakt verbindet, wobei die erste Chipverbindung mindestens teilweise über der zweiten Seite in einem Gebiet gegenüber dem metallfreien Bereich angeordnet ist.

HYBRIDIZATION FACE-TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEALING UV

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS TOGETHER, FLIP CHIP TYPE

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

Technique for controlling positions of stacked dies

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.

Integrated circuit package system with leadfinger support

An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.

No flow underfill

A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.

Method of yield prejudgment and bump re-assignment and computer readable storage medium

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving reliability in connection between a wiring pattern and a bump electrode. SOLUTION: The semiconductor device is provided with a film substrate having the wiring pattern on the surface thereof, a semiconductor chip having an electrode on the surface thereof and mounted on the film substrate, and insulating resin previously applied on the film substrate or the semiconductor chip and filled between the film substrate and the semiconductor chip after mounting the semiconductor chip, while the wiring pattern is provided with a projection having a sectional configuration tapered off toward the electrode of the semiconductor chip and the projection invades into the electrode whereby the projection is electrically connected to the electrode. COPYRIGHT: (C)2005,JPO&NCIPI ...

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

METHOD FOR EXCHANGING A SEMICONDUCTOR CHIP OF A FLIP-CHIP MODULE AND A FLIP-CHIP MODULE SUITABLE THEREFOR

The present invention relates to a method for exchanging a semiconductor chip of such a flip-chip module, and to a suitable flip-chip module and a device for performing the method. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip has contact pillars arranged at a surface approximately perpendicularly to the surface. It is connected by said contact pillars to contact locations of the substrate via a soldering connection. The end faces of the contact pillars completely cover the contact locations. This makes it possible to press the solder between the contact pillars and contact locations after renewed heating completely from the intermediate region between the contact locations and the contact pillars. This permits a renewed fixing of a further semiconductor chip.

Chip stack with electrically insulating walls

A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Flip chip interconnection structure

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Under bump passives in wafer level packaging

반도체 소자 및 그 제조 방법

... 반도체 소자는 다이의 표면위에 형성된 다수의 복합 범프를 구비한 반도체 다이를 갖는다. 상기 복합 범프는 전도성 필라 및 그 위에 형성된 범프와 같은 가용성부 및 비가용성부를 갖는다. 복합 범프는 또한 테이퍼질 수 있다. 전도성 트레이스가 이스케이프 라우팅 밀도를 증가시키기 위해 평면으로부터 전도성 트레이스에 평행한 에지를 갖는 상호접속 사이트를 구비한 상태로 기판 위에 형성된다. 상호접속 사이트는 전도성 트레이스 폭의 1.2 배 이하의 폭을 가질 수 있다. 복합 범프는 상호접속 사이트보다 넓다. 복합 범프의 가용성부는 상호접속 사이트에 결합되어 가용성부가 상호접속 사이트의 정상부 및 측부를 커버한다. 봉지재가 반도체 다이 및 기판 사이의 복합 범프 주위에 전착된다.

EMIB 칩 상호접속을 위한 방법 및 프로세스

... 집적 회로(IC)를 IC 패키지 기판에 부착하기 위한 방법은, IC 다이의 본드 패드 상에 솔더 범프를 형성하는 단계와, IC 패키지 기판의 본드 패드 상에 솔더 웨이팅 돌출부를 형성하는 단계와, IC 패키지 기판의 솔더 웨이팅 돌출부에 IC 다이의 솔더 범프를 본딩하는 단계를 포함한다.

Reliable device assembly

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Semiconductor devices

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A plurality of first electrodes (107) is formed on a first substrate (101). A first insulating film (108) is formed on the side walls of each of the first electrodes (107). The first insulating film (108) is formed so that the spaces between the first electrodes (107) are not filled.

Semiconductor device and production method therefor

A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.

Copper post solder bumps on substrates

A method of assembling a semiconductor flip chip comprising a wafer having solderable electrical conducting sites and a substrate having electrical connecting pads and electrically conductive posts operatively associated with the pads and extending away from the pads to terminate in distal ends, comprises the pre-assembly steps of solder bumping the distal ends through openings in a solder mask by injection molding solder onto the distal ends so that the distal ends extend into the mask through the openings to produce a solder bumped substrate, and soldering the solder bumped substrate to the sites.

RELIABLE DEVICE ASSEMBLY

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Semiconductor package and method for manufacturing the same

The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.

Semiconductor test interconnect with variable flexure contacts

An interconnect for testing semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses. The interconnect can be used to construct a wafer level ...

SEMICONDUCTOR DEVICE WITH TALL AND SLENDER INTERCONNECTING BUMPS AND CORRESPONDING MANUFACTURING METHOD

A semiconductor device (100) includes a first plate-like element (104) having a first substantially planar connection surface (112) with a first connection pad (114) and a second plate-like element (102) having a second substantially planar connection surface (110) with a second connection pad (114) corresponding to the first connection pad (114); and a connection (106+108) electrically and physically coupling the first and second plate-like elements (104, 102) and arranged between the first and second connection pads (114). The connection (106+108) includes an elongate element (108) arranged on the first connection pad (114) and extending toward the second connection pad (114) and solder (106) in contact with the second connection pad (114) and the elongate element (108). The first or second plate-like element (104, 102) may comprise a die, in particular, a bridge die. An electronic system (800) may comprise the semiconductor device (100) and an electrical component electrically coupled ...

POROUS FIRST LEVEL INTERCONNECT (FLI) BUMPS FOR REDUCING BUMP THICKNESS VARIATION SENSITIVITY TO ENABLE BUMP PITCH SCALING

Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

Solder bump manufacturing method e.g. for use in wafer level package fabrication, involves forming two reinforcing protrusions upwardly extending from chip and mounting substrate, respectively, that are embedded in solder material

Two reinforcing protrusions (311,311) are formed extending upwardly from contact pad (102) of semiconductor chip (101), and from ball pad (108) of mounting substrate (109), respectively. The two protrusions are embedded in a solder material (105). Independent claims are also included for the following: (1) solder bump structure; (2) method of forming solder bump connection between semiconductor chip and mounting substrate; and (3) semiconductor device.

VERFAHREN ZUM HERSTELLEN EINER ELEKTRISCHEN VERBINDUNG, ELEKTRISCHE KONTAKTANORDNUNG UND ELEKTRISCHE VERBINDERANORDNUNG

Die vorliegende Erfindung betrifft ein Verfahren zum Herstellen einer elektrischen Verbindung, eine elektrische Kontaktanordnung und elektrische Verbinderanordnung, insbesondere für den Einsatz bei implantierbaren Komponenten. Das Verfahren zum Herstellen einer elektrischen Verbindung zwischen einem Kontaktträger (102) und einem zugehörigen Gegenkontaktträger (104) weist die folgenden Schritte auf: Herstellen des Kontaktträgers (102) mit mindestens einem elektrisch leitfähigen Kontaktelement (106) und mindestens einer Leiterbahn, die mit dem Kontaktelement verbunden ist, Bereitstellen des Gegenkontaktträgers (104), der mindestens ein elektrisch leitendes Gegenkontaktelement (108) aufweist und Positionieren des Kontaktträgers (102), so dass das mindestens eine Kontaktelement (106) und das mindestens eine Gegenkontaktelement (108) übereinander ausgerichtet sind, Anbringen einer Isolierlage (118, 154) zwischen dem Kontaktträger (102) und dem Gegenkontaktträger (104), so dass das Kontaktelement ...

Under bump passives in wafer level packaging

MANUFACTORING PROCESS OF TWO SUBSTRATES CONNECT BY AT LEAST A MECHANICAL CONNECTION AND ELECTRICALLY CONDUCTING OBTAINED

Un premier substrat (2) muni d'une zone d'accueil (1) en premier matériau métallique est fourni. Un second substrat (4) muni d'une zone d'insertion (3) comportant une surface de base (6) et au moins un plot (7) en un second matériau métallique est disposé en face du premier substrat (2). Le plot (7) fait sailli depuis la surface de base (6). Une pression est appliquée entre le premier substrat (2) et le second substrat (4) de manière à faire pénétrer le plot (7) à l'intérieur de la zone d'accueil (1). Le premier matériau métallique (5) réagit avec le second matériau métallique de manière à former une couche continue d'un composé intermétallique (5) à base des premier et second matériaux métalliques le long de l'interface entre le plot (7) et la zone d'accueil (1).

PROCESS FOR CONNECTING INTERCOMPOSANTS DENSITY OPTIMIZED

L'invention concerne un procédé de connexion électrique par hybridation d'un premier composant (100) à un deuxième composant (200). Le procédé comportant les étapes suivantes : formation de plots en matériau ductile (111, 121) en contact respectif des zones de connexion (110, 120) du premier composant (100) ; formation d'inserts (211, 221) en matériau conducteur en contact de des zones de connexion (210, 220) du deuxième composant (200) ; formation de barrières d'hybridation (212, 222) disposées entre les inserts (211, 221) et isolées électriquement l'une de l'autre, lesdites première et deuxième barrière d'hybridation (212, 222) pour faire office de barrière en contenant la déformation des plots en matériau ductile (111, 121) lors de la connexion des zones de connexion (210, 220) du premier composant (100) avec celles du deuxième composant (200). L'invention concerne en outre un ensemble (1) de deux composants (100, 200) connectés ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

... 반도체 칩(1)의 복수의 돌기형 전극(4)이, 반도체 기판(11)에 형성되어 있는 복수의 전극(13)에, 복수의 땜납부를 개재하여 맞닿은 상태로, 복수의 땜납부가 용융하여, 반도체 칩(1)의 복수의 돌기형 전극(4)과 반도체 기판(11)의 복수의 전극(13)에 접합하는 복수의 땜납 접합부(7)가 형성된다. 다음에, 반도체 칩(1)의 일부분과 반도체 기판(11) 사이의 간격(A)이, 반도체 칩(1)의 다른 부분과 반도체 기판(11) 사이의 간격(B)보다 커져, 복수의 땜납 접합부(7) 중 적어도 일부의 땜납 접합부가 길게 늘어난다. 이에 의해, 복수의 땜납 접합부(7)의 높이에, 편차가 발생한다. 다음에, 복수의 땜납 접합부(7) 중, 적어도, 높이가 최대가 되는 땜납 접합부(7a) 내에, 공공(8)이 형성된다. 그 후, 복수의 땜납 접합부(7)가 응고한다.

ELECTRONIC COMPONENT, ELECTRONIC APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHOD OF THE ELECTRONIC APPARATUS

... 전자 부품간을 높은 신뢰성으로 접합한다. 전자 부품(1A)은, 전극부(21)와, 그 위에 형성된 땜납(22)을 구비한다. 전극부(21)는, 그 상면에 땜납(22)의 성분에 대한 확산 계수가 상이한 도전부, 예를 들면 배리어 메탈(21b)과 그 위에 형성된 돌기(21c)를 갖는다. 땜납(22)은, 전극부(21)의 배리어 메탈(21b)과 돌기(21c) 위에 형성된다. 상대측 부품과의 접합 시에는, 돌기(21c)에서 우선적으로 땜납(22)의 성분의 확산 및 반응이 발생하여, 전극부(21)의 상면으로부터 측면으로의 땜납(22)의 성분의 확산이 억제되어, 부품간의 접합부의 파단이 억제된다.

본딩 구조물 및 그 형성 방법

... 방법은 도전성 패드 위에 제 1 유전체 층을 형성하는 단계, 제 1 유전체 층 위에 제 2 유전체 층을 형성하는 단계, 및 제 2 유전체 층을 에칭하여 제 1 개구부를 형성하는 단계를 포함하며, 제 1 유전체 층의 최상면이 제 1 개구부에 노출된다. 템플릿 층은 제 1 개구부를 채우도록 형성된다. 그 후, 제 2 개구부가 템플릿 층 및 제 1 유전체 층 내에 형성되고, 도전성 패드의 최상면이 제 2 개구부에 노출된다. 도전성 필러는 제 2 개구부 내에 형성된다.

FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD

SEMICONDUCTOR DEVICE

According to embodiments of the present invention, a semiconductor device comprises: a semiconductor chip; pads provided on the semiconductor chip; insulation patterns provided on the semiconductor chip, and having openings for exposing the pads; and conductive patterns provided in the openings, and connected to the pads. In a plan view, both ends of the pads cannot be overlapped with the conductive patterns, and both ends of the conductive patterns cannot be overlapped with the pads. The conductive patterns include: a first conductive pattern having a major axis parallel to a first direction; and a second conductive pattern having a major axis parallel to a second direction in a plan view, wherein the second direction can intersect with the first direction. COPYRIGHT KIPO 2018 ...

METHOD OF FORMING A MICROELECTRONIC ASSEMBLY BY PLATING METAL CONNECTORS AFTER ASSEMBLYING FIRST AND SECOND COMPONENTS AND CORRESPONDING DEVICE

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises: assembling first and second components (102, 128) to have first major surfaces (104, 130) of the first and second components (102, 128) facing one another and spaced apart from one another by a predetermined spacing, the first component (102) having first and second oppositely-facing major surfaces (104, 106), a first thickness extending in a first direction between the first and second major surfaces (104, 106), and a plurality of first metal connection elements (112) at the first major surface (104), the second component (128) having a plurality of second metal connection elements (132) at the first major surface (130) of the second component (128); and then plating (electroplating or electroless plating) a plurality of metal connector regions (146) each connecting and extending continuously between a respective first connection ...

Semiconductor packages having interconnection members

A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

Semiconductor device

PROCESS Of ASSEMBLY OF TWO Electronics components

PROCESS Of ASSEMBLY OF TWO Electronics components

Ce procédé d'assemblage de deux composants électroniques (12, 16) par insertion d'inserts creux et ouverts (50) dans des éléments pleins convexes (14) de dureté inférieure à celle des inserts, consiste, lors de l'insertion d'un insert (50) dans un élément plein (14), à ce qu'au moins une surface (52) de l'extrémité ouverte (54) de l'insert (50) soit laissée libre de manière à créer un passage de sortie pour des gaz contenus dans l'insert (50).

솔더링 연결핀, 상기 솔더링 연결핀을 이용한 반도체 패키지 기판 및 반도체칩의 실장방법

... 본 발명은 솔더링 연결핀, 상기 솔더링 연결핀을 이용한 반도체 패키지 기판 및 반도체칩의 실장방법에 관한 것으로 인쇄회로기판의 관통홀에 삽입된 솔더링 연결핀을 이용하여 반도체칩을 인쇄회로기판에 실장함으로써, 반도체 패키지 기판의 변형 및 외부충격에 의한 피로파괴를 방지한다.

METHOD FOR EXCHANGING A SEMICONDUCTOR CHIP OF A FLIP-CHIP MODULE AND A FLIP-CHIP MODULE SUITABLE THEREFOR

The present invention relates to a method for exchanging a semiconductor chip of such a flip-chip module, and to a suitable flip-chip module and a device for performing the method. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip has contact pillars arranged at a surface approximately perpendicularly to the surface. It is connected by said contact pillars to contact locations of the substrate via a soldering connection. The end faces of the contact pillars completely cover the contact locations. This makes it possible to press the solder between the contact pillars and contact locations after renewed heating completely from the intermediate region between the contact locations and the contact pillars. This permits a renewed fixing of a further semiconductor chip. © KIPO & WIPO 2009 ...

Semiconductor package and stacked semiconductor package

Semiconductor Structures and Method for Fabricating the Same

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Semiconductor package and stacked semiconductor package

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Flip packaging device

Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.

Bump-on-Trace Structures with High Assembly Yield

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μmand about 1,300 μm. 1. A package comprising: 'a first metal trace at a surface of the first package component, wherein the first metal trace has a trace width, with the trace width being measured in a direction perpendicular to a lengthwise direction of the first metal trace;', 'a first package component comprising a first portion, wherein the first portion has a first width smaller than the trace width; and', 'a second portion and a third portion on opposite sides of the first portion, wherein the second portion and the third portion have second widths greater than the first width; and, 'a second package component over the first package component, wherein the second package component comprises a metal bump, and the metal bump comprisesa solder region bonding the metal bump to the first metal trace.2. The package of claim 1 , wherein the second widths are further greater than the trace width.3. The package of claim 1 , wherein the solder region contacts a first portion of the first metal trace claim 1 , and a ratio of a volume of the solder region to the trace width is between about 1 claim 1 ,100 μmand about 1 claim 1 ,300 μm.4. The ...

LEAD-FREE SOLDER JOINING OF ELECTRONIC STRUCTURES

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate. 1. A method of joining a semiconductor structure comprising:forming a first low melting temperature lead free solder having a liquidus temperature less than 230° C. on a first substrate;placing a lead free ball comprising copper and tin having a liquidus temperature greater than 250° C. on the first low melting temperature lead free solder;reflowing the first low melting temperature lead free solder at a temperature lower than the liquidus temperature of the lead free ball;annealing at a temperature of 140 to 165° C. to convert the first low melting temperature lead free solder into a higher melting temperature lead free solder having a liquidus temperature of 240 to 250° C.;placing a second low melting temperature lead free solder having a liquidus temperature of 220° C. or less on a second substrate;placing the lead free ball in direct contact with the second low melting temperature lead free solder; andheating at 240 to 260° C. the semiconductor structure to cause the second low melting temperature lead free solder to reflow and join with the lead free ball.2. The method of wherein the first low melting temperature lead free solder and the second low melting temperature lead free solder each comprise an alloy of tin claim 1 , silver and copper.3. The method of wherein the lead free ball has a liquidus temperature of 250-280 C.4. The method of wherein the lead free ball is an alloy comprising tin/silver/nickel/copper/gold having the composition claim 1 , in weight percent claim 1 , of 0.01 to 6% copper ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate. 125-. (canceled)26. A method for attaching an integrated circuit (IC) to an IC package substrate , the method comprising:forming a solder bump on a bond pad of an IC die;forming a solder-wetting protrusion on a bond pad of an IC package substrate; andbonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.27. The method of claim 26 , wherein forming a solder-wetting protrusion on the bond pad of the IC package substrate includes laser direct deposition of the solder-wetting protrusion onto the bond pad of the IC package substrate.28. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging a film of solder-wetting material opposite the bond pad of the IC package substrate; andapplying laser energy to the film of solder-wetting material to transfer the solder-wetting material to the bond pad of the IC package substrate.29. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging, opposite the bond pad of the IC package substrate, a film having solder-wetting material on one side and a transparent material on the other side, and applying laser energy to the transparent side of the film.30. The method of claim 28 , wherein arranging a film of solder-wetting material includes arranging the film of solder-wetting material opposite a plurality of bond pads of one or more IC package substrates claim 28 , and wherein applying laser energy includes scanning a laser energy source to positions on the film of solder-wetting material opposite the plurality of bond pads and applying pulses of laser energy to the film of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder hump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump, ...

CHIP PACKAGE STRUCTURE WITH BUMP

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure. 1. A chip package structure , comprising:a redistribution structure;a first chip structure over the redistribution structure;a first solder bump between the redistribution structure and the first chip structure;a first molding layer surrounding the first chip structure;a second chip structure over the first chip structure;a second molding layer surrounding the second chip structure; anda third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, wherein the third molding layer is in direct contact with the first molding layer and the first solder bump, and is disposed at least partially between the first molding layer and the redistribution structure.2. The chip package structure as claimed in claim 1 , further comprising:a conductive pillar between the first chip structure and the first solder bump.3. The chip package structure as claimed in claim 2 , wherein the conductive pillar is in direct contact with the first chip structure and the first solder bump.4. The chip package structure as claimed in claim 2 , wherein the first solder bump is made of a first conductive material claim 2 , the conductive pillar is made of a second conductive ...

Flexible package-to-socket interposer

A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

CHIP CARD MODULE, CHIP CARD, CHIP CARD ARRANGEMENT, METHOD OF FORMING A CHIP CARD MODULE, AND METHOD OF FORMING A CHIP CARD

A chip card module is provided. The chip card module may include a carrier having a first side and an opposite second side, a chip arranged over the carrier, the chip having a first chip contact, a first and a second antenna contact formed over the first side, a metal-free area formed over the first side between the first antenna contact and the second antenna contact, wherein the metal-free area extends between a first edge portion and a second edge portion of the carrier, and a first chip connection electrically connecting the first chip contact to the first antenna contact, wherein the first chip connection is at least partially arranged over the second side in a region opposite the metal-free area. 1. A chip card module , comprising:a carrier having a first side and an opposite second side;a chip arranged over the carrier, the chip having a first chip contact;a first and a second antenna contact formed over the first side;a metal-free area formed over the first side between the first antenna contact and the second antenna contact, wherein the metal-free area extends between a first edge portion and a second edge portion of the carrier; anda first chip connection electrically connecting the first chip contact to the first antenna contact,wherein the first chip connection is at least partially arranged over the second side in a region opposite the metal-free area.2. The chip card module according to claim 1 ,wherein the first and the second antenna contacts may include through holes.3. The chip card module according to claim 1 ,wherein the metal-free area has a width of at least 1 mm.4. The chip card module according to claim 1 ,wherein the chip is arranged over the first side.5. A chip card module arrangement claim 1 , comprising: a carrier having a first side and an opposite second side;', 'a chip arranged over the carrier, the chip having a first chip contact;', 'a first and a second antenna contact formed over the first side;', 'a metal-free area formed over ...

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Backplane, Preparation Method Thereof, Backlight Module and Display Device

A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad. 1. A semiconductor package , comprising:a redistribution substrate that includes a dielectric pattern and a redistribution pattern in the dielectric pattern;a first substrate pad on a top surface of the redistribution substrate, the first substrate pad penetrating the dielectric pattern and being coupled to the redistribution pattern;a second substrate pad on the top surface of the redistribution substrate and spaced apart from the first substrate pad;a semiconductor chip on the redistribution substrate;a first connection terminal that connects the first substrate pad to one of chip pads of the semiconductor chip; anda second connection terminal that connects the second substrate pad to another one of the chip pads of the semiconductor chip,wherein a top surface of the second substrate pad is located at a level higher than a level of a top surface of the first substrate pad, andwherein a width of the second substrate pad is less than a width of the first substrate pad.2. The semiconductor package of claim 1 , whereinthe width of the first substrate pad is ...

Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components. 1. A semiconductor package comprising:a flexible substrate;a plurality of traces formed on said flexible substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties constructed in five layers, which are optimized for both diffusion bonding and soldering of passive components wherein a topmost layer of each said trace comprises gold; andat least one die mounted on said substrate wherein there is a diffusion bond between at least one of said plurality of traces and said at least one die.2. The semiconductor package according to claim 1 , wherein said diffusion bond is via a gold plated bump or a gold stud bump on said die.3. The package according to claim 1 , wherein said topmost layer of each said trace comprises gold having a purity of about 99.9% claim 1 , a hardness of about 100 HV claim 1 , and a thickness of between about 0.05 μm and 1.0 μm.4. The semiconductor package according to claim 3 , wherein a second layer of each of said traces next closest to said diffusion bond comprises palladium claim 3 , having a purity of 99.9% claim 3 , a hardness of between about 250 and 450 HV claim 3 , and a thickness of between about 0.05 μm and 1.0 μm.5. The semiconductor package according to claim 4 , wherein a third layer of each of said traces comprises gold having a purity of about 99.9% claim 4 , a hardness of about 100 HV claim 4 , and a thickness of between about 0.01 μm and 1.0 μm.6. The semiconductor ...

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

Light-emitting device, manufacturing method thereof and display module using the same

The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A package structure is provided. The package structure includes a substrate, a sensor device, an encapsulant and a signal blocking structure. The substrate has a signal passing area. The sensor device is disposed over the substrate. The sensor device has a first surface, a second surface opposite to the first surface and a sensing area located at the second surface. The second surface of the sensor device faces the substrate. The encapsulant covers the sensor device and the substrate. The signal blocking structure extends from the substrate into the encapsulant. 11. A package structure , comprising:a substrate having a signal passing area;a sensor device disposed over the substrate, wherein the sensor device has a first surface, a second surface opposite to the first surface and a sensing area located at the second surface, and wherein the second surface of the sensor device faces the substrate;an encapsulant covering the sensor device and the substrate; anda signal blocking structure extending from the substrate into the encapsulant.213. The package structure of claim 1 , wherein a distance D from a distal end of the signal blocking structure to the substrate is greater than a distance D from the second surface of the sensor device to the substrate.312. The package structure of claim 2 , wherein the distance D from the distal end of the signal blocking structure to the substrate is greater than a distance D from the first surface of the sensor device to the substrate.5. The package structure of claim 1 , wherein L is a smallest horizontal distance L from an edge of the sensing area to an edge of the signal passing area of the substrate claim 1 , G is a smallest horizontal distance from an edge of the first surface of the sensor device to the signal blocking structure claim 1 , and L>0.5G.6. The package structure of claim 5 , wherein L>G.7. The package structure of claim 1 , wherein the signal blocking structure surrounds the sensor device.8. The package structure ...

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package. 1. An electronic package , comprising:a first substrate;a first electronic component disposed on the first substrate;a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer, wherein the first conductive elements are different in structure from the second conductive elements; anda first encapsulant formed between the first substrate and the second substrate and encapsulating the first electronic component, the first conductive elements and the second conductive elements.2. The electronic package of claim 1 , wherein a ratio of a number of the first conductive elements to a number of the second conductive elements is 1:0.5 to 1:1.5.3. The electronic package of claim 1 , wherein the first conductive elements are metal bumps.4. The electronic package of claim 1 , wherein the first conductive elements are metal bumps encapsulated by a conductive material.5. The electronic package of claim 1 , wherein the second conductive elements are solder bumps.6. The electronic package of claim 1 , wherein the bonding layer is made of a thin film or a heat ...

Flip Chip Interconnection Structure

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer. 1. A method for forming a semiconductor device , the method comprising:forming a tilt surface on an edge each of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer; andforming a first conductive bump on the tilt surface, wherein the first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and a profile of the first conductive bump extends beyond a side surface of the edge.2. The method for forming a semiconductor device of claim 1 , wherein the at least one semiconductor substrate includes two semiconductor substrates claim 1 , the method further comprising:jointing the first conductive bumps of the two semiconductor substrates so as to connect the two semiconductor structures laterally.3. The method for forming a semiconductor device of claim 1 , wherein forming the tilt surface on the edge of the at least one semiconductor substrate comprises:providing a substrate;forming a passivation layer on the substrate;forming an inclined plane on an edge of the substrate;forming a metal layer on the passivation layer;patterning the metal layer to form a first conductor layer on the passivation layer, wherein an upper surface of a portion of the first conductor layer on the edge of the substrate is the tilt surface;forming a second conductor layer on the passivation layer and the first conductor layer, wherein the second ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width. 1. A semiconductor package , comprising:a sequential stack of a first semiconductor chip and a second semiconductor chip; anda first internal connection member that connects the first semiconductor chip to the second semiconductor chip, a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and', 'a first conductive pad on the first top surface,, 'wherein the first semiconductor chip includes'} a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and', 'a second conductive bump on the second bottom surface,, 'wherein the second semiconductor chip includes'}wherein the first internal connection member connects the first conductive pad to the second conductive bump,wherein the first conductive pad has a first width in one direction,wherein the second conductive bump has a second width in the one direction, andwherein the first width is smaller than the second width.2. The semiconductor package of claim 1 , wherein the first width is about 0.8 to 0.9 times the second width.3. The ...

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided. 17-. (canceled)8. A package structure , comprising:a circuit substrate;a semiconductor structure comprising an integrated circuit die comprising a plurality of bump pads and a plurality of conductive bumps disposed on the plurality of bump pads, each of the plurality of conductive bumps respectively comprising a first pillar portion disposed on one of the plurality of bump pads and a second pillar portion disposed on the first pillar portion, the second pillar portion being electrically connected to one of the plurality of bump pads through the first pillar portion respectively, a first width of the first pillar portion being greater than a second width of the second pillar portion, and the integrated circuit die being disposed on and electrically connected to the circuit substrate through the plurality of conductive bumps;a memory cube disposed on and electrically connected to the circuit substrate; andan insulating encapsulation laterally encapsulating the integrated circuit die and the memory cube, and a rear surface of the integrated circuit die being accessibly exposed from the insulating encapsulation.9. The package structure as claimed in claim 8 , wherein a ratio of a height of the plurality of conductive bumps to a thickness of the integrated circuit die ranges from about 0.05 to about 1.10. The ...

Chip Package Structure with Bump

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure. 1. A chip package structure , comprising:a first redistribution structure;a first chip structure over the first redistribution structure;a first solder bump between the first redistribution structure and the first chip structure;a first molding layer surrounding the first chip structure;a second redistribution structure over the first molding layer;a second chip structure over the second redistribution structure;a second molding layer surrounding the second chip structure; anda third molding layer surrounding the first molding layer, the second molding layer, the second redistribution structure, and the first solder bump, wherein the third molding layer is in direct contact with the first molding layer and the first solder bump, and is disposed at least partially between the first chip structure and the first redistribution structure.2. The structure of claim 1 , wherein lateral edges of the first molding layer are aligned with lateral edges of the second redistribution structure.3. The structure of claim 2 , wherein the lateral edges of the second redistribution structure are aligned with lateral edges of the second molding layer.4. The structure of claim 1 , wherein an upper surface of the ...

METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE

The present disclosure provides a method for preparing a semiconductor package. The method includes providing a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner. The method also includes forming a bump structure over the first upper surface, wherein the bump structure extends laterally across the first side of the first device. 1. A method for preparing a semiconductor package , comprising:providing a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner; andforming a bump structure over the first upper surface, wherein the bump structure extends laterally across the first side of the first device.2. The method for preparing a semiconductor package of claim 1 , comprising:forming a second upper surface and a second side in the first device, wherein the second upper surface and the second side form a second corner of the first device; andforming the bump structure over the second upper surface and extending laterally across the second side of the first device.3. The method for preparing a semiconductor package of claim 2 , wherein the first upper surface and the second upper surface are formed at different levels claim 2 , and the bump structure extends vertically from the first upper surface to the second upper surface of the first device.4. The method for preparing a semiconductor package of claim 1 , comprising:forming a missing corner in the first device; andforming the bump structure over the first upper surface and filling the missing corner.5. The method for preparing a semiconductor package of claim 1 , further comprising:providing a second device laterally adjacent to the first device, wherein the second device comprises a second upper surface and a second side, and the second upper surface and the second side form a second corner of the second device;wherein the bump structure extends laterally from ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

Substrate and Package Structure

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area. 1. A device comprising:a substrate comprising a first pad and a second pad, the first pad being disposed in a first region of the substrate, the second pad being disposed in a second region of the substrate, the first region being in an inner region of the substrate, the second region extending from the first region to a first edge of the substrate, the first pad and the second pad having a same first height, a first width of the first pad being greater than a second width of the second pad;a chip comprising a first bump and a second bump, the first bump and the second bump having a same third width;a first connector coupling the first bump to the first pad; anda second connector coupling the second bump to the second pad.2. The device of claim 1 , wherein the substrate further comprises a third pad claim 1 , the third pad being disposed in a third region of the substrate claim 1 , the third region extending from the second region to a second edge of the substrate claim 1 , the third pad having the first width claim 1 , and wherein the chip further comprises a third bump claim 1 , the third bump having the third width.3. The device of further comprising:a third connector coupling the third bump to the third pad.4. The device of claim 1 , wherein the first connector and the second connector are solder connectors.5. The device of claim 1 , wherein the substrate further comprises a plurality of first pads in the first region and a plurality of second pads in the second region claim 1 , each of the first pads having the first width claim 1 , each of the second pads having the second width claim 1 , wherein a width of the first region is about 80% of a width of the substrate claim 1 , and a width of the second region ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...

SEMICONDUCTOR DEVICE

A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape. 1. A semiconductor device comprising:a multilayer chip including a first semiconductor chip and a second semiconductor chip that are bonded together, whereina first electrode pad is provided on a principal surface of the first semiconductor chip,a first bump is provided on the first electrode pad,a second bump is provided on a principal surface of the second semiconductor chip and is bonded to the first bump,the first electrode pad has an opening,the opening and an entire peripheral portion of the opening form a stepped shape, andthe first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.2. The semiconductor device of claim 1 , whereinthe first electrode pad has a hollow cylindrical shape in plan view.3. The semiconductor device of claim 2 , whereinthe second bump has a diameter equal to or smaller than an inner diameter of the hollow cylindrical shape of the first electrode pad.4. The semiconductor device of claim 2 , further comprising:a first passivation layer that covers the first semiconductor chip, is sandwiched between the first bump and the first electrode pad, and has an opening in which the first electrode pad is exposed such that an end of the opening is located on the first electrode pad, whereinthe opening of the first passivation layer has a diameter ...

Bump-on-Trace Design for Enlarge Bump-to-Trace Distance

A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes an interconnection structure, an electronic component, a package body and an electrical contact. The dielectric layer has a top surface and a bottom surface. The dielectric layer defines a cavity extending from the bottom surface into the dielectric layer. A patterned conductive layer is disposed on the top surface of the dielectric layer. The conductive pad is at least partially disposed within the cavity and electrically connected to the patterned conductive layer. The conductive pad includes a first metal layer and a second metal layer. The second metal layer is disposed on the first metal layer and extends along a lateral surface of the first metal layer. The electronic component is electrically connected to the patterned conductive layer. The package body covers the electronic component and the patterned conductive layer. The electrical contact is electrically connected to the conductive pad.

PROCESS FOR MOLDING A BACK SIDE WAFER SINGULATION GUIDE

A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer. 1. A method comprising:forming a plurality of bump structures on a contact surface of a device layer of a substrate;forming a channel in the contact surface extending through the device layer into substrate material of the substrate;disposing an overmold on the contact surface and into the channel, the overmold disposed in the channel forming an overmold rib;removing the substrate material from a back side of the substrate to expose the overmold rib;forming an encapsulating layer on the back side of the substrate and over the overmold rib;thinning the encapsulating layer on the back side of the substrate to expose a surface of the overmold rib; andsingulating the substrate by cutting along the surface of the overmold rib.2. The method of claim 1 , wherein forming the plurality of bump structures further comprises electrically coupling the plurality of bump structures to a device in the device layer.3. The method of claim 1 , wherein the substrate further comprises a wafer and forming the channel further comprises forming the ...

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a method for manufacturing a semiconductor package that comprises a unit substrate, for example to which a semiconductor chip is attached, embedded in a base substrate on which a semiconductor device may be mounted. The base substrate may, for example, comprise vias between top and bottom surfaces thereof and/or vias between the top surface of the base substrate and a top surface of the unit substrate embedded within the base substrate. 1. A semiconductor package comprising:a unit substrate comprising a unit substrate top surface, a unit substrate bottom surface, and unit substrate side surfaces connecting the unit substrate top surface and the unit substrate bottom surface;a semiconductor die comprising a die top surface, a die bottom surface, and die side surfaces connecting the die top surface and the die bottom surface, wherein the die bottom surface is coupled to the unit substrate top surface;a base substrate comprising a base substrate top surface, a base substrate bottom surface, and base substrate side surfaces connecting the base substrate top surface and the base substrate bottom surface; anda semiconductor device coupled to the base substrate top surface,wherein the unit substrate and the semiconductor die are embedded in the base substrate, such that at least the top and side surfaces of the unit substrate and at least the side and top surfaces of the semiconductor die are contacted and surrounded by the base substrate.2. The semiconductor package of claim 1 , comprising a first electrically conductive via that extends between the unit substrate top surface and the base substrate top surface.3. The semiconductor package of claim 2 , comprising a second electrically conductive via that extends between the base substrate bottom surface and the base substrate top surface.4. The semiconductor package of claim 3 , wherein the second electrically conductive via comprises a vertical side extending completely through the base ...

Radio frequency (rf) apparatus

A radio-frequency (RF) apparatus that reduces signal reflections at input and output terminals is disclosed. The RF apparatus includes an assembly base and a semiconductor chip mounted on the assembly base in upside down. The semiconductor chip includes first to third metal layers and a top metal layer that provides a top ground layer and a pad. The pad is connected to the input or output terminals on the assembly base and extracts a signal line and a stub line in the third metal layer, where lines are transferred to the first metal layer. The semiconductor chip further includes an inner ground layer formed in the second metal line. The inner ground layer and the signal line just pulled out from the pad and formed in the third metal layer form a micro-strip line.

Chip package structure with bump

A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.

DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die. 1. An integrated chip (IC) , comprising:a substrate;a first die disposed over the substrate;a metal wire attached to a frontside of the first die; anda first plurality of die stopper bumps disposed along a backside of the first die, wherein the first plurality of die stopper bumps directly contacts the backside of the first die.2. The IC of claim 1 , further comprising:a housing structure disposed over the first die and surrounding sidewalls of the first die; anda plurality of housing stopper bumps directly contacting and disposed between the housing structure and the substrate, wherein the plurality of housing stopper bumps contacts a bottom surface of the housing structure and is configured to control an angle of operation of the housing structure.3. The IC of claim 2 , further comprising:a plurality of metal pads disposed along a lateral portion of an inner surface of the housing structure, wherein the lateral portion of the inner surface is above the bottom surface, wherein the backside of the first die is above the frontside of the first die, wherein the metal wire is attached to the plurality of metal pads, and wherein the first plurality of die stopper bumps directly contacts the plurality of metal pads.4. The IC of claim 1 , wherein each of the first plurality of die stopper bumps comprises a solder ball bump.5. The IC of claim 1 , wherein each of the first plurality of die stopper bumps comprises a stud bump claim 1 , wherein the stud bump comprises a lower portion and an upper portion claim 1 , wherein the lower ...

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A package structure , comprising:a first substrate;a second substrate;a pillar bump bonded to the first substrate and the second substrate, the pillar bump being electrically coupled to the first substrate and the second substrate, wherein the pillar bump comprises a pillar and a bonding layer, the pillar is a non-solder material having a higher reflow temperature than the bonding layer, the bonding layer is between the pillar and the second substrate, and the pillar includes a linear sidewall profile; andan elongated solder bump bonded to the first substrate and the second substrate, wherein a height of the elongated solder bump is substantially equal to a height of the pillar bump, wherein the elongated solder bump and the bonding layer are formed of a solder.2. The package structure of claim 1 , wherein the first substrate comprises a semiconductor die.3. The package structure of claim 2 , wherein the bonding layer is interposed between the pillar and the second substrate.4. The package structure of claim 1 , wherein the elongated solder bump has convex sidewalls.5. The package structure of claim 1 , wherein the elongated solder bump has a solder portion having a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated ...

Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnecdt

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components. 1. A method of manufacturing a semiconductor package comprising:providing a flexible substrate; electrolytically plating copper traces on said flexible substrate, said copper traces having a pitch of between about 15 μm and 30 μm;', 'immersion plating a first gold layer on top and side surfaces of said plurality of copper traces;', 'electroless plating a palladium layer on said nickel-phosphorus layer; and', 'immersion plating a second gold layer on said palladium layer;, 'forming a plurality of traces on said flexible substrate, said forming comprisingforming a gold bump on a die surface; anddiffusion bonding said die to at least one of said plurality of traces by thermal compression of said gold bump to complete said semiconductor package.2. The method according to wherein said copper has a purity of more than 99.9% and a hardness of about 100 HV and is plated to a thickness of between about 2 μm and 25 μm claim 1 , and preferably about 8 μm.3. The method according to wherein a pH of a gold solution used in said immersion plating said first gold layer is maintained at between about 7.5 and 9.5 and wherein said first gold layer comprises about 99.9% pure gold claim 1 , having a hardness of about 100 HV claim 1 , and a thickness of between about 0.01 μm and 1.0 μm claim 1 , and preferably about 0.06 μm.4. The method according to wherein a pH value of a palladium solution used in said electroless plating is maintained at between about 4.5 and 6.5 and wherein said palladium layer has a purity of ...

Semiconductor package process and structure thereof

A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.

Flow underfill for microelectronic packages

A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal.

BUMP BONDED CRYOGENIC CHIP CARRIER

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius. 1. A device comprising:a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region;a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; anda superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein at least one of the first or second stack of thin films are electrically conductive.3. The device of claim 1 , wherein the first stack of thin films has a first opposing film and a first connection film claim 1 , the first opposing film and the first connection film positioned on opposite ends of the stack of thin ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

Wiring substrate and semiconductor device

A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture. 1. A semiconductor device , comprising:a semiconductor chip; anda packaging substrate on which the semiconductor chip is mounted,wherein the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body,the packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, the plurality of wirings and the solder resist layer being provided on a front surface of the substrate body,the solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings,the plurality of solder-including electrodes include at least one gap control electrode, andthe at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along ...

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A method for forming a package structure , the method comprising:forming a pillar bump over a semiconductor die;forming a solder joint over the semiconductor die, wherein the pillar bump has a melting point higher than that of the solder joint; andbonding the pillar bump and the solder joint to a substrate through a reflow process, thereby forming an elongated solder joint, wherein a height of the elongated solder joint is substantially equal to a height of the pillar bump, wherein the elongated solder joint has a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder joint, and a second width at a second horizontal plane passing through a midpoint of the sidewall surface, and wherein a ratio of the second width to the first width is in a range from about 0.5 to about 1.1.2. The method of claim 1 , wherein the pillar bump is formed before the solder joint.3. The method of claim 1 , further comprising:forming a first conductive element over the semiconductor die before forming the solder joint, wherein forming the solder joint comprises forming the solder joint on the first conductive element; andforming a second conductive element over the semiconductor die before forming the pillar bump, wherein forming the pillar ...

System and Method for an Improved Fine Pitch Joint

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Microelectronics h-frame device

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

Apparatus and method for controlling cooling fan of vehicle

An apparatus and a method for controlling a cooling fan of a vehicle are capable of preventing a fan motor from being damaged by locking the fan motor in cold weather conditions. The apparatus includes: a fan motor driving the cooling fan; and a controller generating an operation signal for controlling the cooling fan and providing the operation signal to the fan motor, where the controller confirms an ignition-off time for which an ignition was turned off when the ignition is turned on, confirms a change rate of an air conditioner refrigerant pressure for a measurement time when the ignition-off time exceeds a decision-possible time and an intake air temperature is present within a predetermined temperature, and locks the fan motor depending on the change rate of the air conditioner refrigerant pressure.

Electronic element and electronic device comprising the same

A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 μm and less than or equal to 14 μm. In addition, the disclosure further provides an electronic device including the first electronic element. 1. A first electronic element , comprising:a first substrate having a first surface;a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; andan insulating layer disposed on the first surface, wherein the insulating layer comprises an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface,wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 μm and less than or equal to 14 μm.2. The first electronic element of claim 1 , wherein the first electrode pad comprises a first electrode layer and a second electrode layer claim 1 , the first electrode layer disposed between the first substrate and the second electrode layer claim 1 , and the second electrode layer electrically connects to the first ...

Semiconductor Devices Including Stacked Semiconductor Chips

A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other. 1. A semiconductor device comprising:a chip stack structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,wherein the first semiconductor chip comprises:a first substrate;a first circuit layer on a front surface of the first substrate; anda first connecting layer on the first circuit layer, the first connecting layer comprising a first metal pad electrically connected to the first circuit layer,wherein the second semiconductor chip comprises:a second substrate;a second circuit layer on a front surface of the second substrate; anda second connecting layer on the second circuit layer, the second connecting layer comprising a second metal pad electrically connected to the second circuit layer,wherein the first connecting layer and the second connecting layer face each other,wherein the first metal pad and the second metal pad are in contact with each other to couple the first and second semiconductor chips to each other,wherein the first metal pad comprises a plurality of first metal pad portions separated from each ...

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

MULTI-LAYER SHEET FOR MOLD UNDERFILL ENCAPSULATION, METHOD FOR MOLD UNDERFILL ENCAPSULATION, ELECTRONIC COMPONENT MOUNTING SUBSTRATE, AND PRODUCTION METHOD FOR ELECTRONIC COMPONENT

[Problem] To provide a multi-layer sheet for mold underfill encapsulation, which exhibits good infiltrability between electrodes. [Solution] In order to solve the aforementioned problem, the present invention provides a multi-layer sheet for mold underfill encapsulation, which is characterized by having provided as an outermost layer thereof an (A) layer that comprises a resin composition having a local maximum loss tangent (tan δ) value of 3 or more at a measurement temperature of 125° C. for a measurement time of 0-100 seconds. 1. A multi-layer sheet for mold underfill encapsulation , the multi-layer sheet comprising the following (A)-layer as an outermost layer:(A)-layer: a layer formed from a resin composition having a local maximum value of tan δ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.2. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a filler claim 1 , and the maximum particle size of the filler is 20 μm or less.3. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a curing accelerator whose median diameter (D50) at a cumulative volume of 50% in the volume particle size distribution is 10 μm or less.4. The multi-layer sheet according to claim 1 , wherein the thickness of the (A)-layer is 10 to 500 μm.5. The multi-layer sheet according to claim 1 , further comprising the following (B)-layer:(B)-layer: a layer formed from a resin composition satisfying the following Formula (1), {'br': None, 'i': 'E′≤', '40000≤α×250000 [Pa/K]\u2003\u2003(1)'}, 'in the following Formula (1), “α” represents the coefficient of thermal expansion α [ppm/K] at 80° C. or lower of a thermoset product obtained after subjecting the resin composition to a thermosetting treatment at 175° C. for one hour; and “E′” represents the storage modulus E′ [GPa] at 25° C. of the thermoset product.'}6. The multi-layer sheet according to claim 5 , wherein the ratio (B/A) of the ...

LEAD-FREE SOLDER JOINING OF ELECTRONIC STRUCTURES

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate. 1. A method of joining a semiconductor structure comprising:forming an underbump metallurgy comprising a metal on a semiconductor device;forming lead free solder on the underbump metallurgy, the lead free solder comprising an alloy of tin and bismuth of the composition at least 85 weight percent bismuth, remainder tin;reflowing the lead free solder at 240-260° C. so that the lead free solder reflows to form solder bumps and react with the underbump metallurgy to raise the liquidus temperature of the solder bumps by incorporating the metal from the underbump metallurgy;forming pads of a low melting temperature lead free solder on a substrate, the solder comprising an alloy of tin, bismuth and silver with the composition 56-58 weight percent bismuth, 0.5-1.5 weight percent silver, remainder tin; andjoining the reflowed bumps to the pads of solder at 200 to 230° C.2. The method of wherein the liquidus temperature of the solder bumps is raised from below 250° C. to over 260° C.3. The method of further comprising annealing the semiconductor structure at 140 to 165° C.4. The method of wherein the underbump metallurgy is copper or nickel.5. The method of wherein the solder comprises 5 to 10 weight percent of a final joint mass comprising the solder bumps and the solder.6. The method of wherein the substrate is a chip scale package.7. A semiconductor structure comprising:a semiconductor device having an underbump metallurgy comprising a metal;a plurality of lead free solder bumps on, and alloyed with, the underbump ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

High density package interconnects

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A method of forming a bump-on-trace (BOT) assembly , comprising:forming a landing trace on a substrate;positioning a conductive pillar over the landing trace such that the conductive pillar extends at least to an end of the landing trace; andreflowing a solder feature between the landing trace and the conductive pillar to electrically couple the landing trace to the conductive pillar.2. The method of claim 1 , further comprising positioning the conductive pillar over the landing trace such that the conductive pillar overhangs the end of the landing trace.3. The method of claim 1 , further comprising positioning the conductive pillar such that a length of the landing trace within a conductive pillar periphery is about 20% to about 100% of a diameter of the conductive pillar.4. The method of claim 1 , further comprising positioning the conductive pillar such that a length of the landing trace within a conductive pillar periphery is less than a diameter of the conductive pillar.5. The method of claim 1 , further comprising reducing a length of the landing trace relative to a length of a neighboring trace prior to the positioning of the conductive pillar.6. The method of claim 1 , further comprising removing a portion of the landing trace to generate an augmented wetting area ...

Wafer to Wafer Bonding Process and Structures

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 126-. (canceled)27. A method for forming an interconnect , comprising:providing a first metal bump electrically coupled to an I/O signal region on a die, the first metal bump including a solder resistant coating that covers a first portion of the first metal bump and leaves a second portion of the first metal bump uncovered;providing a substrate having a first pad, the first pad having a pad width;forming a solder connection between the first metal bump and the first pad, wherein the solder connection includes an interface between the solder connection and the second portion of the first metal bump, the interface having a width; andwherein the solder connection is controlled so that the width of the interface between the solder connection and the second portion of the first metal bump is greater than the pad width of the first pad.28. The method of claim 27 , further comprising:providing a second metal bump electrically coupled to a power region on the die, the second metal bump including a solder resistant coating that covers a first portion of the second metal bump and leaves a second portion of the second metal bump uncovered;providing a second pad on the substrate, the second pad having a pad width;forming a second solder connection between the second metal bump and the second pad, wherein the second solder connection includes an interface between the second solder connection and the second portion of the second metal bump, the interface having a width; andwherein the second solder connection is ...

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A method of forming a bump-on-trace (BOT) assembly , the method comprising:forming a landing trace on a substrate, the landing trace having a first portion, a second portion, and a third portion connecting the first portion to the second portion in a plan view, a first sidewall of the first portion being collinear with a first sidewall of the second portion and a first sidewall of the third portion in the plan view, a second sidewall of the first portion being collinear with a second sidewall of the second portion and a second sidewall of the third portion in the plan view, the second portion having a plurality of indents in the plan view;positioning a conductive pillar over the second portion of the landing trace such that the conductive pillar completely overlies the plurality of indents in the second portion of the landing trace; andreflowing a solder feature between the landing trace and the conductive pillar to electrically couple the landing trace to the conductive pillar.2. The method of claim 1 , wherein at least one indent of the plurality of indents are in the first sidewall of the second portion.3. The method of claim 2 , wherein at least one indent of the plurality of indents are in the second sidewall of the second portion.4. The method of claim 1 , wherein the ...

3D IMAGE SENSOR

A three-dimensional (3D) image sensor includes a first substrate having an upper pixel. The upper pixel includes a photoelectric element and first and second photogates connected to the photoelectric element. A second substrate includes a lower pixel, which corresponds to the upper pixel, that is spaced apart from the first substrate in a vertical direction. The lower pixel includes a first transfer transistor that transmits a first signal provided by the first photogate. A first source follower generates a first output signal in accordance with the first signal. A second transfer transistor transmits a second signal provided by the second photogate. A second source follower generates a second output signal in accordance with the second signal. First and second bonding conductors are disposed between the first and second substrates and electrically connect the upper and lower pixels. 1. A three-dimensional (3D) image sensor comprising:a first substrate including an upper pixel array, a plurality of upper pixels of the upper pixel array are disposed in first rows and first columns of a first arrangement;a second substrate including a lower pixel array including a plurality of lower pixels; anda bonding conductor array disposed between the first and second substrates, a plurality of bonding conductors of the bonding conductor array are disposed in second rows and second columns of a second arrangement and electrically connected between the upper pixel array and the lower pixel array,wherein the second arrangement is inclined with respect to the first arrangement.2. The 3D image sensor of claim 1 , wherein:the second arrangement is inclined at an angle of 45° with respect to the first arrangement.3. The 3D image sensor of claim 1 , wherein the number of the bonding conductors in a pixel unit is same as the number of photogates in the upper pixel of the pixel unit.4. The 3D image sensor of claim 1 , wherein horizontal cross sections of the upper and lower pixels are in ...

SEMICONDUCTOR PACKAGE AND METHOD FOR PREPARING THE SAME

A semiconductor package includes a first device and a bump structure disposed over the first device. In some embodiments, the first device has a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device. In some embodiments, the bump structure is disposed over the first upper surface and extends laterally across the first side of the first device. The lateral extension of the bump structure across the first side of the semiconductor device can contact a corresponding conductor of a laterally adjacent device to implement a lateral signal path between the semiconductor device and the laterally adjacent device in the absence of a redistribution structure corresponding to the redistribution layer. 1. A semiconductor package , comprising:a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device; anda bump structure disposed over the first upper surface, wherein the bump structure extends laterally across the first side of the first device.2. The semiconductor package of claim 1 , wherein the first device comprises a second upper surface and a second side claim 1 , the second upper surface and the second side form a second corner of the first device claim 1 , and the bump structure is disposed over the second upper surface and extends laterally across the second side of the first device.3. The semiconductor package of claim 2 , wherein the first upper surface and the second upper surface are at different levels claim 2 , and the bump structure extends vertically from the first upper surface to the second upper surface of the first device.4. The semiconductor package of claim 1 , wherein the first device comprises a missing corner claim 1 , and the bump structure fills the missing corner.5. The semiconductor package of claim 1 , wherein the first side is substantially perpendicular to the first upper surface.6 ...

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Semiconductor packages and methods of forming the same may be provided. According to the semiconductor package of the present inventive concepts, a bump attached to and protruded from a bonding pad on a surface of a semiconductor chip is inserted into a through-hole defined in a package substrate. As a result, a thickness of the semiconductor package may be reduced by at least a height of the bump. Because an empty space does not exist between a semiconductor chip and the package substrate, the semiconductor package does not need a conventional underfill resin layer. Accordingly, processes of forming the semiconductor package may be simplified. 1. A semiconductor package comprising:a package substrate including at least one through-hole and a lower conductive pattern, the through-hole penetrating the package substrate, and the lower conductive pattern on a bottom surface of the package substrate;a first semiconductor chip on the package substrate, the first semiconductor chip including a bonding pad; anda bump attached to the bonding pad and inserted in the though-hole,a first solder pattern in the through-hole, the first solder pattern electrically connecting the bonding pad to the lower conductive pattern and filling a space between the lower conductive pattern and the bump, a height of the first solder pattern being higher than a height of the lower conductive pattern with respect to the bottom surface of the package substrate.2. The semiconductor package of claim 1 , wherein the first solder pattern partially fills the through-hole.3. The semiconductor package of claim 1 , wherein a height of the first bump is substantially the same as the height of the first solder pattern.4. The semiconductor package of claim 1 , wherein the lower conductive pattern includes a first portion on the bottom surface of the package substrate and a second portion extending to cover an inner sidewall of the though-hole.5. The semiconductor package of claim 4 , wherein the height of ...

REDUCED VOLUME INTERCONNECT FOR THREE-DIMENSIONAL CHIP STACK

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers. 1. A method of forming a reduced volume interconnect for a chip stack including a plurality of silicon layers , the method comprising:forming a plurality of conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy (UBM) pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less;transferring the conductive structures to the silicon layers;stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; andheating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers in such a manner that at least a given one of the conductive structures between ...

CONNECTION BODY AND METHOD OF MANUFACTURING CONNECTION BODY

A connection body includes a circuit board terminals arranged into terminal rows, the terminals rows being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the terminals are arranged, and an electronic component including bumps arranged into bump rows corresponding to the terminal rows, the bumps being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the bumps are arranged. The electronic component is connected upon the circuit board interposed by an anisotropic conductive adhesive including electrically conductive particles arranged therein. A distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward the outer sides of the circuit board and the electronic component is greater than a distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward their inner sides. 1. A connection body comprising:a circuit board comprising a plurality of terminals arranged into a plurality of terminal rows, the plurality of terminal rows being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the plurality of terminals are arranged; andan electronic component comprising a plurality of bumps arranged into a plurality of bump rows corresponding to the plurality of terminal rows, the plurality of bump rows being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the plurality of bumps are arranged,whereinthe electronic component is connected upon the circuit board interposed by an anisotropic conductive adhesive comprising electrically conductive particles arranged therein,a distance between mutually opposing terminals of the plurality of terminals and bumps of the plurality of bumps arranged toward outer sides of the circuit board and the electronic component is greater than a distance between mutually opposing terminals of ...

Electronic device and semiconductor device

An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.

Flip-Chip Hybridisation Of Two Microelectronic Components Using A UV Anneal

A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

ELECTRONIC CIRCUIT CONNECTION METHOD AND ELECTRONIC CIRCUIT

The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. 1. An electronic circuit connection method for electrically connecting a first connection surface , in which a first electrode pad is provided in a first region and a second electrode pad is provided in a second region , and a second connection surface , in which a third electrode pad is provided in a third region facing the first region and a fourth electrode pad is provided in a fourth region facing the second region , comprising:a process of forming a first metal bump and a second metal bump, each of which has a cone shape; anda process of joining the first electrode pad and the third electrode pad by the first metal bump and joining the second electrode pad and the fourth electrode pad by the second metal bump,wherein at least one region of between the first region and the second region in the first connection surface and between the third region and the fourth region in the second connection surface has a step, andthe first metal bump and the second metal bump have different heights so as to correct a height of the step.2. The electronic circuit connection method according to claim 1 ,wherein the process of joining includes forming a first gap between the first region of the first connection surface and the third region of the second connection surface, and forming a second gap between the second region of the first connection surface and the fourth region of the second connection surface,a height of the first metal bump is proportional to a height of the first gap, anda height of the second metal bump is proportional to a height of the second gap.3. The electronic circuit connection method according to claim 1 ,wherein the process of forming includes forming the first metal bump and the second metal bump together.4. The electronic circuit connection method according to claim 1 , ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed. 1. A semiconductor package , comprising:a first substrate having a first active surface and a first trench recessed from the first active surface;a second substrate having a second trench facing the first trench; anda pathway cavity defined by the first trench and the second trench;wherein the first trench comprises a first metal protrusion and a first insulating protrusion.2. The semiconductor package of claim 1 , wherein the pathway cavity comprises a narrower width at an edge of the first substrate and a wider width at a center of the first substrate.3. The semiconductor package of claim 1 , wherein the second trench further comprising:a second metal protrusion electrically coupling to the first metal protrusion; anda second insulating protrusion connected to the first insulating protrusion.4. The semiconductor package of claim 3 , further comprising an electroless-plated portion between the first metal protrusion and the second metal protrusion.5. The semiconductor package of claim 3 , further comprising a boundary between the first insulating protrusion and the second insulating protrusion claim 3 , the boundary being at a level higher than a top surface of the first metal protrusion.6. The semiconductor package of claim 1 , wherein the first trench further comprises a plurality of metal protrusions and a plurality of insulating protrusions claim 1 , each of the metal protrusions being staggerly disposed with respect to each of the insulating protrusions.7. The semiconductor package of ...

Semiconductor device

A semiconductor device includes: a first switching element that is provided on a high side; a first diode element that is connected in parallel to the first switching element; a second switching element that is provide on a low side and connected in series to the first switching element; and a second diode element that is connected in parallel to the second switching element, wherein the first switching element and one of the first diode element and the second diode element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, the second switching element and the other of the first diode element and the second diode element that is different from the diode element adjacent to the first switching element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, and the first switching element and the second switching element are not adjacent in a vertical direction of respective electrode surfaces thereof.

Localized sealing of interconnect structures in small gaps

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar. 1. A microelectronic device , comprising:a conductive collar around sidewalls of first interconnects and second interconnects;the conductive collar configured from phase separated self-assembly matrix material;a dielectric layer around the conductive collar; andthe dielectric layer configured from the phase separated self-assembly matrix material.2. The microelectronic device according to claim 1 , wherein:the first and second interconnects respectively include metallization structures.3. The microelectronic device according to claim 1 , wherein:the first and second interconnects are respectively of first and second substrates;the first and second interconnects respectively include metallization structures;a gap between the first and second substrates is equal to or less than a pitch between the sidewalls of two adjacent ones of the first interconnects; andthe first and second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate.4. The microelectronic device according to claim 1 , wherein:the first and second interconnects are respectively of first and second substrates;the first and second interconnects respectively include metallization structures;a gap between the first and second substrates is equal to ...

Connector Structure and Method of Forming Same

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask. 1. A structure comprising:a plurality of metallization layers over a substrate, a topmost metallization layer of the metallization layers including a conductive feature;a first passivation layer over the topmost metallization layer, a portion of the conductive feature being exposed through the first passivation layer, the portion having a first width;a protection layer over the first passivation layer and the conductive feature;a seed layer on the conductive feature, the seed layer having a second width less than the first width; anda connector on the seed layer.2. The structure of claim 1 , wherein the connector has a third width less than the second width.3. The structure of claim 1 , wherein the conductive feature has a fourth width greater than the first width.4. The structure of claim 1 , further comprising:a second passivation layer over the protection layer, the portion of the conductive feature being exposed through the second passivation layer.5. The structure of claim 4 , wherein a first distance from a top surface of the seed layer to a top surface of the connector is less than a second distance from the top surface of the seed layer to a top surface of the second ...

POWER AMPLIFIER MODULE

A power amplifier module includes a substrate, an amplifier circuit including a plurality of transistors to be mounted on the substrate and a bump connected to the plurality of transistors, a harmonic termination circuit and an output matching circuit that are disposed in or on the substrate and configured to be electrically connected to the amplifier circuit, a connection pad disposed on the substrate and configured to be connected to the bump, and a plurality of connection wiring lines branching from the connection pad. The plurality of connection wiring lines include at least a first connection wiring line that connects the connection pad and the harmonic termination circuit to each other, a second connection wiring line that connects the connection pad and the output matching circuit to each other, and a third connection wiring line that connects the connection pad and an external power supply to each other. 1. A power amplifier module comprising:a substrate;an amplifier circuit comprising a plurality of transistors mounted on the substrate, and a bump connected to the plurality of transistors;a harmonic termination circuit;an output matching circuit, the harmonic termination circuit and the output matching circuit being in or on the substrate and electrically connected to the amplifier circuit;a connection pad on the substrate and connected to the bump; anda plurality of connection wiring lines branching from the connection pad, the plurality of connection wiring lines comprising a first connection wiring line that connects the connection pad to the harmonic termination circuit, a second connection wiring line that connects the connection pad to the output matching circuit, and a third connection wiring line that connects the connection pad to an external power supply.2. The power amplifier module according to claim 1 , wherein claim 1 , as seen in a plan view of the substrate in a direction perpendicular to a principal surface of the substrate claim 1 , the ...

ELECTRONIC CIRCUIT DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT DEVICE

An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second electronic component having a set of second terminals disposed at a second pitch on a second surface facing the first surface of the first electronic component. The second pitch of the second terminals is set larger than the first pitch of the first terminals. By doing so, each of the second terminals is connected to at least one of the first terminals if a positional misalignment occurs. As a result, the electronic circuit device has an increased tolerance for positional misalignment between the first electronic component and the second electronic component and reduces the occurrence of connection failure. 1. An electronic circuit device comprising:a first electronic component including a first surface and a set of first terminals disposed at a first pitch on the first surface; anda second electronic component including a second surface facing the first surface, and a set of second terminals disposed at a second pitch on the second surface, the second pitch being larger than the first pitch, the set of second terminals each being connected to at least one of the first terminals.2. The electronic circuit device according to claim 1 , wherein a space between adjacent second terminals among the second terminals is larger than a plane size of the first terminals claim 1 , and a space between adjacent first terminals among the first terminals is smaller than a plane size of the second terminals.3. The electronic circuit device according to claim 1 , wherein a plane size of the first terminals is smaller than a plane size of the second terminals.4. The electronic circuit device according to claim 1 , further comprising a circuit built in the first electronic component and configured to detect a combination of one of the second terminals and at least one of the first terminals connected to the one second terminal.5. ...

Flexible package-to-socket interposer

A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.

Variable temperature solders for multi-chip module packaging and repackaging

Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

Manufacturing method of package substrate with metal on conductive portions

A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.

Semiconductor packages and methods of fabricating the same

A semiconductor package includes a wiring board, a semiconductor chip mounted on the wiring board, and a mounting connection terminal electrically connecting a bonding pad of the semiconductor chip to a first connection pad of the wiring board. The mounting connection terminal includes a core portion and a connecting shell solder portion substantially surrounding the core portion. The core portion of the mounting connection terminal is not in contact with the bonding pad of the semiconductor chip.

PACKAGE STRUCTURE AND METHOD FOR CONNECTING COMPONENTS

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact. 1. A package structure , comprising:a first substrate, comprising a first wiring and at least one first contact, wherein the at least one first contact is electrically connected to the first wiring;a second substrate, comprising a second wiring and at least one second contact, wherein the at least one second contact is electrically connected to the second wiring, and the at least one first contact and the at least one second contact partially physically contact with each other or partially chemically interface reactive contact with each other; andat least one third contact, surrounding the at least one first contact and the at least one second contact,wherein the first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.2. The package structure according to claim 1 , wherein the at least one third contact is disposed between the at least one first contact and the at least one second contact.3. The package structure according to claim 1 , further comprising an intermetallic compound (IMC) or an alloy solid solution formed after the at least one first contact contacts the at least one ...

Integrated Circuit with a Thermally Conductive Underfill and Methods of Forming Same

An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps. 1. A device comprising:a first set of solder bumps bonding a substrate to a first chip;a first insulating film contacting the first set of solder bumps, a first surface of the first chip, and a surface of the substrate, the first insulating film extending along a surface of the substrate from a first solder bump of the first set of solder bumps to a second solder bump of the first set of solder bumps; anda first thermally conductive underfill disposed between the substrate and the first chip, the first thermally conductive underfill being disposed between the first solder bump and the second solder bump.2. The device of claim 1 , wherein the first thermally conductive underfill has a thermal conductivity of at least 0.5 W/mK.3. The device of claim 1 , wherein the first insulating film has a uniform thickness on sidewalls of the first set of solder bumps as measured from the sidewalls of the first set of solder bumps in a direction perpendicular to the sidewalls of the first set of solder bumps.4. The device of claim 3 , wherein the uniform thickness is from 500 Å to 20 μm.5. The device of further comprising:a second set of solder bumps bonding a second chip to the first chip, the first chip being between the second chip and the substrate;a second insulating film contacting the second set of solder bumps, a second surface of the first chip, and a surface of the second chip; anda second thermally conductive underfill disposed between the first chip and the second chip, the second thermally conductive underfill being ...

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first side and a second side opposite to the first side, the landing trace having a plurality of indents extending into the first side in a plan view, the second side being free of indents in the plan view.2. The structure of claim 1 , further comprising a solder feature over the landing trace claim 1 , the solder feature extending into the plurality of indents.3. The structure of claim 2 , wherein solder feature is in physical contact with the plurality of indents.4. The structure of claim 2 , further comprising a conductive pillar over the solder feature claim 2 , the conductive pillar overlapping with the plurality of indents in the plan view.5. The structure of claim 4 , wherein a width of the solder feature is greater than a width of the conductive pillar.6. The structure of claim 4 , wherein a width of the landing trace is less than a width of the conductive pillar.7. The structure of claim 1 , wherein the plurality of indents have a comb pattern in the plan view.8. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall having a plurality ...

Cold-welded flip chip interconnect structure

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 17-. (canceled)8. An apparatus comprising:a semiconductor die structure including I/O signal lines and power lines, the power lines including at least one of core power lines and I/O power lines;the die structure including a plurality of metal bumps, including a first group of metal bumps coupled to the I/O signal lines, and a second group of metal bumps coupled to the power lines; andwherein at least some of the metal bumps of the first group have a different pitch than at least some of the metal bumps of the second group.9. The apparatus of claim 8 , wherein at least some of metal bumps of the first group have at least one difference selected from the group consisting of a different shape and a different width claim 8 , than at least some of the metal bumps of the second group.10. The apparatus of claim 8 , wherein at least some of the metal bumps of the first group are rectangular in shape.11. The apparatus of claim 9 , wherein at least some of the metal bumps of the second group are circular in shape.12. The apparatus of claim 8 , wherein the first group of metal bumps includes a first sub-group of metal bumps and a second sub-group of metal bumps claim 8 , wherein the first sub-group has a smaller pitch than the second sub-group.13. The apparatus of claim 8 , further comprising a solder coupled to each of the first group of metal bumps claim 8 , wherein the solder defines an interface on the metal bump where the solder and metal bump are in contact claim 8 , and wherein the interface has a width that is ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder bump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump.2. The ...

STACKED SEMICONDUCTOR DEVICE, AND SET OF ONBOARD-COMPONENTS, BODY AND JOINTING-ELEMENTS TO BE USED IN THE STACKED SEMICONDUCTOR DEVICE

A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor. 1. A stacked semiconductor device comprising:a mother-plate merging a mother-circuit, having a mounting-main surface and a bottom-main surface facing the mounting-main surface;an onboard-element merging an onboard-circuit, having a connection face facing to the mounting-main surface;a parent bump provided on the mother-plate at a side of the mounting-main surface, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, the parent bump is electrically connected to the mother-circuit; anda repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor, the intersection is defined in a planar pattern viewed from a normal direction of the connection face,wherein conductors with different hardness are non-uniformly included at and in the vicinity of the intersection.2. The stacked semiconductor device of claim 1 , wherein at least one of the mother-site and ...

Semiconductor package and circuit substrate thereof

A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

3D IMAGE SENSOR

A three-dimensional (3D) image sensor includes a first substrate having an upper pixel. The upper pixel includes a photoelectric element and first and second photogates connected to the photoelectric element. A second substrate includes a lower pixel, which corresponds to the upper pixel, that is spaced apart from the first substrate in a vertical direction. The lower pixel includes a first transfer transistor that transmits a first signal provided by the first photogate. A first source follower generates a first output signal in accordance with the first signal. A second transfer transistor transmits a second signal provided by the second photogate. A second source follower generates a second output signal in accordance with the second signal. First and second bonding conductors are disposed between the first and second substrates and electrically connect the upper and lower pixels. 1. A three-dimensional (3D) image sensor comprising:a first substrate including an upper pixel, the upper pixel including a photoelectric element and first and second photogates connected to the photoelectric element;a second substrate including a lower pixel, which corresponds to the upper pixel, and spaced apart from the first substrate in a vertical direction, the lower pixel including a first transfer transistor transmitting a first signal provided by the first photogate, a first source follower generating a first output signal in accordance with the first signal, a second transfer transistor transmitting a second signal provided by the second photogate, and a second source follower generating a second output signal in accordance with the second signal; andfirst and second bonding conductors disposed between the first and second substrates and electrically connecting the upper and lower pixels.2. The 3D image sensor of claim 1 , wherein:the first bonding conductor connects the first photogate and the first transfer transistor, andthe second bonding conductor connects the second ...