Packaging structure and manufacturing method thereof

... 本发明公开种封装结构及其制造方法，该封装结构具有至少部分的第导电元件配置在第基板的贯穿开口(through‑opening)中。导电结构配置在第基板和第导电元件上方，其中该导电结构电性连接至该第基板和该第导电元件的该至少第输入/输出端。导电结构包含第二导电元件、第二基板或导电图案其中至少个。 ...

MULTI-CHIP SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME CAPABLE OF IMPROVING PRODUCTION EFFICIENCY

PURPOSE: A multi-chip semiconductor package and a method for forming the same are provided to reduce a chip crack by using an insulating layer, a protrusion electrode, and an interconnection. CONSTITUTION: A first semiconductor chip(11) having a first protrusion electrode(17) is formed on the upper surface. A second semiconductor chip(21) having a second protrusion electrode(27) is formed on the first semiconductor chip. An insulating layer(8) is formed between the first protrusion electrode and the second protrusion electrode. A groove is formed on the insulating layer. The first protrusion electrode is interconnected with the second protrusion electrode by filling the groove. COPYRIGHT KIPO 2013 ...

반도체 패키지

... 본 발명은 소자 성능 및 신뢰성을 개선할 수 있는 반도체 패키지를 제공하는 것이다. 본 발명의 반도체 패키지는 서로 전기적으로 연결된 제1 디바이스와 제2 디바이스를 포함하고, 제1 디바이스는 기판과, 기판의 상면 상에 형성된 제1 패드와, 기판의 상면 상에 형성되고, 제1 패드를 둘러싸도록 형성된 패시베이션막을 포함하고, 제2 디바이스는 제1 패드와 마주보도록 배치된 제2 패드를 포함하고, 제1 패드는 제1 모듈러스(modulus)를 갖는 센터 패드와, 제1 모듈러스보다 작은 제2 모듈러스를 갖고, 센터 패드를 둘러싸도록 형성되며 패시베이션막과 직접 접촉하는 에지 패드를 포함한다.

Chip structure and manufacturing method thereof

一種晶片結構包含第一基板、第二基板、導電通道與重佈線層。第一基板具有第一傾斜側壁。第二基板位於第一基板的下表面上，且具有上部與下部。下部凸出上部。上部位於第一基板與下部之間。上部具有第二傾斜側壁，且第一傾斜側壁與第二傾斜側壁的斜率大致相同。導電通道位於下部中。重佈線層從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，且電性連接導電通道。

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A package structure and the method to fabricate thereof

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

CONNECTING MICROSIZED DEVICES USING ABLATIVE FILMS

A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.

Semiconductor package including cap layer and dam structure and method of manufacturing the same

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

Semiconductor structure

A semiconductor structure including an insulating encapsulant, a first semiconductor die, a second semiconductor die and a redistribution circuit layer is provided. The first and the second semiconductor dies embedded in the insulating encapsulant and separated from one another. The first semiconductor die includes a first active surface accessibly exposed and a first conductive terminal distributed at the first active surface. The second semiconductor die includes a second active surface accessibly exposed and a second conductive terminal distributed at the second active surface. The redistribution circuit layer including a conductive trace is disposed on the first and the second active surfaces and the insulating encapsulant. The conductive trace is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to the top width of the insulating encapsulant ranges from about 3 to about ...

PRINTED COMPONENTS ON SUBSTRATE POSTS

A device structure comprises a patterned substrate comprising a substrate surface and a substrate post protruding from the substrate surface. The substrate post comprises a substrate post material. A component has a component top side and a component bottom side opposite the component top side. The component bottom side is disposed on the substrate post and extends over at least one edge of the substrate post. The component comprises a component material different from the substrate post material and the component comprises a broken (e.g., fractured) or separated component tether.

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connecting the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connecting the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

Herstellung eines Halbleiter-Bauelements

Es wird ein Verfahren zur Herstellung eines Halbleiter-Bauelements offenbart. In einer Ausführungsform umfasst das Verfahren das Bereitstellen mindestens eines Halbleiterchips, der eine elektrisch leitfähige Schicht umfasst. Eine Spannung wird an eine Elektrode angelegt. Die Elektrode wird über der elektrisch leitfähigen Schicht bewegt, um eine Metallschicht auf die elektrisch leitfähige Schicht aufzuwachsen.

Connecting microsized devices using ablative films

A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and secondsurface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.

Multi-chip fan-outing type is capsulated and its forming method

本发明涉及多芯片扇出型封装及其形成方法，其中，该封装包括：管芯，位于管芯顶面的导电焊盘；柱状凸块，位于导电焊盘上方并与导电焊盘连接；以及再分布线，位于柱状凸块上方并与柱状凸块连接。电连接件位于再分布线上方并与再分布线电耦合。

Raised via for terminal connections on different planes

본 방법은 제1 금속 패드 및 제2 금속 패드에 접촉하도록 유전체 층의 개구 내로 연장하는 금속층을 형성하는 단계와, 컴포넌트 디바이스의 최하부 단자를 금속층에 접합시키는 단계를 포함한다. 금속층은 컴포넌트 디바이스의 바로 아래에 놓여지고 이에 접합된 제1 부분을 갖는다. 융기된 비아가 금속층 상에 형성되고, 금속층은 융기된 비아의 바로 아래에 놓여진 제2 부분을 갖는다. 금속층은 에칭되어 금속층의 제1 부분과 제2 부분을 서로 분리시킨다. 본 방법은 융기된 비아 및 컴포넌트 디바이스를 유전체 층 내에서 코팅하는 단계, 융기된 비아 및 컴포넌트 디바이스의 최상부 단자를 드러내는 단계, 및 융기된 비아를 최상부 단자에 연결하는 재배선 라인을 형성하는 단계를 더 포함한다. The method includes forming a metal layer extending into the opening of the dielectric layer to contact the first metal pad and the second metal pad, and bonding the bottom terminal of the component device to the metal layer. The metal layer lies directly below the component device and has a first portion bonded thereto. The raised via is formed on the metal layer, and the metal layer has a second portion placed directly under the raised via. The metal layer is etched to separate the first and second portions of the metal layer from each other. The method further comprises coating the raised vias and the component device in a dielectric layer, revealing the top terminals of the raised vias and the component device, and forming a redistribution line connecting the raised vias to the top terminal. Include.

STACKED SEMICONDUCTOR PACKAGE

Fan-out semiconductor package

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Microelectronic interconnect element with decreased conductor spacing

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

CONNECTING MICROSIZED DEVICES USING ABLATIVE FILMS

A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device is disclosed. In one embodiment, the method includes providing at least one semiconductor chip including an electrically conductive layer. A voltage is applied to an electrode. The electrode is moved over the electrically conductive layer for growing a metal layer onto the electrically conductive layer.

Verfahren zum Füllen eines Kontaktlochs in einer Chip-Gehäuse-Anordnung und Chip-Gehäuse-Anordnungen

In verschiedenen Ausführungsformen wird ein Verfahren zum Füllen eines Kontaktlochs in einer Chip-Gehäuse-Anordnung bereitgestellt. Das Verfahren kann aufweisen: Einbringen elektrisch leitfähiger diskreter Partikel in ein Kontaktloch eines Chip-Gehäuses; und Bilden eines elektrischen Kontakts zwischen den elektrisch leitfähigen diskreten Partikeln und einem Kontaktanschluss der Vorderseite und/oder der Rückseite des Chips. In various embodiments, a method for filling a contact hole in a chip-housing arrangement is provided. The method can include: introducing electrically conductive discrete particles into a contact hole of a chip housing; and forming an electrical contact between the electrically conductive discrete particles and a contact connection of the front side and / or the rear side of the chip.

Method for stacking semiconductor die on fan-out WLCLCSP and semiconductor device

Chip package and fabrication method thereof

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Microelectronic interconnect element with decreased conductor spacing

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

SEMICONDUCTOR DEVICE PACKAGE

The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a first module disposed on the substrate, a second module disposed on the substrate and spaced apart from the first module, and a conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module. 1. A semiconductor device package , comprising:a substrate;a first module disposed on the substrate;a second module disposed on the substrate and spaced apart from the first module; anda first conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module.2. The semiconductor device package of claim 1 , wherein the first conductive element comprises a passive component.3. The semiconductor device package of claim 2 , wherein the first conductive element comprises a conductive wire claim 2 , an interposer claim 2 , a redistribution structure claim 2 , a conductive pillar claim 2 , a conductive via claim 2 , or a combination thereof.4. The semiconductor device package of claim 1 , whereinthe first module comprises a first interposer disposed on the substrate and a first electronic component disposed on the first interposer, andthe second module comprises a second interposer disposed on the substrate and a second electronic component disposed on the second interposer.5. The semiconductor device package of claim 4 , wherein the first electronic component is spaced apart from the second interposer and the second electronic component is spaced apart from the first interposer.6. The semiconductor device package of claim 4 , wherein the first electronic component and the second electronic component are different from each other in at least one of function claim 4 , operating frequency claim 4 , bandwidth claim 4 , signal type claim 4 , impedance claim 4 , and line/space (L/S) width.7. The ...

반도체 패키지

... 안정성을 향상시켜 전기적 특성이 향상된 반도체 패키지가 제공된다. 반도체 패키지는 제1 반도체 기판을 포함하는 제1 스택, 제1 반도체 기판을 제1 방향으로 관통하는 관통 비아, 제1 스택 상에, 제1 스택의 제1 면과 마주보는 제2 면을 포함하는 제2 스택, 제1 스택의 제1 면 상에, 관통 비아와 접촉하는 제1 패드, 제2 스택의 제2 면 상에, 오목한 내측면에 의해 정의된 삽입 리세스를 포함하는 제2 패드, 제1 패드와 제2 패드를 연결하는 범프를 포함하고, 범프는 제1 패드 상의 제1 상부 범프와, 제1 상부 범프 및 제1 패드 사이의 제1 하부 범프를 포함하고, 제1 상부 범프는 제1 하부 범프와 다른 물질을 포함하고, 제1 상부 범프는 삽입 리세스의 적어도 일부를 채우고, 제1 하부 범프의 측벽 상에 비배치된다.

MODULE STRUCTURES WITH COMPONENT ON SUBSTRATE POST

A module structure comprises a patterned substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post. The component has a component top side and a component bottom side opposite the component top side. The component bottom side is disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

METHOD OF MANUFACTURING HIGH-FREQUENCY DEVICE

A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.

Display device

A display device includes a substrate 110, a plurality of first lines 121 disposed on the substrate and spaced apart from each other, a plurality of second lines 122 disposed alternately between the respective first lines, a plurality of light emitting elements 130 disposed on the first and second lines, and a plurality of third lines 123 disposed on the light emitting elements, between each of the first and second lines. Each light emitting element includes a first semiconductor layer 131 overlapping the first lines 121 and electrically connected to the first and second lines, a light emitting layer 132, a second semiconductor layer 133, a conductor layer 134 in contact with the plurality of third lines 123, and a non-conductor layer 135 overlapping the plurality of second lines 122. The first and second semiconductor layers may be formed by doping a material such as gallium nitride (GaN), indium aluminium phosphide (InAlP) or gallium arsenide (GaAs). The first lines 121 and second lines ...

멀티-칩 반도체 패키지 및 그 형성 방법

상면에 제1 돌출 전극을 갖는 제1 반도체 칩을 준비한다. 상기 제1 반도체 칩 상에 제2 돌출 전극을 갖는 제2 반도체 칩을 상기 제1 돌출 전극이 노출되도록 탑재한다. 상기 제1 돌출 전극과 상기 제2 돌출 전극 사이에 절연막을 형성한다. 상기 절연막 내에 그루브를 형성한다. 상기 그루브의 내부를 채우고 상기 제1 돌출 전극 및 상기 제2 돌출 전극과 접속되는 상호접속을 형성한다. A first semiconductor chip having a first projecting electrode on its upper surface is prepared. A second semiconductor chip having a second protruding electrode on the first semiconductor chip is mounted so that the first protruding electrode is exposed. An insulating film is formed between the first projecting electrode and the second projecting electrode. A groove is formed in the insulating film. And filling the inside of the groove and forming an interconnect to be connected with the first projecting electrode and the second projecting electrode.

MICROELECTRONIC INTERCONNECT ELEMENT WITH DECREASED CONDUCTOR SPACING

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. 1. A microelectronic interconnect element , comprising:a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line;a plurality of second metal lines interleaved with the plurality of first metal lines in a direction of the width of the plurality of first metal lines, each of the plurality of second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line;a dielectric layer separating a metal line of the plurality of first metal lines from an adjacent metal line of the plurality of second metal lines; anda conductive pad extending in directions of the reference plane and a conductive via extending from the conductive pad through the dielectric layerwherein a pitch between the metal line of the plurality of first metal lines and the adjacent metal line of the plurality of second metal lines is smaller than a first pitch between adjacent ones of the plurality of first metal lines and is smaller than a second pitch between ...

LIGHT-EMITTING APPARATUS AND MANUFACTURING METHOD THEREOF

A light-emitting apparatus includes a substrate, pads disposed on the substrate, a sacrificial pattern layer and a light-emitting diode element disposed on the sacrificial pattern layer. The light-emitting diode element includes a first type semiconductor layer, a second type semiconductor layer, an active layer, and electrodes. A connection patterns disposed on at least one of the electrodes and the pads. Materials of the connection patterns include hot fluidity conductive materials. The connection patterns cover a sidewall of the sacrificial pattern layer and are electrically connected to the at least one of the electrodes and the pads. In addition, the manufacturing method of the above light-emitting apparatus is also proposed.

半導體裝置及其製造方法

根據本發明之一實施形態，半導體裝置包括具備第1絕緣膜與第1焊墊之第1晶圓或第1晶片。上述裝置進而包括第2晶圓或第2晶片，上述第2晶圓或第2晶片具備與上述第1絕緣膜相接之第2絕緣膜、及與上述第1焊墊對向且電性連接於上述第1焊墊之第2焊墊。進而，上述第1絕緣膜具有於上述第1焊墊延伸之第1槽，及/或上述第2絕緣膜具有於上述第2焊墊延伸之第2槽。

TSV SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL SHIFT

A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.

Assembling of chips by stacking with rotation

A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.

Semiconductor device and manufacturing of the same

Circuit Board Structure

A printed circuit board structure that includes at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layers are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

Semiconductor device with electroplated die attach

A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

Multi-Chip Fan Out Package and Methods of Forming the Same

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

DISPLAY DEVICE

A display device invention includes a substrate on which a plurality of light emitting elements are disposed. A plurality of lines are disposed on an upper surface of the substrate. A plurality of upper pads are disposed on the upper surface of the substrate and electrically connected to the plurality of lines. A plurality of link lines are disposed on a lower surface of the substrate. A plurality of lower pads are disposed on the lower surface of the substrate and electrically connected to the plurality of link lines. A plurality of side lines electrically connect the plurality of upper pads and the plurality of lower pads. The plurality of side lines include a plurality of first side lines and a plurality of second side lines, and the plurality of first side lines and the plurality of second side lines are disposed on different layers.

Assembling of chips by stacking with rotation

Ultra thin PoP package

一PoP(封裝上封裝)之封裝包括耦接至一頂部封裝之一底部封裝。該底部封裝包括藉由一黏著層耦接至一中介層之一晶粒。一或多個端子在該晶粒之周邊上耦接至該中介層。該等端子及該晶粒至少部分地囊封於一囊封物中。該等端子及該晶粒耦接至一重新分佈層(RDL)。在該RDL之底部上的端子用以將該PoP封裝耦接至一主機板或一印刷電路板(PCB)。一或多個額外端子將該中介層耦接至該頂部封裝。該等額外端子可位於沿著該中介層之表面的任何處。

BUMP ON VIA-PACKAGING AND METHODOLOGIES

BUMP ON VIA - PACKAGING AND METHODOLOGIES A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.

Fan-out semiconductor package

MICROELECTRONIC INTERCONNECT ELEMENT WITH DECREASED CONDUCTOR SPACING

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

IC device having patterned, non-conductive substrate

A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

Semiconductor device with through-mold via

In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically ...

SYSTEMS AND METHODS FOR FLASH STACKING

A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating. 1. A method for producing a microelectronic stack comprising:providing a plurality of wafers having a first face and a second face forming a body thereof for production of microelectronic components, the plurality of wafers each having at least one dielectric region thereon wherein the at least one dielectric region extends from the first face to the second face;disposing a plurality of conductive metallic traces over the dielectric region in a manner selected from a group consisting of printing, direct imaging, and stenciling wherein each of the conductive metallic traces has at least one corresponding trace on each of the plurality of wafers;bonding each of the plurality of wafers thereby forming a layered stack of wafers,wherein the first face of one of the plurality of wafers is bonded to the second face of another one of the plurality of wafers;dicing the layered stack of wafers along predetermined dicing lanes such that the dicing exposes a vertical edge of a stack wherein the exposed vertical edge is formed of the dielectric region and the plurality of conductive metallic traces; andinterconnecting the metallic traces along the vertical edge through electroless plating such that the metallic traces are electronically interconnected through each layer of the stack.2. The method of wherein the dielectric region for each of the plurality of wafers is consistent in size and shape.3. The method of wherein the dielectric region for each of the plurality of wafers is a different size and dimension.4. The method of wherein the metal used in the electroless plating is selected from a group consisting of nickel claim 1 , copper claim 1 , silver claim 1 , and gold.5. The ...

Semiconductor device and its wafer level package

Chip package and manufacturing method thereof

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.

Raised Via for Terminal Connections on Different Planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Package structure

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding ...

Fan-out semiconductor package

Method for producing a printed circuit board structure

A method for producing a printed circuit board structure comprising at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layer are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

Systems and methods for stacked semiconductor memory devices

Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

CHIP-ZU-CHIP-VERBINDUNG IN DER VERKAPSELUNG EINES VERGOSSENEN HALBLEITERGEHÄUSES

Ein gehauster Halbleiter enthält einen elektrisch isolierenden Verkapselungskörper mit einer oberen Oberfläche, einen ersten Halbleiterchip, der innerhalb des Verkapselungskörpers eingekapselt ist, wobei der erste Halbleiterchip eine Hauptoberfläche mit einem ersten leitenden Pad aufweist, das der oberen Oberfläche des Verkapselungskörpers zugewandt ist, einen zweiten Halbleiterchip, der innerhalb des Verkapselungskörpers eingekapselt und seitlich neben dem ersten Halbleiterchip angeordnet ist, wobei der zweite Halbleiterchip eine Hauptoberfläche mit einem zweiten leitenden Pad aufweist, das der oberen Oberfläche des Verkapselungskörpers zugewandt ist, und eine erste Leiterbahn, die in der oberen Oberfläche des Verkapselungskörpers ausgebildet ist und das erste leitende Pad mit dem zweiten leitenden Pad elektrisch verbindet. Der Verkapselungskörper enthält eine laseraktivierbare Vergussmasse. A packaged semiconductor includes an electrically insulating encapsulation body having a top surface, a first semiconductor chip encapsulated within the encapsulation body, the first semiconductor chip having a main surface with a first conductive pad facing the top surface of the encapsulation body, a second semiconductor chip, which is encapsulated within the encapsulation body and arranged laterally next to the first semiconductor chip, wherein the second semiconductor chip has a main surface with a second conductive pad facing the upper surface of the encapsulation body, and a first conductor track which is formed in the upper surface of the encapsulation body and electrically connecting the first conductive pad to the second conductive pad. The encapsulation body contains a laser-activated potting compound.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

TSV SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL SHIFT

Semiconductor package and method of fabricating semiconductor package

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

Semiconductor Structure and Method of Forming

A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.

Herstellung eines Halbleiter-Bauelements

Verfahren zur Herstellung eines Halbleiter-Bauelements, umfassend: Bereitstellen mindestens eines Halbleiterchips, der eine elektrisch leitfähige Schicht umfasst; Anlegen einer Spannung an eine Elektrode; und Relief der Elektrode über der elektrisch leitfähigen Schicht, um eine Metallschicht auf die elektrisch leitfähige Schicht aufzuwachsen, wobei die Metallschicht als eine nicht-planare Schicht aufgewachsen wird. A method of manufacturing a semiconductor device, comprising: providing at least one semiconductor chip comprising an electrically conductive layer; Applying a voltage to an electrode; and relief of the electrode over the electrically conductive layer to grow a metal layer on the electrically conductive layer, wherein the metal layer is grown as a non-planar layer.

Halbleiterkonstruktion

Es wird eine Halbleiterkonstruktion mit einem isolierenden Verkapselungsstoff, einem ersten Halbleiter-Die, einem zweiten Halbleiter-Die und einer Umverdrahtungsschicht bereitgestellt. Der erste und der zweite Halbleiter-Die [Lakune] in den isolierenden Verkapselungsstoff eingebettet und voneinander getrennt. Der erste Halbleiter-Die weist eine zugänglich freigelegte erste aktive Fläche und einen ersten Leitungsanschluss auf, der an der ersten aktiven Fläche verdrahtet ist. Der zweite Halbleiter-Die weist eine zugänglich freigelegte zweite aktive Fläche und einen zweiten Leitungsanschluss auf, der an der zweiten aktiven Fläche verdrahtet ist. Die Umverdrahtungsschicht mit einer Leiterbahn ist auf der ersten und der zweiten aktiven Fläche und dem isolierenden Verkapselungsstoff angeordnet. Die Leiterbahn ist elektrisch mit dem ersten Halbleiter-Die verbunden und windet sich zu dem zweiten Halbleiter-Die hin, und ein Verhältnis einer Gesamtlänge der Leiterbahn zur oberen Breite des isolierenden ...

Semiconductor device and method of manufacturing the same

根據本發明之一實施形態，半導體裝置包括具備第1絕緣膜與第1焊墊之第1晶圓或第1晶片。上述裝置進而包括第2晶圓或第2晶片，上述第2晶圓或第2晶片具備與上述第1絕緣膜相接之第2絕緣膜、及與上述第1焊墊對向且電性連接於上述第1焊墊之第2焊墊。進而，上述第1絕緣膜具有於上述第1焊墊延伸之第1槽，及/或上述第2絕緣膜具有於上述第2焊墊延伸之第2槽。

Multi-chip fan out package and methods of forming the same

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING REDUCED HEIGHT SEMICONDUCTOR PACKAGES FOR MOBILE ELECTRONICS

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

Via for semiconductor device connection and methods of forming the same

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Multiple plated via arrays of different wire heights on a same substrate

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.

Semiconductor structure and method of forming

A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.

Semiconductor light-emitting device

A light-emitting diode has a GaN-based multi-layer structure arranged on a sapphire substrate. A pair of electrode pads are arranged on a light-output face of the multi-layer structure. The first and second electrode pads have a total projected area set at 25% or less of that of the light-output face. The electrode pads are connected to electrode pads on a mount frame by solder wiring layers arranged on an insulating film covering the side wall of the multi-layer structure.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Multiple Bond Via Arrays of Different Wire Heights on a Same Substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

LIGHT EMITTING DIODE DISPLAY DEVICE

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

Fan-out semiconductor package

A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; an interconnection member disposed on the active surface of the semiconductor chip; a resin layer disposed on the encapsulant and including a redistribution layer; a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant; and a connection member penetrating through the rear redistribution layer and the encapsulant, wherein the redistribution layer and the rear redistribution layer are electrically connected to the connection pads of the semiconductor chip.

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE THEREOF

Raised via for terminal connections on different planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Device package and method of manufacturing the same

PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.

Verfahren und Waferlevelpackage für heterogene Integrationstechnologie

Es werden Verfahren und Einheiten zur Bildung eines WLP offenbart, das einen ersten Chip, das nach einer ersten Technologie gefertigt ist, und einen zweiten Chip, der nach einer zweiten Technologie, die sich von der ersten Technologie unterscheidet, gefertigt ist. Diese werden durch ein Formmaterial, das den ersten Chip und den zweiten Chip einkapselt, gepackt. Eine Nachpassivierungsverbindungs(PPI)-Leitung kann auf dem Formmaterial, das mit einem ersten Kontaktpad des ersten Chips durch eine erste Verbindung ist, gebildet sein und mit einem zweiten Kontaktpad des zweiten Chips durch eine zweite Verbindung verbunden sein, wobei die erste Verbindung und die zweite Verbindung ein Cu Kügelchen, eine Cu Durchkontaktierung, ein Cu Stutzen oder andere Arten von Verbindungen sein können.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Circuit board structure

A printed circuit board structure that includes at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layers are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

Die Structures and Methods of Forming the Same

Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

With accurate spacing of the electrical interconnection of a semiconductor die

Semiconductor structure

A semiconductor structure including an insulating encapsulant, a plurality of semiconductor dies separately embedded in the insulating encapsulant, and an electrical communication path is provided. The electrical communication path includes at least one turning wiring connected to a conductive terminal of one of the semiconductor dies and extending across and above the insulating encapsulant to reach another conductive terminal of another one of the semiconductor dies. A layout area of the at least one turning wiring is within a region corresponding to an edge of one of the semiconductor dies and a closest edge of the adjacent one of the semiconductor dies.

Circuit Board Structure

A method for producing a printed circuit board structure comprising at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layer are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component. 1. A method for producing a printed circuit board structure comprising:Embedding a component having at least one connection and connection area within a printed circuit board structure;Producing at least one via from a conductor path, having an outer conductor layer, to the at least one connection of the component whereby the via is produced by; 'Chemically cleaning the at least one opening whereby the thickness of the barrier layer is reduced; and', 'Producing at least one opening in the outer conductor layer, in which the opening extends to a barrier layer of the at least one connection; and'}contacting the component embedded in the printed circuit board structure on a conductor segment by way of the at least one via.2. The method of claim 1 , wherein the printed circuit board structure further comprises a least one insulation layer and at least one conductor layer claim 1 , andwherein the component has at least two connections, each of the at least two connections comprising a contact layer and an adhesion layer, and wherein the outer barrier layer is disposed on an outer surface of the adhesion layer, and wherein the opening is produced in an area of the at least two connections.3. The method of claim 1 , wherein a currentless copper-plating is used on at least one side of the printed circuit board structure to form a copper layer on the surface and in the openings claim 1 ,.4. The method of claim 1 , characterized in that the at least one opening is produced by laser cutting.5. The method ...

ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME

An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

Semiconductor light-emitting device

A light-emitting diode has a GaN-based multi-layer structure arranged on a sapphire substrate. A pair of electrode pads are arranged on a light-output face of the multi-layer structure. The first and second electrode pads have a total projected area set at 25% or less of that of the light-output face. The electrode pads are connected to electrode pads on a mount frame by solder wiring layers arranged on an insulating film covering the side wall of the multi-layer structure.

Semiconductor structure

A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10. 1. A manufacturing method of a semiconductor structure , comprising: the first semiconductor die comprises a first active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the first active surface, and', 'the second semiconductor die comprises a second active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the second active surface; and, 'covering a first semiconductor die and a second semiconductor die with an insulating encapsulant, wherein a conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and', 'a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first semiconductor die and the second semiconductor die ranges from about 3 to about 10., 'forming a redistribution circuit layer on the insulating encapsulant, the first active ...

PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOF

Packaged device having a carrying base; an accommodation cavity in the carrying base; a semiconductor die in the accommodation cavity, the semiconductor die having die pads; a protective layer, covering the semiconductor die and the carrying base; first vias in the protective layer, at the die pads; and connection terminals of conductive material. The connection terminals have first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along a side surface of the packaged device. 1. A packaged device , comprising:a front surface, a back surface opposite to the front surface, and a side surface extending between the front surface and the back surface;a carrying base;an accommodation cavity in the carrying base;a semiconductor die in the accommodation cavity, the semiconductor die having die pads;a protective layer, covering the semiconductor die and the carrying base;first vias in the protective layer, at the die pads; andconnection terminals of conductive material, the connection terminals having first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along the side surface of the packaged device.2. The packaged device according to claim 1 , further comprising second vias extending in the protective layer at delimitation walls of the carrying base and base connection terminals having first base connection portions extending in the second vias claim 1 , in electrical contact with the carrying base claim 1 , and second base connection portions claim 1 , extending above the protective layer and along the side surface of the packaged device claim 1 , and wherein the carrying base is of conductive material and has delimitation walls of the accommodation cavity.3. The packaged device according to claim 1 , wherein the front surface and the back surface are arranged at a distance along ...

FAN-OUT PACKAGING STRUCTURE AND METHOD

The present disclosure provides a fan-out chip packaging structure and a method to fabricate the fan-out chip package. . The fan-out chip packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first packaging layer, a stacked chip package, a passive element, a filling layer, a metal bumps, and a second packaging layer. By means of the present disclosure, various chips having different functions can be integrated into one package structure, thereby improving the integration level of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertically stacked package is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity. 1. A method of fabricating a fan-out chip package , the method comprising following steps:providing a support substrate, and forming a separation layer on the support substrate;forming a first redistribution layer on the separation layer, wherein the first redistribution layer comprises a first surface in contact with the separation layer and a second surface opposite to the first surface;forming metal connecting posts on the second surface of the first redistribution layer, wherein the metal connecting posts are electrically connected to the first redistribution layer;providing a semiconductor chip, wherein the semiconductor chip is disposed on the second surface of the first redistribution layer, wherein a back side of the semiconductor chip is bonded to the first redistribution layer, and a front side of the semiconductor chip is facing away from the second surface of the first redistribution layer;packaging the first redistribution layer, the metal ...

Multi-Chip Fan Out Package and Methods of Forming the Same

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. 1. A method comprising:placing a first device die over a carrier, the first device die comprising a surface conductive feature;forming a first stud bump on the first device die;placing a second device die over the carrier;encapsulating the first device die and the second device die in an encapsulant;performing a planarization to planarize top surfaces of the encapsulant, the first stud bump, and a conductive feature of the second device die; andforming redistribution lines over and electrically coupling to the first stud bump and the surface conductive feature.2. The method of claim 1 , wherein the forming the first stud bump comprises:performing a wire bonding on the first device die; andcutting a metal wire used for the wire bonding to leave the first stud bump on the first device die.3. The method of further comprising:forming a second stud bump on the second device die through wire bonding; andsawing a wafer comprising the second device die and the second stud bump into discrete dies, wherein the discrete dies comprise the second device die.4. The method of claim 3 , wherein the first stud bump is formed after the first device die is placed claim 3 , and the second device die is placed on the wafer after the sawing.5. The method of further comprising claim 3 , before the sawing claim 3 , forming a polymer layer to embed a lower portion of the second stud bump therein claim 3 , wherein after the planarization claim 3 , the polymer layer is exposed.6. The method of claim 3 , wherein after the second device die is placed on the carrier claim 3 , an entirety of the second stud bump is higher than a surface dielectric layer of the second device die.7. The method of claim 6 , wherein after the ...

Semiconductor Structure and Method of Forming

A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure. 1. A method comprising:forming a first die and a second die;forming a first passivation layer over the first die;forming a second passivation layer over the first passivation layer;forming a third passivation layer over the second die;attaching the first die and the second die to a first insulating layer;forming a molding compound over the first die and the second die, the molding compound extending along sidewalls of the first die and sidewalls of the second die;removing a portion of the molding compound to expose an upper surface of the second passivation layer, wherein an upper surface of the third passivation layer is covered by a remaining portion of the molding compound; andforming a second insulating layer over the molding compound, wherein the upper surface of the second passivation layer is in physical contact with the second insulating layer.2. The method of claim 1 , wherein the first passivation layer and the third passivation layer comprise a same material.3. The method of claim 1 , wherein the first passivation layer and the second passivation layer comprise different materials.4. The method of claim 1 , wherein removing the portion of the molding compound comprises performing a planarization process on the molding compound.5. The method of claim 1 , further comprising forming a first conductive column ...

INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE

An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed. 110-. (canceled)11. An electronic component array , comprising:a backplane substrate;a plurality of integrated circuit elements disposed on the backplane substrate, each of the integrated circuit elements comprising a chiplet substrate, a connection pad, and a conductor element disposed on a surface of the chiplet substrate, wherein the connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad, and wherein at least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; anda plurality of conductive wires on the backplane substrate, wherein the connection pad of each of the plurality of integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding that the at least one of the integrated circuit ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes a connection structure including one or more redistribution layers, a first semiconductor chip disposed on a first surface of the connection structure and having a first connection pad, a first encapsulant disposed on a first surface of the connection structure and covering at least a portion of the first semiconductor chip, and a second semiconductor chip disposed on a second surface of the connection structure and having a second connection pad, wherein the first connection pad is electrically connected to the one or more redistribution layers by a connection via of the connection structure, the second connection pad is electrically connected to the one or more redistribution layers by a wire, and the first and second connection pads are electrically connected to each other through the one or more redistribution layers. 1. A fan-out semiconductor package comprising:a connection structure including one or more redistribution layers;a first semiconductor chip, disposed on a first surface of the connection structure, having a first active surface, on which a first connection pad is disposed, and a first inactive surface opposing the first active surface, the first active surface facing the first surface of the connection structure;a first encapsulant, disposed on the first surface of the connection structure, covering at least a portion of the first semiconductor chip; anda second semiconductor chip, disposed on a second surface of the connection structure opposing the first surface, having a second active surface, on which a second connection pad is disposed, and a second inactive surface opposing the second active surface, the second inactive surface facing the second surface of the connection structure,wherein the first connection pad is electrically connected to the one or more redistribution layers by a connection via of the connection structure,the second connection pad is electrically connected to the one or more ...

Vertically connected integrated circuits

In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board.

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps. 1. A fan-out semiconductor package comprising: a plurality of insulating layers,', 'a plurality of wiring layers disposed on the plurality of insulating layers, and', 'a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and', 'having a recess portion having a stopper layer disposed on a bottom surface thereof;, 'a frame including'} connection pads,', 'an active surface on which the connection pads are disposed, and', 'an inactive surface opposing the active surface, and', 'being disposed in the recess portion so that the inactive surface is connected to the stopper layer;, 'a semiconductor chip having'}first metal bumps disposed on the connection pads of the semiconductor chip;second metal bumps disposed on an uppermost wiring layer of the plurality of wiring layers;an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; anda connection member disposed on the frame and the ...

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

SYSTEMS AND METHODS FOR FLASH STACKING

A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating. 1. A method for producing a microelectronic stack comprising:providing a plurality of semiconductor substrates having a first face and a second face forming a body thereof for production of microelectronic components, the plurality of semiconductor substrates each having at least one dielectric region thereon wherein the at least one dielectric region extends from the first face to the second face;disposing a plurality of conductive metallic traces over the dielectric region in a manner selected from a group consisting of printing, direct imaging, and stenciling wherein each of the conductive metallic traces has at least one corresponding trace on each of the plurality of wafers;bonding each of the plurality of semiconductor substrates thereby forming a layered stack of wafers, wherein the first face of one of the plurality of wafers is bonded to the second face of another one of the plurality of wafers;predetermining a plurality of dicing lanes on the stack of semiconductor substrates;dicing the layered stack of wafers along the predetermined dicing lanes such that the dicing exposes a vertical edge of a stack wherein the exposed vertical edge is formed of the dielectric region and the plurality of conductive metallic traces; andinterconnecting the metallic traces along the vertical edge through electroless plating such that the metallic traces are electronically interconnected through each layer of the stack.2. The method of wherein the dielectric region for each of the plurality of semiconductor substrates is a different size and dimension.3. The method of wherein the metal used in the electroless plating is selected from a group consisting of nickel claim 1 , ...

Via for Semiconductor Device Connection and Methods of Forming the Same

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Raised Via for Terminal Connections on Different Planes

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal. 1. A structure comprising:a first metal pad and a second metal pad, wherein top surfaces of the first metal pad and the second metal pad are coplanar;a dielectric layer;a first metal layer and a second metal layer extending into the dielectric layer to contact the first metal pad and the second metal pad;a component device overlapping and contacting the first metal layer;a raised via over and contacting the second metal layer; andan encapsulant encapsulating the raised via and the component device therein.2. The structure of claim 1 , wherein the component device is a two-terminal device comprising:a bottom terminal contacting the first metal layer; anda top terminal at a top surface of the component device.3. The structure of claim 2 , wherein the bottom terminal is planar claim 2 , and edges of the bottom terminal are flushed with respective edges of the first metal layer.4. The structure of claim 3 , wherein the first metal layer has undercuts extending directly underlying edge portions of the bottom terminal.5. The structure of further comprising a redistribution line over the raised via claim 1 , wherein the redistribution line electrically connect the raised via to the top terminal.6. The ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies. 1. A semiconductor structure , comprising:a plurality of semiconductor dies;an insulating encapsulant interposed between adjacent two of the plurality of semiconductor dies, the insulating encapsulant comprising a first portion wider than a second portion connected to the first portion; and a dielectric layer overlying the insulating encapsulant; and', 'a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant, the conductive trace comprising at least one turn and connected to a conductive terminal of one of the adjacent two of the plurality of semiconductor dies, and the conductive trace extending across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the plurality of semiconductor dies., 'a redistribution structure disposed on the plurality of semiconductor dies and the insulating encapsulant, the redistribution structure comprising2. The semiconductor structure according to claim 1 , wherein a layout area of the at least one turns is located above the insulating encapsulant interposed ...

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

SEMICONDUCTOR DEVICE

The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface. 1. A semiconductor device comprising:a first semiconductor element and a second semiconductor element, each of which has an element obverse surface and an element reverse surface that face opposite to each other in a thickness direction, with an element first electrode arranged on the element reverse surface, and with an element second electrode arranged on the element obverse surface;a first lead having a lead obverse surface and a lead reverse surface that face opposite to each other in the thickness direction;an insulating layer covering the first lead, the first semiconductor element, and the second semiconductor element;a first electrode electrically connected to the element second electrode of the first semiconductor element; anda second electrode electrically connected to the first lead,wherein the first semiconductor element and the first lead are bonded to each other with the element reverse surface of the first semiconductor element facing the lead obverse surface, andthe second semiconductor element and the first lead are ...

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.

Package structure and method of fabricating the same

A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

CHIP STACK PACKAGES

A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure. 1. A chip stack package comprising:a first semiconductor chip configured to have a first surface and a second surface being opposite to each other and configured to have a first side surface connecting edges of the first surface to edges of the second surface;a second semiconductor chip configured to have a third surface and a fourth surface being opposite to each other and configured to have a second side surface connecting edges of the third surface to edges of the fourth surface, wherein the second semiconductor chip is stacked on the second surface of the first semiconductor chip;a first redistribution line structure configured to be disposed on the first surface to be electrically connected to the first semiconductor chip and configured to extend onto the first side surface;a second redistribution line structure configured to be disposed on the first surface to electrically bypass the first semiconductor chip and configured to extend onto the first side surface; anda third redistribution line structure configured to be disposed on the third surface to be electrically connected to the second semiconductor chip and configured to extend onto the second side surface to be electrically connected to the second ...

Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Semiconductor device with through-mold via

In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

Chip-stacked package and method of manufacturing the same

A chip-stacked package and a manufacturing method thereof are provided to prevent the generation of a void within a via by forming the via through a plating method. A substrate(130) includes a wiring pattern(132) and a seed layer(134) formed on the wiring pattern. Each of chips(110) includes an electrode pad and a first through-hole penetrating the electrode pad. The chips are arranged on the seed layer in order to align the through-holes. A plurality of adhesive layers(120) are inserted between the substrate and the chip or between the chips. The adhesive layers have second through-holes. A via(140) is formed by performing a plating process using the seed layer. The via is used for filling up the first and second through-holes and penetrating the electrode pads of the chips in order to connect electrically the electrode pads with the wiring pattern.

Fan-out semiconductor package

본 개시는 관통홀을 갖는 제1연결부재, 상기 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측에 배치된 비활성면을 갖는 반도체칩, 상기 제1연결부재 및 상기 반도체칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 상기 제1연결부재 및 상기 반도체칩의 활성면 상에 배치된 제2연결부재, 상기 봉합재에 일면이 노출되도록 매립된 백사이드 재배선층, 및 상기 백사이드 재배선층 및 상기 봉합재를 관통하는 접속부재를 포함하며, 상기 제1연결부재 및 상기 제2연결부재는 각각 상기 반도체칩의 접속패드와 전기적으로 연결된 재배선층을 포함하며, 상기 백사이드 재배선층은 상기 접속부재를 통해 상기 제1연결부재의 재배선층과 전기적으로 연결되며, 상기 제1연결부재의 재배선층 및 상기 제2연결부재의 재배선층을 거쳐 상기 반도체칩의 접속패드와 전기적으로 연결된, 팬-아웃 반도체 패키지에 관한 것이다. The present disclosure relates to a semiconductor chip having a first connecting member having a through hole, an active surface disposed in a through hole of the first connecting member and having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, A first connecting member and a second connecting member disposed on the active surface of the semiconductor chip, a backside member embedded in the sealing member so as to expose one surface thereof, And a connecting member penetrating the backside re-wiring layer and the sealing material, wherein the first connecting member and the second connecting member each include a re-wiring layer electrically connected to a connection pad of the semiconductor chip, The backside re-wiring layer is electrically connected to the redistribution layer of the first connection member through the connection member, and the redistribution layer of the first connection member and the redistribution layer Through and electrically connected to the connection pad of the semiconductor chip, the fan-out relates to a semiconductor package.

Chip stack package

칩 스택 패키지는 서로 스택된 제1 및 제2반도체 칩들을 포함한다. 제1재배선(redistribution line) 구조는 제1반도체 칩에 전기적으로 연결되고, 제1반도체 칩의 제1표면 상으로부터 제1측면 상으로 연장된다. 제2재배선 구조는 제1반도체 칩을 전기적으로 바이패스(bypass)하고, 제1반도체 칩의 제1표면 상으로부터 제1측면 상으로 연장된다. 제3재배선 구조는 제2반도체 칩에 전기적으로 전기적으로 연결되고, 제2반도체 칩의 제3표면 상으로부터 제2측면 상으로 연장되어 제2재배선 구조에 전기적으로 더 연결된다. The chip stack package includes first and second semiconductor chips stacked on each other. A first redistribution line structure is electrically connected to the first semiconductor chip and extends from the first surface to the first side of the first semiconductor chip. The second redistribution structure electrically bypasses the first semiconductor chip and extends from on the first surface of the first semiconductor chip onto the first side. The third redistribution structure is electrically and electrically connected to the second semiconductor chip, and extends from the third surface to the second side surface of the second semiconductor chip to further electrically connect to the second redistribution structure.

Fan-out-type semiconductor package part

本发明提供了一种扇出型半导体封装件，所述扇出型半导体封装件包括框架、半导体芯片、第一金属凸块、第二金属凸块、包封剂以及连接构件。框架包括绝缘层、布线层和连接过孔层，并且包括具有止挡层的凹入部。半导体芯片具有连接焊盘并设置在凹入部中以使无效表面面对止挡层。第一金属凸块设置在连接焊盘上。第二金属凸块设置在布线层的最上布线层上。包封剂覆盖框架、半导体芯片以及第一金属凸块和第二金属凸块中的每个的至少部分并且填充凹入部的至少部分。连接构件设置在框架和半导体芯片的有效表面上并且包括通过第一金属凸块和第二金属凸块电连接到连接焊盘和最上布线层的重新分布层。

Semiconductor light-emitting device

A light-emitting diode has a GaN-based multi-layer structure arranged on a sapphire substrate. A pair of electrode pads are arranged on a light-output face of the multi-layer structure. The first and second electrode pads have a total projected area set at 25% or less of that of the light-output face. The electrode pads are connected to electrode pads on a mount frame by solder wiring layers arranged on an insulating film covering the side wall of the multi-layer structure.

Multiple bond via arrays of different wire heights on a same substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Semiconductor Package

본 발명은 반도체 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 고비용이 요구되는 와이어 본딩 또는 도전성 범프를 구비하지 않고, 반도체 다이의 도전성 패드와 리드프레임 사이를 도전성 패드 및 리드프레임과 동일한 금속인 전해 도금층 또는 도전성 접착층을 통해 직접 접속시킴으로써, 상호 접속이 용이하고 비용 절감할 수 있으며, 고전류에 의한 손상을 방지하는데 있다. 이를 위해 본 발명은 다수의 도전성 패드가 구비된 반도체 다이 및, 다수의 도전성 패드와 각각 전기적으로 접속된 다수의 리드를 갖는 리드프레임을 포함하고, 리드프레임은 리드에 형성된 전해 도금층을 더 포함하며 리드는 전해도금층을 통해 도전성 패드와 전기적으로 접속을 개시한다. An object of the present invention is to provide a semiconductor package which does not have wire bonding or conductive bumps requiring high cost and which is capable of electrically connecting a conductive pad of a semiconductor die and a lead frame to an electroplating layer Or directly connected through a conductive adhesive layer, thereby facilitating interconnection and reducing costs, and preventing damage due to high currents. To this end, the present invention comprises a semiconductor die having a plurality of conductive pads and a lead frame having a plurality of leads each electrically connected to a plurality of conductive pads, wherein the lead frame further comprises an electroplated layer formed on the leads, Is electrically connected to the conductive pad through the electrolytic plating layer.

Chip laminate encapsulation

本公开涉及一种芯片层叠封装。该芯片层叠封装包括第一半导体芯片和第二半导体芯片。在所述第一半导体芯片的前表面上设置有第一重分布线结构，并且所述第一重分布线结构延伸到所述第一半导体芯片的侧表面上。在所述第一半导体芯片的前表面上设置有第二重分布线结构，并且所述第二重分布线结构延伸到所述第一半导体芯片的侧表面上。在所述第二半导体芯片的前表面上设置有第三重分布线结构，并且所述第三重分布线结构延伸到所述第二半导体芯片的侧表面上以电连接于所述第二重分布线结构。

Package and method of manufacturing the same

一种封装及其制造方法。封装的制造方法包括：形成延伸到介电层的开口中的金属层，以接触第一金属垫及第二金属垫；以及将组件装置的底部端子接合到所述金属层。所述金属层具有直接位于所述组件装置之下且接合到所述组件装置的第一部分。在所述金属层上形成凸起通孔，且所述金属层具有直接位于所述凸起通孔之下的第二部分。刻蚀所述金属层，以将所述金属层的所述第一部分与所述第二部分彼此分离。所述方法进一步包括：以介电层涂布所述凸起通孔及所述组件装置；显露出所述凸起通孔及所述组件装置的顶部端子；以及形成将所述凸起通孔连接到所述顶部端子的重布线。

Fan-out-type semiconductor package part

本发明提供一种扇出型半导体封装件，所述扇出型半导体封装件包括：第一连接构件，具有通孔；半导体芯片，设置在通孔中，并具有有效表面和无效表面，所述有效表面上设置有连接焊盘，所述无效表面与有效表面背对；包封件，包封第一连接构件和半导体芯片的无效表面的至少一部分；第二连接构件，设置在第一连接构件和半导体芯片的有效表面上；树脂层，设置在包封件上；背重新分布层，嵌在包封件中，使得背重新分布层的一个表面通过包封件暴露，其中，树脂层覆盖背重新分布层的所述暴露的一个表面的至少一部分，且背重新分布层通过形成在贯穿树脂层和包封件的第一开口中的连接构件电连接到第一连接构件的重新分布层。

Functional stiffener that enables land grid array interconnections and power decoupling

An exemplary assembly includes a top circuit substrate; a bottom circuit assembly that underlays the top circuit substrate and is attached to the top circuit substrate by an adhesive layer as a stiffener, the adhesive layer, and a plurality of conductive balls. The top circuit substrate includes a plurality of upper vias that extend through the top circuit substrate. The bottom circuit assembly includes a plurality of lower vias that extend through the bottom circuit assembly. The adhesive layer includes internal connections that electrically connect the upper vias to the lower vias. The conductive balls are housed in the lower vias. The bottom circuit assembly has an elastic modulus at least six times the elastic modulus of the top circuit substrate, and has a coefficient of thermal expansion at least two times the coefficient of thermal expansion of the top circuit substrate.

Chip structure and manufacturing method thereof

一種晶片結構包含第一基板、第二基板、導電通道與重佈線層。第一基板具有第一傾斜側壁。第二基板位於第一基板的下表面上，且具有上部與下部。下部凸出上部。上部位於第一基板與下部之間。上部具有第二傾斜側壁，且第一傾斜側壁與第二傾斜側壁的斜率大致相同。導電通道位於下部中。重佈線層從第一基板的上表面依序沿第一傾斜側壁與第二傾斜側壁延伸至第二基板之下部的上表面，且電性連接導電通道。

Package unit, stacking structure thereof and manufacturing method thereof

Electrical interconnect formed by pulsed dispense

전기적 상호연결을 위해 타겟에 인터커넥트 물질을 증착하기 위한 방법이 개시된다. 이 방법은 인터커넥트 물질을 펄스 분출 방식으로 분출하는 단계를 포함한다. 일실시예에서는 인터커넥트 물질의 비말이 발사체 방식으로 증착된다. 일실시예에서는 증착 펄스 이후, 그리고 툴로부터 비말 분리 이전에, 증착 툴의 움직임에 의해 비말이 성형된다. A method for depositing an interconnect material on a target for electrical interconnections is disclosed. The method includes ejecting the interconnect material in a pulsed ejection fashion. In one embodiment, droplets of interconnect material are deposited in a projectile fashion. In one embodiment, after the deposition pulse, and before the droplet separation from the tool, the droplet is shaped by the movement of the deposition tool.

Semiconductor die with conversion coating

A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

Manufacturing method of semiconductor device and semiconductor device

本發明之實施形態提供一種能夠一面抑制半導體晶圓損傷、一面在將複數個半導體晶圓積層後一起進行單片化之半導體裝置之製造方法及半導體裝置。 本實施形態之半導體裝置之製造方法係將第1半導體基板與第2半導體基板積層，該第1半導體基板具有包含半導體元件之第1面及位於該第1面之相反側之第2面，該第2半導體基板具有包含半導體元件之第3面及位於該第3面之相反側之第4面。自第1半導體基板之第2面進行蝕刻，形成自該第2面到達至第1面之第1接觸孔，並且於第1半導體基板之第2面中之第1區域形成第1槽。形成被覆第1槽之第1遮罩材。將第1遮罩材用作遮罩而於第1接觸孔內形成第1金屬電極。去除第1遮罩材之後，將第1半導體基板之第1區域切斷。

ULTRA THIN PoP PACKAGE

A PoP (package-on-package) package includes a bottom package (120) coupled to a top package (100). The bottom package includes a die (108) coupled to an interposer layer (102) with an adhesive layer (110). One or more terminals (104) are coupled to the interposer layer on the periphery of the die. The terminals and the die are at least partially encapsulated in an encapsulant (112). The terminals and the die are coupled to a redistribution layer (RDL). Terminals (116) on the bottom of the RDL (114) are used to couple the PoP package to a motherboard or a printed circuit board (PCB). One or more additional terminals (132) couple the interposer layer to the top package. The additional terminals may be located anywhere along the surface of the interposer layer.

MANUFACTURE OF SEMICONDUCTOR COMPONENTS

Die Erfindung betrifft ein Verfahren zum Herstellen von oberflächenmontierbaren Halbleiterbauelementen. Das Verfahren umfasst ein Bereitstellen einer metallischen Leiterstruktur, wobei die Leiterstruktur in einer ersten Ebene angeordnete vorderseitige Leiterabschnitte, in einer zweiten Ebene versetzt zur ersten Ebene angeordnete rückseitige Leiterabschnitte, sich zwischen den vorderseitigen und rückseitigen Leiterabschnitten erstreckende Zwischenabschnitte und die rückseitigen Leiterabschnitte verbindende Verbindungselemente aufweist. Weiter vorgesehen ist ein Umformen der Leiterstruktur mit einer Formmasse, so dass ein Träger mit einer Vorderseite und einer Rückseite bereitgestellt wird, wobei die vorderseitigen Leiterabschnitte an der Vorderseite und die rückseitigen Leiterabschnitte an der Rückseite des Trägers freiliegen. Das Verfahren umfasst ferner ein Anordnen von Halbleiterchips auf der Vorderseite des Trägers und ein Durchführen eines Vereinzelungsprozesses. Hierbei wird der Träger im Bereich der Verbindungselemente und der rückseitigen Leiterabschnitte durchtrennt und werden vereinzelte oberflächenmontierbare Halbleiterbauelemente gebildet. Die Erfindung betrifft des Weiteren ein oberflächenmontierbares Halbleiterbauelement und eine Anzeigevorrichtung. The invention relates to a method for producing surface mount semiconductor devices. The method comprises providing a metallic conductor structure, the conductor structure having front-side conductor sections arranged in a first plane, rear-side conductor sections arranged in a second plane offset from the first plane, connecting elements connecting between the front-side and rear-side conductor sections, and connecting elements connecting the rear-side conductor sections. It is further provided a forming of the conductor pattern with a molding compound, so that a carrier is provided with a front and a back, wherein the front conductor portions at the front and the rear conductor portions at the back of the ...

Raised via for terminal connections on different planes

본 방법은 제1 금속 패드 및 제2 금속 패드에 접촉하도록 유전체 층의 개구 내로 연장하는 금속층을 형성하는 단계와, 컴포넌트 디바이스의 최하부 단자를 금속층에 접합시키는 단계를 포함한다. 금속층은 컴포넌트 디바이스의 바로 아래에 놓여지고 이에 접합된 제1 부분을 갖는다. 융기된 비아가 금속층 상에 형성되고, 금속층은 융기된 비아의 바로 아래에 놓여진 제2 부분을 갖는다. 금속층은 에칭되어 금속층의 제1 부분과 제2 부분을 서로 분리시킨다. 본 방법은 융기된 비아 및 컴포넌트 디바이스를 유전체 층 내에서 코팅하는 단계, 융기된 비아 및 컴포넌트 디바이스의 최상부 단자를 드러내는 단계, 및 융기된 비아를 최상부 단자에 연결하는 재배선 라인을 형성하는 단계를 더 포함한다.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Bump on via-packaging and methodologies

Production of semiconductor components, semiconductor component, and display device

The invention relates to a method for producing surface-mountable semiconductor components. The method comprises providing a metallic conductor structure, wherein the conductor structure has front-side conductor sections arranged in a first plane, rear-side conductor sections arranged in a second plane offset with respect to the first plane, intermediate sections extending between the front-side and rear-side conductor sections, and connecting elements connecting the rear-side conductor sections. Provision is furthermore made for encapsulating the conductor structure with a molding compound, such that a carrier having a front side and a rear side is provided, wherein the front-side conductor sections are exposed on the front side and the rear-side conductor sections are exposed on the rear side of the carrier. The method furthermore comprises arranging semiconductor chips on the front side of the carrier and carrying out a singulation process. In this case, the carrier is severed in the region of the connecting elements and the rear-side conductor sections and singulated surface-mountable semiconductor components are formed. The invention furthermore relates to a surface-mountable semiconductor component and a display device.

Semiconductor package and method of manufacturing the same

本技术涉及一种半导体封装体。所述半导体封装体包含：包含多个上下叠置的第一裸芯的第一部件，第一裸芯中的每一个包含至少一个侧表面，和暴露在所述侧表面上的电接触，并且多个第一裸芯对齐，使得全部第一裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；第一导电图案，形成在侧壁之上，并且从侧壁至少部分地间隔开，第一导电图案将多个第一裸芯的电接触电互连；至少一个第二部件；以及形成在第二部件的表面上的第二导电图案，第二导电图案固定并且电连接到第一导电图案。

Semiconductor device

半導体装置は、第１半導体素子および第２半導体素子を備えており、各半導体素子は、素子主面および素子裏面を有し、さらに前記素子裏面に配置された素子第１電極と、前記素子主面に配置された素子第２電極とを備える。また、半導体装置は、リード主面およびリード裏面を有する第１リードと、前記第１リード、前記第１半導体素子および前記第２半導体素子を覆う絶縁層と、前記第１半導体素子の前記素子第２電極に導通する第１電極と、前記第１リードに導通する第２電極とを備える。前記第１半導体素子の前記素子裏面と前記リード主面とが対向する姿勢で、前記第１半導体素子と前記第１リードとが接合される。前記第２半導体素子の前記素子裏面と前記リード裏面とが対向する姿勢で、前記第２半導体素子と前記第１リードとが接合される。 The semiconductor device includes a first semiconductor element and a second semiconductor element, and each semiconductor element has an element main surface and an element back surface, and further, an element first electrode arranged on the element back surface and the element main surface. It is provided with a second element electrode arranged on a surface. Further, the semiconductor device includes a first lead having a lead main surface and a lead back surface, an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element, and the element first of the first semiconductor element. A first electrode conducting the two electrodes and a second electrode conducting the first lead are provided. The first semiconductor element and the first lead are joined in a posture in which the back surface of the element and the main surface of the lead of the first semiconductor element face each other. The second semiconductor element and the first lead are joined in a posture in which the back surface of the element and the back surface of the lead of the second semiconductor element face each other.

Chip-to-chip interconnection in an encapsulation of a molded semiconductor package

本发明公开了一种封装半导体器件，其包括：具有上表面的电绝缘包封体主体；包封在所述包封体主体内的第一半导体管芯，所述第一半导体管芯包括主表面，所述主表面具有面对所述包封体主体的上表面的第一导电焊盘；包封在所述包封体主体内并与第一半导体芯片横向并排设置的第二半导体管芯，所述第二半导体管芯具有主表面，所述主表面具有面对所述包封体主体的上表面的第二导电焊盘；以及第一导电轨，其形成在所述包封体主体的上表面中，并且将所述第一导电焊盘电连接到所述第二导电焊盘。包封体主体包括可激光激活的模制化合物。

Electrical interconnect formed by pulsed dispense

Chip assembly having via interconnects joined by plating

An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.

Semicondutor package substrate with die cavity and redistribution layer

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

Wafer level edge stacking

A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.

A method for wafer level packaging and package structure thereof

本揭露提供一種晶圓級之封裝方法及封裝結構，其包含下列步驟。例如，形成一貫穿孔於一中介層，其中該中介層的厚度不大於該第一導電柱的長度；設置該第一導電柱於該貫穿孔；沉積一線路重佈層，其電性連接該第一導電柱；設置一錫球於該線路重佈層上，以形成一晶圓級封裝結構。

CHIP-TO-CHIP CONNECTION IN THE PACKAGE OF A MOLDED SEMICONDUCTOR PACKAGE AND METHOD FOR ITS MANUFACTURE

Gehäuste Halbleitervorrichtung, umfassend:einen elektrisch isolierenden Verkapselungskörper (128) mit einer oberen Oberfläche (130);einen ersten Halbleiterchip (108), der innerhalb des Verkapselungskörpers (128) eingekapselt ist, wobei der erste Halbleiterchip (108) eine Hauptoberfläche (112) mit einem ersten leitenden Pad (118) aufweist, das der oberen Oberfläche (130) des Verkapselungskörpers (128) zugewandt ist;einen zweiten Halbleiterchip (110), der innerhalb des Verkapselungskörpers (128) eingekapselt ist und seitlich neben dem ersten Halbleiterchip (108) angeordnet ist, wobei der zweite Halbleiterchip (110) eine Hauptoberfläche (112) mit einem zweiten leitenden Pad (120) aufweist, das der oberen Oberfläche (130) des Verkapselungskörpers (128) zugewandt ist;eine erste Leiterbahn (138), die in der oberen Oberfläche (130) des Verkapselungskörpers (128) ausgebildet ist und das erste leitende Pad (118) mit dem zweiten leitenden Pad (120) elektrisch verbindet,wobei der Verkapselungskörper (128) eine laseraktivierbare Vergussmasse umfasst;wobei die erste Leiterbahn (138) in einem ersten laseraktivierten Bereich (134) der laseraktivierbaren Vergussmasse ausgebildet ist;eine erste vertikale Verbindungsstruktur (126), die auf dem ersten leitenden Pad (118) angeordnet ist; undeine zweite vertikale Verbindungsstruktur (126), die auf dem zweiten leitenden Pad (120) angeordnet ist,wobei die ersten und zweiten leitenden Pads (118, 120) mit Material des Verkapselungskörpers (128) bedeckt sind, undwobei die ersten und zweiten vertikalen Verbindungsstrukturen (126) jeweils äu-ßere Enden (132) aufweisen, die an der oberen Oberfläche (130) vom Verkapselungskörper (128) freiliegen. A packaged semiconductor device comprising: an electrically insulative encapsulation body (128) having a top surface (130); a first semiconductor die (108) encapsulated within the encapsulation body (128), the first semiconductor die (108) having a major surface (112). a first conductive pad (118) ...

Package unit, stacking structure thereof and manufacturing method thereof

Display device

根据本发明的实施方式的显示装置包括：基板，在该基板上设置有多个发光元件；设置在基板的上表面上的多条线；设置在基板的上表面上并且连接至多条线的多个上焊盘；设置在基板的下表面上的多条链接线；设置在基板的下表面上并且连接至多条链接线的多个下焊盘；以及将多个上焊盘连接至多个下焊盘的多条侧线，其中，多条侧线包括多条第一侧线和多条第二侧线，并且多条第一侧线和多条第二侧线被设置在不同的层上。

Microelectronic interconnect element with decreased conductor spacing

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Display device

표시 장치가 제공된다. 표시 장치는 기판 상에 배치된 제1 전극과 제2 전극, 상기 제1 전극과 상기 제2 전극을 이격하도록 형성된 이격 영역, 상기 제1 전극과 상기 제2 전극 상에 배치되고, 상기 이격 영역을 채우도록 배치되는 제1 절연층, 상기 제1 절연층 상에 배치되며, 상기 제1 전극 상에 배치되는 제1 단부 및 상기 제1 단부와 마주보는 제2 단부를 갖는 발광 소자, 및 상기 제1 단부에 인접하며 상기 제1 절연층을 노출하는 제1 개구부를 포함하고, 상기 이격 영역은 상기 제2 단부에 인접하도록 배치된다.

Microelectronic assemblies with through die attach film connections

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

Fan-out semiconductor package

一種扇出型半導體封裝包括：連接結構，包括一或多個重佈線層；第一半導體晶片，配置於所述連接結構的第一表面上且具有第一連接墊；第一包封體，配置於所述連接結構的所述第一表面上且覆蓋所述第一半導體晶片的至少部分；以及第二半導體晶片，配置於所述連接結構的第二表面上且具有第二連接墊，其中所述第一連接墊藉由所述連接結構的連接通孔電性連接至所述一或多個重佈線層，所述第二連接墊藉由焊線電性連接至所述一或多個重佈線層，且所述第一連接墊與所述第二連接墊藉由所述一或多個重佈線層電性連接至彼此。

Glass core with cavity structure for heterogeneous packaging architecture

A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

Display device

A display device includes first banks extending in a first direction and that are spaced apart from each other in a second direction intersecting the first direction, a first electrode extending in the first direction and including a first part disposed between the first banks, a second electrode extending in the first direction and including a second part spaced apart from the first part in the second direction and disposed between the first banks, a first dummy pattern disposed on one of the first banks and spaced apart from the first part, a second dummy pattern disposed on another one of the first banks and spaced apart from the second part, and light-emitting elements disposed between the first banks, the light-emitting elements having at least one end portion disposed on one of the first part of the first electrode and the second part of the second electrode.

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

封装结构及封装系统

本申请公开一种封装结构及封装系统，该封装结构可以用于封装各种类型的芯片，与PCB耦合后可以形成封装系统。该封装结构包括封装基层、芯片、封装体及连接组件，封装基层具有相对的第一表面和第二表面；芯片耦合于第一表面，芯片背离封装基层的表面具有芯片焊盘；封装体包覆上述封装基层和芯片以保护结构，芯片焊盘通过连接组件走线至封装体的表面。该封装结构中的芯片以贴装的方式耦合于封装基层，芯片的信号可以通过连接组件引出到封装体的表面，不需要使用pin针，方便封装结构减小尺寸，有利于封装结构的小尺寸实现；而且连接组件的结构方便减少引线走线路径，可以减少引线可能带来的寄生效应。

Workpiece chuck, workpiece handling apparatus, manufacturing method of semiconductor package

A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.

電気めっきされたダイ取り付けを備える半導体デバイス

Forming electrical interconnections using capillary microfluidics

A method for manufacturing an electronic device includes providing a substrate with a first major surface having a microchannel, wherein the microchannel has a first end and a second end; dispensing a conductive liquid in the microchannel to cause the conductive liquid to move, primarily by capillary pressure, in a first direction toward the first end of the microchannel and in a second direction toward the second end of the microchannel; and solidifying the conductive liquid to form an electrically conductive trace electrically connecting a first electronic device at the first end of the microchannel to a second electronic device at the second end of the microchannel.

回転を伴う積層によるチップの組み立て

扇出型半导体封装件

本发明提供了一种扇出型半导体封装件，所述扇出型半导体封装件包括框架、半导体芯片、第一金属凸块、第二金属凸块、包封剂以及连接构件。框架包括绝缘层、布线层和连接过孔层，并且包括具有止挡层的凹入部。半导体芯片具有连接焊盘并设置在凹入部中以使无效表面面对止挡层。第一金属凸块设置在连接焊盘上。第二金属凸块设置在布线层的最上布线层上。包封剂覆盖框架、半导体芯片以及第一金属凸块和第二金属凸块中的每个的至少部分并且填充凹入部的至少部分。连接构件设置在框架和半导体芯片的有效表面上并且包括通过第一金属凸块和第二金属凸块电连接到连接焊盘和最上布线层的重新分布层。

Semiconductor devices and methods of manufacturing semiconductor devices

A semiconductor device can comprise a substrate dielectric structure and a substrate conductive structure that traverses the substrate dielectric structure and comprises first and second substrate terminals; an electronic component with a component terminal coupled to the first substrate terminal; and a first antenna element with a first element terminal coupled to the second substrate terminal, a first element head side adjacent a first antenna pattern, a first element base side opposite the first element side, and a first element sidewall. The first element terminal can be exposed from the first element dielectric structure at the first element base side or at the first element sidewall. The first antenna pattern can be coupled to the substrate through the first element terminal. The substrate conductive structure can couple the first antenna element to the electronic component. Other examples and methods are also disclosed.

高周波装置の製造方法

【課題】コストを抑制することが可能な高周波装置の製造方法を提供する。【解決手段】高周波装置の製造方法は、金属ベース１０上に、上面に第１ピラー１６ａが設けられた第１チップ２０ａを搭載する工程と、前記金属ベース１０上に、前記第１チップ２０ａを覆う絶縁体層１２を形成する工程と、前記第１ピラー１６ａの上面を前記絶縁体層１２から露出させる工程と、前記絶縁体層１２上に前記第１ピラー１６ａと接続し、高周波信号を伝送する第１配線１８ａ、１８ｂを形成する工程と、を含む。【選択図】図１

半导体装置及其制造方法

本发明涉及一种半导体装置及其制造方法。根据一实施方式，半导体装置包括具备第1绝缘膜与第1焊垫的第1晶圆或第1芯片。所述装置还包括第2晶圆或第2芯片，所述第2晶圆或第2芯片具备与所述第1绝缘膜相接的第2绝缘膜、及与所述第1焊垫对向且电连接于所述第1焊垫的第2焊垫。进而，所述第1绝缘膜具有在所述第1焊垫延伸的第1槽，及/或所述第2绝缘膜具有在所述第2焊垫延伸的第2槽。