Frame exposes multicore piece to be taken to load in mixture more and piles up double -layered core packaging structure

... 本实用新型涉及一种框架外露多芯片多搭混装堆叠夹芯封装结构，它包括第一引线框（21）、第二引线框（22）、第三引线框（23）、第一芯片（24）和第二芯片（25），所述第一芯片（24）夹设在第一引线框（21）与第二引线框（22）之间，所述第一芯片（24）背面配置于所述第一引线框（21）上，所述第二芯片（25）夹设在第二引线框（22）与第三引线框（23）之间，所述第二芯片（25）正面配置于所述第一上水平段（221）上，所述第一引线框（21）下表面和第二上水平段上表面均暴露于塑封料之外。本实用新型的有益效果是：具有较低的封装电阻和封装电感，具有较好的散热性，整条产品一体成型，生产效率高。 ...

Semiconductor component of integration converter and packaging structure thereof

Semiconductor device and method of manufacturing semiconductor device

The one end portion of the connector of the semiconductor device includes: a horizontal portion; a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction. The lower surface of the control bending portion is in contact with an upper surface of the second terminal.

Power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component, a stack from a vertical junction field effect transistor and MOSFET, bridge circuit, and cascade circuit

The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its ...

Photovoltaic diode

Double-lead frame

Novel structure used for fixing heat radiation copper sheet

Power chip interconnection structure and interconnecting the method

Apparatus and method for forming electro-clip

Semiconductor package with adhesive material pre-printed on the lead frame and chip and the manufacturing method

A combined packaged power semiconductor device

Integrated circuit device packages and substrates for making the packages

Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bone wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.

Leistungsmodul für einen Elektromotor

Die Erfindung betrifft ein Leistungsmodul für einen Elektromotor. Das Leistungsmodul weist wenigstens eine Halbleiterschalter-Halbbrücke auf. Erfindungsgemäß weist die Halbleiterschalter-Halbbrücke einen High-Side-Haltleiterschalter und einen Low-Side-Halbleiterschalter auf, wobei die Halbleiterschalter der Halbbrücke jeweils durch einen insbesondere flach ausgebildeten Oberflächenbereich des Halbleiterschalters gebildete Schaltstreckenanschlüsse aufweisen. Die Schaltstreckenanschlüsse, insbesondere ein Normalenvektor des Schaltstreckenanschlusses, weisen jeweils in dieselbe Richtung. Der High-Side-Halbleiterschalter und der Low-Side-Halbleiterschalter schließen wenigstens eine elektrisch leitfähige Schicht zwischeneinander ein, welche einen Schaltstreckenanschluss des Low-Side-Halbleiterschalters und einen Schaltstreckenanschluss des High-Side-Halbleiterschalters der Halbbrücke miteinander elektrisch verbindet. Bevorzugt ist durch wenigstens eine elektrisch leitfähige Schicht ein Ausgangsanschluss ...

Method and arrangement for contact-connecting semiconductor chips on a metallic substrate

Small-signal diode device

POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Electric Power Conversion Apparatus

An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.

Electric power conversion apparatus

An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.

ELECTRONIC MODULE

An electronic module has a first substrate 11; a second substrate 21 provided in one side of the first substrate 11; and a chip module 100 provided between the first substrate 11 and the second substrate 21. The chip module 100 has an electronic element 13, 23 and a connecting body 60, 70, 80 electrically connected to the electronic element 13, 23. The electronic element 13, 23 extends along a first direction that is a thickness direction of the electronic module.

SEMICONDUCTOR PACKAGE HAVING EXPOSED HEAT SINK FOR HIGH THERMAL CONDUCTIVITY

Provided is a semiconductor package having an exposed heat sink for high thermal conductivity. The semiconductor package includes at least one semiconductor chip 110, the lead frame 120, a signal line 130, the sealing member 140, and at least one heat sink 150, wherein the lead frame 120 has a first surface, to which the semiconductor chips 110 are attached, and a second surface facing the first surface, the signal line 130 electrically connects the semiconductor chips 110 and the semiconductor chip 110 to the lead frame 120 by wire bonding or clip bonding, the sealing member 140 surrounds areas where the semiconductor chips 110 are attached, except for an external connection terminal 121 of the lead frame 120, and exposes the second surface of the lead frame 120, and the at least one heat sink 150 are attached to the second surface of the exposed lead frame 120. Here, spaces A and B are interposed between the sealing member 140 and the heat sink 150 which face each other, and the heat ...

Thin soldering type commutation bridge stack

Solar panel with integrated bypass chip

Power module package

Power semiconductor module having latchable lead member

Substrate structure, method of mounting semiconductor chip, and solid state relay

This invention provides a substrate structure that can effectively prevent scattering of solder balls which are produced due to explosion attributable to evaporation of flux during reflow soldering, and spreading of molten solder to the surroundings. On a substrate, a semiconductor chip is mounted via solder paste. The substrate is provided with a groove portion which continuously or discontinuously surrounds the solder paste.

Leistungshalbleiteranordnung und Verfahren zum Herstellen derselben

Bei einer Leistungshalbleiteranordnung (1) ist eine Kollektorelektrode eines IGBT (11a) mittels eines Verbindungsmaterials (9) mit einer Metallplatte (5) verbunden. Eine Kathodenelektrode einer Diode (11b) ist mittels des Verbindungsmaterials (9) mit der Metallplatte (5) verbunden. Ein Verbindungselement (15a) ist durch ein Verbindungsmaterial (13) mit einer Emitterelektrode des IGBT (11a) verbunden. Das Verbindungsmaterial (13) umfasst ein Verbindungsmaterial (13a) und ein Verbindungsmaterial (13b). Das Verbindungsmaterial (13a) ist zwischen dem IGBT (11a) und dem Verbindungselement (15a) angeordnet. Das Verbindungsmaterial (13b) füllt eine Durchgangsbohrung (16a), die an dem Verbindungselement (15a) ausgebildet ist. Das Verbindungsmaterial (13b) erreicht das Verbindungsmaterial (13a) und ist daher mit dem Verbindungsmaterial (13a) verbunden.

Mehrchipmodul

Es werden ein Mehrchipmodul und ein Verfahren offenbart. Eine Ausführungsform stellt ein Elektronikmodul mit einer ersten Metallstruktur und einer zweiten Metallstruktur bereit. Ein erster Halbleiterchip ist elektrisch mit seiner Rückseite mit der ersten Metallstruktur verbunden. Ein zweiter Halbleiterchip ist mit seiner Rückseite über der Vorderseite des ersten Halbleiterchips liegend angeordnet. Die zweite Metallstruktur enthält mehrere externe Kontaktelemente, die über der Vorderseite des zweiten Halbleiterchips angebracht sind. Mindestens zwei der mehreren externen Kontaktelemente sind elektrisch mit der Vorderseite des zweiten Halbleiterchips verbunden.

Electronic circuit with transmission line type noise filter

Electronic circuit with transmission line type noise filter

Heat dissipation substrate for mounting electric component

Square flat no-pin metal oxide semiconductor (MOS) packaging structure

Semiconductor device packaged with printing bonding materials and manufacturing method thereof

Power Module Package and Method for Manufacturing the same

Power module for an electric motor

A power module for an electric motor includes at least one semiconductor switch half bridge. The half bridge includes a high-side semiconductor switch and a low-side semiconductor switch. Each switch has a contact gap terminal formed by a surface region of the switch, in particular a flat surface region. The contact gap terminals, in particular a normal vector of the terminals, each points in a same direction. At least one electrically conductive layer is enclosed between the switches and electrically connects the contact gap terminal of the low-side semiconductor switch and the contact gap terminal of the high-side semiconductor switch of the half bridge to each other. Preferably an output terminal of the half bridge is formed by at least one electrically conductive layer.

HALBLEITERBAUTEIL, LEISTUNGSMODUL UND HERSTELLUNGSVERFAHREN FÜR DAS HALBLEITERBAUTEIL

Ein Halbleiterbauteil weist auf: einen Halbleiterchip (12); eine gebrannte Ag-Kappe (22), die so gebildet ist, dass sie eine Source-Pad-Elektrode (14) bedeckt, die an dem Halbleiterchip (12) gebildet ist. Der Halbleiterchip (12) ist an einer ersten Substratelektrode (10B) angeordnet, und ein Ende eines Cu-Drahtes (18) ist an die gebrannte Ag-Kappe (22) gebondet, und zwar mittels einer Ultraschallwelle. Es wird ein Halbleiterbauteil bereitgestellt, das dazu in der Lage ist, eine Arbeits- bzw. Leistungszyklus-Fähigkeit zu verbessern, sowie ein Herstellungsverfahren für ein derartiges Halbleiterbauteil.

Wafer packaging structure

Low-thermal-resistance bridge rectifier with main heat conducting surface made of aluminum-based copper-clad plate

A applied to the power switch circuit of the semiconductor packaging structure

LIGHT EMITTING DEVICE PACKAGE

Improved structure of diode element

Semiconductor packaging and fabrication method using connecting plate for internal connection

A semiconductor package with plate bonding is disclosed.The package contains plurality of chips, each of the chip has many top contact regions and bottom contact regions; plurality of base plates, which is used to place the chips, wherein the base plate have many external pins and there is electrical connections between the bottom contact regions and the base plate; plurality of bonding plates, wherein the bonding plate is connect to plurality of chips, and wherein the bonding plate is used to connect correspondence plurality of top contact regions which belongs to plurality of chips so as to make the chips fixed, the end of the bonding plate serve as chip pin for connecting with external part; and a package model which is used to assemble the chips, base plates and bonding plates.During the manufacture process, plurality of chips are fixed by one or more bonding plates, after molding, shallow sawing or grinding the top of the package so as to set apart the bonding plates, the fixed connection ...

Integrated shunt in circuit package

The disclosure is directed to a circuit on a substrate, such as a leadframe package, that includes shunt to measure current. The shunt is an arched conductor positioned to bridge over a die mounted on the package with voltage measurement terminals of the die electrically connected to the shunt. The techniques of this disclosure determine the shunt material, shunt size and shape to accurately control the value of the resistance of the shunt. The arrangement of the die and the shunt may include advantages of maintaining a small package size and allow accurate temperature compensation. The shunt may be long enough to have a measurable resistance that may be used to determine the current through the shunt. In some examples, the arrangement of the die and the shunt may provide additional structural support to the circuit.

Power Module for an Electric Motor

A power module for an electric motor includes at least one semiconductor switch half bridge. The half bridge includes a high-side semiconductor switch and a low-side semiconductor switch. Each switch has a contact gap terminal formed by a surface region of the switch, in particular a flat surface region. The contact gap terminals, in particular a normal vector of the terminals, each points in a same direction. At least one electrically conductive layer is enclosed between the switches and electrically connects the contact gap terminal of the low-side semiconductor switch and the contact gap terminal of the high-side semiconductor switch of the half bridge to each other. Preferably an output terminal of the half bridge is formed by at least one electrically conductive layer.

A PACKAGE STRUCTURE FOR POWER SEMICONDUCTOR DEVICES WITH IMPROVED PARASITIC PARAMETERS

The present invention discloses a package structure for a power semiconductor device, comprising: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies comprises a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, wherein the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

HALBLEITERBAUTEIL MIT INTEGRIERTEM SHUNT-WIDERSTAND UND VERFAHREN ZU DESSEN HERSTELLUNG

Halbleiterbauteil, aufweisend:ein erstes Chippad (30);einen Leistungshalbleiterchip (20), der auf dem ersten Chippad (30) angeordnet ist und zumindest eine erste und eine zweite Leistungselektrode aufweist; undeinen Clip (10) mit einem zentralen Teil, der einen Shunt-Widerstand ausbildet, und einem ersten Kontaktfinger (14), der seitlich aus dem zentralen Teil herausragt, wobei der zentrale Teil mit der ersten Leistungselektrode verbunden ist, wobei ein distales Ende des ersten Kontaktfingers (14) einen ersten externen Anschluss (50, 50.3) des Halbleiterbauteils bildet,wobei der Clip (10) einen zweiten Kontaktfinger (15) des Shunt-Widerstands (220) aufweist, undwobei ein distales Ende des zweiten Kontaktfingers (15) einen zweiten externen Anschluss (50, 50.4) des Halbleiterbauteils bildet.

Semiconductor field effect transistor structure

Single-phase bridge-type rectification module

Plastic packaging type rectifier bridge

Multi-chip stacked package structure and packaging method thereof

Power package module of multiple power chips and method of manufacturing power chip unit

The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.

CARRIER BOARD AND POWER MODULE USING SAME

Verfahren und Anordnung zum Kontaktieren von Halbleiterchips auf einem metallischen Substrat

Die Erfindung betrifft ein Verfahren zum Kontaktieren von Halbleiterchips auf einem metallischen Substrat, auf dem sich mindestens auf einer Seite ein Resist befindet, sowie ein Substrat und ein Modul zur Aufnahme von Halbleiterchips. DOLLAR A Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren und ein Modul der eingangs genannten Art anzugeben, das bei minimaler Dicke des Moduls für hochwertige Halbleiterchips bis 5 x 5 mm·2· Fläche einen optimalen Schutz gegen Stoß, Biegebelastung, Feuchte und gegen Lichteinfluss ermöglicht. DOLLAR A Die Aufgabe wird erfindungsgemäß mit einem Verfahren gelöst, mit dem das Substrat in Form eines einteiligen Grundsubstrates (4) in Bereiche, die künftigen Modulen entsprechen, vorkonstruiert wird, Pads des Halbleiterchips (1) in vorgegebenen Bereichen einer ersten Fläche des vorstrukturierten Grundsubstrats (4) kontaktiert werden und auf der Oberseite (12) des vorstrukturierten Grundsubstrates (4) und der aktiven Flächenseite des Halbleiterchips (1) eine ...

ZWISCHENTRAEGERLEITER FUER DAS FILMTRAEGERBONDEN VON BAUELEMENTEN DER MIKROELEKTRONIK

HALBLEITERBAUTEIL MIT INTEGRIERTEM SHUNT-WIDERSTAND UND VERFAHREN ZU DESSEN HERSTELLUNG

Ein Halbleiterbauteil umfasst ein erstes Chippad, einen Leistungshalbleiterchip, der auf dem ersten Chippad angeordnet ist und zumindest eine erste und eine zweite Leistungselektrode aufweist, und einen Clip, der mit der ersten Leistungselektrode verbunden ist. Dabei bildet ein integraler Teil des Clips einen Shunt-Widerstand und ein erster Kontaktfinger des Shunt-Widerstands ist integral mit dem Clip ausgebildet.

Thin encapsulation body and manufacturing method thereof

The invention discloses a thin encapsulation body, which comprises a lead frame, a chip, a sheet metal and a plastic package body, wherein the lead frame comprises a chip mount part and pins; the chip is arranged on the chip mount part of the lead frame; the sheet metal is used for electrically connecting the chip with the corresponding pin of the lead frame; the plastic package body at least covers the chip, the sheet metal, the joint between the sheet metal and the chip, and the joint between the sheet metal and the pins; and the sheet metal and the pin connecting the sheet metal and the lead frame are respectively provided with at least one transverse buckling to buffer heat stress generated when the chip operates, and the plastic package body further covers the buckling part of the pin. The invention has the advantages that by arranging a buckling structure on the sheet metal and the pin connected with the sheet metal, the heat stress generated on the plastic package body by the chip ...

Can promote power module bridge of thermal capacitance

Stacked package with dual chip and fabricating method thereof

This invention aims to providing a stacked package with dual chip and fabricating method thereof. Bond a first chip to a paddle of lead frame with flip chip technology, and bond a first clip on backside of the first chip. Stack a second chip on the first clip with flip chip, then bond a second clip on backside of the second chip. Encapsulate the stacked package and exposed the bottom surface of the paddle, and exposed top side of the second clip if needed.

Chip package structure

A chip package structure is provided. The chip package structure adapted to be assembled on a printed circuit board and includes a lead frame and a chip. The lead frame has a bottom portion and a partition plate protruding from the bottom portion. The partition plate is electrically connected to the bottom portion. The chip is disposed on the bottom portion, and the chip and the partition plate are located at the same side of the bottom portion. The chip has an electrode disposed on the back of the chip and facing to the bottom portion, and the electrode is electrically connected to the bottom portion. The chip package structure has a gap between the partition plate and the chip.

Stacked package with dual chip and fabricating method thereof

Power encapsulation module of multi-power chip and manufacturing method of power chip unit

Integrated power package

An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical conductor is located between the first surface and another point on the substrate. At least one transistor is electrically and mechanically coupled to the at least one first conductor. A support structure is electrically and mechanically coupled to the at least one transistor, wherein the at least one transistor is located between the first surface of the substrate and the support structure.

MULTI-CHIP MODULE

A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip.

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS UNTER VERWENDUNG VERSCHIEDENER VERBINDUNGSVERFAHREN FÜR DEN HALBLEITERDIE UND DEN CLIP

Halbleiterbauelement (10), das einen Träger (11), einen ersten externen Kontakt (12) und einen zweiten externen Kontakt (13), einen Halbleiterdie (14) mit einer ersten Hauptfläche und einer zweiten Hauptfläche gegenüber der ersten Hauptfläche, ein erstes Kontaktpad (14.1), das auf der ersten Hauptfläche angeordnet ist, ein zweites Kontaktpad (14.2), das auf der zweiten Hauptfläche angeordnet ist, und ein drittes Kontaktpad (14) umfasst, das auf der zweiten Hauptfläche angeordnet ist, wobei der Halbleiterdie (14) einen vertikalen Transistor umfasst und mit seiner ersten Hauptfläche auf dem Träger (11) angeordnet ist, ein Clip (15), der das zweite Kontaktpad (14.2) mit dem zweiten externen Kontakt (13) verbindet, und einen ersten Bonddraht (16), der mit dem ersten externen Kontakt (12) verbunden ist, wobei der erste Bonddraht (16) zwischen das dritte Kontaktpad (14.3) und den ersten externen Kontakt (12) geschaltet ist, und wobei der erste Bonddraht (16) zumindest teilweise unter der Klammer ...

Ultrathin diode pin

Power control device and its preparation method

Power semiconductor device and manufacturing method thereof

The present invention relates to a power converter device which integrates a low side MOSFET and a high side MOSFET to form a control IC. A first chip is attached on a first region in a manner of flip-chip and its metal pads disposed on front face are abutting joint with the solder pads in the first region. A second chip is attached on a second region in a manner of flip-chip and its metal pads disposed on front face are abutting joint with the solder pads in the second region. A conductive structure is connected between a bonding pad and metal layer disposed on backside of the first chip, a plastic package is disposed on the front-side of substrate and encapsulates the first and second chip and the conductive structure.

Power semiconductor device and power module

Provided is a small-sized power semiconductor device in which interference between power modules adjacently disposed is prevented and the areas of the gaps occurring between the power modules are reduced. In a power semiconductor device formed by adjacently disposing power modules in an arc shape on a heat sink, each of which power modules is obtained by sealing, with a mold resin, a switchable power semiconductor chip, a lead frame in which potential leads and signal terminals connected to the power semiconductor chip are formed, and a metallic inner lead electrically connecting an upper surface electrode of the power semiconductor chip and the lead frame, any one of the adjacent power modules is formed in a pentagonal shape having, at a portion adjacent to the other power module, an oblique side 10a obtained by cutting out one corner of a quadrangle.

Halbleitervorrichtung

Es besteht das Problem, dass die Zuverlässigkeit der Isolation abgesenkt wird. Eine Länge L2 von einer Mitte P einer Leiterschicht 334 bis zu einem Umfangskantenabschnitt eines Isolierelements 333 ist derart gebildet, dass sie länger als eine Länge L1 von der Mitte P der Leiterschicht 334 bis zu einem Umfangskantenabschnitt eines vorstehenden Abschnitts 307a eines Grundelements 307 ist. Mit anderen Worten, eine Grund-Endfläche 308 des Umfangskantenabschnitts des vorstehenden Abschnitts 307a ist in Bezug auf eine Isolierelement-Endfläche 336 des Umfangskantenabschnitts des Isolierelements 333 auf einer Innenseite angeordnet. Ferner bilden die Isolierelement-Endfläche 336 des Isolierelements 333 und eine Leiterschicht-Endfläche 344 der Leiterschicht an derselben Position eine Endfläche. Da die Grund-Endfläche 308 des Umfangskantenabschnitts des vorstehenden Abschnitts 307a auf diese Weise in Bezug auf die Isolierelement-Endfläche 336 des Umfangskantenabschnitts des Isolierelements 333 auf ...

HALBLEITERBAUTEIL UND VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUTEILS

Ein Halbleiterbauteil A1 weist ein Halbleiterelement 10A mit einer Elementvorderfläche 101 und einer Elementrückfläche 102 auf, wobei die Elementvorderfläche 101 eine darauf ausgebildete Vorderflächenelektrode 11 und die Elementrückfläche 102 eine darauf ausgebildete Rückflächenelektrode 12 aufweist, ein leitfähiges Substrat 22A, das eine der Elementrückfläche 102 gegenüberliegende Vorderfläche 221A aufweist, und mit dem die Rückflächenelektrode 12 leitend verbunden ist, ein leitfähiges Substrat 22B, das eine Vorderfläche 221B aufweist und von dem leitfähigen Substrat 22A in einer Breitenrichtung x beabstandet ist, und ein Anschlusselement 51, das sich in der Breitenrichtung x erstreckt und die Vorderflächenelektrode 11 und das leitfähige Substrat 22B elektrisch verbindet. Das Anschlusselement 51 ist in der Richtung, in der die Vorderfläche 221B ausgerichtet ist, vor der Vorderfläche 221B angeordnet und mit der Vorderflächenelektrode 11 über eine Anschluss-Bondschicht 32 gebondet. Das leitfähige ...

Semiconductor device

Single row direct insert full wave rectifier bridge stack

Semiconductor package

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR

An electronic device and a manufacturing method thereof are provided. The pattern circuit of each surface mount structure of the electronic device is disposed on the substrate; at least two through holes are respectively corresponding to at least two signal lines of the pattern circuit; and the two ends of at least one optoelectronic element are respectively electrically connected to at least two signal lines of the pattern circuit. Each connection pad group of the driving circuit board is corresponding to each surface mount structure, and at least two connection pads are respectively corresponding to the at least two through holes of the surface mount structure. At least two conductive members of each conductive member unit are disposed in the at least two through holes of the surface mount structure, respectively, and extending to the first surface and the second surface of the substrate. The conductive member disposed in each through hole electrically connects the signal lines of each ...

Semiconductor encapsulation structure

Rectifying chip for microelectronic device

ELECTRONIC CIRCUIT WITH TRANSMISSION LINE TYPE NOISE FILTER

Semiconductor package structure

A semiconductor package structure includes a first conductor, a first bonding layer, a first conductive sheet and a second conductive sheet. The first bonding layer is disposed at the first conductor. The first conductive sheet includes a first bonding portion and a first extending portion connected to each other. The first bonding portion is bonded to the first bonding layer, wherein the first conductive sheet has a first trench and the first bonding portion is divided into two first bonding branches arranged side by side through the first trench. The second conductive sheet includes a second bonding portion and a second extending portion connected to each other. The second bonding portion is bonded to the first bonding layer, wherein the second conductive sheet has a second trench and the second bonding portion is divided into two second bonding branches arranged side by side through the second trench. The first extending portion and the second extending portion are arranged side by side ...

Elektronikmodul, Verfahren

Die Erfindung betrifft ein Elektronikmodul (6), insbesondere Leistungsmodul, mit zumindest einem elektrischen/elektronischen Bauteil (7) und mit einem das Bauteil (7) zumindest teilweise umgebenden Gehäuse (8), wobei das Gehäuse (8) aus Zementkomposit (1) gefertigt ist, und wobei der Zementkomposit (1) zumindest einen partikelförmigen Füllstoff (2) aufweist. Es ist vorgesehen, dass der partikelförmige Füllstoff (2) Aluminiumnitrid-Partikel (3) aufweist, die jeweils eine Beschichtung nur aus Aluminiumoxid (4) aufweisen.

Slim bridge rectifier of new construction

Paster type diode device

Non-pin power metal-oxide semiconductor field effect transistor (MOSFET) device

Semiconductor device and electronic device

Semiconductor packaging through metallic bonding and method for same

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes a first insulating resin member sealing a mounting surface of a lead frame, and a second insulating resin member sealing a heat dissipating surface. The second insulating resin member contains a filler having a maximum diameter of 0.02 mm to 0.075 mm. The second insulating resin member includes a thin molded portion formed in contact with the heat dissipating surface of the lead frame. The thin molded portion has a thickness 1.1 times to 2 times the maximum diameter of the filler. The semiconductor device includes, at an interface between the first insulating resin member and the second insulating resin member, a mixture layer in which these resins are mixed with each other.

Electronic circuit with transmission line type noise filter

In an electronic circuit having an integrated circuit (110) having a power supply terminal, a noise filter disposed adjacent to the integrated circuit, and a printed board (101) having a pattern for supplying a power supply to the power supply terminals of the integrated circuit through the noise filter, the noise filter consists of a transmission line type noise filter (121-124) for removing noises having a wide frequency band.

Three phase bridge apparatus

Voltage-stabilizing semiconductor device for small signals

Apparatus and method for fabricating semiconductor chip package

Molded Leadless Package and LED Package fabricated using the same

전기 모터용 파워 모듈

... 본 발명은 전기 모터용 파워 모듈에 관한 것이다. 파워 모듈은 적어도 하나의 반도체 스위치 하프 브리지를 포함한다. 본 발명에 따르면, 반도체 스위치 하프 브리지는 하이 측 반도체 스위치와 로우 측 반도체 스위치를 포함하고, 하프 브리지의 반도체 스위치는 각각 반도체 스위치의 특히 평평한 표면 영역에 의해 형성된 콘택 갭 단자를 포함한다. 콘택 갭 단자, 특히 콘택 갭 단자의 법선 벡터는 각각 동일한 방향으로 향한다. 하이 측 반도체 스위치 및 로우 측 반도체 스위치는 그들 사이에 적어도 하나의 전기 전도성 층을 포함하고, 상기 전기 전도성 층은 하프 브리지의 로우 측 반도체 스위치의 콘택 갭 단자와 하이 측 반도체 스위치의 콘택 갭 단자를 전기 접속한다. 바람직하게는 적어도 하나의 전기 전도성 층에 의해 하프 브리지의 출력 단자가 형성된다.

SEMICONDUCTOR DEVICE

A semiconductor device includes a metal member (15), a first semiconductor chip (13), a second semiconductor chip (14), a first solder (24) and a second solder (25). A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer (13a) connected to the metal member through a first solder (24) at a surface facing the metal member. The second semiconductor chip has a second metal layer (14a) connected to the metal member through a second solder (25) at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.

LEISTUNGSHALBLEITERMODUL UND VERFAHREN ZUR HERSTELLUNG DES MODULS

Power module

Plate thyristor and plate transistor as well as application technology thereof

The invention discloses a semiconductor substrate of a plate thyristor and a plate transistor researched by adopting a novel power electronics technology according to an arc-free cutout theory and a semiconductor theory on the basis of the invention patent of a cutoff switch, and a whole set of special application technology is researched. The plate thyristor and the plate transistor are used together with a contactor or a circuit breaker to realize the arc-free operation and manufacture a safe, explosion-proof and environment-friendly power switch. A derived branch system is respectively added for the two big families of the thyristors and the transistors in the semiconductor field. The invention provides continuously innovated technical conditions for high-disjunction technology and safe anti-explosion technology of an arc-free breaking-closing switch in the field of electric switches, the environment-friendly technology for eliminating the serious pollution of operation overvoltage to ...

Solar connecting box

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor die package including low stress configuration

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Support structures and clamping systems for semiconductor devices during wire and ribbon bonding operations

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Electronic module

An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 μm.

Semiconductor device and driving apparatus including semiconductor device

A semiconductor device includes a semiconductor module and a pressing member configured to press the semiconductor module to a heat radiation member. The semiconductor module includes switching elements, conductors, and a molded member. Each of the switching elements is mounted on a corresponding one of the conductors. The molded member covers the switching elements and the conductors. More than three of the switching elements are disposed around the pressing member. The switching elements are disposed in a region in which a pressure generated between the semiconductor module and the heat radiation member by pressing with the pressing member is greater than or equal to a predetermined pressure with which heat generated from the switching elements is releasable from the semiconductor module to the heat radiation member.

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Power Module with Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Power Converter Device

A power converter device includes first through third semiconductor modules provided for phases of a three-phase inverter circuit, and incorporating upper and lower arms series circuit, and a flow path forming cabinet in a rectangular prism shape having an electric equipment containing space and a coolant flow path formed to surround the electric equipment containing space, the coolant flow path includes a first flow path provided along a first side face of the flow path forming cabinet, a second flow path provided along a second side face contiguous to one side of the first side face and connected to one end of the first flow path, and a third flow path provided along a third side face contiguous to other side of the first side face and connected to other end of the first flow path.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Power converter apparatus

A power converter apparatus includes a first substrate and a second substrate closely arranged to face each other, switching elements mounted on respective mounting surfaces of the first and second substrates, a primary and a secondary bus bars extending between the first and second substrates, an output terminal electrically connected to the primary bus bar, and two input terminals provided on the second substrate. The direction in which current flows into the first substrate and the direction in which current flows into the second substrate via the input and the output terminals are opposite to each other, and the direction in which the current flows into the primary bus bar and a direction in which the current flows into the secondary bus bar are opposite to each other. The first substrate and second substrate include heat dissipating members provided on surfaces opposite to the mounting surfaces for the switching elements.

Dual Power Converter Package Using External Driver IC

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

Monolithic Power Converter Package

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Semiconductor device and method of packaging a semiconductor device with a clip

A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Reliable Area Joints for Power Semiconductors

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Packaged semiconductor device with an exposed metal top surface

In a manufacturing technique for packaged semiconductor devices, a pre-form of a packaged semiconductor device is formed by a molding process which encapsulates the semiconductor device and its associated heat transfer component in a passivating material presenting a surface. The surface is then processed to at least remove excess passivating material and expose the heat transfer component. The processing may further remove a portion of the heat transfer component. The removal process may, for example, utilize a grinding and/or polishing process. The process may be controlled so as to expose or form a heat transfer surface of desired shape and size.

Cooling apparatus

A cooling apparatus includes a case in which a refrigerant passage through which a refrigerant flows is formed inside, and an element module partially disposed within the refrigerant passage and including an element provided inside. A portion of the element module in contact with the refrigerant is formed of an insulating material.

Thermally Enhanced Semiconductor Package with Conductive Clip

One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Semiconductor Device Apparatus and Assembly with Opposite Die Orientations

An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device, and method of manufacturing semiconductor device

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

Electronic device and semiconductor device

Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Semiconductor Device Having a Clip Contact

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Semiconductor package

Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

Semiconductor device

A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board. 1. A semiconductor package comprising:a molding compound having a top surface and a bottom surface;a chip encapsulated in the molding compound and having a bottom on which a solder layer is formed, the solder layer being exposed from the bottom surface of the molding compound; and a bottom exposed from the bottom surface of the molding compound;', 'a perpendicular side surface; and', 'an anchor flange formed around a top surface of the conductive pad to engage the molding compound., 'a conductive pad encapsulated in the molding compound and electrically connected to the chip and having'}2. The semiconductor package as claimed in claim 1 , wherein the top surface of the conductive pad is substantially co-planar with a top surface of the chip.3. The semiconductor package as claimed in claim 1 , wherein the conductive pad is formed by multiple layers of metal material electroplated on a carrier.4. The semiconductor package as claimed in claim 3 , wherein the metal material comprises aurum claim 3 , nickel claim 3 , copper or a combination thereof; andthe metal material at the bottom of the conductive pad is exposed from the bottom surface of the molding compound.5. The semiconductor package as claimed in claim 3 , wherein the chip is electrically connected to the top surface of the conductive pad via a redistribution layer.6. The semiconductor package as claimed in claim 1 , wherein the solder layer on the bottom ...

Exposed die clip bond power package

In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Resin-sealed electronic control device

The present invention is intended to increase the moisture resistance of a resin-sealed electronic control device. The resin-sealed electronic control device includes: a semiconductor chip; a chip capacitor; a chip resistor; a bonding member; a substrate; a case; a heat radiating plate; a glass coating; and a first sealing material. The glass coating directly covers the electronic circuit formed by the element group including: the semiconductor chip; the chip capacitor; and the chip resistor, the bonding member and the substrate, and is sealed by the first sealing material. By being water impermeable, the glass coating prevents water absorption in the vicinity of the element group, and can prevent an increase in the leak current of the semiconductor chip due to water absorption, and an insulation performance drop such as lowered insulation resistance caused by migration within the element group.

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. 1. A semiconductor component having at least first and second terminals , comprising:a leadframe having first and second opposing sides, a device receiving area, and a first lead integrally formed with the leadframe;an insulated metal substrate having a first surface and a second surface, the second surface coupled to the leadframe;a first semiconductor chip mounted to the insulated metal substrate, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the insulated metal substrate; anda second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, an anode formed from the first surface and a cathode formed from the second surface, wherein the cathode is coupled to the first source bond pad.2. The semiconductor component of claim 1 , further including a second lead that is electrically isolated from the leadframe and wherein the first gate bond pad is electrically coupled to ...

Lead frame assembly for a semiconductor device

This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

GANG CLIP

An integrated circuit (IC) package includes a lead frame and a first die attached to the lead frame. The IC package also includes a first clip attached to first die and the lead frame. The IC package further includes a second die attached to first clip and the lead frame. The IC package still further includes a second clip with a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending to and contacting a side of the second die via a layer of solder paste. The second clip includes a sawn or lased edge at a second side of the second clip opposing the first side of the second clip. 1. An integrated circuit (IC) package comprising:a lead frame;a first die adhered to the lead frame on a first side of the first die;a first clip having a clip foot adhered to the lead frame, the first clip extending from the lead frame and contacting a second side of the first die on a first side of the first clip via a first layer of solder paste wherein the second side of the first die opposes the first side of the first die;a second die with a first side adhered to a second side of the first clip via a second layer of solder paste, wherein the second side of the first clip opposes the first side of the first clip; anda second clip having a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending from the lead frame to a second side of the second die via a third layer of solder paste, the second side of the second die opposing the first side of the second die, wherein the second clip has an sawn or lased edge on a second side of the second clip, wherein the second side of the second clip opposes the first side of the second clip.2. The IC package of claim 1 , wherein the sawn or lased edge is parallel to an edge of the lead frame.3. The IC package of claim 1 , wherein the second clip comprises a high side that includes the sawn or lased edge claim 1 , and wherein a surface of the high side that is ...

POWER SEMICONDUCTOR DEVICE

At the time of clamping, excessive stress is applied to bonding parts between substrates and input/output terminals, which may cause the bonding parts to be detached and cause the substrates to be cracked. 1. A power semiconductor device comprising:a semiconductor element including an upper electrode and a lower electrode;a first interconnection layer arranged to be opposed to the lower electrode of the semiconductor element and connected to the lower electrode of the semiconductor element via a bonding material;a second interconnection layer arranged to be opposed to the upper electrode of the semiconductor element and connected to the upper electrode of the semiconductor element via the bonding material;a first main terminal connected to the first interconnection layer via the bonding material;a second main terminal connected to the second interconnection layer via the bonding material; anda spacer,wherein the spacer is arranged to be parallel to the first interconnection layer or the second interconnection layer and is provided with the first main terminal or the second main terminal.2. The power semiconductor device according to claim 1 , wherein the spacer is a third interconnection layer connected via the bonding material to an opposite surface of a bonding surface between the first interconnection layer or the second interconnection layer and the first main terminal or the second main terminal.3. The power semiconductor device according to claim 2 , wherein the first interconnection layer and the third interconnection layer are separated from a lead frame.4. The power semiconductor device according to claim 2 , whereinthe first interconnection layer is connected via the bonding material to a side of the lower electrode of the semiconductor element, and the second interconnection layer is connected via the bonding material to a side of the upper electrode of the semiconductor element,an insulating layer and a heat dissipating layer are laminated on a side of ...

Semiconductor module

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

DAMAGING COMPONENTS WITH DEFECTIVE ELECTRICAL COUPLINGS

A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective. 1. A method of determining a defective component , the method comprising:providing a component having a first electrical coupler and a second electrical coupler;determining that the component lacks a functional electrical coupling between the first electrical coupler and the second electrical coupler;damaging at least part of the component by shorting the first electrical coupler to the second electrical coupler as a result of the determination; anddetermining, as a result of the damage, that the component is defective.2. The method of claim 1 , wherein damaging at least part of the component further comprises using a laser to short one or more electrical connections in the component.3. The method of claim 1 , wherein damaging at least part of the component further comprises dispensing an electrically conductive material to short one or more electrical connections in the component.4. The method of claim 1 , wherein damaging at least part of the component further comprises electrically coupling a first surface of a die to a second surface of the die.5. The method of claim 1 , wherein damaging at least part of the component further comprises electrically coupling one of a first surface or a second surface of a die to a side surface of the die.6. The method of claim 1 , further comprising damaging using a wire bonding machine.7. The method of claim 1 , wherein determining that the component is defective further comprises determining that the component is defective using an electrical test.8. The method of claim 1 , wherein the first electrical coupler comprises a die.9. The method of claim 1 , wherein ...

Electronic component device

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar. 1. A method of forming packaged semiconductor devices , comprising:providing a first conductive frame having joined conductive portions;attaching semiconductor components to the first conductive frame;providing a second conductive frame comprising interconnected conductive clips;attaching the second conductive frame to the first conductive frame to provide a first sub-assembly, wherein the interconnected conductive clips are coupled to the first conductive frame;encapsulating the first sub-assembly with an encapsulant to provide an encapsulated sub-assembly; andseparating the encapsulated sub-assembly to provide the packaged semiconductor devices, wherein the step of separating disconnects the interconnected conductive clips from the second conductive frame.2. The method of claim 1 , further comprising:removing the joined conductive portions of the first conductive frame to form conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly; and 'the step of separating comprises providing each of the packaged semiconductor devices having portions ...

BUSBAR, METHOD FOR MANUFACTURING THE SAME AND POWER MODULE COMPRISING THE SAME

A conducting busbar () suitable for use in a semiconductor power module () is provided. The busbar () comprises a main plate (), one or more legs () extending from the main plate (), and one or more feet () formed at the free end of the legs (). According to the invention, the intersection line (L) between at least one of the legs () and the associated foot () forms an offset angle (α) with respect to the longitudinal direction (X) of the main plate (). 1. A conducting busbar suitable for use in a semiconductor power module , comprising a main plate , one or more legs extending from the main plate , and one or more feet formed at the free end of the legs , wherein the intersection line between at least one of the legs and the associated foot forms an offset angle with respect to the longitudinal direction of the main plate.2. The conducting busbar of claim 1 , wherein at least one of the legs of the busbar comprises a twisted section through which the plane of the leg is rotated by the offset angle.3. The conducting busbar of claim 1 , wherein the offset angle formed by the intersection line between the at least one of the legs and the associated foot with respect to the longitudinal direction of the main plate is from 3° up to 180° claim 1 , in particular from 45° to 135° claim 1 , in particular approximately 90°.4. The conducting busbar of claim 2 , wherein each leg of the busbar comprises a twisted section through which the plane of the leg is rotated by an offset angle.5. The conducting busbar of claim 4 , wherein all the legs are twisted through the same angle and in the same direction.6. The conducting busbar of claim 1 , wherein the legs of the busbar extend from one side or two opposite sides of the main plate of the busbar claim 1 , in particular the two longitudinal sides.7. A busbar system comprising two or more busbars of claim 1 , wherein the busbars are in close proximity with an air gap or an insulating film or layer between them.8. A power module ...

CLIPS FOR SEMICONDUCTOR PACKAGES

A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars. 1. A clip for a semiconductor package , the clip comprising:a first planar portion;a plurality of first pillars, each first pillar of the plurality of first pillars coupled to the first planar portion; anda plurality of first solder balls, each first solder ball of the plurality of first solder balls coupled to a corresponding first pillar of the plurality of first pillars.2. The clip of claim 1 , further comprising:a second planar portion;a third portion coupling the first planar portion to the second planar portion;a plurality of second pillars, each second pillar of the plurality of second pillars coupled to the second planar portion; anda plurality of second solder balls, each second solder ball of the plurality of second solder balls coupled to a corresponding second pillar of the plurality of second pillars.3. The clip of claim 2 , wherein the first planar portion and the second planar portion are in different planes.4. The clip of claim 1 , wherein each first pillar of the plurality of first pillars is cylindrically shaped.5. The clip of claim 1 , wherein each first pillar of the plurality of first pillars has a height up to 80 μm.6. The clip of claim 1 , wherein each first pillar of the plurality of first pillars has a diameter of 0.25 mm or larger.7. The clip of claim 1 , wherein the plurality of first pillars are arranged in a symmetric pattern.8. The clip of claim 1 , wherein each first pillar of the plurality of first pillars is integral to the first planar portion.9. The clip of claim 1 , wherein each first pillar of ...

Semiconductor module

A semiconductor module according to the present disclosure includes: an insulating substrate; a first conductor disposed on the insulating substrate; a second conductor disposed on the insulating substrate; a first semiconductor element disposed on the first conductor; a second semiconductor element disposed on the second conductor; a first busbar connected to the first conductor in a region between the first semiconductor element and the second semiconductor element; a second busbar connected to the second semiconductor element; and an output busbar connecting the first semiconductor element to the second conductor and connected to the second conductor in the region between the first semiconductor element and the second semiconductor element. The output busbar is disposed at least partially overlapping the first busbar, and in an overlap region between the output busbar and the first busbar, the output busbar is located above the first busbar.

Power device package structure

A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.

FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF

A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. 1. A radio-frequency (RF) device comprising:an integrated circuit (IC) die, the IC die including at least one RF amplifier to implement the RF device;a package containing the IC die; anda flexible circuit lead coupled to the IC die inside the package, the flexible circuit lead extending from inside the package to outside the package, the flexible circuit lead comprising at least one flexible base layer and at least one conductor, the flexible circuit lead providing an electrical connection to the at least one RF amplifier on the IC die, wherein the at least one conductor is configured to form at least one passive device in a filter, with the filter electrically connected to the RF amplifier inside the package and through the flexible circuit lead.2. The RF device of wherein the at least one passive device formed with the least one conductor comprises a spiral inductor.3. The RF device of wherein the at least one passive device formed with the least one conductor comprises an inductor and a capacitor.4. The RF device of wherein the filter further includes at least one lumped passive element mounted on the flexible circuit lead.5. The RF device of wherein the at least one conductor in the flexible circuit lead is further configured to form a transmission line in the flexible circuit lead such that the transmission line is electrically connected to the RF amplifier claim 1 , and wherein the transmission line is formed ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent. 1. A semiconductor device , comprising:a seal portion;a first electronic element disposed in the seal portion;a second electronic element disposed in the seal portion;a first lead terminal having one end, on a top surface of which the first electronic element is disposed within the seal portion, and another end that is exposed from the seal portion;a second lead terminal having one end, on a top surface of which the second electronic element is disposed within the seal portion, and another end that is exposed from the seal portion;a connecting element having one end that is electrically connected to an input/output electrode of the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; anda first conductive bonding agent for joining together the other end of the connecting element and the top surface of the one end of the second lead terminal,wherein a groove is formed on the top surface of the one end of the second lead terminal, the groove preventing the first conductive bonding agent from flowing toward the second electronic element when the connecting element and the second lead terminal are joined together, and performing a mold lock when the seal portion is sealed,wherein the groove is formed on the top surface of the one end of the ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support. 1. A semiconductor component , comprising:a support having a first device receiving structure and a second device receiving structure, the first device receiving structure comprising a device receiving area, the second device receiving structure comprising a drain contact area and a first interconnect, the support further including a contact extension, the contact extension common to the first device receiving structure and the second device receiving structure;a first lead spaced apart from the support;a first semiconductor chip having a first surface and a second surface, wherein a first gate bond pad extends from a first portion of the first surface, a source bond pad extends from a second portion of the first surface, and a drain bond pad extends from a third portion of the first surface, the first gate bond pad of the first semiconductor chip coupled to the first interconnect of the second device receiving structure, the drain bond pad coupled to the drain contact area of the second device receiving structure, and the source bond pad of the first ...

Semiconductor component and method of manufacture

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

Power module

A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low.

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

SWITCHING DEVICE AND ELECTRONIC CIRCUIT

A switching device includes a SiC semiconductor chip which has a gate pad , a source pad and a drain pad and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal electrically connected to the source pad for applying the drive voltage, and an external resistance (source wire ) that is interposed in a current path between the sense source terminal and the source pad , is separated from sense source terminal , and has a predetermined size. 18-. (canceled)9. A switching device including:a switching element having a gate electrode, a first output electrode, and a second output electrode;a second output terminal electrically connected to the second output electrode and having an island on which the switching element is mounted;a gate terminal electrically connected to the gate electrode;a first output terminal electrically connected to the first output electrode;a third output terminal electrically connected to the first output electrode and spaced apart from the first output terminal, anda resin package sealing the switching element, a part of the gate terminal, a part of the first output terminal, a part of the third output terminal and a part of the second output terminal; whereinthe gate terminal, the first output terminal, the third output terminal and the second output terminal each include a sealing portion sealed in the resin package and a terminal portion protruding in the same direction with respect to the resin package and protruding therefrom,the distance between the terminal portion of the first output terminal and the terminal portion of the second output terminal is greater than the distance between the terminal portion of the third output terminal and the terminal portion of the gate terminal.10. The switching device according to claim 9 , wherein the first output electrode ...

Unit power module and power module package comprising the same

Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate.

Semiconductor leadframes and packages with solder dams and related methods

A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.

Semiconductor device, method for assembling semiconductor device, semiconductor device component, and unit module

A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion. The radiation portion of the radiation block has a pin shape, a fin shape, or a porous shape.

All-in-one power semiconductor module

Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

Method and apparatus for making integrated circuit packages

A method of making a plurality of integrated circuit (“IC”) packages includes picking up a plurality of physically unconnected IC components; and simultaneously placing each of the physically unconnected IC components on corresponding portions of an unsingulated IC package strip that includes a sheet of integrally connected leadframes.

Electronic device including a hemt

An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

PCB Based Semiconductor Package Having Integrated Electrical Functionality

A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

SEMICONDUCTOR DEVICE

A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure. 1. A semiconductor device comprising:an insulating circuit substrate;a semiconductor element including a first main electrode bonded to a top surface of a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on a top surface of the first main electrode, and a second main electrode deposited on a top surface of the semiconductor substrate; anda resistive element including a bottom surface electrode bonded to a top surface of a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a first top surface electrode electrically connected to another end of the resistive layer,wherein the first main electrode includes a first bonded layer bonded to the first bonding material,the bottom surface electrode includes a second bonded layer bonded to the second bonding material, andthe first bonded layer and the second bonded ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device. 120-. (canceled)21. A semiconductor device comprising:a semiconductor chip on which first and second electrodes are formed on a front surface side of a semiconductor layer and a third electrode is formed on a back surface side of the semiconductor layer, the semiconductor chip configured to perform a switching operation between the first electrode and the third electrode in accordance with a signal supplied to the second electrode;an insulating film formed to cover a front surface of the semiconductor chip, the first electrode and the second electrode being disposed on a surface of the insulating film, the first electrode and the second electrode being electrically connected to a transistor formed in the semiconductor layer at a position where the first electrode is formed;a metal layer formed so as to cover at least a part of a front side surface of the first electrode; anda wire selected from the group consisting of a plate-like wire and a bonding wire, the wire being connected to the metal layer, whereinan area of the first electrode is larger than an area of the second electrode.22. The semiconductor device according to claim 21 , whereinthe metal layer covers the first electrode, except for a part of the surface of the first electrode.23. The semiconductor device according to claim 22 , whereinan area of the surface of the first electrode covered by the metal layer is larger than an area of the surface of the first electrode not covered by the metal layer.24. The semiconductor device according to claim 21 , ...

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material. 1. A method of soldering a conductor to an aluminum metallization , the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;at least partly reducing a substitute metal oxide in the substitute metal oxide layer or in the substitute metal alloy oxide layer; andsoldering the conductor to the aluminum metallization using a solder material.2. The method of claim 1 , wherein a substitute metal of the substitute metal oxide layer is one of Zn claim 1 , Cr claim 1 , Cu claim 1 , Pb claim 1 , or Sn.3. The method of claim 2 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.4. The method of claim 1 , wherein a substitute metal alloy of the substitute metal alloy oxide layer comprises at least two of the elements Zn claim 1 , Cr claim 1 , V claim 1 , Cu claim 1 , Pb claim 1 , Sn and Mo.5. The method of claim 4 , wherein substituting comprises depositing the substitute metal alloy over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.6. The method of claim 1 , wherein substituting comprises applying one or more of hydrofluoric acid (HF) and methanesulfonic acid (MSA) to the aluminum oxide layer.7. The method of claim 1 , wherein substituting comprises applying a halogenide via a plasma process to ...

POWER MODULE

Power module includes: first transistors Q, Q forming at least one half bridge, and disposed at upper and lower arms thereof; second transistors QM, QM of which drains are respectively connected to gates G and G sides of the first transistors, and sources are respectively connected to the sources S, S sides thereof; source signal wiring patterns SSP, SSP respectively connected to the sources S, S of the first transistors; first connected conductors MSW, MSW for respectively connecting between the source signal wiring patterns and the sources of the second transistors; second gate signal wiring patterns MGP, MGP respectively connected to gates MG, MG of the second transistors; and second connected conductors MGW, MGW for respectively connecting between the gate signal wiring patterns and the gates of the second transistors. Lengths of the first connection conductors are respectively equal to or shorter than lengths of the second connection conductors. 1. A power module comprising:first transistors disposed on an insulating substrate, the first transistors forming at least one set of a half bridge having upper and lower arms, the first transistors respectively disposed at the upper and lower arms;second transistors disposed on the insulating substrate, the second transistors of which drains are respectively connected to gates sides of the first transistors and sources are respectively connected to sources sides of the first transistors;first source signal wiring patterns disposed on the insulating substrate, the first source signal wiring patterns respectively connected to the sources of the first transistors;first connected conductors for respectively connecting between the first source signal wiring patterns and the sources of the second transistors;second gate signal wiring patterns disposed on the insulating substrate, the second gate signal wiring patterns respectively connected to gates of the second transistors; andsecond connected conductor for respectively ...

CURRENT SENSOR

In a current sensor, primary conductors each include front and back surfaces, a length direction, a width direction orthogonal or substantially orthogonal to the length direction, and a thickness direction orthogonal or substantially orthogonal to the length direction and the width direction, and further include a bent portion surrounding at least a portion of an outer periphery of a housing at an intermediate position in the length direction when viewed in the width direction. The housing is disposed in a region surrounded by the bent portion of each of the plurality of primary conductors when viewed in the width direction. 1. A current sensor comprising:a plurality of primary conductors, through each of which a current to be measured flows and which are arranged parallel or substantially parallel to each other;a plurality of magnetic sensors, each of which corresponds to one of the plurality of primary conductors and detects an intensity of a magnetic field generated by the current to be measured that flows through the corresponding primary conductor; anda single housing that accommodates the plurality of magnetic sensors; whereineach of the plurality of primary conductors includes a front surface and a back surface, has a length direction, a width direction orthogonal or substantially orthogonal to the length direction, and a thickness direction orthogonal or substantially orthogonal to the length direction and the width direction, and further includes a bent portion that is bent to surround at least a portion of an outer periphery of the housing at an intermediate position in the length direction when viewed in the width direction; andthe housing is disposed in a region surrounded by the bent portion of each of the plurality of primary conductors when viewed in the width direction.2. The current sensor according to claim 1 , whereinthe housing has a longitudinal direction; andthe longitudinal direction of the housing coincides or substantially coincides with the ...

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate. 1. A stacked package comprising:a package substrate configured with a die attach region with first and second terminal pads;a first die mounted onto the die attach region, the first die is electrically coupled to the first terminal pads;a second component disposed over the first die; anda conductive gang disposed between the first die and second component, wherein the conductive gang comprises a patterned conductive gang with gang legs, the gang legs are configured to electrically couple the second component to the second terminal pads of the package substrate.2. The stacked package in wherein the gang legs comprises lower gang legs coupled to the second terminal pads of the package substrate claim 1 , wherein the second terminal pads are disposed around the die attach region of the package substrate.3. The stacked package in wherein the gang legs comprises upper gang legs coupled to component contact pads of the second component claim 2 , wherein the component contact pads are disposed on a bottom major surface of the second component claim 2 , wherein the upper and lower gang legs are linked by a riser gang leg portion.4. The stacked package in comprises a clip bond coupling die contact pads on a top major surface of the first die to the first terminal pads of the package substrate.5. The stacked package in wherein the first die and the clip bond are encapsulated by an encapsulant.6. The stacked package in wherein the gang legs are linked to the clip bond by a vertical linking portion.7. A method for forming a device claim 4 , comprising:providing a package substrate having a die attach region;attaching and electrically coupling a ...

Power Converter Package Using Driver IC

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Semiconductor device

A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

SEMICONDUCTOR DEVICE

A first power supply terminal P is provided with an internal wiring connection portion A, an upright portion B which is joined to the internal wiring connection portion A, an inclined portion C which is joined to the upright portion B and an external wiring connection portion D which is joined to the inclined portion C. A second power supply terminal N is provided with an internal wiring connection portion A, an upright portion B which is joined to the internal wiring connection portion A, an inclined portion C which is joined to the upright portion B and an external wiring connection portion D which is joined to the inclined portion C. The upright portion B of the first power supply terminal P and the upright portion B of the second power supply terminal N are arranged so as to face each other, with a predetermined interval kept therebetween. 115-. (canceled)16. A semiconductor device , comprising:a first power supply terminal and a second power supply terminal which are arranged so as to be adjacent in a predetermined one direction in a plan view; anda circuit element which is electrically connected between the first power supply terminal and the second power supply terminal; wherein,the first power supply terminal includes a first internal wiring connection portion and a first external wiring connection portion which are flat plate-shaped and arranged so as to face each other, with an interval kept, in a vertical direction along a plan view direction and a first coupling portion which couples an edge portion of the first internal wiring connection portion and that of the first external wiring connection portion on the side of the second power supply terminal,the second power supply terminal includes a second internal wiring connection portion and a second external wiring connection portion and a second coupling portion which couples the second internal wiring connection portion and the second external wiring connection portion and is disposed adjacent to the ...

Dual Step Laser Processing of an Encapsulant of a Semiconductor Chip Package

A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.

Semiconductor device, method for manufacturing the same, and power conversion device

In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.

LEAD FRAME WIRING STRUCTURE AND SEMICONDUCTOR MODULE

A lead frame wiring structure including first and second bonding parts positioned apart from each other, and a coupling part extending in a first direction to couple the first and second bonding parts. The coupling part includes a coupling face section, and first and second leg sections extending respectively from two opposite end portions of the coupling face section toward the first and second bonding parts. The first bonding part includes a wide section having a side edge portion and a peripheral section adjacent to the side edge portion in a second direction, and a narrow section protruding in the first direction from the side edge portion. In the coupling part, the coupling face section is spaced apart from the two bonding parts in a third direction, and the first leg section is connected to the peripheral section of the first bonding part. The first to third directions are perpendicular to one another. 1. A lead frame wiring structure for a semiconductor module including a semiconductor element and an object , for electrically connecting the semiconductor element to the object , the lead frame wiring structure comprising:a first bonding part, to be soldered to the semiconductor element;a second bonding part positioned apart from the first bonding part, to be soldered to the object; anda coupling part extending in a first direction between the first and second bonding parts, to couple the first and second bonding parts, wherein a coupling face section having opposite first and second end portions thereof in the first direction,', 'a first leg section extending from the first end portion of the coupling face section toward the first bonding part, and', 'a second leg section extending from the second end portion of the coupling face section toward the second bonding part;, 'the coupling part includes'} the wide section has a side edge portion, and a peripheral section adjacent to the side edge portion in the second direction, and', 'the narrow section protrudes ...

PACKAGE STRUCTURE FOR POWER DEVICE

A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, at least one conductive clip, and a heat dissipation baseplate. The heat dissipation insulating substrate has a first surface and a second surface opposite thereto, and the power devices form a bridge circuit topology and are disposed on the first surface, wherein active regions of at least one of the power devices are flip-chip bonded to the first surface. The conductive clip is configured to electrically connect at least one of the power devices to the first surface, and the heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate. 1. A package structure for power devices , comprising:a heat dissipation insulating substrate, comprising a first surface and a second surface opposite thereto;a plurality of power devices forming a bridge circuit topology and disposed on the first surface, wherein active regions of at least one of the power devices are flip-chip bonded to the first surface;at least one conductive clip, configured to electrically connect at least one of the power devices to the first surface; anda heat dissipation baseplate, disposed at the second surface of the heat dissipation insulating substrate.2. The package structure for power devices according to claim 1 , wherein one conductive clip electrically connects one or more of the power devices to the heat dissipation insulating substrate and is disposed at an opposite side of the power device opposite to a side where the power device is bonded to the heat dissipation insulating substrate.3. The package structure for power devices according to claim 1 , wherein a material of the conductive clip comprises aluminium claim 1 , copper or graphite.4. The package structure for power devices according to claim 1 , wherein the plurality of power devices comprise vertical power devices claim 1 , active regions of the vertical power devices are ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease. 1. A semiconductor device comprising:a semiconductor module comprising a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed;a cooler;first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler; andsecond insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.2. The semiconductor device according to claim 1 , wherein the resin has a resin through hole formed therein which communicates with the at least one radiator plate through hole.3. The semiconductor device according to claim 2 , whereinthe resin has a wide portion formed in at least part of the resin through hole, the wide portion having a larger width than the at least one radiator plate through hole, andthe wide portion has third insulating grease provided therein.4. The semiconductor device according to claim 2 , further comprising a stopper for blocking at least part of the resin through hole.5. The semiconductor device according to claim 4 , further comprising gel for fixing the stopper in place.6. The ...

Method of Manufacturing a Multi-Chip Semiconductor Power Device

A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip. 1. A method of manufacturing a semiconductor device , the method comprising:mounting a first semiconductor power chip on a first carrier;mounting a second semiconductor power chip on a second carrier;bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip; andmounting a third semiconductor chip over the contact clip.2. The method of claim 1 , further comprising:depositing a first bonding substance onto the first carrier;placing the first semiconductor power chip on the first bonding substance;depositing a second bonding substance onto the second carrier;placing the second semiconductor power chip on second bonding substance;depositing a third bonding substance onto the contact clip;placing the third semiconductor chip on third bonding substance; andapplying energy for mounting the first semiconductor power chip, the second semiconductor power chip and the third semiconductor chip.3. The method of claim 2 , wherein the first bonding substance and the second bonding substance are a solder material and wherein the third bonding substance is an electrically insulating adhesive.4. The method of claim 1 , further comprising:depositing a first bonding substance onto the first carrier;placing the first semiconductor power chip on the first bonding substance;depositing a second bonding substance onto the second carrier;placing the second semiconductor power chip on second bonding substance;applying energy for mounting the first semiconductor power chip and the second semiconductor power chip and the third semiconductor chip; thereafterdepositing a third bonding substance onto the ...

Electronic device

Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a semiconductor chip and exposed from a main surface of a sealing body located on a front surface side of the semiconductor chip. Each of the first and second semiconductor devices includes a collector terminal electrically connected with a back surface electrode of the semiconductor chip and exposed from the main surface of the sealing body located on a back surface side of the semiconductor chip. The collector terminal of the first semiconductor device is electrically connected with the emitter terminal of the second semiconductor device via a conductor pattern formed on an upper surface of the substrate.

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

LONG-LIFE EXTENDED TEMPERATURE RANGE EMBEDDED DIODE DESIGN FOR ELECTROSTATIC CHUCK WITH MULTIPLEXED HEATERS ARRAY

A substrate support for a plasma chamber includes a base plate arranged along a plane, a first layer of an electrically insulating material arranged on the base plate along the plane, a plurality of heating elements arranged in the first layer along the plane, and a plurality of diodes arranged in respective cavities in the first layer. The plurality of diodes are connected in series to the plurality of heating elements, respectively. Each of the plurality of diodes includes a die of a semiconductor material arranged in a respective one of the cavities. The semiconductor material has a first coefficient of thermal expansion. A first side of the die is arranged on the first layer along the plane. A first terminal of the die is connected to a first electrical contact on the first layer.

Leadframe and method of manufacturing the same

A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad.

THERMALLY ENHANCED LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF

Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate. 1. A semiconductor package comprising:a package substrate comprising a top substrate surface and a bottom substrate surface, wherein the package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface;a heat spreader disposed on the top substrate surface, the heat spreader comprises a top planar surface and a bottom planar surface, wherein the top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region, wherein the heat spreader comprises a thickness extending from the top planar surface the bottom planar surface;a semiconductor die, wherein the semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region; andwherein the thickness of the heat spreader is greater relative to the thickness of the package substrate.2. The semiconductor package of wherein the package substrate is a lead frame comprising a die-attach paddle and a plurality of lead fingers peripherally located relative to the die-attach paddle claim 1 , wherein the heat spreader is directly disposed on a top ...

Semiconductor module

In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal.

Damaging components with defective electrical couplings

A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.

HOLES AND DIMPLES TO CONTROL SOLDER FLOW

A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface. 1. A system , comprising:a first surface of a lead frame;a second surface of the lead frame, opposite the first surface, said second surface having been etched;one or more cylindrical holes passing through said lead frame and coincident with the first and second surfaces; andfluid on the first surface, the fluid at least partially encircling an aperture of said one or more holes,wherein said one or more holes are adapted to control flow of the fluid on said first surface.2. The system of claim 1 , wherein said fluid comprises reflowed solder.3. The system of claim 1 , wherein said second surface comprises a half-etched area.4. The system of claim 1 , wherein said fluid has a distribution on the first surface that is influenced at least in part by said one or more holes.5. The system of claim 1 , wherein said fluid partially fills said one or more holes.6. (canceled)7. The system of claim 1 , wherein said fluid straddles at least one aperture of said one or more holes.8. The system of claim 1 , wherein said fluid is selected from the group consisting of epoxy claim 1 , polyimide claim 1 , silicone adhesives claim 1 , hybrid organic adhesives claim 1 , soft solder claim 1 , and eutectic solder.9. The system of claim 1 , further comprising a die coupled to the first surface using solder claim 1 , a position of the die on the first surface is influenced at least in part by said one or more holes.10. The system of claim 9 , further comprising a clip coupling said lead frame to the die using solder claim 9 , said clip having one or more additional holes claim 9 , a position of the clip relative to the die ...

Power module

A power module including a carrier assembly and a power device disposed on the carrier assembly is provided. The carrier assembly includes a bottom board, a circuit board, a lead frame, and a pad group. The circuit board is disposed on the bottom board and includes a device mounting portion and an extending portion protruding from a side of the device mounting portion. The lead frame disposed on the bottom board includes a first conductive portion and a second conductive portion insulated from each other. The extending portion of the circuit board is disposed between the first and second conductive portions, and an upper surface of the lead frame is flush with a top surface of the extending portion. A pad group includes a first pad disposed on the extending portion, a second pad and a third pad respectively disposed on the first and second conductive portions.

Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package. 1. A power semiconductor package , comprising:a power semiconductor chip;an electrical connector arranged at a first side of the power semiconductor chip and comprising a first surface that is coupled to a power electrode of the power semiconductor chip;an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector; andan electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface,wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.2. The power semiconductor package of claim 1 , wherein the encapsulation body and the electrical insulation layer comprise grinding traces at the coplanar surface of the semiconductor package.3. The power semiconductor package of claim 1 , wherein the electrical insulation layer comprises a thermal interface material claim 1 , and wherein the coplanar surface is configured to be coupled to a heatsink.4. The power semiconductor package of claim 1 , further comprising:a die carrier,wherein the power semiconductor chip is arranged on the die carrier, andwherein the die carrier is exposed from the encapsulation body at a side of the power semiconductor package opposite to the coplanar surface.5. The power semiconductor package of claim 1 , wherein the parts ...

Semiconductor device

There is provided a semiconductor device including: a first semiconductor element including a first gate electrode, a first source electrode, and a first drain electrode; a second semiconductor element including a second gate electrode, a second source electrode, and a second drain electrode; a gate lead, a source lead, a first drain lead, and a second drain lead; and a resin part, wherein the first gate electrode and the first source electrode, and the first drain electrode are provided on opposite sides to each other in a first direction, wherein the second gate electrode and the second source electrode, and the second drain electrode are provided on opposite sides to each other in the first direction, wherein the first gate electrode and the second gate electrode are opposed to the first source electrode and the second source electrode, respectively, in the first direction.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal.

Semiconductor device

A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips

A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.

Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips

A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Flip chip backside mechanical die grounding techniques

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

STRAY INDUCTANCE REDUCTION IN PACKAGED SEMICONDUCTOR DEVICES

In a general aspect, a semiconductor device can include a substrate and a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane. The device can also include a first negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The device can further include a second negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The positive power supply terminal can be disposed between the first and second negative power supply terminals. The device can also include a conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge. A portion of the conductive bridge can be arranged in a second plane that is parallel to, and non-coplanar with the first plane. 1. A semiconductor device package comprising:a substrate;a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane;a first negative power supply terminal that is laterally disposed from the positive power supply terminal, the first negative power supply terminal being arranged in the first plane;a second negative power supply terminal that is laterally disposed from the positive power supply terminal, the second negative power supply terminal being arranged in the first plane, the positive power supply terminal being disposed between the first negative power supply terminal and the second negative power supply terminal; anda conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge, a portion of the conductive bridge being arranged in a second plane that is parallel to, and non-coplanar with the first plane.2. The semiconductor device package of claim ...

Electronic power module with enhanced thermal dissipation and manufacturing method thereof

An electronic power module comprising a case that houses a stack, which includes: a first substrate of a DBC type or the like; a die, integrating an electronic component having one or more electrical-conduction terminals, mechanically and thermally coupled to the first substrate; and a second substrate, of a DBC type or the like, which extends over the first substrate and over the die and presents a conductive path facing the die. The die is mechanically and thermally coupled to the first substrate by a first coupling region of a sintered thermoconductive paste, and the one or more conduction terminals of the electronic component are mechanically, electrically, and thermally coupled to the conductive path of the second substrate by a second coupling region of sintered thermoconductive paste.

Electric Power Conversion Apparatus

An electric power conversion apparatus includes a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that has an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module includes first and second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further includes a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.