СИЛОВОЙ ПРЕОБРАЗОВАТЕЛЬ ИМПУЛЬСНОГО ТИПА, ВЫПОЛНЕННЫЙ С ВОЗМОЖНОСТЬЮ УПРАВЛЕНИЯ ПО МЕНЬШЕЙ МЕРЕ ОДНОЙ ФАЗОЙ МНОГОФАЗНОГО ЭЛЕКТРИЧЕСКОГО ПРИЕМНИКА С ПО МЕНЬШЕЙ МЕРЕ ТРЕМЯ ФАЗАМИ

LED-Modul mit einer LED

Die vorliegende Erfindung betrifft ein LED-Modul mit einer LED (3) mit einer LED-Anschlussfläche (9) und einem Substrat mit einer Kontaktierungsstruktur (2) mit einer Kontaktfläche (8), wobei sich zwischen LED-Anschlussfläche (9) und Kontaktfläche (8) ein Bonddraht (13) erstreckt und diese beiden Flächen (8, 9) hinsichtlich ihres (vertikalen) Abstands in Abstandsrichtung (4) so angepasst sind, dass sie näherungsweise auf derselben Höhe liegen, damit beim Platzieren des Bonddrahts (13) ein entsprechend geringer Abstand in der Abstandsrichtung (4) überbrückt werden muss und eine Mehrzahl LEDs (3) so (lateral) näher beisammen angeordnet werden können.

Electronic apparatus

Die Erfindung betrifft ein Elektronisches Gerät umfassend zumindest eine Leiterplatine (1) und zumindest ein elektrisches Bauteil (4), wobei das Bauteil (4) an einem starren Körper (2) befestigt ist, wobei der starre Körper (2) starr mit der Leiterplatine (1) und/oder einem Gehäuseteil des elektronischen Geräts verbunden ist und das Bauteil (4) mit flexiblen Kabeln (3) mit der Leiterplatine (1) und/oder anderen elektrischen Bauteilen (4) leitend verbunden ist und ein Verfahren zur Herstellung einer solchen Schaltung.

MICROCASE Of ENCAPSULATION OF JUST CIRCUITS LOGICAL FUNCTIONING IN VERY High frequency

L'INVENTION CONCERNE UN MICROBOITIER PLAT, A MULTISORTIES PERIPHERIQUES, DE TYPE CERAMIQUE-METAL, POUR LES CIRCUITS INTEGRES ULTRA-RAPIDES TELS QUE CEUX SUR GAAS PAR EXEMPLE. AFIN DE FACILITER L'INSERTION D'UN CIRCUIT INTEGRE ULTRA-RAPIDE SUR UN SUBSTRAT COMPORTANT UN CIRCUIT ELECTRIQUE HYPERFREQUENCE, LE MICROBOITIER SELON L'INVENTION COMPREND UN CADRE ISOLANT 8 DONT LA FACE SUPERIEURE SUPPORTE DES CONDUCTEURS DU TYPE LIGNE DE TRANSMISSION EN MICROBANDES 15 ADAPTEES EN IMPEDANCE. DES MICROBANDES EPAISSES 14, BRASEES SUR LES PRECEDENTES 15 CONSTITUENT LES CONNEXIONS EXTERIEURES. LE CADRE ISOLANT 8 COMPREND EN SON CENTRE UNE CAVITE 9 DANS LAQUELLE EST LOGE LE CIRCUIT INTEGRE 10: LES FACES SUPERIEURES DES MICROBANDES 15 ET DU CIRCUIT INTEGRE 10 SONT DANS LE MEME PLAN. L'EMBASE METALLIQUE 6 DU BOITIER CONSTITUE LE PLAN DE MASSE. APPLICATION A L'ENCAPSULATION DES CIRCUITS INTEGRES LOGIQUES ULTRA-RAPIDES CONSTITUANT LES COMPOSANTS CLES UTILISES EN TELECOMMUNICATION, EN AVIONIQUE, EN INFORMATIQUE ET EN INSTRUMENTATION.

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies. © KIPO & WIPO 2007 ...

Light transceiver with heat radiation

Semiconductor device

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands. 1. A method , comprising:forming a first layer of molding compound on a substrate, a semiconductor die attached to the substrate, and a plurality of conductive stud bumps coupled to the semiconductor die, wherein the plurality of conductive stud bumps are embedded in the first layer of molding compound, wherein the first layer of molding compound is a laser-activatable direct structuring molding compound;leveling the first layer of molding compound to expose a distal end of a first stud bump of the plurality of conductive stud bumps at a surface of the of the first layer molding compound;using a laser, forming a plurality of recesses in the first layer of molding compound to form laser ablated areas, wherein a first recess of the plurality of recesses is at the distal end of the first stud bump;forming a plurality of electrically-conductive lines at the laser ablated areas, wherein a first line of the plurality of electrically-conductive lines forms a land in the first recess and at the distal end of the first stud bump; andforming a second layer of molding compound covering at least one of the plurality of electrically-conductive lines.2. The method of claim 1 , further comprising removing the substrate.3. The method of claim 1 , wherein the substrate is one of: a tape material claim ...

Semiconductor device and mounting structure of semiconductor device

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

МОЩНАЯ ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА СВЧ ДИАПАЗОНА

FIELD: semiconductor microelectronics. SUBSTANCE: integrated circuit has board with depression on its underside under base ridge; holes of definite size are provided in depression bottom; upper chip-free part of base ridge is electrically connected with depression bottom; some of contact pads of chip are grounded through holes in depression bottom; distance between chip and walls of holes mounting it and that between chip hole and grounding hole are less than 150 mcm. EFFECT: improved electric characteristics, reduced mass and size, facilitated manufacture. 4 cl, 6 dwg САЗЗУГсС ПЧ ГЭ (19) РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ ВИ” 2 148 872 Сл 5 МК” НОлЕ 27/02, 25/16 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 98111687/28, 26.09.1996 (24) Дата начала действия патента: 26.09.1996 (46) Дата публикации: 10.05.2000 (56) Ссылки: Усилитель транзисторный, М М4413, 6Ш2030295 ТУ, Ред. 2-89 КРПГ 434815.005 СЬ, 1989. Иовдальский В.А. и др. Улучшение тепловых характеристик ГИС. - Электронная техника. Сер.СВЧ-техника, вып.1 (467), 1996, с.34-38. ОЕ 3501310 АЛ, 24.07.1986. $ 1808148 АЗ, 07.04.1993. СВ 1426539 А, 03.03.1976. Ч$ 4975065 А, 04.12.1990. (85) Дата перевода заявки РСТ на национальную фазу: 26.06.1998 (86) Заявка РСТ: КУ 96/00276 (26.09.1996) (87) Публикация РСТ: \М/О 98/13874 (02.04.1998) (98) Адрес для переписки: 113834, Москва, Раушская наб. 4/5, к.235, ПК "Агентство по патентной информации", Скибневскому А.Ю. (71) Заявитель: Самсунг Электроникс Ко., Лтд. (КК), Иовдальский Виктор Анатольевич (КИ) (72) Изобретатель: Иовдальский В.А.(КОЦ), Айзенберг Э.В.(КЦ), Бейль В.И. (КО) (73) Патентообладатель: Самсунг Электроникс Ко., Лтд. (КК), Иовдальский Виктор Анатольевич (54) МОЩНАЯ ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА СВЧ ДИАПАЗОНА (57) Реферат: Использование: полупроводниковая микроэлектроника. Сущность изобретения: в мощной гибридной интегральной схеме СВЧ диапазона на обратной стороне платы под выступом основания выполнено углубление с ...

METHOD OF MANUFACTURING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE

Integrerad mikrovåghybridströmkrets

Three dimensional device integration method and integrated device

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection ...

Semiconductor Package

A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.

Semiconductor device

In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.

Halbleiteranordnung mit einem Abstandshalterelement und Verfahren zu deren und dessen Herstellung

Halbleiteranordnung (100), aufweisend:• einen Metallträger (102);• ein direkt an den Metallträger (102) angebrachtes Abstandshalterelement (106), wobei das Abstandshalterelement (106) aus einem elektrisch isolierenden Material besteht;• eine erste gesinterte Metallschicht (108) auf dem Abstandshalterelement (106), wobei die erste gesinterte Metallschicht (108) gesinterte nanometergroße Metallpartikel aufweist; und• einen Halbleiterchip (110) direkt auf der ersten gesinterten Metallschicht (108).

Method of packaging microwave semiconductor components and integrated circuits

Integration and packaging of monolithic microwave integrated circuits (MMIC) components is facilitated by using a motherboard comprising high resistivity silicon, which having a thermal conductivity three times that of gallium arsenide. Ultra high purity, uncompensated silicon preferably is used. Anisotropic etching of recesses in the motherboard facilitates precise placement of the MMICs in the recesses, enabling use of automated die and wire bonding techniques to reduce required assembly time substantially. Using a silicon motherboard also ultimately enables incorporation of required control circuitry. The silicon motherboard also transmits RF energy well, a useful characteristic particularly in C-band and X-band applications in which microstrip is used, though other transmission media function well at even higher frequencies.

Electronic apparatus

Die Erfindung betrifft ein Elektronisches Gerät umfassend zumindest eine Leiterplatine (1) und zumindest ein elektrisches Bauteil (4), wobei das Bauteil (4) an einem starren Körper (2) befestigt ist, wobei der starre Körper (2) starr mit der Leiterplatine (1) und/oder einem Gehäuseteil des elektronischen Geräts verbunden ist und das Bauteil (4) mit flexiblen Kabeln (3) mit der Leiterplatine (1) und/oder anderen elektrischen Bauteilen (4) leitend verbunden ist und ein Verfahren zur Herstellung einer solchen Schaltung.

METHOD OF PACKAGING MICROWAVE SEMICONDUCTOR COMPONENTS AND INTEGRATED CIRCUITS

Integration and packaging of monolithic microwave integrated circuits (MMIC) components is facilitated by using a motherboard comprising high resistivity silicon, which having a thermal conductivity three times that of gallium arsenide. Ultra high purity, uncompensated silicon preferably is used. Anisotropic etching of recesses in the motherboard facilitates precise placement of the MMICs in the recesses, enabling use of automated die and wire bonding techniques to reduce required assembly time substantially. Using a silicon motherboard also ultimately enables incorporation of required control circuitry. The silicon motherboard also transmits RF energy well, a useful characteristic particularly in C-band and X-band applications in which microstrip is used, though other transmission media function well at even higher frequencies.

MICROCASE Of ENCAPSULATION OF JUST CIRCUITS LOGICAL FUNCTIONING IN VERY High frequency

Integrated Circuit Electrostatic Discharge Bus Structure and Related Method

An integrated circuit ESD bus structure includes a circuit area; a plurality of electrostatic discharge (ESD) buses; a plurality of pad groups adjacent and connected to the plurality of ESD buses; a common ESD bus; and a plurality of bonding wires configured to connect the plurality of pad groups to the common ESD bus.

Low cost millimeter wave integrated LTCC package and method of manufacturing

LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.

SEMICONDUCTOR DEVICE

A gate electrode (4) and a source electrode (5) of a semiconductor chip (3) are connected to a gate terminal (7) and a source terminal (9), respectively, via electric conductors (11a and 11b). A portion of the gate terminal (7) which portion is joined to the electric conductor (11a) is close to the gate electrode (4), and a portion of the source terminal (9) which portion is joined to the electric conductor (11b) is close to the source electrode (5).

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

СИЛОВОЙ ПРЕОБРАЗОВАТЕЛЬ ИМПУЛЬСНОГО ТИПА, ВЫПОЛНЕННЫЙ С ВОЗМОЖНОСТЬЮ УПРАВЛЕНИЯ ПО МЕНЬШЕЙ МЕРЕ ОДНОЙ ФАЗОЙ МНОГОФАЗНОГО ЭЛЕКТРИЧЕСКОГО ПРИЕМНИКА С ПО МЕНЬШЕЙ МЕРЕ ТРЕМЯ ФАЗАМИ

Изобретение относится к электротехнике, а именно к силовым преобразователям импульсного типа. Технический результат заключается в уменьшении массогабаритных показателей силового преобразователя и уменьшении потерь в силовом преобразователе за счет уменьшения паразитной индуктивности. Технический результат достигается за счет того, что силовой преобразователь импульсного типа выполнен с возможностью управления по меньшей мере одной фазой многофазного электрического приемника с по меньшей мере тремя фазами. Кроме того, силовой преобразователь содержит по меньшей мере один блок из двух плеч преобразователя, в котором полуплечо (40) плеча преобразователя содержит: первый набор (ENS1) из Р≥2 ключей (I1, I2), соединенных последовательно; второй набор (ENS2) из Р≥2 ключей (I3, I4), соединенных последовательно; и третий набор (ENS3) диодов (D1, D2, D3, D4), расположенный между первым набором (ENS1) и вторым набором (ENS2), содержащий М≥2 поднаборов (SE1, SE2, ..., SEM), соединенных последовательно ...

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

GATE DRIVER PACKAGE FOR UNIFORM COUPLING TO DIFFERENTIAL SIGNAL BOND WIRE PAIRS

In examples, a semiconductor package comprises a first driver die adapted to be coupled to a high-side switch of a power supply, the first driver die adapted to drive a gate of the high-side switch. The package also includes a second driver die adapted to be coupled to a low-side switch of the power supply, the second driver die adapted to drive a gate of the low-side switch. The package also includes a controller die positioned between the first and second driver dies and configured to control the first and second driver dies. The package also includes a pair of bond wires configured to provide a differential signal between the controller die and the first driver die, a vertical plane of a bond wire in the pair of bond wires and a vertical plane of a side surface of the first driver die having an angle therebetween ranging from 80 to 95 degrees.

SEMICONDUCTOR DEVICE PACKAGE

The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a first module disposed on the substrate, a second module disposed on the substrate and spaced apart from the first module, and a conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module. 1. A semiconductor device package , comprising:a substrate;a first module disposed on the substrate;a second module disposed on the substrate and spaced apart from the first module; anda first conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module.2. The semiconductor device package of claim 1 , wherein the first conductive element comprises a passive component.3. The semiconductor device package of claim 2 , wherein the first conductive element comprises a conductive wire claim 2 , an interposer claim 2 , a redistribution structure claim 2 , a conductive pillar claim 2 , a conductive via claim 2 , or a combination thereof.4. The semiconductor device package of claim 1 , whereinthe first module comprises a first interposer disposed on the substrate and a first electronic component disposed on the first interposer, andthe second module comprises a second interposer disposed on the substrate and a second electronic component disposed on the second interposer.5. The semiconductor device package of claim 4 , wherein the first electronic component is spaced apart from the second interposer and the second electronic component is spaced apart from the first interposer.6. The semiconductor device package of claim 4 , wherein the first electronic component and the second electronic component are different from each other in at least one of function claim 4 , operating frequency claim 4 , bandwidth claim 4 , signal type claim 4 , impedance claim 4 , and line/space (L/S) width.7. The ...

Elektrische/elektronische Schaltungseinrichtung, Steuergerät

Die Erfindung betrifft eine elektrische/elektronische Schaltungseinrichtung (1), insbesondere anwenderspezifische Schaltung, mit zumindest einer Funktionseinheit (5) und mit zumindest einer Abschalteinrichtung (6), die in einem gemeinsamen Gehäuse (3) angeordnet sind, wobei die Funktionseinheit (5) und die Abschalteinrichtung (6) an einem gemeinsamen Trägersubstrat (4) angeordnet sind. Es ist vorgesehen, dass eine elektrische Verbindung der Funktionseinheit (5) mit der Abschalteinrichtung (6) nur durch zumindest eine innerhalb des Gehäuses (3) und getrennt von dem Trägersubstrat (4) ausgebildete Drahtverbindung (10) ausgebildet ist.

HALBLEITERVORRICHTUNG

Erste und zweite Schaltungsmuster (5, 6) sind auf einem isolierenden Substrat (1) vorgesehen. Erste und zweite Halbleiter-Chips (7, 8) sind auf dem ersten Schaltungsmuster (5) vorgesehen. Ein Relais-Schaltungsmuster (10) ist zwischen dem ersten Halbleiter-Chip (7) und dem zweiten Halbleiter-Chip (8) auf dem isolierenden Substrat (1) vorgesehen. Ein Draht (11) ist fortlaufend mit dem ersten Halbleiter-Chip (7), dem Relais-Schaltungsmuster (10), dem zweiten Halbleiter-Chip (8) und dem zweiten Schaltungsmuster (6) verbunden, welche nacheinander in einer Richtung angeordnet sind.

Electronic package

Provided is an electronic package including: a substrate, an electronic element disposed on the substrate, and an antenna structure, wherein the antenna structure comprises a plurality of spacing members and at least one solder wire connected between each of the spacing members, thereby achieving the object of miniaturization without increasing any layout area on the substrate surface.

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

Halbleitervorrichtung

In einem Schaltungssubstrat verbinden mehrere erste Mikrostreifenleitungen jeweils Ausgänge einer Mehrzahl von Schaltungsmustern, welche einen Parallelkondensator umfassen, mit einer Mehrzahl von ersten Ausgangskontaktstellen. Mehrere zweite Drähte verbinden jeweils die ersten Ausgangskontaktstellen des Schaltungssubstrats mit Eingängen einer Mehrzahl von Transistorzellen eines Halbleitersubstrats. Die Anzahlen der Finger der Transistorzellen sind gleich. Die ersten Mikrostreifenleitungen, welche mit den Schaltungsmustern verbunden sind, die auf beiden Seiten der in einer Reihe angeordneten Schaltungsmuster angeordnet sind, sind länger als die anderen ersten Mikrostreifenleitungen.

Apparatuses for communication systems transceiver interfaces

Integrated circuit having electromagnetic shielding capability and manufacturing method thereof

Semiconductor module

A semiconductor module includes: a circuit board on which a first semiconductor chip and a second semiconductor chip are mounted and includes a first through hole formed with a conductor foil therein; a press-fit terminal that is electrically connected to the conductor foil in the first through hole of the circuit board; and a second resin that is disposed on a surface side and a back surface side of the circuit board. Further, the press-fit terminal is provided with a pressure contact portion which is press-fitted into the first through hole and is electrically connected to the conductor foil in the first through hole, and the second resin on the surface side of the circuit board and the second resin on the back surface side of the circuit board are integrally formed via a second resin that is filled in the first through hole.

Packaged leadless semiconductor device

A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).

Capacitor Formed On Heavily Doped Substrate

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Semiconductor device

A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.

Hochfrequenz-Leistungsverstärker

Die vorliegende Erfindung betrifft einen Hochfrequenz-Leistungsverstärker, in welchem hauptsächlich ein Verstärkungs-GaN-Chip und ein GaAs-Chip, welcher eine darauf ausgebildete Voranpassungsschaltung für Vorgenannten aufweist, mittels Drähten auf einer identischen Metallplatte verbunden sind. Der Hochfrequenz-Leistungsverstärker gemäß der vorliegenden Erfindung ist mit einem Koppler bereitgestellt, welcher eine Gegeninduktivität einer subtraktiven Polarität auf dem GaAs-Chip aufweist, wodurch es ermöglicht wird: eine Gegeninduktivität zwischen benachbarten Drähten aufzuheben; eine Ausbreitung einer Impedanz einer zweiten Harmonischen bezüglich einer Frequenz zu reduzieren, wenn ein Signal von einem Gate-Anschluss des GaAs-Chips betrachtet wird; und einen hohen Wirkungsgrad des Leistungsverstärkers in einem gewünschten Grundwellenband aufrechtzuerhalten.

POWER ELECTRONIC ARRANGEMENT AND ELECTRIC VEHICLE WITH SUCH ARRANGEMENT

REDUCED INDUCTANCE INTERCONNECT FOR ENHANCED MICROWAVE AND MILLIMETER-WAVE SYSTEMS

According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire.

Common-source packaging structure

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

Segmented Bond Pads and Methods of Fabrication Thereof

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

Three dimensional device integration method and integrated device

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

LIGHT MODULE AND LIDAR APPARATUS HAVING AT LEAST ONE LIGHT MODULE OF THIS TYPE

A light module has a carrier with a circuit die. On the top side of the carrier, a light-emitting diode die, and a charge store component are electrically connected to the conduction path terminal fields of a transistor by means of die-to-die bondings. The electrical connection between the two dies and the conduction path of the transistor is as short as possible. A terminal field is situated in each case on the top side of the two dies, which terminal fields are connected to one another using a first bonding wire. The charge store component is charged by means of a charging circuit which is electrically connected to the charge store component via a second bonding wire. The second bonding wire is longer than the first bonding wire. The light module may be part of a LIDAR apparatus.

Three dimensional device integration method and integrated device

전자 부품을 매설한 수지 구조체 및 그 제조 방법

... 수지 성형체(5)와, 수지 성형체(5) 내에 매설된 복수의 전자 부품(2)을 구비하는 수지 구조체(1)에 있어서, 수지 성형체(5)는 전자 부품(2)의 전극(3)이 노출되는 복수의 노출면을 갖고, 수지 성형체(5)에는, 오목부(7)가 형성되어 있고, 오목부(7)의 저면(13)이 복수의 노출면의 적어도 1개이다.

THREE DIMENSIONAL DEVICE INTEGRATION METHOD, INTEGRATED DEVICE AND BONDED STRUCTURE

Power semiconductor module

A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.

Electronic Module with Improved Heat Dissipation and Fabrication Thereof

An electronic module includes a semiconductor package having a die pad, a semiconductor die, and an encapsulant. The encapsulant has a first main face and a second main face opposite to the first main face. The die pad has a first main face and a second main face opposite to the first main face. The semiconductor die is disposed on the second main face of the die pad. An insulation layer is disposed on at least a portion of the first main face of the encapsulant and on the first main face of the die pad. The insulation layer is electrically insulating and thermally conducting. A heatsink is disposed on or in the insulation layer. 1. An electronic module , comprising:a semiconductor package comprising a die pad, a semiconductor die, and an encapsulant, the encapsulant comprising a first main face and a second main face opposite to the first main face, the die pad comprising a first main face and a second main face opposite to the first main face, the semiconductor die being disposed on the second main face of the die pad;an insulation layer on at least a portion of the first main face of the encapsulant and on the first main face of the die pad, the insulation layer being electrically insulating and thermally conducting; anda heatsink on or in the insulation layer,{'b': '3', 'wherein a main face of the heatsink () is exposed to the outside.'}2. The electronic module of claim 1 , wherein the insulation layer comprises at least one of a resin matrix material claim 1 , a thermoset material claim 1 , an epoxy claim 1 , a silicone claim 1 , a thermal interface material claim 1 , a thermoplast claim 1 , a thermal adhesive claim 1 , a thermoplast claim 1 , and a thermal interface material.3. The electronic module of claim 1 , wherein the insulation layer comprises a resin matrix material or a host material which is filled with a filler material configured to increase a thermal conductivity of the host material.4. The electronic module of claim 3 , wherein the filler ...

Package structure integrating a start-up component, a controller, and a power switch

A package structure integrating a start-up component, a controller, and a power switch for a power converter, wherein the power converter has a coil having a first end and a second end, and the first end is coupled to a rectifier, the package structure including: a first die pad for carrying a chip of the controller; a second die pad for carrying a chip of the start-up component and a chip of the power switch, wherein the chip of the start-up component has a bottom surface providing a first drain contact; and the chip of the power switch has a bottom surface providing a second drain contact; and a plurality of external connection leads, of which one is connected with the second die pad via a wire and is used to couple with the second end of the coil.

Electronic Package and Electronic Device Comprising the Same

Example embodiments relate to electronic packages and electronic devices that include the same. One embodiment includes an electronic package. The electronic package includes a package body. The electronic package also includes a heat-conducting substrate arranged inside the package body and having a bottom surface that is exposed to an outside of the package body. Additionally, the electronic package includes an electronic circuit arranged inside the package body and including a semiconductor die that has a bottom surface with which it is mounted to the heat-conducting substrate and an opposing upper surface. Further, the electronic package includes one or more leads partially extending from outside the package body to inside the package body and over the minimum bounding box, each lead having a first end that is arranged inside the package body. In addition, the electronic package includes one or more bondwires for connecting the first end(s) to the electronic circuit.

Vorrichtungen für Kommunikationssystem-Sendeempfängerschnittstellen

Eine integrierte Schaltungsvorrichtung zum Schützen von Schaltungen vor transienten elektrischen Ereignissen ist offenbart. Eine integrierte Schaltungsvorrichtung weist ein Halbleitersubstrat auf, worin ein bidirektionaler Halbleitergleichrichter (SCR) ausgebildet ist, der eine Kathode/Anode, die elektrisch mit einem ersten Anschluss verbunden ist, und eine Anode/Kathode, die elektrisch mit einem zweiten Anschluss verbunden ist, aufweist. Die integrierte Schaltungsvorrichtung weist zusätzlich mehrere Metallisierungsebenen auf, die oberhalb des Halbleitersubstrats ausgebildet sind. Die integrierte Schaltungsvorrichtung weist ferner eine Auslösevorrichtung auf, die im Halbleitersubstrat auf einer ersten Seite und angrenzend an den bidirektionalen SCR ausgebildet ist. Die Auslösevorrichtung weist eines oder mehrere von einem Bipolar-Sperrschichttransistor (BJT) oder einer Lawinen-PN-Diode auf, wobei ein erster Vorrichtungsanschluss der Auslösevorrichtung gemeinsam mit der K/A mit T1 verbunden ...

FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS AND METHODS OF MAKING AND USING THE SAME

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

Semiconductor device

Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

Electronic module and method for producing an electronic module

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

SWITCHED MODE POWER CONVERTER CONFIGURED TO CONTROL AT LEAST ONE PHASE OF A POLYPHASE ELECTRICAL RECEIVER WITH AT LEAST THREE PHASES

A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises: a first set of P≥2 switches in series; a second set of P≥2 switches in series; and a third set of diodes, arranged between the first set and the second set, comprising M≥2 subsets in series, indexed i∈[[1; M]], respectively comprising N≥2 diodes in parallel. 1. A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases , comprising at least one block of two converter arms , wherein a half-arm of a converter arm comprises:{'b': 1', '1', '2, 'a first set (ENS) of P≥2 switches (I, I) in series;'}{'b': 2', '3', '4', '2, 'a second set (ENS) of P≥2 switches (I, I) in series, the second set (ENS) being electrically connected in parallel between a power supply line (DCBUS+, DCBUS−) of a coplanar electrical power supply (DCBUS) and a power interface; and'}{'b': 3', '1', '2', '1', '2', '3, 'sub': 'i', 'a third set (ENS) of diodes, arranged between the first set (ENS) and the second set (ENS), comprising M≥2 subsets (SE, SE, . . . , SEM) in series, indexed i∈[[1; M]], respectively comprising N≥2 diodes in parallel, said third set (ENS) being electrically connected between the power interface and the other power supply line (DCBUS+, DCBUS−) of the coplanar electrical power supply (DCBUS).'}2. The switched-mode power converter according to claim 1 , wherein the M subsets comprise a same number Nof diodes in parallel.3. The switched-mode power converter according to claim 1 , comprising at least one temperature sensor.412123. The switched-mode power converter according to claim 1 , wherein the switches of the first set (ENS) are aligned and/or the switches of the second set (ENS) are aligned and/or the subsets (SE claim 1 , SE) of diodes of the third set (ENS) are aligned ...

Method for fabricating an electronic module via compression molding

An electronic module includes a semiconductor package having a die pad, a semiconductor die, and an encapsulant. The encapsulant has a first main face and a second main face opposite to the first main face. The die pad has a first main face and a second main face opposite to the first main face. The semiconductor die is disposed on the second main face of the die pad. An insulation layer is disposed on at least a portion of the first main face of the encapsulant and on the first main face of the die pad. The insulation layer is electrically insulating and thermally conducting. A heatsink is disposed on or in the insulation layer.

Reduced Inductance Interconnect for Enhanced Microwave and Millimeter-Wave Systems

According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.

Power semiconductor device

REDUCED INDUCTANCE INTERCONNECT FOR ENHANCED MICROWAVE AND MILLIMETER-WAVE SYSTEMS

According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.

Three dimensional device integration method and integrated device

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member. 1. A package structure , comprising:a first carrier plate, wherein at least a power component is disposed on a first top surface of the first carrier plate;a second carrier plate disposed on the first top surface of the first carrier plate, wherein a driving circuit is disposed on a second top surface of the second carrier plate for driving the power component, wherein at least an opening runs through the second carrier plate and corresponds to the power component, and the power component is accommodated within the opening when the second carrier plate is disposed on the first top surface of the first carrier plate;a pin group assembled on the first carrier plate and/or the second carrier plate, wherein the pin group comprises a first pin group and a second pin group; andan encapsulant member encapsulating the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.2. The package structure according to claim 1 , wherein the current-flowing capability and the heat- ...

Three dimensional device intergration method and intergrated device

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection ...

Halbleitermodul

Ein Halbleitermodul umfasst: eine Leiterplatte 1, auf der ein erster Halbleiterchip 3 und ein zweiter Halbleiterchip 4 montiert sind und die ein erstes Durchgangsloch 11 aufweist, das mit einer Leiterfolie 12 darin ausgebildet ist; einen Presspassanschluss 13, der mit der Leiterfolie 12 in dem ersten Durchgangsloch 11 der Leiterplatte 1 elektrisch verbunden ist; und ein zweites Harz 23, das auf einer Seite der Oberfläche 1a und einer Seite der hinteren Oberfläche 1b der Leiterplatte 1 angeordnet ist. Ferner ist der Presspassanschluss 13 mit einem Druckkontaktabschnitt versehen, der in das erste Durchgangsloch 11 eingepresst ist und elektrisch mit der Leiterfolie 12 in dem ersten Durchgangsloch 11 verbunden ist, und das zweite Harz 23 auf der Seite der Oberfläche 1a der Leiterplatte 1 und das zweite Harz 23 auf der Seite der hinteren Oberfläche 1b der Leiterplatte 1 sind über ein zweites Harz 25, das in das erste Durchgangsloch 11 gefüllt ist, einstückig ausgebildet.

HALBLEITERVORRICHTUNG

Halbleitervorrichtung umfassend:• ein isolierendes Substrat (1);• erste und zweite Schaltungsmuster (5, 6), welche auf dem isolierenden Substrat (1) angeordnet sind;• erste und zweite Halbleiter-Chips (7, 8), welche auf dem ersten Schaltungsmuster (5) angeordnet sind;• ein Relais-Schaltungsmuster (10), welches zwischen dem ersten Halbleiter-Chip (7) und dem zweiten Halbleiter-Chip (8) auf dem isolierenden Substrat (1) angeordnet ist; und• einen Draht (11), welcher fortlaufend mit dem ersten Halbleiter-Chip (7), dem Relais-Schaltungsmuster (10), dem zweiten Halbleiter-Chip (8) und dem zweiten Schaltungsmuster (6) verbunden ist, welche nacheinander in einer Richtung angeordnet sind,• wobei das Relais-Schaltungsmuster (10) über eine höhere Wärmeleitfähigkeit verfügt, als die ersten und zweiten Schaltungsmuster (5, 6).

Embedding the electronic component of the resin structure and its manufacturing method

METHOD FOR INTEGRATING SEMICONDUCTOR DEVICES

Semiconductor device including an embedded controller die and method of making same

A semiconductor device including a substrate with a cavity formed therein for receiving a semiconductor die. In examples, the semiconductor die is a controller die. The controller die may be electrically connected to the substrate with electrical traces which may be formed for example by printing. After the controller is electrically connected to the substrate, one or more memory die may be affixed to the substrate, over the cavity and controller die.

SEMICONDUCTOR DEVICE

A gate electrode (4) and a source electrode (5) of a semiconductor chip (3) are each connected by a conductor (11a, 11b) to a gate terminal (7) and a source terminal (9). The connection portion of the gate terminal (7) that connects with the conductor (11a) is disposed in such a manner as to be close to the gate electrode (4), and the connection portion of the source terminal (9) that connects with the conductor (11b) is disposed in such a manner as to be close to the source electrode (5).

SEMICONDUCTOR DEVICE INCLUDING SPACER ELEMENT

A semiconductor device includes a metal carrier and a spacer element attached to the metal carrier. The semiconductor device includes a first sintered metal layer on the spacer element and a semiconductor chip on the first sintered metal layer.

SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM

A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. 1. A semiconductor device comprising:a chip mounting unit comprising a die paddle and a plurality of pins arranged close to the die paddle;a semiconductor chip attached onto a front side of the die paddle;a plurality of interconnection structures for electrically connecting each bonding pad arranged on a front side of the semiconductor chip to a bonding part of a corresponding pin close to the die paddle;a plastic package body covering the front side of the die paddle, the semiconductor chip, the interconnection structures and the bonding parts of the pins;a metal layer formed at the front side of the die paddle and a surface of each pin; anda passivation layer formed at a backside of the die paddle, wherein the passivation layer covers a remainder surface of the die paddle exposed from the plastic package body and a bottom surface of the passivation layer is coplanar with a bottom surface of the plastic package body.2. The semiconductor device of claim 1 , wherein the semiconductor chip is a vertical power device claim 1 , wherein a back metal layer formed at a backside of the semiconductor chip is attached onto the front side of the die paddle through a conductive adhesive.3. The semiconductor device of claim 1 , wherein the interconnection structure is a metal sheet claim 1 , a conductive band or a bonding wire.4. The semiconductor device of claim 1 , wherein the chip mounting unit further comprisesa heat sink connecting to the ...

LIGHT EMITTING DEVICE

A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode ...

Capacitor formed on heavily doped substrate

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Image sensor with large chip size

Die Erfindung betrifft einen Bildsensor mit großer Chipfläche, enthaltend einen auf einem Chipträger befindlichen Bildsensor-Chip mit an dessen Peripherie angeordneten Drahtbondpads. Mit der Erfindung soll ein Bildsensor mit großer Bildfläche geschaffen werden, der kostengünstig herstellbar ist und einen stressarmen Aufbau mit möglichst geringer Chipkrümmung ermöglicht. Erreicht wird das dadurch, dass der Bildsensor-Chip (2) zentrisch auf dem Chipträger (7) angeordnet ist, der seinerseits an einem Schaltungsträger (12) befestigt ist, das der Bildsensor-Chip (2) durch einen Rahmen (6) umgeben ist, der mit dem Chipträger (7) verbunden ist und dass sich zwischen dem Bildsensor-Chip (2) und dem Chipträger (7) sowie zwischen dem Chipträger (7) und dem Schaltungsträger (12) ein duktiler Kleber (5; 11) befindet.

Halbleiterbauteil

Halbleiterbauteil (1), das Folgendes aufweist:ein Chip-Pad (61,66);ein Schaltbauteil (11, 12, 13, 14), das an eine Oberfläche des Chip-Pads chip-gebondet ist, wobei das Schaltbauteil (11, 12, 13, 14) ein erstes Elektrodenpad (11, 12, 11A-11D) auf einer der Chip-gebondeten Oberfläche gegenüberliegenden Oberfläche aufweist;ein Dioden-Bauteil (21, 22, 23, 24), das an die Oberfläche des Chip-Pads Chip-gebondet ist, wobei das Dioden-Bauteil (21, 22, 23, 24) ein zweites Elektrodenpad (21, 22, 21A-22D) aufweist, das elektrisch mit dem ersten Elektrodenpad auf einer der Chip-gebondeten Oberfläche gegenüberliegenden Oberfläche zu verbinden ist;ein leitfähiges Element (63, 68), das lateral zu dem Chip-Pad angeordnet ist und das elektrisch mit dem zweiten Elektrodenpad (21, 22, 21A- 22D) zu verbinden ist; undein Bond-Draht (31, 34), wobei ein Ende von diesem an das erste Elektrodenpad gebondet ist, das andere Ende von diesem an das leitfähige Element (63, 68) gebondet ist und ein Zwischenabschnitt ...

METHOD OF PACKAGING MICROWAVE SEMICONDUCTOR COMPONENTS AND INTEGRATED CIRCUITS

Apparatuses for communication systems transceiver interfaces

Transistor Arrangement

A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.

METHOD OF MANUFACTURING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer. 1. A semiconductor module comprising:a first semiconductor chip including a first power transistor therein and having a first surface formed with a first terminal electrically connected to the first power transistor and a second surface opposite to the first surface, the second surface being formed with a second terminal electrically connected to the first power transistor;a second semiconductor chip including a second power transistor therein and having a first surface formed with a third terminal electrically connected to the second power transistor and a second surface opposite to the first surface, the second surface being formed with a fourth terminal electrically connected to the second power transistor;a first chip mounting portion having a first surface and a second surface opposite to the first surface, the first chip mounting portion mounting the first semiconductor chip thereon through a first conductive bonding material so that the first surface of the first chip mounting portion and the second surface of the first semiconductor chip face each other;a second chip mounting portion having a first surface and a second surface opposite to the first surface, the second chip mounting portion mounting the second semiconductor chip thereon through a second conductive bonding material so that the first surface of the ...

Method of manufacturing semiconductor device

A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Wire bonding between isolation capacitors for multichip modules

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Halbleitervorrichtung und Herstellungsverfahren für eine Halbleitervorrichtung

Eine Halbleitervorrichtung (100) umfasst ein Gehäuse (Cs1), das einen Bereich (Rg1) umschließt, wo ein Halbleiterelement (S1) als eine Komponente einer elektrischen Schaltung vorhanden ist. Ein Harzteil (50) ist an einer Innenseite des Gehäuses (Cs1) in Kontakt mit dem Bereich (Rg1) fixiert. Das Harzteil (50) ist mit einem leitfähigen Film (E2) versehen, der ein Teil der elektrischen Schaltung ist. Der leitfähige Film (E2) ist im Harzteil (50) so vorgesehen, dass der leitfähige Film (E2) mit dem Bereich (Rg1) in Kontakt kommt.

Integrerad mikrovåghybridströmkrets

METHODS OF MANUFACTURING AND OPERATING DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES

Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire. 1. A semiconductor device comprising:a first semiconductor chip that is a rectangle having a first side, a second side facing the first side, a third side, and a fourth side;a second semiconductor chip that is a rectangle having a fifth side, a sixth side facing the fifth side, a seventh side, and an eighth side;a chip mounting part, over the same surface of which the first semiconductor chip and the second semiconductor chip are mounted; anda plurality of bonding wires that couple the first semiconductor chip to the second semiconductor chip,wherein the first side of the first semiconductor chip faces the fifth side of the second semiconductor chip,wherein the first semiconductor chip has a plurality of first electrode pads arranged along the first side,wherein the second semiconductor chip has a plurality of second electrode pads arranged along the fifth side,wherein, of the bonding wires, a first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along the first side,wherein, when viewed from a direction perpendicular to the chip mounting part, a maximum of a space between the first bonding wire and the second bonding wire is larger than that of a space between the ...

3次元デバイスの集積化方法および集積デバイス

... デバイス集積化方法および集積デバイス。本方法は、第1および第2の加工物の表面を各々約5~10Åの表面粗さまで研磨する工程を含む。第1および第2の加工物の研磨された表面は、互いに接合される。第3の加工物の表面は、前記表面粗さまで研磨される。第3の加工物の表面は、第1および第2の加工物に接着される。第1、第2および第3の加工物は、各々好ましくはウエハ形態にある1つの表面上に形成される薄い材料を有する半導体デバイスであり得る。薄い材料は、所望の表面粗さまで研磨され、その後、互いに接合される。薄い材料は、各々この薄い材料が上に形成される材料の表面非平面度の約1~10倍の厚さを有する。多数のデバイスが互いに接合され得、デバイスは、異なるタイプのデバイスまたは異なる技術であり得る。 ...

Semiconductor module

Semiconductor device and manufacturing method for semiconductor device

A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.

Method and apparatus for multi-chip structure semiconductor package

A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.

RESIN STRUCTURE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN, AND METHOD FOR MANUFACTURING SAID STRUCTURE

In a resin structure including a resin molded body and a plurality of electronic components embedded in the resin molded body, (i) the resin molded body has a plurality of exposed surfaces on which electrodes of the plurality of electronic components are exposed, (ii) the resin molded body has a recess formed therein, and (iii) the recess has a bottom surface which is at least one of the plurality of exposed surfaces.

APPARATUS FOR COMMUNICATION ACROSS A CAPACITIVELY COUPLED CHANNEL

For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier. 1. A circuit comprising:a substrate;a first plate substantially parallel to the substrate, thereby forming a first capacitance intermediate the first plate and the substrate;a second plate substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate;a third plate substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate;a fourth plate substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate; andan inductor connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.2. The circuit of claim 1 , wherein the inductor is a planar inductor.3. The circuit of claim 2 , wherein the planar inductor is substantially parallel to the substrate.4. The circuit of claim 1 , wherein a first surface area of the first plate is smaller than a second surface area of the substrate.5. The circuit of claim 4 , wherein a third surface area of the second plate is smaller than the first surface area of the ...

Halbleiteranordnung mit einem Abstandshalterelement und Verfahren zu deren und dessen Herstellung

Halbleiteranordnung (100), aufweisend: einen Metallträger (102); ein direkt an den Metallträger (102) angebrachtes Abstandshalterelement (106), wobei das Abstandshalterelement (106) entweder aus einem elektrisch isolierenden Material oder aus einem elektrisch leitfähigen Material besteht; eine erste gesinterte Metallschicht (108) auf dem Abstandshalterelement (106), wobei die erste gesinterte Metallschicht (108) gesinterte nanometergroße Metallpartikel aufweist; und einen Halbleiterchip (110) direkt auf der ersten gesinterten Metallschicht (108).

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die. 1. An integrated circuit package , comprising:a first guard bond wire having a first and second end coupled to ground;a second guard bond wire having a first and second end coupled to ground;a die mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die, wherein the die has a surface area with a first side and a second side that is opposite to the first side and at least a portion of the first guard bond wire is aligned with the first side of the die and at least a portion of the second guard bond wire is aligned with the second side of the die; anda flange on which the die is mounted;wherein the at least a portion of the first guard bond wire is aligned with the first side such that the at least a portion of the first bond wire runs parallel to the first side of the die, and wherein the at least a portion of the second guard bond wire is aligned with the second side such that the at least a portion of the second guard bond wire runs parallel to the second side of the die,wherein the first and/or second end of the first guard bond wire is/are coupled to ground through a flange mounted first and/or second capacitor, respectively, and the first and/or second end of the second guard bond wire is/are coupled to ground through a flange mounted third and/or fourth capacitor, respectively.215-. (canceled)16. The ...

FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF

A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. 1. A radio-frequency (RF) device comprising:an integrated circuit (IC) die, the IC die including at least one RF amplifier to implement the RF device;a package containing the IC die; anda flexible circuit lead coupled to the IC die inside the package, the flexible circuit lead extending from inside the package to outside the package, the flexible circuit lead comprising at least one flexible base layer and at least one conductor, the flexible circuit lead providing an electrical connection to the at least one RF amplifier on the IC die, wherein the at least one conductor is configured to form at least one passive device in a filter, with the filter electrically connected to the RF amplifier inside the package and through the flexible circuit lead.2. The RF device of wherein the at least one passive device formed with the least one conductor comprises a spiral inductor.3. The RF device of wherein the at least one passive device formed with the least one conductor comprises an inductor and a capacitor.4. The RF device of wherein the filter further includes at least one lumped passive element mounted on the flexible circuit lead.5. The RF device of wherein the at least one conductor in the flexible circuit lead is further configured to form a transmission line in the flexible circuit lead such that the transmission line is electrically connected to the RF amplifier claim 1 , and wherein the transmission line is formed ...

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region. 1the semiconductor device comprising a case that encloses a region where at least a first member as a component of an electric circuit exists, a resin part made of resin is fixed to an inside of the case, the inside being in contact with the region,', 'the resin part is provided with a conductive film, which is a part of the electric circuit,', 'the conductive film is provided in the resin part so that the conductive film comes into contact with the region, and', 'an electrode is further fixed to the inside of the case,, 'wherein'}the manufacturing method comprising a step of fixing the resin part and the electrode to the inside of the case by insert molding.. A manufacturing method for a semiconductor device This application is a Divisional of U.S. patent application Ser. No. 16/558,482 filed Sep. 3, 2019, which claims benefit of priority to Japanese Patent Application No. 2018-228965 filed Dec. 6, 2018, the entire content of which is incorporated herein by reference.The present invention relates to a semiconductor device having a configuration utilizing a case, and a manufacturing method for the semiconductor device.As a formation technique of a wiring pattern in a semiconductor device, there has been known a technique disclosed in Japanese Patent Application Laid-Open No. 2005-032779 (hereinafter, also referred to as a “related art A”).In the related art A, the wiring pattern is formed in a package body. Therefore, a product having a package small in size, and mass-produced is advantageous in cost, so that a low cost can be realized.However, when the ...

CHIP PACKAGING STRUCTURE, CHIP MODULE AND ELECTRONIC TERMINAL

Embodiments of the present application provide the chip packaging structure, the chip module and the electronic terminal. In the chip packaging structure, the chip is accommodated in the trench of the substrate to decrease the thickness and volume of the chip packaging structure; and the plastic package is provided on the surface of the substrate on which the chip is disposed to plastically package the chip, which not only ensures the structural strength of the chip packaging structure, but also reduces the warpage that may be caused due to the decrease of the thickness of the chip packaging structure as much as possible. In addition, the surface of the plastic package is treated to be a flat surface, such that the chip module has good flatness and the adaptability of the chip module is improved. 1. A chip packaging structure , comprising: a substrate and a plastic package; whereinthe substrate is provided with a trench, the trench being configured to accommodate a chip;the plastic package is configured to cover an upper surface of the substrate on which the chip is disposed, and an upper surface of the plastic package is a flat surface; orthe plastic package is configured to cover a lower surface of the substrate on which the chip is disposed, and a lower surface of the plastic package is a flat surface.2. The chip packaging structure according to claim 1 , wherein an upper surface of the chip and the upper surface of the substrate are in the same horizontal plane.3. The chip packaging structure according to claim 1 , wherein a lower surface of the chip and the lower surface of the substrate are in the same horizontal plane.4. The chip packaging structure according to claim 1 , wherein the substrate is further provided with a first electrical connection structure connected to a peripheral circuit claim 1 , the first electrical connection structure being configured to be electrically connected to a second electrical connection structure that is provided on the chip. ...

Segmented Bond Pads and Methods of Fabrication Thereof

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments. 1. A semiconductor device comprising:a first bond pad disposed at a first side of a substrate, the first bond pad comprising a first plurality of pad segments, wherein at least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.2. The device of claim 1 , further comprising a second bond pad spaced from the first bond pad disposed at the first side claim 1 , the second bond pad comprising a second plurality of pad segments claim 1 , wherein at least one pad segment of the second plurality of pad segments is electrically isolated from the remaining pad segments of the second plurality of pad segments.3. The device of claim 2 , wherein the first bond pad is coupled to a source node of a transistor claim 2 , and wherein the second bond pad is coupled to a gate node of the transistor.4. The device of claim 2 , wherein the first bond pad is coupled to a drain node of a transistor claim 2 , and wherein the second bond pad is coupled to a gate node of the transistor.5. The device of claim 1 , wherein each of the first plurality of pad segments is separated from an adjacent pad segment of the first plurality of pad segments by a plurality of openings.6. The device of claim 5 , wherein the plurality of openings comprise a dielectric material.7. The device of claim 1 , wherein the semiconductor device comprises a discrete semiconductor device.8. The device of claim 1 , wherein the semiconductor device comprises an integrated circuit.9. The device of claim 1 , wherein the first bond pad is a solder pad.10. A ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. 117-. (canceled)18. A semiconductor device comprising: a first upper surface including a chip mounting region and a first bent part, and', 'a first lower surface located on an opposite side from the first upper surface;, 'a die pad that includes a second upper surface,', 'a second lower surface located on an opposite side from the second upper surface, and', 'an electrode formed over the second upper surface;, 'a semiconductor chip that is mounted in the chip mounting region and includesa sealing body that includes a third upper surface and a third lower surface located on an opposite side from the third upper surface, and that seals the semiconductor chip and the first upper surface of the die pad;a lead having a first portion that is located in the sealing body and a second portion that is located outside the sealing body; anda wire that is located in the sealing body and connects the electrode of the semiconductor chip and the first portion of the lead,wherein the first lower surface of the die pad is exposed from the third lower surface of the sealing body,wherein the first bent part is located in the sealing body,wherein the first bent part extends from the chip mounting region in a first direction,wherein the electrode of the semiconductor chip and the first portion of the lead ...

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member. 1. A package structure , comprising:a first carrier plate, wherein at least a power component is disposed on a first top surface of the first carrier plate;a second carrier plate disposed on the first top surface of the first carrier plate, wherein a driving circuit is disposed on a second top surface of the second carrier plate for driving the power component, wherein at least an opening runs through the second carrier plate and corresponds to the power component, and the power component is accommodated within the opening when the second carrier plate is disposed on the first top surface of the first carrier plate;a pin group assembled on the first carrier plate and/or the second carrier plate, wherein the pin group comprises a first pin group and a second pin group; andan encapsulant member encapsulating the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member,wherein both of the first pin group and the second pin group are assembled on the first carrier plate ...

Semiconductor device including sense insulated-gate bipolar transistor

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM

A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. 1. A semiconductor device comprising:a chip mounting unit comprising a die paddle and a plurality of pins arranged close to the die paddle;a semiconductor chip attached onto a front side of the die paddle;a plurality of interconnection structures for electrically connecting each bonding pad arranged on a front side of the semiconductor chip to a bonding part of a corresponding pin close to the die paddle;a plastic package body covering the front side of the die paddle, the semiconductor chip, the interconnection structures and the bonding parts of the pins;a metal layer formed at the front side of the die paddle and a surface of each pin; anda passivation layer formed at a backside of the die paddle, wherein the passivation layer covers a remainder surface of the die paddle exposed from the plastic package body and a bottom surface of the passivation layer is coplanar with a bottom surface of the plastic package body.2. The semiconductor device of claim 1 , wherein the semiconductor chip is a vertical power device claim 1 , wherein a back metal layer formed at a backside of the semiconductor chip is attached onto the front side of the die paddle through a conductive adhesive.3. The semiconductor device of claim 1 , wherein the interconnection structure is a metal sheet claim 1 , a conductive band or a bonding wire.4. The semiconductor device of claim 1 , wherein the chip mounting unit further comprisesa heat sink connecting to the ...

Semiconductor module

In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal.

SUBSTRATE FOR MOUNTING MULTIPLE POWER TRANSISTORS THEREON AND POWER SEMICONDUCTOR MODULE

Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization. 1. A substrate comprising:multiple power transistors mounted thereon;a first metallization, on which the power transistors are commonly mountable with their collector or emitter, and which extends in at least one line on the substrate;a second metallization, which extends in an area next to the at least one line of the first metallization, for connection to other ones of the emitters or collectors of the power transistors; anda third metallization for connection to gate contact pads of the power transistors, wherein the third metallization includes at least two gate metallization areas, which are interconnectable through bonding means, whereby the gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line;at least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization, wherein the second metallization is adapted for mounting multiple power transistors with their collectors or emitters thereon, whereby the ...

SEMICONDUCTOR DEVICE AND MOUTING STRUCTURE OF SEMICONDUCTOR DEVICE

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface. 120-. (canceled)21. A semiconductor device comprising:a semiconductor element;a first conductive member electrically connected to and spaced apart from the semiconductor element;a second conductive member electrically connected to the semiconductor element and spaced apart from the semiconductor element and the first conductive member; anda resin member covering the semiconductor element, at least a part of the first conductive member and at least a part of the second conductive member,wherein the resin member comprises a first surface, a second surface, a third surface and a fourth surface, the first surface and the second surface being disposed to face away from each other in a first direction, the third surface and the fourth surface being disposed to face away from each other in a second direction perpendicular to the first direction,the first conductive member comprises a first end portion, a second end portion, a third end portion and a fourth end portion, the first end portion being exposed from the first surface of the resin member, the second end portion being exposed from the second surface of the resin member, the third end portion being exposed from the third surface of the resin member, the fourth end portion being smaller in size measured in the first direction ...

Sensor device and method of manufacture

A method of manufacturing a sensor device ( 100 ) comprises providing ( 200 ) a package ( 102 ) having a first die-receiving subframe volume ( 104 ) separated from a second die-receiving subframe volume ( 106 ) by a partition wall ( 116 ). An elongate sensor element ( 120 ) is disposed ( 202 ) within the package ( 102 ) so as to bridge the first and second subframe volumes ( 104, 106 ) and to overlie the partition wall ( 116 ). The elongate sensor element ( 120 ) resides substantially in the first subframe volume ( 104 ) and partially in the second subframe volume ( 106 ). The elongate sensor element ( 120 ) is electrically connected within the second subframe volume ( 106 ).

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. 1. A method of manufacturing a semiconductor device , the method comprising the steps of:(a) preparing a semiconductor chip having a pad electrode made of first copper, on a main surface of the semiconductor chip;(b) preparing a base material having a chip mounting portion and a lead;(c) after the step (b), mounting the semiconductor chip in the chip mounting portion; and(d) after the step (c), coupling the pad electrode and the lead by using a wire which is made of second copper and has a ball portion and a wire portion,wherein the step (d) includes the steps of(d-1) exposing the wire and the pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of the ball portion, and forming a second hydroxyl layer on a surface of the pad electrode,(d-2) a first bonding step of joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and(d-3) after the first bonding step, joining the ball portion to the pad electrode by performing a heat treatment on the semiconductor chip and the base material.2. The method of manufacturing a semiconductor device according to claim 1 ,wherein the reducing gas atmosphere contains nitrogen and hydrogen.3. The method of manufacturing a semiconductor device according to claim 1 ,wherein the second hydroxyl layer is formed on a surface of an oxidized layer formed on a surface of the pad electrode.4. The method of manufacturing a semiconductor device according to claim 3 ,wherein after the step (d-2), a first bonding layer foamed by first hydrogen bond and first ionic bond is formed between the ball portion and the pad electrode.5. The method of manufacturing a semiconductor device according to claim 4 ,wherein the step (d-2) is performed in 130° C.-250° C.6. The method of manufacturing a semiconductor device according to claim 4 ,wherein the first ionic bond included in the first bonding layer is formed of a first ...

Flexible circuit leads in packaging for radio frequency devices and methods thereof

A packaged RF device is provided that can provide improved performance and flexibility though the use of flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.

SEMICONDUCTOR DEVICE

In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines. 1. A semiconductor device comprising:an input terminal;a circuit substrate including a plurality of circuit patterns containing a parallel capacitor, a plurality of first input pads connected to inputs of the circuit patterns respectively; a plurality of first output pads, and a plurality of first microstrip lines connecting outputs of the circuit patterns to the first output pads respectively;a semiconductor substrate including a plurality of transistor cells, a plurality of second input pads connected to inputs of the transistor cells, and a plurality of second output pads connected to outputs of the transistor cells;an output terminal;a plurality of first wires connecting the input terminal to the first input pads respectively;a plurality of second wires connecting the first output pads to the second input pads respectively; anda plurality of third wires connecting the second output pads to the output terminal respectively,wherein each of the transistor cells has a plurality of fingers connected in parallel and a source electrode connected to a rear electrode through a via hole,the numbers of the fingers of the transistor cells are the same, andthe first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.2. The semiconductor device according to claim 1 , wherein the ...

SEMICONDUCTOR DEVICE

Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD and a plurality of leads LD via a metal plate. As viewed in a plane, the leads LD intersect with a side MRd of the sealing portion and the leads LD intersect with a side MRd of the sealing portion. 1. A semiconductor device comprising:a first semiconductor chip including a first power transistor for high-side switch and having a first principal surface and a first back face located on the opposite side to the first principal surface,wherein the first semiconductor chip includes a first back electrode formed in the first back face and coupled to the first power transistor, a first electrode formed in the first principal surface and coupled to the first power transistor, and a first gate electrode formed in the first principal surface and controlling continuity between the first electrode and the first back electrode;a second semiconductor chip including a second power transistor for high-side switch and having a second principal surface and a second back face located on the opposite side to the second principal surface,wherein the second semiconductor chip includes a second back electrode formed in the second back face and coupled to the second power transistor, a second electrode formed in the second principal surface and coupled to the second power transistor, and a second gate electrode formed in the second principal surface and controlling continuity between the second electrode and the second back electrode;a third ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin. 116-. (canceled)17. A semiconductor device comprising:a semiconductor element;a terminal spaced apart from and electrically connected to the semiconductor element; anda sealing resin covering the semiconductor element and at least a part of the terminal,wherein the sealing resin includes an obverse surface formed with a mark representing information relating to the semiconductor device, and the mark comprises at least one recess formed in the obverse surface and at least one flat portion.18. The semiconductor device according to claim 17 , further comprising a wire connecting the semiconductor element to the terminal claim 17 , wherein the mark is spaced apart from a top of the wire as viewed in a direction parallel to the obverse surface of the sealing resin.19. The semiconductor device according to claim 17 , wherein the sealing resin has a pair of first sides and a pair of second sides as viewed in plan claim 17 , the second sides being longer than the first sides claim 17 , and wherein an entirety of the mark is spaced apart from the first sides and the second sides as viewed in plan.20. The semiconductor device according to claim 19 , further ...

SEMICONDUCTOR LIGHT EMITTING DEVICE

A semiconductor light emitting device includes a main lead, a sub lead, a semiconductor light emitting element bonded to the main lead, and a protective element bonded to the sub lead, wherein the semiconductor light emitting element is connected to the main lead and the sub lead via a first wire and a second wire, respectively, wherein the protective element has a main surface electrode and a back surface electrode which is connected to the sub lead via a conductive bonding material, and wherein the main surface electrode of the protective element is connected to the main lead via a third wire, a connecting wiring which connects electrodes of the semiconductor light emitting element, and a connecting member including the second wire. 1. A semiconductor light emitting device comprising:a main lead having a main surface and a first back surface facing a side opposite to the main surface;a sub lead arranged in a first direction with respect to the main lead, and having a main surface facing the same side as the main surface of the main lead and a second back surface facing the side opposite to the main surface of the sub lead;a case configured to support the main lead and the sub lead, and having a case main surface facing the same side as the main surfaces of the main lead and the sub lead, and an opening formed in the case main surface to expose portions of the main lead and the sub lead;a semiconductor light emitting element arranged on the main surface of the main lead, and having an element main surface facing the same side as the main surface of the main lead, an element back surface facing the main surface of the main lead, a first electrode formed on the element main surface, and a main surface connecting portion formed on the element main surface;a first bonding material bonding the semiconductor light emitting element to the main lead;a first wire connecting the first electrode of the semiconductor light emitting element to the sub lead;a protective element ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package () includes a die pad (), a source lead (), a first MOSFET (), and a first Schottky barrier diode (). A source electrode () of the first MOSFET (), an anode electrode () of the first Schottky barrier diode (), and the source lead () are electrically connected by the bonding wire (), one end of which is bonded to the source electrode () of the first MOSFET (), the other end of which is bonded to the source lead (), and the center of which is bonded to the anode electrode () of the first Schottky barrier diode (). 1. A semiconductor device comprising:a die pad;a bipolar device die-bonded to a surface of the die pad, the bipolar device having a first electrode pad on a surface opposite to a die-bonded surface;a unipolar device die-bonded to the surface of the die pad, the unipolar device having a second electrode pad to be connected electrically to the first electrode pad on a surface opposite to a die-bonded surface;a conductive member disposed laterally to the die pad to be connected electrically with the second electrode pad; anda bonding wire, one end of which is bonded to the first electrode pad, the other end of which is bonded to the conductive member, and the center of which is bonded to the second electrode pad, whereina first wire portion of the bonding wire between the portion bonded to the first electrode pad and the portion bonded to the second electrode pad is at an angle of 90 degrees or more, in a plan view, with respect to a second wire portion of the bonding wire between the portion bonded to the second electrode pad and the portion bonded to the conductive member.2. The semiconductor device according to claim 1 , whereinthe ...

Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device. 1. A method of forming and transferring shaped metallic interconnects , comprising:providing a donor substrate comprising an array of metallic interconnects;using a laser system to prepare the metallic interconnects;forming shaped metallic interconnects; andtransferring the shaped metallic interconnect to an electrical device.2. The method of forming and transferring shaped metallic interconnects of claim 1 , further comprising the steps of:delivering laser pulses to the metallic interconnects on the donor substrate; andutilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.3. The method of forming and transferring shaped metallic interconnects of claim 1 , wherein the step of providing a donor substrate comprising an array of metallic interconnects further includes the steps of:forming an adhesion/release layer on the donor substrate;wherein the adhesion/release layer comprises a material with high UV absorption and wherein the material softens or melts above room temperature;placing a metal foil on the adhesion/release layer;bonding the metal foil to the adhesion/release layer; andpatterning the metal foil by machining or etching.4. The method of forming and transferring ...

Transistor arrangement

A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a first semiconductor element, a second semiconductor element, and a metal pattern formed on the second semiconductor clement. The metal pattern includes a first connection connected to the first semiconductor element and a second connection connected to a first terminal portion of the first semiconductor element and positioned away from the first connection. A first electrically conductive path formed between the first and second connections has a larger electric resistance than an electric resistance of a second electrically conductive path formed between the second connection and the first terminal portion. 1. A semiconductor apparatus comprising:a lead frame;a first semiconductor element that is disposed on the lead frame and through which a main current flows;a second semiconductor element disposed on the lead frame and connected in parallel with the first semiconductor element; anda metal pattern formed on an upper surface of the second semiconductor element, a die pad portion on which the first and second semiconductor elements are disposed;', 'a first terminal portion of the first semiconductor element that is connected to the first semiconductor element via the metal pattern; and', 'a second terminal portion of the first semiconductor element that is formed continuously with the die pad portion,, 'the lead frame including at least one first connection connected to the first semiconductor element; and', 'at least one second connection connected to the first terminal portion and positioned away from the first connection,, 'the metal pattern includinga first electrically conductive path formed between the first and second connections has a larger electric resistance than an electric resistance of a second electrically conductive path formed between the second connection and the first terminal portion.2. The semiconductor apparatus according to claim 1 , further comprising a first wire that connects the second connection with ...

SEMICONDUCTOR DEVICE

First and second circuit patterns () are provided on an insulating substrate (). First and second semiconductor chips () are provided on the first circuit pattern (). A relay circuit pattern () is provided between the first semiconductor chip () and the second semiconductor chip () on the insulating substrate (). A wire () is continuously connected to the first semiconductor chip (), the relay circuit pattern (), the second semiconductor chip () and the second circuit pattern () which are sequentially arranged in one direction. 1. A semiconductor device comprising:an insulating substrate;first and second circuit patterns provided on the insulating substrate;first and second semiconductor chips provided on the first circuit pattern;a relay circuit pattern provided between the first semiconductor chip and the second semiconductor chip on the insulating substrate; anda wire continuously connected to the first semiconductor chip, the relay circuit pattern, the second semiconductor chip and the second circuit pattern which are sequentially arranged in one direction.2. The semiconductor device according to claim 1 , wherein pluralities of each of the first and second semiconductor chips are provided claim 1 , andthe relay circuit pattern is electrically connected to upper surface electrodes of the pluralities of first and second semiconductor chips to equalize potentials of the upper surface electrodes of the pluralities of first and second semiconductor chips.3. The semiconductor device according to claim 1 , wherein the relay circuit pattern is higher in thermal conductivity than the first and second circuit patterns.4. The semiconductor device according to claim 1 , further comprising a high thermal conductivity film which is provided on the relay circuit pattern and higher in thermal conductivity than the relay circuit pattern and the first and second circuit patterns.5. The semiconductor device according to claim 1 , wherein thickness of the relay circuit pattern is ...

Semiconductor device and leadframe

A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns. 1. An electronic device comprising:a substrate having a top surface and a bottom surface opposite to the top surface, a shape in a plan view of the top surface being comprised of a rectangle having a first long side, a second long side, a first short side and a second short side,a first metal pattern formed on the top surface of the substrate;a second metal pattern formed on the top surface of the substrate, and spaced apart from the first metal pattern;a third metal pattern formed on the top surface of the substrate, and spaced apart from the first and second metal patterns;a fourth metal pattern formed on the top surface of the substrate, and spaced apart from the first, second and third metal patterns;a first semiconductor chip mounted on a first region in a surface of the first metal pattern via a first bonding material;a second semiconductor chip mounted on a first region in a surface of the second metal pattern via a second bonding material;a first terminal mounted on a first region in a surface of the third metal pattern via a third bonding material, and connected with the third metal pattern via the third bonding material;a second terminal mounted on a first region in a surface of the fourth metal pattern via a fourth bonding material, and connected with the fourth terminal via the fourth bonding material;a cover ...

PACKAGE STRUCTURE INTEGRATING A START-UP COMPONENT, A CONTROLLER, AND A POWER SWITCH

A package structure integrating a start-up component, a controller, and a power switch for a power converter, wherein the power converter has a coil having a first end and a second end, and the first end is coupled to a rectifier, the package structure including: a first die pad for carrying a chip of the controller; a second die pad for carrying a chip of the start-up component and a chip of the power switch, wherein the chip of the start-up component has a bottom surface providing a first drain contact; and the chip of the power switch has a bottom surface providing a second drain contact; and a plurality of external connection leads, of which one is connected with the second die pad via a wire and is used to couple with the second end of the coil. 1. A package structure integrating a start-up component , a controller , and a power switch for a power converter , wherein said power converter has a coil for transferring power , said coil has a first end and a second end , and said first end is coupled to a rectifier , said package structure comprising:a first die pad made of a conductor, used for carrying a chip of said controller;a second die pad made of said conductor, used for carrying a chip of said start-up component and a chip of said power switch, wherein said chip of said start-up component has a top surface providing a first gate contact and a first source contact, and a bottom surface providing a first drain contact which is electrically connected with said second die pad; and said chip of said power switch has a top surface providing a second gate contact and a second source contact, and a bottom surface providing a second drain contact which is electrically connected with said second die pad;a plurality of external connection leads, wherein one of said plurality of external connection leads is connected with said second die pad via a wire and is used to couple with said second end of said coil; anda resin material, used to enclose said chip of said ...

Method and apparatus for multi-chip structure semiconductor package

A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.

DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES AND METHODS

Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces. 1. A device comprising:a first integrated circuit (IC) die that includes a first coil proximate to a first surface of the first IC die, and a plurality of first bond pads, wherein the plurality of first bond pads are electrically coupled to the first coil;an inductive coupling substrate that includes a second coil and a first signal communication interface, wherein the second coil is proximate to a first surface of the inductive coupling substrate, and the second coil is electrically coupled to the first signal communication interface;a second IC die that includes a second signal communication interface and a plurality of second bond pads, wherein the second signal communication interface is electrically coupled to the plurality of second bond pads, and whereinthe first IC die, the second IC die, and the inductive coupling substrate are arranged within the device so that the first surface of the inductive coupling substrate faces the first surface of the first IC die and a first surface of the second IC die, the first coil and the second coil are aligned with each ...

COMMON-SOURCE PACKAGING STRUCTURE

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body. 1. A common-source packaging structure , comprising: a main body, having a common-source region, a first gate region, a second gate region, a first arrangement region, and a second arrangement region, wherein the first arrangement region and the second arrangement region are separated from each other;', 'a first metal-oxide-semiconductor field-effect transistor (MOSFET) die, located on the first arrangement region, having a first upper layer, and comprising:', 'at least one first source electrode pad, exposed through the first upper layer; and', 'at least one first gate electrode pad, spaced apart from the at least one first source electrode pad, and exposed through the first upper layer;, 'an integrated circuit (IC) unit, comprising at least one second source electrode pad, exposed through the second upper layer; and', 'at least one second gate electrode pad, spaced apart from the at least one second source electrode pad, and exposed through the second upper layer;, 'a second MOSFET die, located on the second arrangement region, having a second upper layer, and comprisingat least one common-source connection element, connected to ...

COMMON-SOURCE PACKAGING STRUCTURE

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body. 1. A common-source packaging structure , comprising:an integrated circuit (IC) unit, comprising:a main body, having a common-source region, a first gate region, a second gate region, a first arrangement region, and a second arrangement region, wherein the first arrangement region and the second arrangement region are separated from each other;a first metal-oxide-semiconductor field-effect transistor (MOSFET) die, located on the first arrangement region, having a first upper layer, and comprising:at least one first source electrode pad, exposed through the first upper layer; andtwo first gate electrode pads, respectively located at two corresponding corners of the at least one first source electrode pad, spaced apart from the at least one first source electrode pad, and exposed through the first upper layer;a second MOSFET die, located on the second arrangement region, having a second upper layer, and comprising:at least one second source electrode pad, exposed through the second upper layer; andtwo second gate electrode pads, respectively located at two corresponding corners of the at least one second source electrode pad, spaced ...

Ribbon Bond Solution for Reducing Thermal Stress on an Intermittently Operable Chipset Controlling RF Application for Cooking

Power amplifier electronics for controlling application of radio frequency (RF) energy generated using solid state electronic components may further be configured to control application of RF energy in cycles between high and low powers. The power amplifier electronics may include a semiconductor die on which one or more RF power transistors are fabricated, an output matching network configured to provide impedance matching between the semiconductor die and external components operably coupled to an output tab, and bonding ribbon bonded at terminal ends thereof to operably couple the one or more RF power transistors of the semiconductor die to the output matching network. The bonding ribbon may have a width of greater than about five times a thickness of the bonding ribbon. 1. An oven comprising:a cooking chamber configured to receive a food product; anda radio frequency (RF) heating system configured to provide RF energy into the cooking chamber using solid state electronic components to heat the food product,wherein the solid state electronic components include power amplifier electronics configured to provide a signal into the cooking chamber via a launcher assembly operably coupled to the cooking chamber via a waveguide assembly,wherein the power amplifier electronics are configured to control application of RF energy into the cooking chamber at least in part based on a learning procedure that generates a power cycling between high and low powers when the learning procedure is executed, a semiconductor die on which one or more RF power transistors are fabricated,', 'an output matching network configured to provide impedance matching between the semiconductor die and external components operably coupled to an output tab, and', 'a bonding ribbon that is bonded at terminal ends thereof to operably couple the one or more RF power transistors of the semiconductor die to the output matching network, and, 'wherein the power amplifier electronics includewherein the ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Embodiments of the present disclosure provide a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device. The semiconductor device comprises: a semiconductor die; an electrical isolation layer formed on a surface of the semiconductor die; a substrate; and a non-conductive adhesive layer disposed between the electrical isolation layer and the substrate, so as to adhere the electrical isolation layer to the substrate. 1. A semiconductor device , comprising:a semiconductor die;an electrical isolation layer formed on a surface of the semiconductor die;a substrate; anda non-conductive adhesive layer disposed between the electrical isolation layer and the substrate, so as to adhere the electrical isolation layer to the substrate.2. The semiconductor device according to claim 1 , wherein the semiconductor die comprises a bonding pad claim 1 , the bonding pad being disposed at another surface of the semiconductor die opposite to the surface.3. The semiconductor device according to claim 2 , further comprising a lead claim 2 , the lead being connected to the bonding pad using a bonding wire.4. The semiconductor device according to claim 1 , further comprising:a further semiconductor die; anda conductive adhesive layer configured to adhere the further semiconductor die to the substrate.5. The semiconductor device according to claim 1 , wherein the non-conductive adhesive layer comprises a die attach film or an adhesive glue.6. The semiconductor device according to claim 1 , wherein the electrical isolation layer is a molding layer or a spin-coated layer.7. The semiconductor device according to whereina molding compound encapsulates the semiconductor device to form a semiconductor package.8. A method for manufacturing a semiconductor device claim 1 , comprising:forming an electrical isolation layer on a surface of a semiconductor wafer;attaching a die attach film to the electrical isolation layer;dicing the semiconductor wafer, the ...

OPTICAL COMPONENT AND OPTICAL MODULE USING THE SAME

An optical component configured to be mounted on a circuit board has a casing made of a ceramic electrical insulator and having a cavity, a photonic circuit device provided in the cavity, a lid configured to cover the cavity, and protruding electrodes provided along an outer periphery of the cavity of the casing, wherein a first linear expansion coefficient of the casing is smaller than a second linear expansion coefficient of the circuit board, and a third linear expansion coefficient of the lid is greater than the second linear expansion coefficient of the circuit board. 1. An optical component configured to be mounted on a circuit board , comprising:a casing made of a ceramic electrical insulator and having a cavity;a photonic circuit device provided in the cavity;a lid configured to cover the cavity; andprotruding electrodes provided along an outer periphery of the cavity of the casing,wherein a first linear expansion coefficient of the casing is smaller than a second linear expansion coefficient of the circuit board, and a third linear expansion coefficient of the lid is greater than the second linear expansion coefficient of the circuit board.2. The optical component as claimed in claim 1 , wherein an overall linear expansion coefficient of a combination of the casing and the lid is balanced with the second linear expansion coefficient of the circuit board.3. The optical component as claimed in claim 1 , wherein a position of an outer surface of the lid opposite to the cavity is aligned with a distal end of the protruding electrodes in a height direction.4. The optical component as claimed in claim 1 , wherein a position of an outer surface of the lid opposite to the cavity is lower than a distal end of the protruding electrode in a height direction.5. The optical component as claimed in claim 1 , wherein an outer surface of the lid opposite to the cavity is provided with surface treatment that enables soldering.6. The optical component as claimed in claim 1 , ...

Package with terminal pins with lateral reversal point and laterally exposed free end

A package ( 120 ), wherein the package ( 120 ) has at least one electronic chip ( 124 ), an encapsulation body ( 138 ) that encapsulates the electronic chip(s) ( 124 ), and a plurality of terminal pins ( 122 ) to connect the electronic chip(s) ( 124 ), wherein each of the said terminal pins ( 122 ) has an encapsulated section ( 126 ), which is encapsulated at least partially by the encapsulation body ( 138 ) and has an exposed section ( 128 ) that protrudes from the encapsulation body ( 138 ), and wherein at least a portion of the exposed sections ( 128 ) laterally extends from the encapsulation body ( 138 ) up to a reversal point ( 130 ) and laterally extends back from the reversal point ( 130 ) to the encapsulation body ( 138 ), so that a free end ( 132 ) of the exposed sections ( 128 ) is laterally aligned with or to a corresponding side wall ( 134 ) of the encapsulation body ( 138 ) or is spaced from the corresponding side wall ( 134 ) of the encapsulation body ( 138 ) laterally outwardly.

Power Semiconductor Device

This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is formed; and a plurality of press-fit terminals each having a wire-bond portion electrically connected in the package to the electric circuit, a press-fit portion for making electrical connection with an apparatus to be connected, and a body portion whose one end portion continuous to the wire bond portion is internally fastened to the package and whose other end portion supports the press-fit portion so as to place the press-fit portion away from the package; wherein in each of the plurality of press-fit terminals, at a portion in the body portion exposed from the package, there is formed a constriction portion that is constricted from both sides in a direction perpendicular to the center line, so as to leave a portion around the center line. 1. A power semiconductor device which is to be electrically connected to an apparatus , comprising:a circuit board which is disposed in a housing made of a resin, and on which a power semiconductor element is formed; anda plurality of press-fit terminals which are each electrically connected, at one end, to the circuit board, and are each to be electrically connected, at the other end, to the apparatus, 'an inner terminal portion electrically connected in the housing to the circuit board;', 'said press-fit terminals being formed of a metal plate member, and each comprisinga body portion which has an embedded portion that is continuous to the inner terminal portion and embedded in the housing, and an exposed portion exposed from the housing; anda press-fit portion which is supported by the body portion, has branched portions that are branched in a width direction of the body portion, and serves as an electrical contact with the apparatus;wherein, in the exposed portion, there is formed a constriction portion that is concaved from both sides of the body portion in the width ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region. 1. A semiconductor device comprising a case that encloses a region where at least a first member as a component of an electric circuit exists ,whereina resin part made of resin is fixed to an inside of the case, the inside being in contact with the region,the resin part is provided with a conductive film, which is a part of the electric circuit, andthe conductive film is provided in the resin part so that the conductive film comes into contact with the region.2. The semiconductor device according to claim 1 , whereina part of the resin part is embedded in the case, andanother part of the resin part projects from the case.3. The semiconductor device according to claim 2 , whereinan electrode is fixed to the inside of the case, andthe resin part is disposed so that the resin part straddles the electrode.4. The semiconductor device according to claim 1 , whereina part of the resin part is embedded in the case, andthe part of the resin part embedded in the case has a fixing portion that is fixed to a part of the case.5. The semiconductor device according to claim 4 , wherein the fixing portion is a groove provided in a side surface of the resin part.6. The semiconductor device according to claim 4 , wherein the fixing portion is a through hole that penetrates the resin part.7. The semiconductor device according to claim 1 , whereinthe resin part is provided with a plurality of wiring circuits, andeach of the wiring circuits is the conductive film.8. The semiconductor device according to claim 1 , whereinanother resin part made of resin is further fixed to the ...

SEMICONDUCTOR DIE WITH VARIABLE LENGTH BOND PAD

A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes. 1. A semiconductor die , comprising:a plurality of elongate adjacent external interface cells forming an interface cell row, wherein each of the external interface cells provides an external interface for a circuit node of the die; anda plurality of bond pads, each of the bond pads electrically connected to a directly underlying interface cell of the interface cell row, each of the bond pads having a longitudinal axis aligned with a lengthwise axis of the respective directly underlying interface cell, and wherein each of the bond pads has a plurality of potential wire bond site locations along the respective longitudinal axis thereof.2. The semiconductor die of claim 1 , wherein each of the bond pads are rectangular.3. The semiconductor die of claim 1 , wherein each of the bond pads extends to a non-overlying region of the interface cell row.4. The semiconductor die of claim 3 , wherein the bond pads comprise a plurality of first row bond pads that form a first row of spaced first bond pads claim 3 , and a plurality of second row bond pads that form a second row of spaced second bond pads claim 3 , wherein each of the second row bond pads is electrically connected to a directly underlying interface cell of the interface cell row.5. The semiconductor die of claim 4 , wherein each of the first row bond pads overlay two other of the adjacent circuit ...

SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES

A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads. 1. A packaged semiconductor device , comprising:a semiconductor die having a plurality of bond pads;a first bond wire wire-bonded between a first bond pad and a second bond pad, wherein the first and second bond pads are configured to be charged to a first voltage level; anda second bond wire wire-bonded between a third bond pad and a fourth bond pad, wherein the second bond wire is adjacent to the first bond wire, and the third and fourth bond pads are configured to be charged to a second voltage level different from the first voltage level such that the first and second bond wires function as a decoupling capacitor for the die.2. The device of claim 1 , wherein the first and second bond wires are insulated bond wires having insulation along their respective intermediate lengths.3. The device of claim 1 , wherein the decoupling capacitor provides charge for integrated circuitry implemented within the die in a location below the decoupling capacitor.4. The device of claim 1 , wherein claim 1 , when charged to the first and second voltage levels claim 1 , respectively claim 1 , no current flows through the first and second bond wires.5. The device of claim 1 , wherein the first bond wire is substantially parallel to the second bond wire.6. The device of claim 1 , wherein:the first and second bond pads lie along a first line;the third and fourth bond pads lie along a second line parallel to the first line; andthe first bond wire is horizontally aligned with the second bond wire.7. The device of claim 1 , wherein:the first, second, third, and fourth bond pads are substantially collinear; andthe first bond wire is ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. 1. A semiconductor device comprising:a chip mounting portion that includes a first upper surface and a first lower surface located on the opposite side of the first upper surface;a semiconductor chip that includes a second upper surface, an electrode formed over the second upper surface, and a second lower surface located on the opposite side of the second upper surface and mounted over the first upper surface;a lead;a wire that connects the electrode of the semiconductor chip and the lead; anda sealing body that includes a third upper surface and a third lower surface located on the opposite side of the third upper surface and seals the semiconductor chip, the wire, a part of the lead, and a part of the chip mounting portion,wherein the first lower surface of the chip mounting portion is exposed from the third lower surface of the sealing body,wherein the chip mounting portion and the wire are comprised of copper, andwherein a thickness of the semiconductor chip is larger than the sum of a thickness of the chip mounting portion and a thickness from the second upper surface of the semiconductor chip to the third upper surface of the sealing body.2. The semiconductor device according to claim 1 ,wherein the lead extends in a first direction in planar view,wherein the chip mounting ...

Wire bonding between isolation capacitors for multichip modules

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device. 1. A method of forming and transferring shaped metallic interconnects , comprising:providing a donor substrate comprising an array of metallic interconnects;using a laser system to prepare the metallic interconnects;forming shaped metallic interconnects; andtransferring the shaped metallic interconnect to an electrical device.2. The method of forming and transferring shaped metallic interconnects of claim 1 , further including the step of:laser bending the shaped metallic interconnect and then transferring the shaped metallic interconnect onto a receiving substrate or device.3. The method of forming and transferring shaped metallic interconnects of claim 1 , further comprising the steps of:delivering laser pulses to the metallic interconnects on the donor substrate; andutilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.4. The method of forming and transferring shaped metallic interconnects of claim 2 , wherein the laser fluence during bending of the shaped metallic interconnects is 1.1 J/cmfor 12.5 μm thick interconnects.5. The method of forming and transferring shaped metallic interconnects of claim 1 , wherein the step of providing a donor substrate comprising an ...

ELECTRONIC DEVICE

An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer. 114.-. (canceled)15. An electronic device comprising a carrier and a semiconductor chip ,wherein the carrier comprises a first dielectric layer and a second dielectric layer,a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer,the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer,the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer,and the carrier comprises a solder terminal for electrical contacting arranged on the second dielectric layer.16. The electronic device according to claim 15 , wherein the second dielectric layer comprises an opening by which the mounting area is provided.17. The electronic device according to claim 15 , wherein the carrier comprises a mounting pad arranged on the first dielectric layer in the mounting area claim 15 , and the semiconductor chip is arranged on the mounting pad.18. The electronic device according to claim 15 , wherein the carrier comprises a metal base layer on which the first dielectric layer is arranged.19. The electronic device according to claim 15 , wherein the carrier comprises a contact layer arranged on the second dielectric layer and a covering layer partially ...

APPARATUS FOR COMMUNICATION ACROSS A CAPACITIVELY COUPLED CHANNEL

Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier. 1. A circuit comprising:a substrate;a first plate substantially parallel to the substrate, thereby forming a first capacitance intermediate the first plate and the substrate;a second plate substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate;a third plate substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate;a fourth plate substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate; andan inductor connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.2. The circuit of claim 1 , wherein the inductor is a planar inductor.3. The circuit of claim 2 , wherein the planar inductor is substantially parallel to the substrate.4. The circuit of claim 1 , wherein a first surface area of the first plate is smaller than a second surface area of the substrate.5. The circuit of claim 4 , wherein a third surface area of the second ...

Packaged leadless semiconductor device

A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.

Electronic Device By Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device. 1. An electronic device made from the method of providing a donor ribbon , wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate , providing a stencil to the metal structures on the donor substrate , applying a laser pulse through the donor substrate to the metal structures , laser bending the shaped metallic interconnect; and transferring the shaped metallic interconnect onto a receiving substrate or device.2. The electronic device of wherein the method further comprises the steps of delivering laser pulses to the metallic interconnects on the donor substrate; and utilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.3. The electronic device of wherein the laser fluence during bending of the shaped metallic interconnects is 1.1 J/cmfor 12.5 μm thick interconnects and wherein the laser bending of the shaped metallic interconnect comprises the steps of placing a stencil over the metallic interconnects and firing the laser through the donor substrate into open regions of the stencil.4. The electronic device of wherein the step of providing a donor substrate comprising an array of metallic interconnects further includes the steps of dissolving a low temperature wax in toluene and forming a solution; spin coating the solution at room temperature and forming a wax layer; placing a copper foil over the wax layer; bonding the copper foil to the wax layer by heating and pressing at about 80° C.; applying a photoresist to the copper foil; exposing and developing the ...

THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME

A thermally enhanced semiconductor assembly with three dimensional integration includes a semiconductor chip electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the semiconductor chip is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the semiconductor chip and the wiring board for interconnecting the semiconductor chip to terminal pads provided in the wiring board. 1. A method of making a thermally enhanced semiconductor assembly with three dimensional integration , comprising: inserting a heat spreader into a through opening of a first wiring structure, with a backside surface of the heat spreader being substantially coplanar with a first surface of the first wiring structure, and', 'forming a second wiring structure on the backside surface of the heat spreader and the first surface of the first wiring structure, wherein the second wiring structure is electrically coupled to the first wiring structure and thermally conductible to the heat spreader through metallized vias;, 'providing a wiring board, includingdisposing a first semiconductor chip in the through opening of the first wiring structure and over the heat spreader; andproviding a plurality of bonding wires that electrically couple the first semiconductor chip to a second surface of the first wiring structure opposite to the first surface.2. The method of claim 1 , further comprising a step of providing a second semiconductor chip stacked over the first semiconductor chip by an adhesive and electrically coupled to the first wiring structure by a plurality of additional bonding wires.3. The method of claim 1 , further comprising a step of providing a semiconductor device stacked over ...

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE

The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit. 1. A semiconductor package , comprising:a base substrate; anda semiconductor chip mounted on the base substrate,wherein the semiconductor chip comprises:a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions;a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit; andan inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit, andwherein a first set of a first non-inverting pad electrode and a first inverting pad electrode is disposed above a first IO cell region of the plurality of IO cell regions, and the first set is disposed so that the first non-inverting pad electrode and the first inverting pad electrode are disposed along a first line along the side of the semiconductor chip; andwherein a second set of a second non-inverting pad electrode and a second inverting pad electrode is disposed above a second IO cell region of ...

POWER SEMICONDUCTOR DEVICE

A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads. 1. A power semiconductor device , comprising:a leadframe, which comprises a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive,at least one first power semiconductor component applied on the first chip carrier part,at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, anda capacitor,wherein the capacitor is mounted on two adjacent external leads.2. The power semiconductor device of claim 1 ,wherein the two adjacent external leads comprise soldering connections for connecting the capacitor.3. The power semiconductor device of claim 1 , further comprising:bonding wires configured to electrically connect contact areas on active top sides of the first power semiconductor component and of the second power semiconductor component and contact areas on the external leads.4. The power semiconductor device of claim 3 ,wherein the soldering connections differ from the contact areas on the external leads.5. The power semiconductor device of claim 1 ,wherein the external leads in each case comprise a first part, on which the contact areas are arranged and which lies in the same horizontal plane as the first chip carrier part and the second chip carrier part, a signal lead, which is oriented parallel to the first part and ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

A resin casing is insert-molded while clamp protrusions of clamp portions formed in bonding portions of lead terminals are put between an upper mold and a lower mold. An insulating substrate which has a wiring pattern mounted with semiconductor elements is fitted into an opening portion of the resin casing and adhesively bonded to the resin casing. Electric connection between the semiconductor elements and the bonding portions of the lead terminals and between the wiring pattern on the insulating substrate and the bonding portions of the lead terminals is made by bonding wires. Thus, it is possible to provide a method for manufacturing a semiconductor device and the semiconductor device, in which stress applied to lead terminals of a lead frame formed by insert molding can be suppressed, and wire bonding properties and reliability can be improved even when the thickness of each of the lead terminals is reduced. 1. A method for manufacturing a semiconductor device including a semiconductor element received in an annular resin casing which has an opening portion and which is molded integrally with lead terminals by insert molding using at least two molds , the method comprising:an insert molding step of placing clamp portions, which have clamp protrusions and which are formed in bonding portions of the lead terminals, on one of the molds to protrude the clamp portions into the opening portion, and insert-molding the resin casing while putting the clamp protrusions between the one mold and another mold;a substrate mounting step of fitting an insulating substrate, which has a wiring pattern mounted with the semiconductor element, into the opening portion of the insert-molded resin casing and adhesively bonding the insulating substrate and the resin casing to each other; anda wire bonding step of making electric connection between the semiconductor element and one of the bonding portions of the lead terminals and/or between the wiring pattern on the insulating substrate ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip. 1. A semiconductor package , comprising:a package substrate;at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate;at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate;at least one third semiconductor chip stacked on the first and second semiconductor chips; andat least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.2. The semiconductor package of claim 1 , wherein the at least one support structure comprises:at least one dummy pad on the second semiconductor chip; andat least one dummy wire having first and second end portions adhered to the at least one dummy pad and making contact with a lower surface of the at least one third semiconductor chip.3. The semiconductor package of claim 2 , wherein the second semiconductor chip comprises a redistribution wiring layer claim 2 , which is an uppermost layer of the second semiconductor chip claim 2 , and the redistribution wiring layer comprises the at least one dummy pad.4. The semiconductor package of ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE

A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.

SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface. 1. A semiconductor substrate structure , comprising:a conductive structure having a first conductive surface and a second conductive surface opposite to the first conductive surface; anda dielectric structure covering at least a portion of the conductive structure, and having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, wherein the first conductive surface does not protrude from the first dielectric surface, the second conductive surface is recessed from the second dielectric surface, wherein the dielectric structure includes, or is formed from, a cured photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.2. The semiconductor substrate structure according to claim 1 , wherein a side wall defining the dielectric opening is curved.3. The semiconductor substrate structure according to claim 1 , wherein the dielectric opening has a first width at the second dielectric surface and a ...

Electronic package with antenna structure

Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.

Semiconductor module

A semiconductor module includes: a circuit board on which a first semiconductor chip and a second semiconductor chip are mounted and includes a first through hole formed with a conductor foil therein; a press-fit terminal that is electrically connected to the conductor foil in the first through hole of the circuit board; and a second resin that is disposed on a surface side and a back surface side of the circuit board. Further, the press-fit terminal is provided with a pressure contact portion which is press-fitted into the first through hole and is electrically connected to the conductor foil in the first through hole, and the second resin on the surface side of the circuit board and the second resin on the back surface side of the circuit board are integrally formed via a second resin that is filled in the first through hole.

Power electronics assemblies and vehicles incorporating the same

A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips.

SEMICONDUCTOR DEVICE INCLUDING SENSE INSULATED-GATE BIPOLAR TRANSISTOR

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell. 1. A semiconductor device comprising:a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other;a first channel formed by using a gate wiring portion of the sense IGBT cell; anda first resistance portion having a first resistance value incorporated in the first channel.2. The semiconductor device according to claim 1 , whereinthe gate wiring portion of the sense IGBT cell includes a gate electrode formed in a predetermined wiring pattern which partitions the sense IGBT cell into each cell unit, andthe first resistance portion is arranged at a peripheral portion of the gate electrode.3. The semiconductor device according to claim 2 , wherein the main IGBT cell includes a striped pattern.4. The semiconductor device according to claim 3 , wherein the sense IGBT cell monitors the amount of current flow into the main IGBT cell.5. The semiconductor device according to claim 4 , wherein the sense IGBT cell is arranged in proximity to one side of the ...

Power semiconductor device

This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is formed; and a plurality of press-fit terminals each having a wire-bond portion electrically connected in the package to the electric circuit, a press-fit portion for making electrical connection with an apparatus to be connected, and a body portion whose one end portion continuous to the wire bond portion is internally fastened to the package and whose other end portion supports the press-fit portion so as to place the press-fit portion away from the package; wherein in each of the plurality of press-fit terminals, at a portion in the body portion exposed from the package, there is formed a constriction portion that is constricted from both sides in a direction perpendicular to the center line, so as to leave a portion around the center line.

SEMICONDUCTOR DEVICE

On a semiconductor substrate, coils CL and CL and pads PD, PD, and PD are formed. The coil CL and the coil CL are electrically connected in series between the pad PD and the pad PD, and the pad PD is electrically connected between the coil CL and the coil CL. The coil magnetically coupled to the coil CL is formed just below the coil CL, the coil magnetically coupled to the coil CL is formed just below the coil CL, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL and CL, directions of induction current flowing in the coils CL and CL are opposed to each other in the coils CL and CL 1. A semiconductor device comprising:a semiconductor substrate; anda first coil, a second coil, a third coil, a fourth coil, a first pad, a second pad, and a third pad formed on the semiconductor substrate through an insulation film,wherein the first coil and the third coil are electrically connected in series between the first pad and the second pad,the third pad is electrically connected between the first coil and the third coil,the second coil and the fourth coil are electrically connected in series,the first coil is arranged above the second coil,the third coil is arranged above the fourth coil,the first coil and the second coil are not connected by a conductor but are magnetically coupled to each other,the third coil and the fourth coil are not connected by a conductor but are magnetically coupled to each other, and,when a current is flowed in the second coil and the fourth coil connected in series, directions of induction currents flowing in the first coil and the third coil are opposed to each other in the first coil and the third coil.2. The semiconductor device according to claim 1 ,wherein, when a current is flowed in the second coil and the fourth coil connected in series, directions of the current flowing in the second coil and the fourth coil are opposed to each other.3. The semiconductor device according ...

SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE

A semiconductor device in an embodiment comprises a first chip in a first resin and a second resin covering the first resin. A first lead frame is in the first resin and has a first end portion extending through the second resin. A second end portion of the first lead frame terminates in the second resin. A second lead frame is spaced from the first lead frame in the first resin. The second lead frame has a first end portion in the first resin and a second end portion that terminates in the second resin. The first chip is disposed on the first end portion of the second lead frame, and a first bonding wire electrically connects the first chip to the first lead frame. 1. A semiconductor device , comprising:a first chip in a first resin;a second resin covering the first resin;a first lead frame in the first resin and having a first end portion extending through the second resin and a second end portion terminating in the second resin;a second lead frame in the first resin and spaced from the first lead frame, the second lead frame having a first end portion disposed in the first resin and a second end portion terminating in the second resin, the first chip being disposed on the first end portion of the second lead frame; anda first bonding wire electrically connecting the first chip to the first lead frame.2. The semiconductor device according to claim 1 , wherein the second end portion of the first lead frame and the second end portion of the second lead frame are on a same side of the second resin.3. The semiconductor device according to claim 1 , further comprising:a third resin on the first end portion of the second lead frame and covering the first chip and a portion of the first bonding wire, the third resin being between the first resin and the first chip.4. The semiconductor device according to claim 1 , further comprising:a third lead frame in the first resin and spaced from the first and second lead frames, the third lead frame having a first end portion of ...

SEMICONDUCTOR DEVICE

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell. 1. A semiconductor device comprising:a semiconductor layer including a main IGBT cell and a sense IGBT cell connected parallel to each other;a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value;a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion;a first diode provided between the gate wiring and the first resistance portion;a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode;an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell; anda sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.2. The semiconductor device according to claim 1 , wherein ...

MULTI-CHIP PACKAGE WITH HIGH THERMAL CONDUCTIVITY DIE ATTACH

A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device. 1. A packaged semiconductor device , comprising:a metal substrate having a first through-hole aperture and a second through-hole aperture each having an outer ring, and a plurality of metal pads around the first and the second through-hole apertures on dielectric pads;a first and a second semiconductor die that each have a back side metal (BSM) layer on its bottom side mounted top side up on a top portion of the apertures;a metal die attach layer directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures;leads that contact the plurality of metal pads, wherein the leads include a distal portion that extends beyond the metal substrate;bondwires between the plurality of metal pads and bond pads on the first and the second semiconductor die, anda mold compound providing encapsulation for the packaged semiconductor device.2. The packaged semiconductor device of claim 1 , wherein the dielectric pads comprise a polymer.3. The packaged semiconductor device of claim 1 , wherein the ...

APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels. 1. An integrated circuit device , comprising:a semiconductor substrate having formed therein a bidirectional semiconductor-controlled rectifier (SCR) having a cathode/anode (K/A) electrically connected to a first terminal (T1) and an anode/cathode (A/K) electrically connected to a second terminal (T2), wherein the bidirectional SCR comprises a first bipolar transistor, a second bipolar transistor, and a bidirectional bipolar transistor comprising a base coupled to a central region of the bidirectional SCR;a plurality of metallization levels formed outside the semiconductor substrate; anda triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR and comprising one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, wherein a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and wherein a second device terminal of the triggering ...

Microelectronic packages having cavities for receiving microelectronic elements

Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING PRODUCT

A method of manufacturing semiconductor products includes: providing a semiconductor product lead frame including a semiconductor die mounting area and an array of electrically conductive leads, molding semiconductor product package molding material, e.g., laser direct structuring material, and forming on the package molding material molded onto the lead frame electrically-conductive lines extending between the semiconductor die mounting area and the array of electrically-conductive leads. 1. A method , comprising:molding a first package molding material on a portion of a lead frame, the lead frame including a die pad and an array of electrically-conductive leads; andforming electrically-conductive lines on the first package molding material, the electrically-conductive lines extending between the die pad and the array of electrically-conductive leads, the electrically conductive lines being coupled to the electrically-conductive leads.2. The method of claim 1 , wherein molding comprises molding laser-activatable package molding material on the portion of the lead frame claim 1 , wherein forming the electrically-conductive lines includes applying laser treatment of the laser-activatable package molding material.3. The method of claim 1 , wherein forming the electrically-conductive lines comprises ink-printing electrically-conductive lines onto the first package molding material.4. The method of claim 1 , wherein molding comprises molding laser-activatable package molding material on the portion of the lead frame claim 1 , and wherein forming the electrically-conductive lines includes at least one of:forming at least one electrically-conductive metallization layer on the first package molding material;overmolding at least one dielectric layer onto the electrically-conductive lines; andforming electrically-conductive vias through the first package molding material molded onto the lead frame.5. The method of claim 1 , wherein the die pad is recessed below a surface of ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands. 1. A semiconductor package , comprising:a semiconductor die;a first stud bump coupled to the semiconductor die; anda first layer of molding compound on the semiconductor die and along side surfaces of the first stud bump, wherein the first stud bump includes a distal end at a surface of the first layer of molding compound, wherein the first layer of molding compound is a laser-activatable direct structure molding compound, wherein a first portion and a second portion of the surface of the first layer of molding compound have been laser activated to form first and second laser activated areas, respectively, wherein the first laser activated area is proximate the distal end of the stud bump;an electrically-conductive line on the second laser activated area;an electrically-conductive land on the first laser activated area; anda second layer of molding compound covering the first electrically-conductive line and along side surfaces of the electrically-conductive land.2. The semiconductor package of claim 1 , wherein the first laser activated area forms a first recess in the surface of the first layer of molding compound and the second laser activated area forms a second recess in the surface of the first layer of molding compound claim 1 , wherein the second recess has a depth that is ...

Discrete flexible interconnects for modules of integrated circuits

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

Semiconductor device

Semiconductor device and manufacturing method thereof, lead frame and manufacturing method thereof

Semiconductor device and its manufacture method, lead frame and its manufacture method

半导体装置包括引线框架、装设在引线框架上的半导体芯片、覆盖引线框架及半导体芯片的密封树脂。引线框架具有柱状的端子。端子具有第1端面、与第1端面为相反侧的第2端面、以及在第1端面与第2端面之间沿纵方向延伸的侧面。在侧面设有阶差部，形成与第2端面为相反侧且具有凹凸部的阶差面。在端子中，从第1端面朝向第2端面延伸且包括阶差面的第1部分被密封树脂覆盖，从第1部分延伸至第2端面的第2部分从密封树脂突出。

Packaging structure and manufacture method thereof

本发明公开了一种封装结构及其制造方法。该封装结构包含一第一载板、一第二载板、一引导组件及一封装体；第一载板的一第一上表面上设置至少一功率器件；第二载板设置于第一上表面上，且包含一驱动电路组件及至少一贯穿孔，其中驱动电路组件设置于第二载板的一第二上表面上，用以驱动功率器件，贯穿孔与功率器件相对应设置，当第二载板设置于第一上表面上时，贯穿孔供功率器件穿设；导引组件与第一载板及/或第二载板组接；封装体包覆第一载板、第二载板、部份导引组件，且导引组件部份外露于封装体。本发明的封装结构具备较小尺寸及较佳散热效率的优势，减少线路阻抗及寄生参数。

Measurement device

本发明提供一种测定装置，通过使金属线与传感器芯片的电极极板的接合位置明确，能够防止金属线与其他装置构成构件的干渉。该测定装置包括：对配管(11)内流动的流体的流量进行测定的传感器芯片(12、13)；从测温部(23)及加热器(33)朝芯片外侧延伸的电极极板(24、34)；与电极极板(24、34)电性接合、将从测温部(23)及加热器(33)输出的测定信号发送到传感器芯片(12、13)的外部的金属线(14)，电极极板具有从测温部(23)及加热器(33)呈直线状地延伸的直线部(24a,34a)；形成于电极极板的顶端且具有宽度比直线部(24a、34a)的宽度尺寸宽的宽度尺寸的宽幅部(24b、34b)，将宽幅部的整个表面作为金属线(14)的金属线接合容许区域。

Microwave hybrid integrated circuit

본 발명에 따른 마이크로웨이브 하이브리드 집적회로는 위상 금속화 패턴층(2)과 반도체칩(5)이 고착제(4)로 고착되는 공간인 다수의 리세스(3)를 구비한 유전체판(1)을 포함한다. 접촉패드(6)를 구비한 상기 칩(5)의 표면은 상기 유전체판(1)의 표면과 동일평면상에 위치하고 상기 칩(5)의 접촉패드(6)는 상기 위상 금속화 패턴층(2)에 전기적으로 연결된다. 상기 리세스(3)의 벽은 상기 유전체판(1)의 평면을 향해 90.1-150。 각도(α)로 경사지게 형성된다.

Semiconductor device

半导体芯片（3）的栅极电极（4）/源极电极（5）通过导电体（11a/11b）分别与栅极端子（7）/源极端子（9）连接，栅极端子（7）的与导电体（11a）的接合部分以与栅极电极（4）接近的方式被配置，源极端子（9）的与导电体（11b）的接合部分以与源极电极（5）接近的方式被配置。

A kind of high light intensity high-capacity LED device

本实用新型公开了一种高光密度高功率LED装置，包括散热基板和LED发光芯片，散热基板上表面的中心区域设有绝缘导热基板，绝缘导热基板的上表面设有LED发光芯片，绝缘导热基板的上表面还设有与LED发光芯片电连接的金属触片，散热基板上表面在中心区域的周围设有绝缘基板，绝缘基板与绝缘导热基板之间具有间隙，绝缘基板上表面设有金属线路层，金属线路层上表面设有油漆层，油漆层上设有与金属线路层电连接的电路引出位，绝缘导热基板上表面的金属触片通过电路连接线与电路引出位电连接。本实用新型的高光密度高功率LED装置既能高效散热，又能实现热电分离，从而降低了电源制作成本，提高了产品的安全性能，降低了灯具制作难度。

Semiconductor device

本发明提供一种半导体装置。在半导体基板上形成有线圈CL5、CL6以及焊盘PD5、PD6、PD7。线圈CL5与线圈CL6串联地电连接在焊盘PD5与焊盘PD6之间，在线圈CL5与线圈CL6之间电连接有焊盘PD7。在线圈CL5的正下方形成有与线圈CL5磁耦合的线圈，在线圈CL6的正下方形成有与线圈CL6磁耦合的线圈，它们串联连接。当在线圈CL5、CL6的正下方的串联连接的线圈中流过电流时，在线圈CL5、CL6中流过的感应电流的方向在线圈CL5和线圈CL6中成为相反方向。

Semiconductor package body

本发明提供一种具备搭载晶体管元件以防止故障的引线框架的半导体封装体。本发明的半导体封装体包括：引线框架，其包括用于设置第一晶体管元件和第二晶体管元件的至少一个晶体管芯片焊盘、用于设置驱动器半导体芯片的驱动器芯片焊盘、与上述驱动器半导体芯片电连接的第一驱动器引线和设置于第一驱动器引线与上述至少一个晶体管芯片焊盘之间的第二驱动器引线；芯片焊线，其电连接在上述第一晶体管元件和上述驱动器半导体芯片之间；第一晶体管焊线，其电连接在上述第一驱动器引线和上述第二晶体管元件之间；和第一绝缘体，其设置于上述第二驱动器引线上以使上述第二驱动器引线与上述第一晶体管焊线绝缘。

Semiconductor package and method of manufacturing the semiconductor package

반도체 패키지는 패키지 기판, 상기 패키지 기판 상에 배치되고 상기 패키지 기판으로부터 제1 높이를 갖는 적어도 하나의 제1 반도체 칩, 상기 패키지 기판 상에 상기 제1 반도체 칩과 이격 배치되며 상기 패키지 기판으로부터 상기 제1 높이보다 작은 제2 높이를 갖는 적어도 하나의 제2 반도체 칩, 상기 제1 및 제2 반도체 칩들을 커버하도록 상기 제1 및 제2 반도체 칩들 상에 적층되는 적어도 하나의 제3 반도체 칩, 및 상기 제2 반도체 칩과 상기 제3 반도체 칩 사이에 배치되어 상기 제3 반도체 칩을 지지하는 적어도 하나의 지지 구조물을 포함한다. The semiconductor package includes a package substrate, at least one first semiconductor chip disposed on the package substrate and having a first height from the package substrate, the first semiconductor chip on the package substrate and spaced apart from the first semiconductor chip from the package substrate. at least one second semiconductor chip having a second height less than 1 height, at least one third semiconductor chip stacked on the first and second semiconductor chips to cover the first and second semiconductor chips, and the and at least one support structure disposed between the second semiconductor chip and the third semiconductor chip to support the third semiconductor chip.

Semiconductor device and mounting structure of semiconductor device

本发明提供一种半导体器件和半导体器件的安装结构。上述半导体器件包括：半导体元件、多个端子和密封树脂。上述半导体元件具有正面和背面。上述正面和上述背面在上述半导体元件的厚度方向上彼此朝向相反侧。上述多个端子与上述半导体元件隔开间隔，且与上述正面导通。上述密封树脂具有朝向与上述正面所朝向的方向同方向的第一面。上述密封树脂覆盖上述半导体元件。各个上述多个端子具有从上述第一面露出的主面。

Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Power Microwave Hybrid Integrated Circuits

본 발명에 따른 파워 마이크로웨이브 하이브리드 집적회로에 있어서, 리세스(10)는 기판(1)의 돌출부(2) 아래의 유전체판(5)의 배면상에 형성되고, 상기 리세스(10)는 그 저부에 일정한 크기의 구멍(11)을 갖는 반면, 칩(3)과 접촉하지 않는 상기 기판(1)의 상기 돌출부(2)의 상부는 상기 리세스(10)의 저부에 전기적으로 연결되고, 상기 칩(3)의 접합 패드(4)의 일부는 상기 리세스(10)의 저부에 형성된 구멍(11)을 통해 접지되며, 상기 칩(3)과 상기 칩(3)을 지지하기 위한 구멍(8)의 벽사이의 간격은 150μm 이하이고, 상기 칩 구멍(8)과 상기 접지 구멍(11)사이의 간격은 150μm 이하이다.

Semiconductor device

一端がバイポーラデバイスに接続され、他端が導電部材に接続され、中間部がユニポーラデバイスに接続されているボンディングワイヤを含む半導体装置において、ワイヤボンディングの信頼性を向上化できる半導体装置を提供する。 パッケージ４は、ダイパッド６１と、ソース用リード６３と、第１のＭＯＳＦＥＴ１１と、第１のショットキーバリアダイオード２１と含む。第１のＭＯＳＦＥＴ１１のソース電極１１ Ｓ と第１のショットキーバリアダイオード２１のアノード電極２１ Ａ とソース用リード６３は、一端部が第１のＭＯＳＦＥＴ１１のソース電極１１ Ｓ に接合され、他端部がソース用リード６３に接合され、中間部が第１のショットキーバリアダイオード２１のアノード電極２１ Ａ に接合されたボンディングワイヤ３１によって電気的に接合されている。 Provided is a semiconductor device including a bonding wire in which one end is connected to a bipolar device, the other end is connected to a conductive member, and an intermediate portion is connected to a unipolar device, and the reliability of wire bonding can be improved. The package 4 includes a die pad 61, a source lead 63, a first MOSFET 11, and a first Schottky barrier diode 21. The source electrode 11 S of the first MOSFET 11, the anode electrode 21 A of the first Schottky barrier diode 21, and the source lead 63 have one end joined to the source electrode 11 S of the first MOSFET 11 and the other end. is joined to the source lead 63, the intermediate portion is electrically connected by a bonding wire 31 is bonded to the anode electrode 21 a of the first Schottky barrier diode 21.