ЭЛЕКТРОННЫЙ МОДУЛЬ ДЛЯ ЭЛЕКТРОННОЙ КАРТОЧКИ

Изобретение относится к электронному модулю, предназначенному, в частности, для установки в электронное устройство типа чип-карты. Технический результат - изготовление электронного модуля ограниченной высоты и реализация карточки с большей толщиной на уровне модуля при использовании его в данной карточке, что повышает механическую прочность последней. Модуль содержит подложку, по меньшей мере, одну поверхность с контактными дорожками и микросхему, закрепленную на подложке и имеющую выходные контакты, каждый из которых соединен с контактной дорожкой подложки. Модуль отличается тем, что соединения между выходными контактами и контактными дорожками образованы швами из адгезивного вязкого токопроводящего вещества, нанесенного по методу раздачи из приспособления типа шприца по рельефу между упомянутыми выходными контактами и контактными дорожками. 2 с. и 4 з.п.ф-лы, 3 ил.

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Elektronische Vorrichtung und Verfahren zu deren Fertigung

Eine elektronische Vorrichtung weist ein Leistungselement (30) auf einem ersten Substrat (10) und eine elektronische Komponente (40) auf einem zweiten Substrat (20) auf. Das erste und das zweite Substrat (10, 20) sind derart übereinander angeordnet, dass das Leistungselement (30) und die elektronische Komponente (40) zwischen dem ersten und dem zweiten Substrat (10, 20) angeordnet werden können. Ein erstes Ende eines ersten Drahtes (50) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des ersten Drahtes (50) ist mit dem ersten Substrat (10) verbunden. Ein mittlerer Abschnitt des ersten Drahtes (50) ragt in Richtung des zweiten Substrats (20). Ein erstes Ende eines zweiten Drahtes (60) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des Drahtes (60) erstreckt sich über eine Oberseite (51) des mittleren Abschnitts des ersten leitfähigen Elements (50) und ist mit dem zweiten Substrat (20) verbunden.

Dickdraht-Bondanordnung und Verfahren zum Herstellen

Die Erfindung betrifft eine Dickdraht-Bondanordnung, mit einem Substrat (2), einem Dickdraht (1) und einer Hochstrom-Dickdrahtbondverbindung, bei der ein endseitiger Bondabschnitt (4) des Dickdrahtes (1), welcher sich zum Drahtende (7) des Dickdrahtes (1) hin erstreckt, auf das Substrat (2) gebondet ist, derart, dass im Bereich des Bondabschnitts (4) ein Bondkontakt (5) zwischen dem Dickdraht (1) und dem Substrat (2) gebildet ist, wobei der Dickdraht (1) einen Verjüngungsabschnitt (6) aufweist, welcher sich an das Drahtende (7) anschließt und in welchem sich der Drahtquerschnitt zum Drahtende (7) hin verjüngt. Weiterhin betrifft die Anmeldung ein Verfahren zum Herstellen einer Dickdraht-Bondanordnung.

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

Leistungshalbleitermodul

Es wird ein Leistungshalbleitermodul offenbart. Eine Ausführungsform enthält ein Mehrschichtsubstrat mit mehreren Metallschichten und mehreren Keramikschichten, wobei die Keramikschichten zwischen den Metallschichten liegen.

Bonding of metallic leads to semiconductor elements

... 881,834. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Oct. 29, 1957 [Oct. 31, 1956], No. 14256/61. Divided out of 881,832. Class 37. A lead of gold, silver, aluminium, copper or gold-plated or tinned copper is bonded to a strip of gold or aluminium 1 mil. wide on a semi-conductor body by pressing the parts together at a temperature above 100‹ C. but below the lowest eutectic temperature of any combination of the materials in contact, and the dislocation forming and displacing temperatures of the semiconductor, and maintaining the pressure and temperature long enough to make a strong low resistance bond. In an example, 1 mil. wide strips 44, 46 of aluminium and gold respectively are first alloyed to a mesa 52 formed on a germanium or silicon block. Leads 48, 50 of gold and aluminium respectively are then pressed against the alloyed strips in a press for 5 seconds to 15 minutes under a pressure sufficient to deform the leads by from 10 to 20%. The electrodes thus formed constitute the ...

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

PROCEDURE FOR THE PRODUCTION OF A SMART CARD MODULE FOR CONTACTLESS SMART CARDS

Procedure for connecting a metal pus with a semiconductor body

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

Electrical contact structures from flexible wire

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

METHOD FOR PRODUCING AN ELECTRONIC CIRCUIT ASSEMBLY

There is disclosed herein a method for producing a wirebonded electronic circuit assembly which obviates the need for soldering aluminum-copper wirebond pads to substrate mounting pads and other copper bonding surfaces.

Procédé d'établissement d'une liaison entre un conducteur métallique et un élément semi-conducteur

Werkzeug zum permanenten Befestigen eines Drahtes an einer Fläche

Halbleiteranordnung mit einem Feldeffekttransistor

Semiconductor device

本发明提供一种半导体器件，其包括半导体芯片；形成在该半导体芯片的主表面上并且包括第一电源接合焊盘、第二电源接合焊盘和多个信号接合焊盘的多个接合焊盘；设置为围绕该半导体芯片并且包括第一电源引线和多个信号引线的多个引线；包括用于把第一电源接合焊盘与第一电源引线相连接的第一接合线、用于把第一接合焊盘与第二接合焊盘相连接的第二接合线、以及用于把多个信号接合焊盘与多个信号引线相连接的第三接合线的多个接合线；以及密封该半导体芯片、多个接合线和该多个引线中的一些引线的密封体。

Semiconductor device electrical conductor

CASE OF CHIP OF SEMICONDUCTOR HAVING A STRUCTURE COMBINEE DECONDUCTEURS LOCATE ON THE CHIP AND OF STANDARD NORMAL DRIVERS

Compact topological interconnection device - localises nodes and crossovers of complex circuit formed on single layer support with connections formed by metal strips

Semiconductor device package

HALO-HYDROCARBON POLYMER COATING

일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다. In some embodiments, the printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further includes a plurality of conductive tracks coupled to at least one surface of the substrate. The PCB further comprises a multilayer coating deposited on at least one surface of the substrate. The multilayer coating includes (i) at least a portion of a plurality of conductive tracks, and (ii) at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical element connected by solder bonding to the at least one conductive track, wherein the solder joint is soldered through the multilayer so that the solder joint is adjacent the multilayer coating.

SEMICONDUCTOR DEVICE

WIRE BONDING METHOD, SEMICONDUCTOR DEVICE WIRE BONDING CAPILLARY AND BALL BUMP FORMING METHOD

SEMICONDUCTOR DEVICE

PURPOSE: To facilitate wire bonding process and reduce costs regarding a semiconductor device comprising a structure in which a plurality of semiconductor elements are mounted. CONSTITUTION: The semiconductor device is provided with a circuit board 33 on which leads 49 are arranged and a semiconductor element 21 arranged on the other side which is bonded on an upper surface 33A of the circuit board 33 by face-down bonding, a first and a second laminated semiconductor elements 22 and 23 which are mounted on a lower surface 33B of the circuit board 33 and are connected to the circuit board 33 with wires 30 and 31. In addition, the circuit board 33 is provided with a via 60 and a first and a second trailing wirings 59 and 62 which connect the electrodes having the equal electric characteristics (equal characteristic electrodes) with one another among an electrode 21A formed on the semiconductor element 21 on the other side and electrodes 27 and 28 formed on the first and second semiconductor ...

ALUMINUM BUMP BONDING FOR FINE ALUMINUM WIRE

The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a lIadframc having leads with a nickel plating. To form the bump bond between a fine aluminum wire, such as a 2 mil diameter wire, and the lead, an aluminum bump is bonded to the nickel plating and the wire is bonded to the bump. The bump is aluminum doped with nickel and is formed from a large diameter wire, such as a 6 mil diameter wire. © KIPO & WIPO 2009 ...

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE

A semiconductor device comprising a tab (5) supporting a semiconductor chip (8), a sealing part (12) formed by encapsulating the semiconductor chip (8) with resin, tab suspension leads (4) supporting the tab (5), a plurality of leads (2) having parts to be connected and exposed in the periphery of the back of the sealing part (12), and thin parts thinner than the parts to be connected and provided in the edge area of the tab side, and each having an inner dent (2e) and an outer dent (2f) in the wire bonding face (2d) arranged in each of the parts to be connected in the inside of the sealing part (12), wires (10) connecting the pads (7) of the semiconductor chip (8) to the leads (2), wherein the thin parts of the leads (2) are covered with the resin for the sealing, the wires (10) are connected to the parts to be connected respectively at positions between the outer dents (2f) and the inner dents (2e), and the outer dents (2f) and the inner dents (2e) in the thin parts of the leads (2) serve ...

BONDING WITH A COMPLIANT MEDIUM

Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates

Low resistance package for semiconductor devices

A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

WIRE BOND INTERCONNECTION

A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement. In some embodiments the support ...

SEMICONDUCTOR MODULE WITH AT LEAST TWO SUBSTRATES

A semiconductor module includes a module package including a first substrate having a first semiconductor device and a second substrate having a second semiconductor device. A first outer conductor extends from the module package and is connected to the first substrate and a second outer conductor extends from the module package and is connected to the second substrate. A method for producing the semiconductor module includes attaching first outer conductors of a leadframe to a first substrate, where the first substrate includes a first semiconductor device that is attached to the first substrate either before or after attaching the first outer conductors, A second substrate is provided including a signal processing circuit and the second substrate is fastening to second outer conductors of the leadframe.

Wire bonding structure and method for forming same

Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 m, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

Plastic lead frames for semiconductor devices

A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging, circuit card, electronic device, and a computer system. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Substrate with multiple type connections

A novel substrate is disclosed which can mount either flip-chip solder bonded IC chips or wire bonded chips, or both chips, or a single chip having both solder bonds and wire bonds is disclosed. The substrate has an array of solder pads which will accept solder bonds. Those pads which are to be used for wire bonding have mounted thereon a trimetallic pedestal. Each pedestal has a layer of solder metal bonded to the solder pad, a top layer metal suitable for wire bonding, such as, aluminum or gold, and an intermediate layer of metal, such as nickel, which is impervious to both solder metal and the top layer metal.

Wire bonding method and wire bonding apparatus

A wire bonding apparatus includes a bonding tool having a pressing surface for pressing a wire onto a surface to be joined and a wire feeding hole being open to the pressing surface; a wire feeding means for feeding the wire to an outside of the bonding tool through the wire feeding hole; and an attracting and holding means for applying an attraction force to a wire tip end part that is protruded from the wire feeding hole, thereby to bend and hold the wire tip end part towards the pressing surface.

Method for controlling wire balls in electronic bonding

A method for forming a substantially spherical free air ball on a fine non-oxidizable wire in a computerized bonder, which has a computerized flame-off (EFO) apparatus operable to generate pulses of different heights and widths. A train of EFO current pulses is applied between electrode and wire; examples are shown in FIGS. 8 and 9 . The pulse heights are controlled to melt a predetermined volume of wire while minimizing the heat-affected zone of the wire as well as the wire necking, thus creating free air balls of small diameters and high ball/wire strength. The pulse widths are controlled to create a substantially spherical ball shape. The pulse train of various heights and widths is minimized in order to minimize the time needed for one bond and to maximize the number of bonds provided per second.

Thin tin preplated semiconductor leadframes

A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of pure tin, only Подробнее

POWER SEMICONDUCTOR DEVICE

A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Packaged semiconductor device

A semiconductor device includes: a transistor including a main terminal and a sense terminal; a main output electrode connected to the main terminal via a first wire; a sense output electrode connected to the sense terminal via a second wire; and a package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode, wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode.

Wire and solder bond forming methods

Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

Semiconductor device having a heat spreader exposed from a seal resin

A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.

Method and apparatus for implementing selected functionality on an integrated circuit device

A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond. The first bond pad can also be an internal voltage line and the second bond pad an external voltage line or the bond pads can be different internal bus within the integrated ...

BOND-PAD WITH PAD EDGE STRENGTHENING STRUCTURE

A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. A guard band structure is formed in a spaced apart relationship from the metal bond pad layer which is connected to the underlying layer by a hole-fill. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material. The guard band structure exerts a downward force against the middle dielectric layer to help keeping the middle dielectric layer in place. The guard band structure also creates a localized discontinuity in the middle dielectric layer to intercept cracks that may be formed in the middle layer ...

Semiconductor device

A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Opto-electronic assembly having an encapsulant with at least two different functional zones

A radiation emitting device of the present invention includes at least one radiation emitter, first and second electrical leads electrically coupled to the radiation emitter, and an integral encapsulant configured to encapsulate the radiation emitter and a portion of the first and second electrical leads. The encapsulant has at least a first zone and a second zone, where the second zone exhibits at least one different characteristic from the first zone. Such different characteristics may be a physical, structural, and/or compositional characteristic. Preferably, the at least one different characteristic includes at least one of the following: mechanical strength, thermal conductivity, thermal capacity, coefficient of thermal expansion, specific heat, oxygen and moisture impermeability, adhesion, and transmittance with respect to radiation emitted from the radiation emitter. The radiation emitter may be in a form of an emitter, and is preferably an LED.

BONDING OVER INTEGRATED CIRCUITS

An architecture and method of fabrication for an integrated circuit having a bond pad; at lest one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via; a combination of a bondable metal layer, a stress-absorbing metal layer, and a mechanically strengthened, electrically insulating layer; and said combination of layers separating said contact pad and said portion of said integrated circuit, and having sufficient thickness to protect said circuit from bonding impact.

Semiconductor device comprising electrode pads and leads

A semiconductor device includes a plurality of electrode pads P provided on a semiconductor element 1, leads L coupled with the electrode pads via bonding wires W and common lines 2a and 2b provided on the semiconductor element 1 that achieve electrical continuity for electrode pads that handle a common signal among the plurality of electrode pads. At least the surfaces of the common lines 2a and 2b are covered with an insulating member, i.e., a second insulating adhesive tape. With this, the loops of the bonding wires can be lowered, thereby achieving a thinner package.

Semiconductor device having a bonding wire and method for manufacturing it

A semiconductor device in which an end of an aluminium bonding wire (23) is connected to a lead electrode (25) of copper or a copper alloy in a manner such that the thickness of a reaction layer (60) is 0.2 (micron) or more. In manufacture, heat treatment is effected to bring the reaction layer (60) to the desired thickness. The semiconductor device displays excellent electrical characteristics in high temperature conditions or in high temperature high humidity conditions.

METHOD FOR PRODUCING AN ELECTRICAL CONNECTION

SEMICONDUCTOR DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF

PURPOSE: To prevent tab short-circuit, chip short-circuit or short-circuit between wires due to film damage caused by thermal deterioration of a coating film by a method wherein the coating film of a covered wire is specific heat-resistant polyurethane while an end of the covered wire is connected to an external terminal of a semiconductor chip and the other end is connected to a lead. CONSTITUTION: An insulating coating film 5B of a coating wire 5 comprises heat-resistant urethane wherein polyol component and isocyanate are reacted and a structure unit induced from terephthalic acid is contained in a molecular skeleton. An end of the covered wire 5 is connected to an external terminal 2C of a semiconductor chip 2 and the other end is connected to a lead 3. Since film damage of a coating film comprising heat-resistant polyurethane which is caused by thermal deterioration can be thus prevented, electrical short-circuit problems such as tab short-circuit, chip short-circuit and short-circuit ...

SOLID-STATE IMAGE SENSING DEVICE

PURPOSE: To reduce the deterioration of characteristics due to a plating layer, by forming a plating layer on an outer lead part, after plating-resistant coating material is formed on a clad layer on the surface of a positioning member. CONSTITUTION: After plating-resistant coating material 7B is formed on the surface of positioning parts 5B, 5C, a plating layer 11 is formed on an outer lead part 5E. The plating layer 11 is not formed on the surface of the positioning parts 5B, 5C. Therefore, the attaching of foreign matter to the light receiving surface of a solid-state image sensing element chip 3 is reduced, which foreign matter is generated by the exfoliating of a plated layer 11 formed on the surfaces of the positioning parts 5B, 5C during the forming process of the solid-state image sensing device 1. As a result, the deterioration of characteristics of the solid-state image sensing device 1 is prevented. Further manufacturing process can be reduced, by forming the plating-resistant ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To prevent meltdown of an electrode pad and enhance an allowable current value of a current pad without increase in a thickness or an area of the electrode pad of a semiconductor chip. SOLUTION: In at least one electrode pad 21s, 21d of a semiconductor chip 20, a first wire 41 is bonded on a single electrode pad 21 at a plurality of points 45. Further, a second wire 42 is bonded on the first wire 41 at a plurality of points 46 along the first wire 41. In some embodiments, a top shape of the first wire 41 on the electrode pad 21 may be processed prior to the bonding of the second wire 42. COPYRIGHT: (C)2012,JPO&INPIT ...

Halbleiteranordnung und Verfahren zur Herstellung derselben

Verbindungselement eines Halbleiterbauteils und Halbleiterbauteil mit mehreren derartigen Verbindungselementen, sowie Verfahren zu deren Herstellung

Die Erfindung betrifft ein Verbindungselement (4) eines Halbleiterbauteils (1, 2, 3) und ein Halbleiterbauteil (1, 2, 3) mit mehreren derartigen Verbindungselementen (4) sowie ein Verfahren zu deren Herstellung. Dazu weist das Verbindungselement (4) ein auf einer Verbindungsfläche (5) des Halbleiterbauteils (1, 2, 3) fixiertes Bonddrahtstück (6) auf. Dieses Bonddrahtstück (6) weist einen Durchmesser D >= 100 mum (Mikrometer) auf und ist flach auf der Verbindungsfläche (5) angeordnet. Die Stirnseiten (8, 9) des Bonddrahtstückes (6) weisen Trennspuren eines Trennstichels auf. Die Mantellinie (11) des Bonddrahtstückes (6) ist stoffschlüssig mit der Verbindungsfläche (5) verbunden. Dieses Verbindungselement (4) kann auch als Abstandshalter oder als Flipchip-Kontakt eingesetzt werden.

Halbleiterbauteil in einem Standardgehäuse und Verfahren zur Herstellung desselben

Halbleiterbauteil in einem Standardgehäuse (27), das mehrere Außenanschlüsse (1–20) in Flachleitertechnik aufweist, wobei zwischen benachbarten Außenanschlüssen (1–20) für gleiche Versorgungspotentiale oder für gleiche Signale mechanisch versteifende und die Außenanschlüsse (1–20) elektrisch verbindende Flachleiterstege (28) außerhalb des Standardgehäuses (27) angeordnet sind, wobei mehrere Flachleiterstege (28) zwischen zwei elektrisch zu verbindenden Außenanschlüssen (1–20) vorgesehen sind und wobei die Flachleiterstege (28) außerhalb des Standardgehäuses (27) beabstandet zu einem Kunststoffgehäuserand (32) zwischen benachbarten Außenanschlüssen (1–20) angeordnet sind.

Hochfrequenzsignal-Übertragungsband

VERBINDUNGSELEMENTE FÜR MIKROELEKTRONISCHE KOMPONENTEN

Leistungshalbleitermodul

Connection of a junction to an electrical conductor track on a plate

A connection of an electrical junction (13) to a conductor track (5) applied to a glass or glass ceramic plate (1) is to be resistant to temperature change and traction and conductive. For this purpose an electrically conductive connecting element (11) is ultrasonically welded to the composite consisting of the conductor track (5) and plate (1). The connecting element (11) extends to the terminal (13) which is fastened to the plate (1).

RESIN-SEALED SEMICONDUCTOR DEVICE

The semiconductor device comprises a semiconductor element 4, a lead 8, and a wire 7 electrically connecting the semiconductor element and the lead. The semiconductor element, the wire, and a portion of the lead are sealed in resin 9. Corrosion inhibitor selected from the group consisting of lead oxide, calcium hydroxide and zinc oxide is added into the sealing resin. Corrosion of the copper wire is supressed even in high temperature environments. ...

RESIN-SEALED SEMICONDUCTOR DEVICE

Bootstrapping to reduce the effect of bond pad parasitic capacitance in a MEMS microphone circuit

The effect of a parasitic capacitance between a bond pad 126 and the IC substrate is reduced by applying a bootstrapping signal from amplifier 128 to a diffusion region 402 placed under the bond pad. The effective reduction in the parasitic capacitance reduces the attenuation of signals from a capacitive sensor such as a MEMS electret microphone, which may be located on a second IC 100. Bootstrapping may be applied to the parasitic capacitance of the corresponding bond pad on the second IC (122, figures 1 and 10) by use of a similar diffusion region.

Method of manufacturing bonding wire for semiconductor device

Circuit element package having lead patterns

The invention relates to a package in which a circuit element chip (13) is accommodated within a concavity or depression (17) in a ceramic substrate (11) and is electrically connected to conductive layers (14, 15 and 16) printed on the upper surface of the substrate (11) and on the walls of the depression. The package is intended to be mounted onto a separate printed circuit board by electrically connecting the printed conductors on the ceramic substrate to the conductors on the printed circuit board. ...

ELEMENT ARRANGEMENT AND PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ARRANGEMENT

SEMICONDUCTOR ARRANGEMENT WITH A FIELD-EFFECT TRANSISTOR

Device for connecting a thin wire with a small surface range of another part

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

ELECTRONIC SUBSTRATE, ACHIEVEMENT MODULE AND MOTOR DRIVE

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Heavy-wire bond arrangement and method for producing same

The invention relates to a heavy-wire bond arrangement, having a substrate ( 2 ), a heavy wire ( 1 ) and a high-voltage heavy-wire bond connection, in which an end bond section ( 4 ) of the heavy wire ( 1 ), which extends towards the end ( 7 ) of the heavy wire ( 1 ), is bonded to the substrate ( 2 ), such that in the area of the bond section ( 4 ) a bond contact ( 5 ) between the heavy wire ( 1 ) and the substrate ( 2 ) is formed, the heavy wire ( 1 ) having a tapering section ( 6 ) which adjoins the end of the wire ( 7 ) and in which the wire cross-section tapers towards the end of the wire ( 7 ). The application additionally relates to a method for producing a heavy-wire bond arrangement.

Circuit device

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

Methods to fabricate integrated circuits by assembling components

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Impedance Controlled Electrical Interconnection Employing Meta-Materials

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation. 120.-. (canceled)21. A device comprising: the first set of layers includes a second conductor layer and a third conductor layer, wherein the second conductor layer is disposed between the first surface of the first conductor layer and the third conductor layer;', 'the second set of layers includes a fourth conductor layer and a fifth conductor layer, wherein the fourth conductor layer is disposed between the second surface of the first conductor layer and the fifth conductor layer;', 'the second conductor layer includes a first plurality of electrically independent conductors arranged to span the width of the plurality of layers and the third conductor layer extends continuously along the width of the plurality of layers; and', 'the fourth conductor layer includes a second plurality of electrically independent conductors arranged to span the width of the plurality of layers and the ...

SEMICONDUCTOR PACKAGE WITH TERMINAL PATTERN FOR INCREASED CHANNEL DENSITY

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction. 1. An apparatus , comprising:a substrate having a first surface configured to include at least one integrated circuit, and having a second surface opposite the first surface, the second surface having a plurality of terminals, the substrate having a a first, second, third, and fourth sides forming a periphery of the substrate; andat least a first set of the plurality of terminals disposed adjacent the first side of the substrate and forming a periphery of the plurality of terminals adjacent to the first side of the substrate, the first set of the plurality of terminals arranged in a pattern, the pattern comprising a first group of consecutive ones of the terminals extending in a first direction at a first angle to a longitudinal line parallel to the first side and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle with respect to the first direction and extending towards the periphery of the substrate, and a third group of consecutive ones of the of the terminals extending from the ...

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a semiconductor device; a lead frame; a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device; a wire connecting the built-in package to the semiconductor device; and a resin sealing the semiconductor device, the lead frame, the built-in package, and the wire, wherein the built-in package is directly joined to the lead frame. 1. A semiconductor package comprising:a semiconductor device;a lead frame;a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device;a wire connecting the built-in package to the semiconductor device; anda resin sealing the semiconductor device, the lead frame, the built-in package, and the wire,wherein the built-in package is directly joined to the lead frame.2. The semiconductor package according to claim 1 , wherein the built-in package has a first main surface and a second main surface that are opposed to each other claim 1 ,the first main surface is joined to the lead frame,an electrode pad connected to the insulated driver is provided on the second main surface, andthe electrode pad is connected with the semiconductor device by the wire.3. The semiconductor package according to claim 1 , wherein the wire is an Al wire.4. The semiconductor package according to claim 1 , wherein the semiconductor device includes P-side semiconductor devices of three phases claim 1 ,the insulated driver includes three high-voltage-side insulated drivers respectively driving the P-side semiconductor devices of three phases, andthe three high-voltage-side insulated drivers are integrated in the single built-in package.5. The semiconductor package according to claim 1 , wherein the semiconductor device includes P-side semiconductor devices of three phases and N-side semiconductor devices of three phases claim 1 ,the insulated driver includes three high-voltage-side insulated drivers respectively driving ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a transistor including a main terminal and a sense terminal; a main output electrode connected to the main terminal via a first wire; a sense output electrode connected to the sense terminal via a second wire; and a package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode, wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode. 1. A semiconductor device comprising:a transistor including a main terminal and a sense terminal;a main output electrode connected to the main terminal via a first wire;a sense output electrode connected to the sense terminal via a second wire; anda package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode,wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode.2. The semiconductor device according to claim 1 , further comprising:a control IC controlling the transistor and provided in the package; anda resistor provided outside the package and connected to the sense output electrode,wherein the control IC shuts off the transistor upon detecting a short circuit current from a voltage applied to the resistor.3. The semiconductor device according to claim 1 , wherein a length of the first wire is larger than a length of the second wire.4. The semiconductor device according to claim 1 , wherein the number of wires of the second wire is greater than the number of wires of the first wire.5. The semiconductor device according to claim 3 , further comprising a relay electrode provided in the package claim 3 ,wherein the first wire includes a third wire connecting the main terminal to the relay electrode, and a fourth wire connecting the relay ...

Substrate for semiconductor device and manufacturing method thereof

A substrate for a semiconductor device and a manufacturing thereof, and a semiconductor device using the same and a manufacturing method thereof are disclosed. For example, in the substrate according to the present invention, a core is eliminated, so that the substrate has a very thin thickness, as well, the length of electrically conductive patterns becomes shorter, whereby the electrical efficiency thereof is improved. Moreover, since a carrier having a stiffness of a predetermined strength is bonded on the substrate, it can prevent a warpage phenomenon during the manufacturing process of the semiconductor device. Furthermore, the carrier is removed from the substrate, whereby a solder ball fusing process or an electrical connecting process of the semiconductor die can be easily performed.

Apparatus with a multi-layer coating and method of forming the same

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

半导体器件

本发明提供一种半导体器件，其包括半导体芯片；形成在该半导体芯片的主表面上并且包括第一电源接合焊盘、第二电源接合焊盘和多个信号接合焊盘的多个接合焊盘；设置为围绕该半导体芯片并且包括第一电源引线和多个信号引线的多个引线；包括用于把第一电源接合焊盘与第一电源引线相连接的第一接合线、用于把第一接合焊盘与第二接合焊盘相连接的第二接合线、以及用于把多个信号接合焊盘与多个信号引线相连接的第三接合线的多个接合线；以及密封该半导体芯片、多个接合线和该多个引线中的一些引线的密封体。

Halogen-hydrocarbon polymer coating

FIELD: chemistry. SUBSTANCE: invention relates to polymer coatings, namely, to a halogen-hydrocarbon polymer coating for electric devices. A printed circuit board (PCB) includes a substrate, including an insulation material. The PCB additionally includes multitudes of electroconductive printing paths, connected to at least one substrate surface. The PCB additionally includes a multi-layered coating, precipitated on at least one substrate surface. The multilayered coating covers at least a part of a multitude of the electroconductive paths and includes at least one layer of the halogen-hydrocarbon polymer. The PCB additionally includes at least one electric component, connected by a solder connection to at least one electroconductive printing path, with the solder connection being soldered through the multilayered coating in such a way that the connection adjoins the multilayered coating. EFFECT: prevention of oxidation or corrosion of metal surfaces, capable of preventing the formation of strong solder connections or capable of reducing a service term of the said connections. 39 cl, 18 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H05K 1/18 H05K 3/28 H05K 3/34 C09D 4/00 C09D 185/00 C09K 15/32 (13) 2 533 162 C2 (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2011110260/07, 11.08.2009 (24) Дата начала отсчета срока действия патента: 11.08.2009 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (43) Дата публикации заявки: 20.10.2012 Бюл. № 29 (56) Список документов, цитированных в отчете о поиске: US 3931454 A, 06.01.1976. US 2004/ (85) Дата начала рассмотрения заявки PCT на национальной фазе: 18.03.2011 C 2 C 2 0026775 A1, 12.02.2004. US 4693799 A ...

Semiconductor device and the manufacturing method

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Printed board and method for production thereof

FIELD: electrical engineering.SUBSTANCE: invention relates to a halocarbon polymer coating for electrical devices. It is achieved by the fact that the printed circuit board (PCB) includes a substrate including insulating material, and additionally includes multiple electroconductive printed paths connected to at least one surface of the substrate. PP further includes a multilayer coating deposited on at least one surface of the substrate. Multilayer coating (i) covers at least part of multiple electroconductive printed paths and (ii) includes at least one layer of halocarbon polymer. PP further includes at least one electrical component, connected by soldered joint to at least one electroconductive printed path, soldered connection is soldered through multilayer coating so that soldered joint is adjacent to multilayer coating.EFFECT: technical result is protection from environmental conditions.21 cl, 16 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 685 692 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H05K 1/0353 (2019.02); H05K 3/282 (2019.02) (21) (22) Заявка: 2014121727, 28.05.2014 (24) Дата начала отсчета срока действия патента: 11.08.2009 (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) 23.04.2019 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 Номер и дата приоритета первоначальной заявки, из которой данная заявка выделена: 2011110260 18.08.2008 (56) Список документов, цитированных в отчете о поиске: US 2004/0026775 A1, 12.02.2004. US 391453 A, 06.01.1976. US 2008/0176096 A1, 24.07.2008. RU 2032286 C1, 27.03.1995. (43) Дата публикации заявки: 10.12.2015 Бюл. № 2 6 8 5 6 9 2 Приоритет(ы): (30) Конвенционный приоритет: R U Дата регистрации: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 34 C 2 R U 2 6 8 5 6 9 2 C 2 (45) Опубликовано: 23.04.2019 Бюл. № 12 Адрес для переписки: 129090, Москва, ул. Б ...

Power semiconductor device

Semiconductor device

A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

混成集積回路のリ−ド線の接続方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

반도체 장치 및 그 제조방법

베이스 기판의 주면 펠레트 탑재 영역상에 반도체 펠레트가 탑재되고, 상기 반도체 펠레트의 주면에 배치된 외부단자에 베이스 기판의 이면에 배치된 제1전극 패드가 전기적으로 접속되는 반도체 장치에 있어서, 상기 베이스 기판은 리지드 기판으로 구성하고, 상기 베이스 기판의 제1전극패드를 그의 이면에 배치된 제2전극패턴에 전기적으로 접속하며, 상기 반도체 펠레트를 그의 주면을 밑으로해서 베이스 기판의 주면 펠레트 탑재영역상에 탑재하고, 상기 반도체 펠레트의 외부단자와 베이스 기판의 제2전극패드를 베이스 기판에 형성된 슬리트를 통해서 본딩와이어로 전기적으로 접속한다.

半導体装置

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor chip stack package and related fabrication method

본 발명은 플립 칩 본딩과 와이어 본딩을 이용한 반도체 칩 적층 패키지에 관한 것으로 효율적이고 신뢰성 있는 적층 구조를 제공한다. 본 발명의 칩 적층 패키지를 구성하는 각각의 단위 패키지에 있어서, 배선 기판의 제1 표면 가장자리 부분에 형성된 와이어 본딩 패드는 제1 표면에 부착되는 집적회로 칩의 와이어 랜드와 본딩 와이어에 의하여 서로 연결된다. 또한, 배선 기판의 제2 표면 중앙 부분에 형성된 플립 칩 본딩 패드는 상부 단위 패키지의 집적회로 칩 상부면에 형성된 칩 범프와 접합된다. 단위 패키지들의 적층 구조는 제2 배선 기판 위에 적층되며, 적층 구조를 보호하기 위하여 몰딩 수지 또는 언더필 수지가 형성된다. The present invention relates to a semiconductor chip stack package using flip chip bonding and wire bonding, and provides an efficient and reliable stack structure. In each unit package constituting the chip stack package of the present invention, the wire bonding pads formed at edge portions of the first surface of the wiring board are connected to each other by wire lands and bonding wires of the integrated circuit chip attached to the first surface. . In addition, the flip chip bonding pad formed at the center portion of the second surface of the wiring board is bonded to the chip bump formed on the upper surface of the integrated circuit chip of the upper unit package. The laminated structure of the unit packages is stacked on the second wiring substrate, and a molding resin or an underfill resin is formed to protect the laminated structure. 플립 칩 본딩, 와이어 본딩, 칩 적층 패키지, 몰딩 수지, 솔더 볼 Flip chip bonding, wire bonding, chip lamination package, molding resin, solder ball

Semiconductor package

내용 없음. No content.

Bonding method of insulating wire

내용 없음. No content.

半導体チツプおよびその製造方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Wire bonding apparatus and method

Method for manufacturing resin-encapsulated semiconductor device

다이패드가 그 주면에 탑재되는 반도체 칩의 면적에 비교해서 작은 면적으로 형성되고, 상기 반도체 칩 및 다이패드가 수지밀봉체로 밀봉되는 수지밀봉형 반도체장치의 제조방법에 있어서, 상기 몰드금형의 공동내에 상기 다이패드의 이면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극이 상기 방도체 칩의 주면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극보다도 상기 다이패드의 두께에 상당하는 분만큼 좁게되도록, 상기 반도체 칩 및 다이패드를 배치하고, 센터·게이트에서 상기 공동내에 수지를 동시에 주입해서 수지밀봉체를 형성하는 것에 의해, 반도체 칩의 이면측의 충전영역에 충전된 수지에 의해서, 반도체 칩이 그 상방에 밀어 올려지지는 않는다. 이 결과, 반도체 칩, 본딩와이어 등이 수지밀봉체에서 노출하는 문제를 방지할 수 있기 때문에 수지밀봉형 반도체장치의 수율을 높일 수 있다. A method of manufacturing a resin-sealed semiconductor device in which a die pad is formed with a small area compared to the area of a semiconductor chip mounted on its main surface, and the semiconductor chip and the die pad are sealed with a resin sealing body, wherein the die mold is formed in a cavity of the mold mold. The gap from the back surface of the die pad to the inner wall surface of the cavity facing it is narrower than the gap from the main surface of the insulator chip to the inner wall surface of the cavity facing it by an amount corresponding to the thickness of the die pad. By disposing the semiconductor chip and the die pad as much as possible, and injecting the resin into the cavity at the center gate at the same time to form a resin sealing body, the resin is filled with the resin filled in the filling region on the back side of the semiconductor chip. It is not pushed upwards. As a result, since the problem which a semiconductor chip, a bonding wire, etc. expose to a resin sealing body can be prevented, the yield of a resin sealing semiconductor device can be improved.

A semiconductor device

본 발명은, 반도체장치에 관한 것으로, 반도체소자를 절연성 테이프에 접착시키는 유연한 접착부재를, 외부단자를 접합시키는 절연성 테이프 표면의 랜드를 덮는 범위까지 설치하고, 혹은 유연한 저탄성부재로 랜드를 덮음으로써, BGA형 반도체장치에 있어서 반도체장치를 프린트배선기판에 실장한 상태에서 온도변화가 반복되어질 때에 외부단자에 발생하는 단선을 방지할 수 있는 기술이 제공되며, 이로써 신뢰성 높은 반도체장치를 제공하는 기술이 제시된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, wherein a flexible adhesive member for bonding a semiconductor element to an insulating tape is provided to a range covering a land on the surface of an insulating tape for bonding external terminals, or the land is covered with a flexible low elastic member. In the BGA type semiconductor device, there is provided a technology that can prevent disconnection of external terminals when the temperature change is repeated while the semiconductor device is mounted on a printed wiring board, thereby providing a reliable semiconductor device. Presented.

Manufacturing method of semiconductor device

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Backside method for fabricating semiconductor components with conductive interconnects

A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Semiconductor components having through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Power semiconductor module

Method of mounting a spring element on a semiconductor device and testing at a wafer level

Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 DEG C, and can be completed in less than 60 minutes.

Method for producing tin-silver alloy plating film, tin-silver alloy plating film, and lead frame for electronic component provided with the same

Stacking structure of semiconductor chip and semiconductor package using it

이 발명은 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지에 관한 것으로, 도전성와이어가 상부 반도체칩의 하면에 접촉되어도 전기적으로 절연이 가능하고, 기계적으로 손상되는 것을 방지할 수 있으며, 전체적인 두께를 낮출 수 있도록, 다수의 회로패턴이 형성된 섭스트레이트와; 상기 섭스트레이트의 표면에 접착되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 제2면에 접착된 스페이서와; 대략 평면인 제1면과 제2면을 갖고, 상기 제2면에는 다수의 입출력패드가 형성되어 있으며, 상기 제1면에는 절연수단이 부착되어 상기 스페이서에 접착된 제2반도체칩과; 상기 제1반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 연결하는 제1도전성와이어와; 상기 제2반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 연결하는 제2도전성와이어를 포함하여 이루어진 것을 특징으로 한다.

Semiconductor device

Conductor substrate and semiconductor device

Semiconductor device

Apparatus for welding

PROCESS FOR JOINT WELDING OF SMALL COMPONENTS

Semiconductor device and manufacturing method thereof

Plate-shaped body and method for manufacturing semiconductor device

Method of temporarily, then permanently, connecting to a semiconductor device

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of housing components and housed component

Verfahren zum Gehäusen von Bauelementen, wobei ein Basissubstrat (100) an seiner Funktionsseite (101) eine Vielzahl von voneinander beabstandeten Funktionsbereichen (110) aufweist und mit der Funktionsseite (101) mit einem Decksubstrat (200) im Waferverbund dauerhaft derart verbunden wird, dass die Funktionsbereiche (110) jeweils gehäust werden, wobei Kontaktflächen (130) auf dem Basissubstrat (100) von einer Rückseite (102) des Basissubstrats (100), welche der Funktionsseite (101) gegenüber liegt, mittels Erzeugen von Kontaktierungsausnehmungen (301) in dem Basissubstrat (100) freigelegt werden, wobei das Basissubstrat (100) in Rumpfbereiche (104) und Anschlussbereiche (300) unterteilt wird, wobei sich die Rumpfbereiche (104) jeweils über die Funktionsbereiche (110) erstrecken und einen Teil der Gehäuse für die Funktionsbereiche (110) bilden, wobei das Basissubstrat (100) in den Rumpfbereichen (104) oder den Anschlussbereichen (300) gedünnt wird, bis es in den Rumpfbereichen (104) und den Anschlussbereichen (300) unterschiedliche Dicken aufweist und wobei der zumindest aus Basissubstrat (100) und Decksubstrat (200) gebildete... Method for housing components, wherein a base substrate (100) on its functional side (101) has a plurality of spaced-apart functional areas (110) and the functional side (101) with a cover substrate (200) in the wafer composite permanently connected such that the functional areas (110) housed respectively become, wherein contact surfaces (130) on the base substrate (100) are exposed from a back side (102) of the base substrate (100) facing the functional side (101) by creating contact recesses (301) in the base substrate (100), wherein the base substrate (100) is divided into body regions (104) and connection regions (300), wherein the body regions (104) each extend over the functional regions (110) and form part of the housing for the functional regions (110), wherein the base substrate (100) in the body regions (104) or the connection ...

Inspecting device for bonding part

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Aluminum leadframes for semiconductor devices and method of fabrication

집적 회로 칩에 사용하기 위한 리드 프레임은 아연 표면 층을 갖는 알루미늄 또는 알루미늄 합금으로 제조된 리드 프레임 기부, 알루미늄 및 아연이 조합되도록 적층된 상기 아연 층 상의 제1 니켈 층, 상기 제1 니켈 층 상의 니켈과 귀금속의 합금 층, 리드의 굽힘 및 납땜 부착에 적합하도록 적층된 상기 합금 층 상의 제2 니켈 층, 및 최외곽 귀금속 층을 포함하여, 상기 리드 프레임이 방식, 와이어 접합 및 다른 부품에 대한 납땜 부착에 적합하다. Lead frames for use in integrated circuit chips include a lead frame base made of aluminum or an aluminum alloy with a zinc surface layer, a first nickel layer on the zinc layer laminated to combine aluminum and zinc, nickel on the first nickel layer Soldering to the lead frame, wire bonds, and other components, including an alloy layer of precious metals, a second nickel layer on the alloy layer laminated to suit bending and soldering of the leads, and an outermost precious metal layer. Suitable for 반도체 장치, 리드 프레임, 와이어 접합, 알루미늄, 니켈 Semiconductor device, lead frame, wire junction, aluminum, nickel

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Mounting spring elements on semiconductor devices

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Semiconductor device and manufacturing method thereof

Hybrid integrated circuit

Method for producing a smart card module for contactless smart cards

A method for producing a smart card module includes bonding one end of a thin wire onto a first contact zone of a semiconductor chip. The wire is guided in a plurality of turns forming an antenna coil. The wire is bonded onto a second contact area of the semiconductor chip. The wire turns of the antenna coil and the semiconductor chip are placed on a carrier body.

Wire bonding to copper

본 명세서는 반도체 집적 회로에서의 구리 금속화물에 금 와이어를 접착하는 기법에 대해서 설명한다. 구리 상부에 장벽 층을 형성하고, 그 장벽 층의 상부에 알루미늄 접착 패드를 형성한다. 그 다음, 금 와이어를 알루미늄 패드에 열압축 접착한다. This specification describes a technique for bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on top of copper and an aluminum adhesive pad is formed on top of the barrier layer. The gold wires are then heat compression bonded to the aluminum pads.

Semiconductor device

Atmospheric pressure plasma surface treatment equipment

Gas discharge is caused in a predetermined discharging gas at atmospheric pressure or a pressure close to atmospheric pressure, and an organic material which is liquid at room temperature and which is previously contained in the discharging gas or applied to a surface of a treated member is dissociated or excited by a plasma caused by the gas discharge to generate activated species. By using these excited activated species, a polymerized film of organic material is formed on the surface of the treated member. By variously selecting the organic material or the kind of the discharging material and variously combining them, a water repellent film, a hydrophilic film or a film having a high hardness can easily be formed on the surface of the treated member according to use, or the polymerization speed of the organic material can be increased, or the polymerization can be limited. Further, the adhesion of an organic polymerized film essentially low can be improved with respect to a treated member formed of an inorganic material such as glass or some inactive organic material if the organic material or the kind of gas is used while being changed.

Probe card assembly and kit, and method using the same

Resilient contact structures extend from a top surface of a support substrate and solder-ball (or other suitable) contact structures are disposed on a bottom surface of the support substrate. Interconnection elements (110) are used as the resilient contact structures and are disposed atop the support substrate. Selected ones of the resilient contact structures atop the support substrate are connected, via the support substrate, to corresponding ones of the contact structures on the bottom surface of the support substrate. In an embodiment intended to receive an LGA-type semiconductor package (304), pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally normal to the top surface of the support substrate (302). In an embodiment intended to receive a BGA-type semiconductor package (404), pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally parallel to the top surface of the support substrate (402).

Wire bonding method, and capillary and ball bump forming method for semiconductor device and wire bonding

본 발명은 와이어 본딩 방법 및 반도체장치에 관한 것이며, 본딩처리의 효율화, 피접속부재에 대한 손상의 경감 및 반도체소자의 박형화를 도모하는 것을 목적으로 한다. 와이어(16)에 제1의 볼부(17)를 형성함과 동시에 이 제1의 볼부(17)를 제1의 피접속부재가 되는 이너리드부(13)에 접합하는 제1의 접합공정과, 이너리드부(13)에 대한 접합위치로부터 와이어(16)를소정의 루프로 인출함과 동시에 와이어(16)의 소정 위치에 제2의 볼부(18)를 형성하는 볼부 형성공정과, 형성된 제2의 볼부(18)를 제2의 피접속부재가 되는 반도체소자(10)의 전극패드(11)에 접합하는 제2의 접합공정을 구비한다.

METHOD FOR MANUFACTURING A SCART CARD MODULE FOR A CONTACT SMART CARD (PROCESS FOR PRODUCING A SMART CARD MODULE FOR CONTACTLESS SMART CARDS)

스마트 카드 모듈은 운반체(1)위에 배치된 안테나 코일(5)과, 결합 접촉에 의해서 운반체(1)위에 배치된 반도체 칩(3)에 연결되는 연결부(6)를 갖는다.

Semiconductor device and semiconductor module

(57)【要約】 【課題】 逆バイアス印可時のＩＧＢＴの素子破壊を効 果的に防止しうる、単一のチップ中にＩＧＢＴとダイオ ードの双方が形成された半導体装置を提供する。 【解決手段】 本発明の半導体装置は、ｐ型半導体基板 と、前記ｐ型半導体基板上に形成されたｎ型半導体層 と、前記ｎ型半導体層の表面領域に形成され、ｐ型ベー ス領域と、前記ｐ型ベース領域中に形成されたｎ型エミ ッタ領域およびゲート酸化膜を介して前記ｐ型ベース領 域上に形成されたゲート電極とを有する複数のセルと、 前記セルが形成された領域の外周囲に形成されたｐ型不 純物拡散領域と、前記ｐ型不純物拡散領域の外周囲に形 成されたｎ型不純物拡散領域とを有する二重拡散型トラ ンジスタと、前記ｐ型不純物拡散領域をアノード領域と し、前記ｎ型不純物拡散領域をカソード領域として動作 するｐｎダイオードとを有する。

Semiconductor device and manufacturing method thereof

본 발명은 전극 단자가 배열 설치된 지지 기체(基體)와, 상기 지지 기체 상에 탑재된 중간 부재와, 일부가 상기 중간 부재에 의해 지지되어, 상기 지지 기체 상에 배열 설치된 반도체 소자와, 상기 반도체 소자의 전극 단자에 대응하여, 상기 지지 기체 상 또는 상기 중간 부재 상에 배열 설치된 볼록 형상 부재를 구비하고, 상기 반도체 소자의 전극 단자와 상기 지지 기체 상의 전극 단자가 본딩 와이어(bonding wire)에 의해 접속되어 이루어지는 것을 특징으로 하는 반도체 장치를 제공하는 것을 과제로 한다. 지지 기체, 중간 부재, 반도체 소자, 전극 단자

Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication

A conductive plastic lead frame and method of manufacturing same, suitable for use in IC packaging. In a preferred embodiment the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Patent JPS6347143B2

A chip-array constructed semiconductor device comprises a plurality of semiconductor chips (1-1 to 1-4) and a mounting (5) on which the semiconductor chips are mounted. Connecting pads (2-1 to 2-6) that are common to all of the chips (1-1 to 1-4) are arranged at corresponding positions on all the chips (1-1 to 1-4) and the mounting (5) includes common conducting strips (9-1 to 9-6) commonly connected to all the chips (1-1 to 1-4). The chips (1-1 to 1-4) also include individual connecting pads (3) that are unique to the individual chips (1-1 to 1-4) and these are connected to individual conducting strips (10-1 to 10-4). The common conducting strips (9-1 to 9-6) and the individual conducting strips (10-1 to 10-4) are all formed by dividing a single conducting layer.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Power semiconductor device

【課題】外部配線の接続により主端子部に発生する不良を低減でき、歩留まりが高く生産性に優れるともに、信頼性の高いトランスファーモールド樹脂により封止された電力用半導体装置を得ることである。 【解決手段】回路基板の配線パターンに接合された電力用半導体素子と筒状外部端子連通部と、電力用半導体素子と筒状外部端子連通部との間などを電気的に接続する配線成手段とが、トランスファーモールド樹脂で封止された電力用半導体装置であって、筒状外部端子連通部が、配線パターンに対して略垂直に設置され、外部端子を挿入接続可能であり、且つ各主回路である配線パターンに複数個が２次元に配置されたものである。 【選択図】図１

Semiconductor module for power semiconductor

The module includes power semiconductor components (101,102) which are wired by a metal film (103) deposited on a substrate (106). These components form asymmetric unit arrangements contg. semiconductor components. Each unit is located on the substrate in the same direction. One unit is coupled to electrode terminals (108,110), which are coupled to coupling terminals. The electrode terminals are fitted in given spacing intervals. Pref. the asymmetric unit arrangement is of left-right and/or top-bottom asymmetric direction type.

Encapsulants for protecting MEMS devices during post-packaging release etch

The present invention relates to methods to protect a MEMS or microsensor device through one or more release or activation steps in a “package first, release later” manufacturing scheme: This method of fabrication permits wirebonds, other interconnects, packaging materials, lines, bond pads, and other structures on the die to be protected from physical, chemical, or electrical damage during the release etch(es) or other packaging steps. Metallic structures (e.g., gold, aluminum, copper) on the device are also protected from galvanic attack because they are protected from contact with HF or HCL-bearing solutions.

Power semiconductor module

본 발명은 주전류의 검출을 고주파 영역까지 정밀하게 하는 전류 검출 감지부를 구비하는 것을 목적으로 하고 있으며, 상기 목적을 달성하기 위한 구성으로는 평행 평판 형상으로 꺾어 접은 형상의 전류 감지부(28)를 이용하고, 제 1, 제 2 평판 형상 부분(28a),(28c)이 서로 대향하고 있으므로, 전류 감지부(28)의 인덕턴스가 작게 되어, 검출 단자(34),(35)로부터의 출력은 주파수 의존성이 대폭 감소한다.

Method of treating surface of wiring on circuit board

(목적) A1 본딩 와이어와의 접합성이 양호한 것에 덧붙여 용융연질 땜납 접촉성 및 땜납부착성이 양호하고 상기 땜납 부착성이 히이트사이클의 반복에 의해서도 저하되지 않는 배선기판상의 배선표면처리방법을 제공한다. (Purpose) In addition to having good bonding to A1 bonding wire, the present invention provides a wiring surface treatment method on a wiring board in which molten soft solder contactability and solder adhesion are good and the solder adhesion is not degraded even by repeated cycles of heat cycle. . (구성) 세라믹 적층기판(1)상에는 W에 의한 배선층(2)이 형성되어 있다. Ni-B합금층(10)사에는 Ag페이스트나 연질 땜납 등에 의한 납재 또는 에폭시 수지등의 접착제에 의한 접합층(5)을 거쳐서 반도체 소자(베어칩)(6)가 펠렛 본딩되어 있다. 또, ni-B합금층(10)과 반도체 소자(6)를 A1 본딩 와외어(9)에 의해서 와이어 본딩하므로서 칩 부품(8)과 반도체 소자(6)를 전기적으로 접속하고 있다. (Configuration) A wiring layer 2 made of W is formed on the ceramic laminated substrate 1. The Ni-B alloy layer 10 is pellet-bonded with a semiconductor element (bare chip) 6 via a bonding layer 5 made of a solder such as Ag paste, a soft solder, or the like, or an adhesive such as an epoxy resin. In addition, the chip component 8 and the semiconductor element 6 are electrically connected by wire-bonding the ni-B alloy layer 10 and the semiconductor element 6 with the A1 bonding vortex 9.

Semiconductor package and method for manufacturing the same

A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

Method for production of microchip card unit for contactless reading cards

FIELD: computer engineering. SUBSTANCE: method involves arranging of several turns of wire, thermal compression connection of wire terminals to first and second contact pads of semiconductor microchip, and mounting coil turns, which provide antenna coil, and semiconductor microchip on carrier. Goal of invention is achieved by using thermal compression welding unit, which is embedded directly into pointing head of turning apparatus, for thermal compression connection. Said pointing head arranges wire in several turns after connection of wire end to first contact pad of semiconductor microchip by means of thermal compression welding unit. Then, wire is connected to second contact pad of semiconductor microchip. EFFECT: simplified design, decreased cost and facilitated automation of production. 2 cl, 1 dwg (19) 13) ВИ "” 2155 379 ® С2 ОМ 6 06К 19/077, Н 05 К 3/32 РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ 6 99гс ПЧ сэ (21), (22) Заявка: 97105182109, 05.09.1995 (71) Заявитель: СИМЕНС АГ (ПЕ) (24) Дата начала действия патента: 05.09.1995 . (72) Изобретатель: Иозеф МУНДИГЛ (0Е), (30) Приоритет: 05.09.1994 ОЕ Р4431605.4 Детлеф УДО (0Е) (46) Дата публикации: 27.08.2000 (73) Патентообладатель: СИМЕНС АГ (ОЕ) < (56) Ссылки: ОЕ 3721822 СУ, 10.11.1988. ЗЦ 295217 о А, 26.03.1971. СН 669079 Аб, 15.02.1989. ЗЦ 1398111 АЛ, 23.05.1988. \МО 9309551 АЛ, 13.05.1993. с (85) Дата перевода заявки РСТ на национальную фазу: 05.04.1997 | (86) Заявка РСТ: © ОЕ 95/01201 (05.09.1995) №. (87) Публикация РСТ: о М/О 96/07984 (14.03.1996) == (98) Адрес для переписки: 129010, Москва, ул. Большая Спасская 25, с' стр.3, ООО "Городисский и Партнеры", Емельянову Е.И. — (54) СПОСОБ ИЗГОТОВЛЕНИЯ МОДУЛЯ МИКРОСХЕМНОЙ КАРТЫ ДЛЯ БЕСКОНТАКТНЫХ О’ МИКРОСХЕМНЫХ КАРТ (57) Изобретение относится к вычислительной технике. Его использование при изготовлении микросхемных карт позволяет обеспечить простой, экономичный и легко автоматизируемый процесс их ...

Power device package and method of fabricating the same

본 발명은 적층된 반도체 칩을 포함하는 전력 소자 패키지에 관한 것이다. 본 발명의 일실시예에 따른 전력 소자 패키지는, 적어도 하나 이상의 제 1 다이 어태치 영역을 포함하는 기판; 상기 다이 어태치 영역 상에 순차대로 적층되는 적어도 하나 이상의 제 1 전력 반도체 칩 및 제 2 전력 반도체 칩; 상기 제 1 전력 반도체 칩과 상기 제 2 전력 반도체 칩들 사이에 배치되는 적어도 하나 이상의 다이 어태치 패들; 및 상기 제 1 전력 반도체 칩 및 상기 제 2 전력 반도체 칩 중 적어도 하나와 전기적으로 연결되는 복수의 제 1 리드들을 포함하며, 상기 다이 어태치 패들은 상기 제 1 전력 반도체 칩의 상면에 부착되는 접착층; 상기 제 2 전력 반도체 칩의 저면이 탑재되는 제 2 다이 어태치 영역 및 상기 제 2 다이 어태치 영역과 전기적으로 연결된 와이어 본딩 영역을 포함하는 도전성 패턴; 및 상기 접착층과 상기 도전층 사이의 층간 부재를 포함한다. 스택형 전력 소자 패키지, 스마트 전력 소자, 인텔리전트 전력 소자 패키지

Semiconductor device

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Connection conductor for semiconductor package, semiconductor package, and method for assembling semiconductor package

Semiconductor device and manufacturing method thereof

본 발명에 따른 반도체 장치는 반도체 소자 (1) 위에 제공된 복수의 전극 패드, 본딩선 (W) 을 거쳐 전극 패드와 결합된 리드 (L) 및, 복수의 전극 패드간의 공통 신호를 처리하는 전극 패드의 전기적 연속성을 성취하는 반도체 소자 (1) 위에 제공된 공통선 (2a 및 2b) 을 포함한다. 적어도 공통선 (2a 및 2b) 의 표면은 절연 소자, 즉 2차 절연 접착 테이프로 덮인다. 이로써, 본딩선의 루프가 낮아질 수 있으므로, 더 얇은 패키지가 성취된다. The semiconductor device according to the present invention comprises a plurality of electrode pads provided on the semiconductor element 1, leads L bonded to the electrode pads via a bonding line W, and electrode pads for processing common signals between the plurality of electrode pads. Common lines 2a and 2b provided over the semiconductor element 1 to achieve electrical continuity. At least the surfaces of the common lines 2a and 2b are covered with insulating elements, i.e. secondary insulating adhesive tape. In this way, the loop of the bonding line can be lowered, so that a thinner package is achieved.

Lead frame

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Contactless igniting apparatus

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Wafer scale or full wafer memory system, package, method thereof and wafer processing method employed therein

To package large scale semiconductor wafers (101) a packaging device (103) is provided which engages the wafers (101) e.g. by supporting members (105A, 105B) and hence supports the wafers (101) in a spaced-apart stack. Preferably, the supporting members (105A, 105B) include means for making electrical contact between the device (103) and the wafers (101). The device (103) may be in the form of a pillar extending through holes (102) in the wafers (101). Alternatively (Fig. 1D), the device (103) may be divided into sections which are interposed between adjacent wafers (101) or (Fig. 2A) may have a plurality of pillars (201) which engage the edges of the edges of the wafers (203). Thus large scale wafers can be stacked, and electrical contact made to semiconductor devices on the wafers in the stack.

Joining a metal to semiconductors by thermo-compression

Localized encapsulation of a connection comprising bonding pads and conductors for an intelligent portable object such as a chip card

Procédé d'assemblage d'un module (23) électronique pour objet portable intelligent tel qu'une carte à puce, le module (23) comprenant un circuit (1) électronique, comprenant au moins un groupe comprenant des plots (3) de connexion et d'un support (10) pourvu de plots (13) d'interface de communication, chaque plot (3) de connexion étant connecté électriquement à un plot (13) d'interface de communication, ledit procédé comprenant les étapes suivantes : - associer physiquement le circuit (1) électronique sur le support (10); - connecter les plots (3) du circuit (1) électronique aux plots (13) d'interface de communication correspondants à l'aide d'un apport conducteur (16);- recouvrir à l'aide d'un enrobage (19) chaque ensemble (17), ledit procédé étant caractérisé en ce qu'on réalise le recouvrement de façon à laisser libre d'enrobage une partie de la face active (2).

Semiconductor device on the self type substrate and its manufacturing process.

L'invention concerne un dispositif à semiconducteur et son procédé de fabrication. Le dispositif comprend: un substrat qui possède une couche isolante (22) et une couche semiconductrice reposant sur la couche isolante, la couche semiconductrice ayant été divisée en plusieurs plages semiconductrices isolées (23) par des tranchées (24) s'étendant au travers de la couche semiconductrice jusqu'à la couche isolante; des circuits intégrés formés sur les plages respectives; et des conducteurs (28) traversant les tranchées en passant au-dessus d'elles de façon à connecter électriquement les circuits intégrés se trouvant sur les plages semiconductrices isolées.

Pyroelectric sensor and manufacturing process.

Components such as pyroelectric sensors which are particularly sensitive to piezoelectric effects and can be adversely affected as a result by any mechanical stress or vibration are described. These adverse effects may be controlled by inserting a flexible silicone sheet (42) between the chip (10) bearing the pyroelectric film and the bottom of the package (30) so that it absorbs package distorsion without passing it on to the chip. Means are provided to enable connecting leads (34) to be ultrasonically welded even though the flexible sheet is present. The chip is preferably attached to a metallized ceramic wafer (40), and abutments (44) are preferably provided at the package bottom to limit compression of the flexible sheet (42) during the welding operation.

Patent FR2345053B1

Power semiconductor device

A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

ELECTRONIC MODULE AND ITS MANUFACTURING PROCESS AND CHIP CARD INCLUDING SUCH A MODULE

The invention concerns an electronic module, in particular designed to be fixed in an electronic device in the form of a card, comprising a medium (40) including at least a surface (44) provided with contact pads (46; 48; 50) and a microcircuit (56) which is fixed on said medium (40) and which comprises exit hubs (60, 62) each connected to a medium contact pad. The invention is characterised in that the connections (66, 68) between the exit hubs and the contact pads consist of a cord made of an adhesive conductive substance matching the relief of the medium. Advantageously, the conductive substance is a conductive isotropic adhesive.