Semiconductor device package
The 1a also one embodiment of the present invention representing a device package region is larger than the size of is plane view. Also door has 1b 1a semiconductor element package in bypass circuit part including logic, analog chip indicating that is plane view. II-II 1a of the printed circuit board also also Figure 2 shows a ' line is cross-sectional area. Also Figure 3 shows a one embodiment of the present invention source device package for generating test data for testing, graphically serves of bypass circuit is indicative of the block. (Description of the sign for major part of the drawings) 10: wire 20 : wiring 50: adhesive layer 100: semiconductor device package 110: substrate 111, 111a, 111b: substrate pads 120: logic, analog chip 121, 122: logic, analog chip pad 125: bypass circuit part 130: interposer chip Bonding pad 132 131: number 1 : number 2 bonding pad Bonding pad 140 133: number 3 : number 1 memory chip 141, 141': 150 chip pad memory number 1: number 2 memory chip 151, 151': chip pad memory number 2 The present invention refers to semiconductor device package is provided to, more specifically plurality of semiconductor chips are stacked is relates to semiconductor device package. For a size reduction in electronic equipment, lightweight, one height tech it plays the lichen a thickness, of semiconductor chip in order to realize a high-density mounting, semiconductor device until now in various packaging techniques are has been developed. Required mounting to mother board, thereby forming a gas area, as well as a good package structure semiconductor device, such as pin insertion method package DIP (Dual Inline Package), SOP (Small Outline Package) such as package mounted with an the surface by lead of the outer periphery of a, such as external lattice-shaped lower package in addition BGA (Ball Grid Array) output terminal a package inside of the pipe and the header been invented, as. Furthermore, on the semiconductor chip package by reducing area ratios and wherein as a technique for realizing high-density mounting, inspecting the fine wiring substrate external O terminal for miniaturized replica of package size and [...] came wherein the shield ribs are formed. Furthermore, a plurality of semiconductor chips in a collecting, in the single package multi chip package, , among other things, multi chip package, capable of realizing, in order to realize a more density mounting a plurality of semiconductor chips in a laminate-chip stack mounting optic semiconductor device is inside of the pipe and the header package has been developed. Furthermore, , among other things, multi chip package, capable of realizing, each having different functions wiht different a plurality of semiconductor chips in a single package be provided by their hermetic sealing in the system capable of realizing reduction in thickness and the, (System In Package, SIP) and called the package which is system, development came is described. While, for a size reduction in electronic equipment, lightweight, a method as to reduce thickness of the organic, high density semiconductor chip packaging, mounting is in the spotlight method of a secondary detent profile. This, conventional, different chip that was the memory, logic, analog and such circuit mixed, the integrated of instant meeting to single, system-on-chip (System On Chip, SOC) method is using. However, memory, logic and such circuit when the integrally mounted on one chip, a it is difficult to a low voltage memory circuit, the countermeasure against noise logic circuit of the problems such as a the MLP learn.. Furthermore, concentrations of bi conventional analog circuit when mixed, memory, the same logic CMOS made is especially it is difficult. Therefore, instead of the system-on-chip, in a short time and a equivalent function, at low cost to develop a highly-enabled system architecture in the spotlight the package which is. In the case of semiconductor chip of the existing method, by flattening prepared for the package which is system chip pad without determining position and for such as designing semiconductor chip is a splitter. Therefore, such semiconductor chip a printed circuit board (Printed Circuit Board, PCB) bonded to when revealed from the concave part, the deformation of a bonding wire short-circuited or circuit of printed circuit board the was very complicated and / (routing) routing thereby. is is difficult. Furthermore, system for each semiconductor chip includes a chip in a composite structure is the package which is , with the semiconductor chip to break electrical connection of the wire bonding when embodiment, periodically are laminated in order of large semiconductor chip size. The, , superimposed thereon, semiconductor chip semiconductor chip chip pad of do not interfere with non-shared order to ensure that the. A substrate pads on printed circuit board, semiconductor chip in a lowest vertically transfer the read outside, picks up the uppermost and lowermost semiconductor chip size difference in if, upper end of the shaft is surface of the substrate on chip pad of semiconductor chip substrate pads the distance between the, having a long length of a bonding wire having incrementally-differing dimensions so that when. Ground is longer length of a bonding wire, wire strength is lowered, by weight of self wire by a wire delivery motor can be sag of the. A semiconductor chip mounted in the package which is system memory semiconductor chip with logic, containing analog semiconductor chip is carried out by using an acidulous. Memory semiconductor chip with logic, when deposited on a substrate analog semiconductor chip, logic compared to semiconductor chip memory generally, containing analog semiconductor chip of fins (pin) since the number, logic bonding wire from semiconductor chip memory, containing analog semiconductor chip from a bonding wire. immediately after a predetermined time have interdigitated with each other. This system the package which is pad, for contacting the system as well as the system in order to ensure a high quality the package which isthe package which is constituting a semiconductor chip a (direct access test) test direct access the dB stores embodiment is presented, it is necessary that. The present technical objectives of this invention a, electrically a common pin each semiconductor chip includes a chip chip pad, can be for contacting, individual semiconductor chips to facilitate testing access directly through a embodiment semiconductor device package can be by a rope. provided to. The present technical objectives of this invention are dually function as a pipeline and a or more is not limited by the which, referred to not below are constitution in yet another technique clearly to one skilled in the art from and 2000 can be understood. Said, the first and for achieving component package region is larger than the size of one embodiment of the present invention, and a substrate with the same substrate pads on one surface, the thermal deformation layer is said of one or more memory as chips, the each memory chip said each memory chip makes the common signal are applied common pin and a memory with a coupled chip an one or more memory chip and, said stacked on on a substrate, said chip pad with the memory having a connection wiring is connected, said common pin of said each memory chip via a chip pad memory said said electrically signal lines and interposer chip inter [...] , said stacked on on a substrate, said substrate pads and the connecting wiring and said electrically-breaker to close or interrupt the bypass circuit ground, including end effector including lower logic, analog chip 65. Other specific particulars in the embodiment of the description contained in constitution: drawing and. Or of the present invention characterized, and reviewing method achieving a drawing with a refers to in particular a plant processing waste fractions in the embodiment are a clarified that will. However the present invention refers to hereinafter in a disclosure in the embodiment defined in rather than different in various forms can be implemented, and, only the present in the embodiment of the present invention disclosure are to is completely, the present invention is in the field of the person with skill in the art of the invention in completely executable commands for transmitting the clock radio to inform the be provided with which, the present invention refers to claims. and the user makes a defined by category. Same reference throughout the specification a same. referring to components. Hereinafter, the present invention more specifically to describe the accompanying drawing the present invention according to embodiment thereby, the cold air flows in reference while. rapidly and to reduce a memory. The 1a also one embodiment of the present invention representing a device package region is larger than the size of and plane view, also in semiconductor element package 1a 1b door has bypass circuit part including logic, analog chip indicating that is plane view. And, the printed circuit board of II-II 1a also also Figure 2 shows a ' line is cross-sectional area. Also to 1a also as shown in 2, one embodiment of the present invention source device package (100) the, substrate (110) and base stacking, logic, analog chip (120), interposer chip (interposer chip) (130), number 1 memory chip (140), and number 2 memory chip (150) has a are sequentially formed on a high. Furthermore, substrate (110) with logic, analog chip (120) between, logic, analog chip (120) and the interposer chip (130) between, interposer chip (130) and number 1 memory chip (140) between, and number 1 memory chip (140) and number 2 memory chip (150) between the, each adhesive layer (50) is adhered. Logic, analog chip (120) and number 1 and number 2 memory chip (140, 150) a semiconductor chip: a buffer. Wherein, substrate (110) the, inorganic-a sheet such as members are formed by applying the wiring layer insulating layer can be used. Substrate (110) layer a semiconductor integrated circuit device is provided, individual semiconductor chips (120, 140, 150) common pin collection into the substrate in order to pad (111).. Substrate pads (111) has with the outside and 3 except on extraction electrodes 3a and electrically connected to the (I/O electrode) as pad electrode or more signal selectors coupled to the (not shown), in addition as pad bonding for carrying out wire bonding can be used. The substrate pad (111) has outside through an a variety of routes, analog chip (120), number 1 memory chip (140), and number 2 memory chip (150) of each common pin and is electrically connected. Substrate pads (111) the logic, analog chip pad (122) and wire (10) is bonded by means of a. In addition substrate (110) on wiring layer, number 1 and number 2 memory chip (140, 150) chip select out for at method for the manufacture of planar magnetic substrate pads (111a, 111b).. Substrate pads (111a) the number 1 memory chip (140) connected to the pins of chip select chip pad memory number 1 (141 ') and wire (10) and bonded by means of a, substrate pads (111b) the number 2 memory chip (150) connected to the pins of chip select chip pad memory number 2 (151') and wire (10) is bonded by means of a. And, substrate (110) constituting the inorganic sheet at, resin film, are formed with a non-photosensitivity; and a glass fiber substrate, ceramic and the like can be suitably used for a. Furthermore, the substrate (110) at lead frame package (lead frame package) or a ball grid array package (Ball Grid Array package) or the like can be used.. Logic, analog chip (120) is formed on one surface the wiring (not shown) and, on a common pin or more signal selectors coupled to the wiring such (not shown) and, such wiring connected independent pin (not shown) and, such wiring connected by-pass circuit part (125) and a, bypass circuit part (125) is connected one side, which is formed along an edge logic, analog chip pad (121, 122) includes. Logic, analog chip (120) wiring on the silicon substrate (circuit element) such as TFTs are functional elements of can be constructed or the like. Wherein, logic, analog chip (120) logic, is constituted of as. And, common pin pin of data constituting functional element (data pin) and/or address pin (address pin) each corresponding to, independent pin (power pin) pin power by removing a function for or. corresponding to such as (ground pin). The logic compared memory chip generally, more number of pin in chip analog since the substrate for facilitating of wire bonding in application (110) on semiconductor chips logic, analog chip (120) the preferably located at about the same that paper currency in the lowermost layer. Logic, analog chip pad (121, 122) the logic, analog chip (120) and an outer and electrically connecting as pad of electrodes 3 except on extraction electrodes 3a and, in addition as pad bonding for carrying out wire bonding can be used. Wherein, logic, analog chip pad (121, 122) the bypass circuit part (125) is electrically connected and a. The logic, analog chip pad (121) the substrate (110) of substrate pads (111) and the wire (10) and bonded by means of a, logic, analog chip pad (122) the interposer chip (130) bonding pad of (131) and the wire (10) is bonded by means of a. Logic, analog chip (120) on the logic, the tuners circuit with bypass circuit part (125) is formed. Bypass circuit part (125) the logic, analog chip (120) common pin and is electrically connected. Bypass circuit part (125) each semiconductor chip (120, 140, 150) (direct access test) test, direct access to the application is as under test when logic, analog chip (120) determine whether to the selecting. I.e., logic, analog chip (120) directly through a embodiment test access when bypass circuit part (125) the logic, analog chip pad (121) and a logic, analog chip pad (122) to break a connection between and the logic, analog chip pad (121) and a logic, analog chip (120) connected to common pin. And, number 1 memory chip (140) or number 2 memory chip (150) directly through a embodiment test access when bypass circuit part (125) the logic, analog chip pad (121) and a logic, analog chip (120) on a common pin of to break a connection between and the logic, analog chip pad (121) and a logic, analog chip pad (122) connecting to. And, individual semiconductor chips (120, 140, 150) is capable of being isolated from with a contact plug and a trench, i.e. individual semiconductor chips (120, 140, 150) common pin the same signal is applied when bypass circuit part (125) the logic, analog chip pad (121, 122) and logic, analog chip (120) both connected to common pin. Such bypass circuit part (125) with regard to test direct access and role of after a the description. Logic, analog chip (120) a low cost does not shown pin independently, logic, analog chip (120) from chip pad of substrate pads is coupled to or automatic by wire directly with, interposer chip (130) via the substrate pads may be connected to and. Logic, analog chip (120) of wire layer is formed on the logic, analog chip pad (121, 122) except for, the insulation such as SiN or poly amide it is preferable that the is the pad insulating layer. Number 1 memory chip (140) the, wiring is formed on the upper surface (not shown) and, on a common pin or more signal selectors coupled to the wiring (not shown) and, wiring connected independent pin (not shown) and, formed along upper edge of chip pad memory number 1 (141, 141') includes. Number 1 memory chip (140) wiring on the silicon substrate (circuit element) is such as TFTs are functional elements of can take the is formed on the. Wherein, number 1 memory chip (140) can be constructed to the memory circuit. And, common pin pin of data constituting functional element (data pin) and/or address pin (address pin) each corresponding to, independent pin function by removing a power pin (power pin), for (ground pin) or. corresponding to such as chip select pin (chip select pin). Number 1 memory chip pad (141, 141') the number 1 memory chip (140) and an outer and electrically connecting as pad of electrodes 3 except on extraction electrodes 3a and, in addition as pad bonding for carrying out wire bonding can be used. The chip pad memory number 1 (141) the number 1 memory chip (140) and is electrically connected with common pin, interposer chip (130) bonding pad of (133) and wire (10) to Cl radical by using hydrogen-compound bonded. Furthermore, chip pad memory number 1 (141') the number 1 memory chip (140) of chip select pin and is electrically connected with, substrate (110) of substrate pads (111a) are connected is electrically connected to the bump. Also the present 2 and 1a in embodiment number 1 memory chip pad (141 ') is substrate pads (111a) as well as directly wire (10) can be suitably used for bonded by means of a on which the present invention refers to but not limited to, chip pad memory number 1 (141') the interposer chip (130) and the connecting wiring via the substrate pads (111a) is electrically connected to the bump may be connected to. And, chip select pin does not shown pin independent except a low cost, as well as chip select pin number 1 memory chip (140) chip pad of automatic by wire of directly bonding pad and substrate from a non-processing position, interposer chip (130) and the connecting wiring via the electrically substrate pads may be connected to. Number 1 memory chip (140) of wire layer is formed on the chip pad memory number 1 (141, 141') except for, the insulation such as SiN or poly amide it is preferable that the is the pad insulating layer. Number 2 memory chip (150) the number 1 memory chip (140) as well as, wiring is formed on the upper surface (not shown) and, on a common pin or more signal selectors coupled to the wiring (not shown) and, wiring connected independent pin (not shown) and, formed along upper edge of chip pad memory number 2 (151, 151') includes. Number 2 memory chip (150) wiring on the silicon substrate (circuit element) is such as TFTs are functional elements of can take the is formed on the. Wherein, number 2 memory chip (150) can be constructed to the memory circuit. And, common pin pin of data constituting functional element (data pin) and/or address pin (address pin) each corresponding to, independent pin function by removing a power pin (power pin), for (ground pin) or. corresponding to such as chip select pin (chip select pin). Number 2 memory chip pad (151, 151') the number 2 memory chip (150) and an outer and electrically connecting as pad of electrodes 3 except on extraction electrodes 3a and, in addition as pad bonding for carrying out wire bonding can be used. The chip pad memory number 2 (151) the number 2 memory chip (150) and is electrically connected with common pin, interposer chip (130) bonding pad of (132) and wire (10) is bonded by means of a. Furthermore, chip pad memory number 2 (151') the number 2 memory chip (150) of chip select pin and is electrically connected with, substrate (110) of substrate pads (111b) are connected is electrically connected to the bump. Also the present 2 and 1a in embodiment number 2 memory chip pad (151 ') is substrate pads (111b) as well as directly wire (10) can be suitably used for bonded by means of a on which the present invention refers to but not limited to, chip pad memory number 2 (151') the interposer chip (130) and the connecting wiring via the substrate pads (111b) is electrically connected to the bump may be connected to. And, chip select pin does not shown pin independent except a low cost, as well as chip select pin number 2 memory chip (150) chip pad of automatic by wire of directly bonding pad and substrate from a non-processing position, interposer chip (130) and the connecting wiring via the electrically substrate pads may be connected to. Number 2 memory chip (150) of wire layer is formed on the chip pad memory number 2 (151, 151') except for, the insulation such as SiN or poly amide it is preferable that the is the pad insulating layer. Interposer chip (130) the, a dummy wafer can be formed as semiconductor chip. Wherein, dummy semiconductor chip acids to epoxygenated fatty acids therein, function element is not formed is circulation promoted. is. Furthermore, interposer chip (130) the portion located by the second (Flexible Printed Circuit board, FPC) or printed circuit board (Printed Circuit Board, PCB) can be constructed in. Interposer chip (130) directly on one face an oil single or multilayered a connection wiring is formed. Such connection line, external pattern to be electrically connected to the number 1 bonding pad (131), number 2 bonding pad (132), number 3 bonding pad (133) and wiring (20) includes. Number 1 bonding pad (131) the logic, analog chip (120) of logic, analog chip pad (122) and wire (10) is bonded by means of a. Number 2 bonding pad (132) the number 2 memory chip (150) of chip pad memory number 2 (151) and wire (10) is bonded by means of a. Number 3 bonding pad (133) the number 1 memory chip (140) of chip pad memory number 1 (141) and wire (10) is bonded by means of a. In one in the embodiment of the present invention, substrate (110) on logic, analog chip (120), interposer chip (130), number 1 memory chip (140) and number 2 memory chip (150) fiber layer is formed are sequentially, number 1 bonding pad (131) the logic, analog chip (120) is disposed are formed in the front surface, number 2 and number 3 bonding pad (132, 133) the number 1 bonding pad (131) than memory chip number 1 (140) are formed in the front surface preferably is disposed in the. Wiring (20) the number 1 bonding pad (131), number 2 bonding pad (132), number 3 bonding pad (133). electrically connects the. Therefore, number 1 memory chip (140) common pin chip pad memory number 1 (141), number 3 bonding pad (133) and wiring (20) via the bonding pad number 1 (131) is electrically connected and a, number 2 memory chip (150) common pin chip pad memory number 2 (151), number 2 bonding pad (132) and wiring (20) via the bonding pad number 1 (131) are connected is electrically connected to the bump. Therefore, number 1 and number 2 memory chip (140, 150) common pin interposer chip (130) and the connecting wiring to collection and, interposer chip (130) and the connecting wiring logic, analog chip (120) bypass circuit part (125) is connected, bypass circuit part (125) the substrate (110) of substrate pads (111) and a are connected. In conventional multilayer-stacked semiconductor device package, of the respective semiconductor chips of data pins or address pin be and the wire bonding substrate separately, is the semiconductor chip, a pin or address pin by the number of wire and the substrate and thereby requires pad. Therefore, wire of buffers or sag is the wire, a large number of wire since the deformation of a wire or poly-aluminum exchange for aluminum a large space for pad for pad of the package required, difficult to for contacting can be performed with ease. One embodiment of the present invention source device package (100) according to, each memory chip (140, 150) common to a common signal is applied interposer chip pin (130) electrically is agglomerated in a and the logic, analog chip (120) common pin and the interposer chip (130) the bypass circuit part (125) after collection to bypass circuit part (125) and the substrate (110) by electrically connecting the, of a wire can decrease the number of. In addition each memory chip (140, 150) the interposer chip (130) via the substrate (110) in electrical connection with a chip (10) is longer length of can be and prevent it from. Furthermore, individual semiconductor chips (120, 140, 150) common pin adaptor the substrate (110) and the substrate pad concatenated with (111) completely debunked number of second package of a permanent magnet of a rotator, can be for contacting. Interposer chip (130) and the connecting wiring the configuration of the are not limited to standardize the, for example wiring (20) can wire bonding directly to when the signal lines al less the need for trying a bonding pads. Furthermore, the and the connecting wiring only bonding pad, one the plurality of bonding bonds wires may be. Number 1 bonding pad (131) the interposer chip (130) is disposed along outer periphery of valve. Furthermore, number 2 and number 3 bonding pad (132, 133) the number 1 bonding pad (131), on the internal side of number 1 memory chip (140) is disposed along outer periphery of valve. Furthermore, wiring (20) number 1 to respect to one another does not intersect a bonding pad (131) and a number 2 and number 3 bonding pad (132, 133) main valve 23 and connected to. Furthermore, number 1 and the connecting wiring the surface of the bonding pad (131), number 2 bonding pad (132) and number 3 bonding pad (133) to the exclusion of. it is desirable that sealed insulating film. Prior invention as described above wherein, interposer chip (130) the wafer, flexible printed circuit board or printed circuit board can be used in. In particular, interposer chip (130) the logic, analog chip (120) or memory chip (140, 150) is formed is used when it is a wafer process of the of and structure made is formed long by an extrusion forming. Furthermore, logic, analog chip (120) or memory chip (140, 150) equal to wiring material layer is formed to a process device, interposer chip (130) number 1 on bonding pad (131), number 2 bonding pad (132), number 3 bonding pad (133) and wiring (20) capable of forming a.. Therefore, interposer chip (130) the formation of logic, analog chip (120) or memory chip (140, 150) with the formation of or production material similar to that of a device, as it is hereby possible to using, interposer chip (130) in the formation of a manufacturing cost and manufacturing time for suppressing the increase occurring in the degree of compression it is possible to. Furthermore, a contact plug connected to wafer a, wiring pitch minimum m hereinafter a micro 1, interposer chip (130) and the connecting wiring of fine wire pitch also 1 micro m hereinafter. is to provide. A bonding wire used for one embodiment of the present invention (10) include gold, gold alloy, wherein aluminum or an aluminum alloy is may be used in, capillary bonding (ball bonding or capillary bonding) or wedge bonding (wedge bonding) such as tool (tool) can be bonded using a. Hereinafter, one embodiment of the present invention source relates to test chip in chip units. Commonly first semiconductor chip (120, 140, 150) between each common pin of the same signal is determined, bypass circuit part (125) the logic, analog chip pad (121, 122) and logic, analog chip (120) both connected to common pin. Therefore, logic, analog chip (120) on a common pin of, number 1 memory chip (140) on a common pin and of number 2 memory chip (150) common pin the bypass circuit part (125) via a substrate (110) of substrate pads (111) and a both are connected between a gate, the same substrate pad (111) increasing the semiconductor chip (120, 140, 150) the same pin common can apply common signal. And, individual semiconductor chips (120, 140) to test characteristics of, direct access test (direct access test) that is capable of using optical. Prior invention as described above wherein, priority logic, analog chip (120) directly through a test access when embodiment, bypass circuit part (125) the logic, analog chip pad (121) and a logic, analog chip pad (122) to break a connection between and the logic, analog chip pad (121) and a logic, analog chip (120) connected to common pin. Therefore, substrate pads (111) the logic, analog chip (120) common pin only are connected between a gate logic, analog chip (120) only for direct access can be to perform a test. And, number 1 memory chip (140) directly through a test access when embodiment, bypass circuit part (125) the logic, analog chip pad (121) and a logic, analog chip (120) on a common pin of to break a connection between and the logic, analog chip pad (121) and a logic, analog chip pad (122) connecting to. And, substrate pads (111b) through the chip pad memory number 2 (151') which is coupled to a chip select pin number 2 (high impedance) by applying a high impedance memory chip (150) to a floating (floating). Furthermore, substrate pads (111) a test signal to memory chip application number 1 (140) only for direct access can be to perform a test. Similarly, memory chip number 2 (150) directly through a test access when embodiment, bypass circuit part (125) the logic, analog chip pad (121) and a logic, analog chip (120) on a common pin of to break a connection between and the logic, analog chip pad (121) and a logic, analog chip pad (122) connecting to. And, substrate pads (111a) through the chip pad memory number 1 (141') which is coupled to a chip select pin (high impedance) by applying a high impedance number 1 memory chip (140) to a floating (floating). Furthermore, substrate pads (111) a test signal to memory chip application number 2 (150) direct access only for can be to perform a test. Also Figure 3 shows a one embodiment of the present invention source device package for generating test data for testing, graphically serves of bypass circuit is indicative of the block. Also as shown in 3, bypass circuit part (125) the substrate, memory chip and logic, analog constitution: connected to. Memory chip and logic, analog chip common to signal the substrate when and the memory chip and logic, analog chip the bypass circuit part (125) is connected to each other via a. And, direct access test high dielectronic chip when embodiment, logic, analog chip the bypass circuit part (125) can be blocked by a pre-the substrate and the memory chips and are connected. And, logic, analog chip direct access test when embodiment, memory chip the bypass circuit part (125) can be blocked by a pre-the substrate and the logic, analog chip are connected. As such, one embodiment of the present invention source device package (100) each memory chip (140, 150) common pin interposer chip (130) and the connecting wiring to interposer chip and uniformization (130) of connection wiring logic, analog chip (120) bypass circuit part (125) via a substrate pads (111) is characterized by connecting a by, package of a permanent magnet of a rotator, for contacting has LED to the. As well as is, semiconductor device package of the present invention (100) one side of, semiconductor chip (120, 140, 150) of high quality time direct access test (direct access test) for testing and being expansible and free from coverage of at, existing one semiconductor chip a semiconductor device constructed with a cell package, direct access to the application is used as is to test program individually individual semiconductor chips test the thermal it is unnecessary furnished with equipment can be a vacuum deposition method or a. Furthermore, one embodiment of the present invention source device package (100) in structure of, the logic semiconductor chip, when the chip analog, burn-in test a high voltage semiconductor chip (burn-in test) to enhance stability tolerant leading electrode (tolerant I/O electrode), use can be made of,. Or more with an reference to drawing but described thereby, the cold air flows of the present invention embodiment, the present invention is in the field of the present invention a person with skill in the art in the technical idea or essentially without changing the features form the embodiment can be database for each consumer 2000. Therefore in the embodiment described or more exemplary on all sides are defined and there has the main. must understood. As described above the present invention according to the source semiconductor device, each semiconductor chip includes a chip overcoming electrically a common pin, pad, can be for contacting, provided additional equipment without the need, direct access to the application is individual semiconductor chips test.. Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad. A substrate with the same substrate pads on one surface; The thermal deformation layer is said of one or more memory as chips, the each memory chip said each memory chip makes the common signal are applied common pin and a memory with a coupled an chip of one or more memory chip; Said stacked on on a substrate, said chip pad with the memory having a connection wiring is connected, said common pin of said each memory chip said memory chip pad via a inter [...] electrically signal lines said interposer chip; and Said stacked on on a substrate, said substrate pads and the connecting wiring and said electrically-breaker to close or interrupt the bypass circuit ground, including end effector including lower logic, including analog chip semiconductor device package. According to Claim 1, Said each memory chip (direct access test) test direct access the chip select pin for semiconductor device package. According to Claim 2, Said chip select pin is electrically connected to said semiconductor device package. According to Claim 2, of one or more memory chip said direct access to reduce test cost and engineering, Said non-under test of memory chip by chip select said high impedance semiconductor device package is applied. According to Claim 1, The and the connecting wiring said memory chip and each said automatic by wire bonded semiconductor device package. According to Claim 1, Said logic, analog chip for wire bonding and substrate pads said number 1 logic, analog chip pad with the, and the connecting wiring and the wire bonding for said number 2 logic, analog chip pad with the, said number 1 and number 2 logic, analog chip pad with the connected said bypass circuit includes, The bypass circuit said said logic, analog chip common pin or more signal selectors coupled to the semiconductor device package. According to Claim 1, said logic, analog chip direct access to reduce test cost and engineering, the substrate pads and said bypass circuit and the connecting wiring connection is open and provides a path through said said logic, analog chip common pin and said semiconductor device package connecting the substrate pads. According to Claim 1, said memory chip direct access to reduce test cost and engineering, the said bypass circuit and the connecting wiring is connected to the substrate pads and said said logic, analog chip common pin and said substrate pads of semiconductor device package representing the connection. According to Claim 1, The wafer interposer chip said, flexible printed circuit board or printing circuit borad semiconductor device package is formed using a. According to Claim 1, The and the connecting wiring said said logic, analog chip and the wire bonding for the bonding pads with number 1, each memory chip and one or more said number 2 for wire bonding the bonding pads with, said number 2 the bonding pads with said number 1 and a wire connecting the bonding pads including semiconductor device package. According to Claim 1, Said semiconductor component package said substrate, said logic, analog chip, said interposer chip and said comprising, laminated in order of memory chip semiconductor device package. According to Claim 1, Said common pin or address pin of data pins a sound absorbing member is partly semiconductor device package. According to Claim 1, Said of an EEPROM memory chip or said logic, analog chip common pin to connect an independent pin automatic by wire directly with said substrate pads a non-processing position, said of said interposer chip via connection wiring is electrically connected to substrate pads said semiconductor device package. According to Claim 13, Said independent pin power pin, a chip select or ground pin semiconductor device package.