Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist:ein Cu-Legierungskernmaterial; undeine auf einer Oberfläche des Cu-Legierungskernmaterials gebildete Pd-Überzugschicht, wobeibei Messung von Kristallorientierungen auf einem Querschnitt des Kernmaterials in senkrechter Richtung zu einer Drahtachse des Bonddrahts eine Kristallorientierung <100> im Winkel von höchstens 15 Grad zu einer Drahtachsenrichtung einen Anteil von mindestens 30 % unter Kristallorientierungen in Drahtachsenrichtung hat,eine mittlere Kristallkorngröße im Querschnitt des Kernmaterials in senkrechter Richtung zur Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,5 µm oder weniger beträgt, undder Bonddraht ein oder mehrere Elemente enthält, die aus Ga und Ge ausgewählt sind, und eine Konzentration der Elemente insgesamt 0,011 bis 1,5 Masse-% relativ zum gesamten Draht beträgt.

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

Die-Struktur, Die-Anordnung und Verfahren zum Prozessieren eines Dies

Eine Die-Struktur weist einen Die und eine Metallisierungsschicht, die auf oder über der Vorderseite des Dies angeordnet ist, auf. Die Metallisierungsschicht weist Kupfer auf. Zumindest ein Teil der Metallisierungsschicht weist ein raues Oberflächenprofil auf. Der Teil mit dem rauen Oberflächenprofil weist einen Drahtbondbereich auf, an den eine Drahtbondstruktur gebondet werden soll.

Leistungstransistor und Leistungshalbleiterbauteil

Die Erfindung betrifft einen Leistungstransistor und ein Leistungshalbleiterbauteil. Der vertikal leitende Leistungstransistor weist an seiner Vorderseite (11) eine Sourcezone (14) und einen Steuereingang (16) auf. Eine Durchführung für den Steuereingang weist eine Elektrode auf der Vorderseite (11) und eine Elektrode auf der Rückseite (12) auf, sodass der Steuereingang sowohl von der Vorderseite (11) als auch von der Rückseite (12) kontaktiert werden kann.

Verfahren zur Herstellung einer Chipkarte

Verfahren zur Herstellung einer Chipkarte, umfassend ein Chipmodul (3) mit mindestens einer Kontaktierungsfläche (4.1, 4.2), wobei das Chipmodul (3) in eine Aufnahmeposition (6) eines Substrats (1) einsetzbar ist, wobei für zumindest eine der Kontaktierungsflächen (4.1, 4.2) aus einem mittels einer Drahtführungseinheit zugeführten Drahtleiter (5) jeweils eine Kontaktierungsöse gebildet wird, indem ein erster Abschnitt (7) des Drahtleiters (5) auf einer Oberfläche des Substrats (1) außerhalb der Aufnahmeposition (6) angeheftet wird, wobei ein dem ersten Abschnitt (7) benachbarter zweiter Abschnitt (8) des Drahtleiters (5) so geführt wird, dass er zusammen mit der Oberfläche und aus dieser herausragend die Kontaktierungsöse bildet, wobei ein sich anschließender dritter Abschnitt (9) des Drahtleiters (5) auf der Oberfläche außerhalb der Aufnahmeposition (6) angeheftet wird, wobei das Chipmodul (3) in die Aufnahmeposition (6) eingesetzt wird und wobei der zweite Abschnitt (8) zur Kontaktierungsfläche ...

Mehrfach-Bonddrahtverbund und simultanes Bonden

Verbund, enthaltend eine Isolierung und einen Bonddraht, dadurch gekennzeichnet, dass die Isolierung eine den Bonddraht teilweise einbettende Rinne aufweist, so dass eine Seite des Verbunds aus Isolation besteht und eine Seite des Verbunds eine freiliegende Bonddrahtoberfläche aufweist.

Improved qfn package

METHOD OF TERMINATING A LAMP FILAMENT

... 1,222,905. Welding by pressure. CHICAGO MINIATURE LAMP WORKS. 25 Sept., 1969 [4 Oct., 1968], No. 47285/69. Heading B3R. [Also in Division H1] A method of securing a tungsten lamp filament 10 to a metal lead-in wire 12 comprises the following steps:- (1) Coating the end of the lead-in wire with gold; (2) Placing the filament across the coated end of the lead-in wire; (3) Placing a body 14 of gold on the filament and over the coated end of the lead-in wire; (4) Heating the body to a temperature below the melting point of gold but above the point at which diffusion of gold begins; and (5) Applying pressure to the body to cause the gold to surround the filament and form a diffusion bond with the coating on the lead-in wire. The body 14 is preferably formed as a ball 6-8 mils in diameter on the end of a 1À5 mil diameter wire 16, and the pressure is applied by a member 18 having a 2 mil diameter bore through which the wire passes. The lead-in wire 12 may be made of copper or dumet, and the temperature ...

Substrate for interconnecting electronic integrated circuit components, which is provided with a repair arrangement

An interconnecting substrate according to the invention comprises an insulating base on which rests a set of alternating, superimposed conductive and insulating layers. Contacts are formed on the uppermost insulating layer which border at least one site or zone intended for an integrated circuit chip device whose output conductors are to be connected to the said contacts. Through-connections enable the contacts to be coupled to one of the inner conductive layers. The through-connections include at least one through-connection on the inside of the site relative to at least a predetermined one of the said contacts. A shunt conductor means connected to the predetermined contact has a part outside the site which is connected to an additional contact which serves as a substitute or replaces the said predetermined contact for the connection to the associated output conductor of the chip device. The repair arrangement according to the invention allows one to substitute for a connection inside ...

Production method of semiconductor devices

... 1,070,303. Semi-conductor devices. HITACHI Ltd. Dec. 9, 1965 [Dec. 17, 1964]. No. 52349/65. Heading H1K. Metal is deposited from the vapour phase through a photo-sensitive resist mask on to a semi-conductor in two stages, the second stage at a lower temperature than the first. To bond a deposited metal to a semi-conductor the temperature of deposition must be in the neighbourhood of the metal-semi-conductor eutectic. But to prevent contamination of the surface of the deposited metal by carbonized resist, deposition should occur at a temperature below that at which the resist volatilizes or carbonizes. These considerations define the temperatures of the two stages, which for deposition of aluminium on silicone are 550‹ and 200‹ C. respectively for periods sufficient to deposit 0.2 to 1.0Á in the first stage and up to 0.2Á in the second. The clean deposit of the second stage provides for ready attachment of wire terminals, e.g. of aluminium or gold, which may be attached to it by thermocompression ...

PROCEDURE FOR THE WIRE BONDING OF A MICROELECTRONIC SEMICONDUCTOR CHIP

PROCEDURE FOR FASTENING THE VERBINDUNGSDRAHTE ELECTRICAL MICRO CONSTRUCTION UNITS

PROCEDURE FOR ATTACHING A DUENNEN ELECTRICAL OF LEADING WIRE AT ELECTRONIC CONSTRUCTION UNITS, IN PARTICULAR SEMICONDUCTOR COMPONENTS.

Procedure for connecting a metal pus with a semiconductor body

Procedure for the connection of a metallic leader with a semiconductor body

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

L'invention se rapporte à un substrat d'interconnexion, du type comprenant un support isolant sur lequel repose un ensemble de couches conductrices et isolantes alternées et superposées; des plots formés sur la couche isolante supérieure et bordant au moins un domaine destiné à un composant dont les conducteurs de sortie sont à connecter auxdits plots; et des traversées permettant le couplage des plots, par l'intermédiaire de la couche conductrice supérieure, à l'une des couches conductrices intérieures et comprenant au moins une traversée intérieure au domaine relative à au moins un plot donné desdits plots, ledit substrat étant caractérisé en ce qu'il comporte un dispositif de réparation comprenant un moyen conducteur de dérivation relié audit plot donne et présentant une partie extérieure au domaine connectée à un plot additionnel se substituant audit plot donné pour la connexion audit composant.

FLAT PACKAGE FOR INTEGRATED CIRCUITS

L'invention se rapporte à un boîtier plat pour au moins un dispositif à circuits intégrés pourvu de plots de sortie, du type comprenant un élément de support dudit dispositif, une pluralité de bornes de sortie extérieures au boîtier, un réseau de conducteurs reliant lesdites bornes de sortie auxdits plots de sortie du dispositif, et des éléments de renforcement, caractérisé en ce que: ledit élément de support est une plaquette et lesdites bornes de sortie du boîtier sont des plages de contact disposées sur cette plaquette, au moins les conducteurs dudit réseau qui sont rattachés auxdites plages de contact reposent sur ladite plaquette de support; et ledit moyen de protection comprend un enrobage électriquement isolant, enrobant partiellement la plaquette de support et laissant dégagées au moins lesdites plages de contact.

UHF BAND SEMICONDUCTOR PACKAGE

LSI CHIP PACKAGE AND METHOD

Werkzeug zum permanenten Befestigen eines Drahtes an einer Fläche

Verfahren zum Herstellen einer in einem Schutzgehäuse untergebrachten, mindestens zwei nebeneinander einlegierte Metallelektroden aufweisenden Halbleiterkristallanordnung

Outil pour fixer un fil conducteur d'électricité à la surface d'un semi-conducteur

Träger mit mindestens einer Mikroschaltanordnung und Verfahren zu seiner Herstellung

In ein Gehäuse eingebaute Halbleiteranordnung

Halbleiterbauelement mit einer Hülle, zwei Anschlüsse aufweist

FLAT HOUSING CONTAINING AN INTEGRATED CIRCUIT DEVICE.

SUBSTRATE COMPONENT INTERCONNECT INTEGRATED CIRCUIT ELECTRONIC.

Bond tool with improved surface finish.

Ein Bondwerkzeug enthält einen Körperabschnitt, der an einem Spitzenabschnitt endet. Der Spitzenabschnitt ist aus einem Material gebildet, wobei eine Kornstruktur des Materials über mindestens einen Abschnitt des Spitzenabschnitts hinweg frei liegt.

Method for manufacturing semiconductor device

Wire bonding method and apparatus

Semiconductor power device having a stacked discrete inductor structure

A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.

Manufacturing method for physical quantity sensor using lead frame and bonding device therefor

The structure of the die, the die arrangement and processing die method

Semiconductor package having marking layer

The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 [mu]m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131 ...

Assembly of transistor

A method of manufacturing a semiconductor device

STRUCTURE DE MONTAGE POUR CIRCUITS INTEGRES RAPIDES

L'INVENTION CONCERNE LA TECHNOLOGIE DES CIRCUITS INTEGRES. UNE STRUCTURE DE MONTAGE POUR UN CIRCUIT INTEGRE COMPREND NOTAMMENT UN SUBSTRAT SEMI-CONDUCTEUR 34 SUR LEQUEL EST MONTE UN CIRCUIT INTEGRE 28. DANS CE SUBSTRAT SONT FORMES DES LIGNES DE TRANSMISSION A IMPEDANCE DEFINIE 20, 36, 42, DES LIGNES D'ALIMENTATION ET DE MASSE ET DES COMPOSANTS ELECTRONIQUES 14, 16, 26 CONNECTES AU CIRCUIT INTEGRE. CETTE STRUCTURE DE MONTAGE EVITE LA DEGRADATION DES CARACTERISTIQUES DE VITESSE DU CIRCUIT INTEGRE 28. APPLICATION AUX CIRCUITS INTEGRES A L'ARSENIURE DE GALLIUM.

SUBSTRAT D'INTERCONNEXION DE COMPOSANTS ELECTRONIQUES A CIRCUITS INTEGRES, MUNI D'UN DISPOSITIF DE REPARATION

L'invention concerne un substrat d'interconnexion 10 pourvu d'un ensemble de couches conductrices 19a-C et isolantes 20a, b alternées et superposées; des plots formés sur la couche isolante supérieure 20a et bordant au moins un domaine 13 destiné à un composant 11 dont les conducteurs de sortie 12 sont à connecter aux plots 14; et des traversées 21 comprenant au moins une traversée intérieure au domaine 13. L'invention présente un dispositif de réparation comprenant un moyen conducteur de dérivation 28a, b, 26a, b relié au plot 14 connecté à la traversée intérieure 21 et présentant au moins une plage de connexion auxiliaire 30 extérieure au domaine 13. L'invention permet de réparer le substrat sans avoir à enlever le composant il et s'applique à tout substrat porteur de pastilles de circuits intégrés.

LSI circuit chip package with carrier and underlying substrate

La présente invention concerne un ensemble à dispositif électronique comprenant une puce à circuit intégré à grande échelle (LSI) ayant des parties centrale (4a) et périphérique (4b). Un circuit et des bornes sont formés dans les parties centrale (4a) et périphérique (4b), respectivement. Un substrat porteur est fixé à la partie centrale de la puce LSI. Le substrat porteur (3) a des parties centrale (4a) et périphérique (4b). Des gouttes et des bornes font prévues dans les parties centrale (4a) et périphérique (4b), respectivement du substrat porteur (3). Des fils connectent les bornes de la puce LSI et du substrat porteur (3). Le substrat porteur (3) est monté sur un substrat par l'intermédiaire des gouttes. Le coefficient de dilatation thermique est compris entre ceux de la puce LSI et du substrat.

CIRCUIT CARRIER

radiation Semiconductor

MACHINE FOR ATTACHING THE CONNECTING WIRES TO THE CONNECTION POINTS OF A SEMICONDUCTOR COMPONENT AND OF THE HOUSING ACCOMMODATING THE SEMICONDUCTOR COMPONENT

IMPROVEMENTS IN AND RELATING TO SEMICONDUCTOR DEVICES

HERMETICALLY SEALED PACKAGE FOR USE IN ELECTRONIC COMPONENTS

Semiconductor device package

WIRE BONDING DEVICE AND WIRE BONDING METHOD

ELECTRODE UP/DOWN APPARATUS OF WIRE BONDER

SEMICONDUCTOR CHIP PACKAGE

PURPOSE: A semiconductor chip package is provided to improve a reliability and to suppress a crack generation by making a semiconductor chip be supported by a bonding wire without using a lead frame pad or an adhesive. CONSTITUTION: In a semiconductor chip package, a bottom surface of a semiconductor chip(34) is contacted with a lower metal mold(87). A lead of a lead frame(62) is lifted over an upper surface of the semiconductor chip(34), and is connected only by a wire. An upper metal mold(88) is closed with the lower metal mold(87), and a molding resin is injected through an injection hole(86) along an arrow direction. An air contained in a cavity(84) is discharged at an air vent. A dummy tie bar is formed at both sides of the chip in the same direction as the injection hole(86) is set. COPYRIGHT 2000 KIPO ...

INTEGRATED MODULE HAVING MULTIPLE STRUCTURE AND FABRICATING METHOD THEREOF, CAPABLE OF BEING APPLIED EVEN WITH A THIN THICKNESS AND OPERATING STABLY EVEN IN A HIGH FREQUENCY

PURPOSE: An integrated module having a multiple structure and its fabricating method are provided to achieve thermal stability of a semiconductor chip and shield an electromagnetic wave of a high frequency device without an additional process. CONSTITUTION: An integrated module(300) having a multiple structure includes a printed circuit board(310) and a metal member(340). The printed circuit board has at least one hole(311) and a groove(312). The at least one hole passes through opposite first and second surfaces of the printed circuit board. The groove is formed on the second surface of the printed circuit board. The metal member is received on the second surface of the printed circuit board to be contacted with the second surface of the printed circuit board. The integrated module having the multiple structure further includes a semiconductor chip(333), a high frequency device(331), and a plurality of passive devices(334). The semiconductor chip is inserted into the hole and placed to ...

A film and chip packaging process using the same

ADHESIVE FILM, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

EPOXY RESIN COMPOSITION AND DIE BONDING MATERIAL COMPRISING THE COMPOSITION

DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM

Method for revising wire bonding position

Wire bonding apparatus

Device for preventing wire displacement of semiconductor package and method for manufacturing the same

반도체 장치 및 반도체 장치의 제조방법

... 반도체 장치는 접속단자와, 한 면에 전극패드를 갖는 반도체칩과, 접속단자와 반도체칩의 전극패드를 접속하는 와이어와, 반도체칩의 한 면을 덮고, 접속단자와 와이어를 밀봉하는 투명수지를 구비하며, 와이어는 전극패드에 접합되는 제1 본딩부와, 접속단자에 접합되는 제2 본딩부와, 제1 본딩부에 연속하여 형성되고, 제2 본딩부와는 반대측에 되접힘부를 갖는 루프부를 구비하고, 루프부는 제1 본딩부와의 사이, 및 와이어의 다른 부분과의 사이에, 각각 소정의 간격이 설치되어 있다.

반도체 장치용 본딩 와이어

Cu 합금 코어재와 그 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 고온에 있어서의 볼 접합부의 접합 신뢰성 향상과, 내력비(＝최대 내력/0.2％ 내력): 1.1∼1.6의 양립을 도모한다. 와이어 중에 고온 환경 하에 있어서의 접속 신뢰성을 부여하는 원소를 포함함으로써 고온에 있어서의 볼 접합부의 접합 신뢰성을 향상시키고, 또한 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 대해 결정 방위를 측정한 결과에 있어서, 와이어 길이 방향의 결정 방위 중, 와이어 길이 방향에 대해 각도 차가 15도 이하인 결정 방위 <100>의 방위 비율을 30％ 이상으로 하고, 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 있어서의 평균 결정 입경을 0.9∼1.5㎛로 함으로써, 내력비를 1.6 이하로 한다.

MULTI-CHIP BALL GRID ARRAY IC PACKAGES

PURPOSE: A multiple chip ball grid array package is provided to increase the I/O density by mounting active chips in the standoff space on the underside of the substrate inside the ball grid array. CONSTITUTION: State of the art IC chips can be made thin enough that they can be mounted in the space between the board(16) and the substrate(12). For convenience in this description this space will be referred to herein as the "BGA gap". A BGA package designed, where the IC chip is designated(21) and is die bonded to interconnect substrate(22). Bond pads(23) on the IC chip are interconnected to bond pads(24) on the interconnect substrate by wire bonds(25). The substrate(22) is interconnected to motherboard(26), by solder balls(27) and BGA bond pads(28). Attached to the underside of the substrate(22), in the BGA gap, is an array of IC chips(31-34). Each of the array of IC chips is flip-chip bonded to the underside of substrate(22) using solder bumps(35). Solder bumps(35) are typically provided ...

SEMICONDUCTOR PACKAGE FOR BEING DIRECTLY MOUNTED IN THE SEMICONDUCTOR CHIP AND A METHOD OF FORMATION THEREOF

PURPOSE: It can be connected by an interposer even though the pad of memory device and the logic device or the bump's position is changed. The high speed operation can be implemented by the interposer even though the design change of the memory device and logic device. CONSTITUTION: The semiconductor package comprises a printed circuit board(10); the first semiconductor chip(20) having on the printed circuit board; the chip package having on the first semiconductor chip; the chip package directly contacts with the first semiconductor chip; the second semiconductor chip on interposer. The interposer has the penetrating electrode(110). The first semiconductor chip comprises the first bump pad(24) arranged in the upper side. The first bump(105) contacts with the first bump pad. The printed circuit board comprises the solder ball arranged to the lower surface. © KIPO 2009 ...

BONDING WITH A COMPLIANT MEDIUM

Wire loop and its wire bonding method

The present invention utilizes the loop control of the capillary to form a low wire-loop. The low wire-loop can apply to the multi-chip stacked package or multi-layer bonding wire.

Enhanced method of wire bonding between substrate and semiconductor chip and soldering control system

An enhanced method of wire bonding between a substrate and a semiconductor chip is provided, which includes the following steps. A substrate is provided. At least one first pad is formed on the substrate. A semiconductor chip having at least one second pad is provided on the substrate. A first solder ball and a second solder ball are formed on the first pad and the second pad, respectively. A wire is bonded between the first and second solder balls. The interface between the first solder ball and the first pad is conducted by friction stir welding to enhance the joint of the first solder ball and the first pad.

Bonding wire for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 [mu]m provides a strength ratio of 1.6 or less.

Manufacturing method of resin-sealed semiconductor apparatus and device thereof

A manufacturing method of resin-sealed semiconductor apparatus, which mainly bonds electronic components and leads and seals said electronic components and leads by resin, comprises: (1) Surface treatment process, under atmospheric pressure or near atmospheric pressure using high-frequency voltage to generate gas discharge in gas, exposing at least one of said electronic components or leads to active gas of said gas generated by said discharge; (2) Process of resin-sealing at least one of said components or leads by resin.

Wire bond process

A wire bond process is provided. When a wire bond process is conducted, an insulated conduction wire covered by an insulated film or metal wire but accompanied with insulated glue injection is adopted in a wire bond machine to form plural insulated wires among the chip, substrate and lead frame. Because the insulated layer or glue covers the metal wire surface, the short-circuit problem during the package process can be prevented effectively.

Bonding machine incorporating dual-track transfer mechanism

Semiconductor device and method of manufacturing the same

The occurrence of package crack in the vicinity of the rear surface at a die pad part is suppressed by setting the outer dimensions at the die pad part of a lead frame to be smaller than those of a semiconductor chip to be mounted thereon and the occurrence of package crack in the vicinity of the major surface of the semiconductor chip is suppressed by forming an organic layer exhibiting high adhesion to a resin composing the package body on a surface protective film (final passivation film) covering the uppermost layer wiring of the semiconductor chip.

Image processing method, image processor and bonding device

The object of the present invention is to highly accurately detect a position without performing pattern matching in a rotating direction even in the case that a detection object is arranged in a posture including a position deviation in the rotating direction and to efficiently execute the generation of a mask pattern. To solve the problem, inter-image subtraction is performed between a detection object image and a template image decided by a reticule mark 42 and a mark pattern image is generated/stored by utilizing the result (area hatched). In runtime, the area corresponding to the mask pattern image is excluded from the object of pattern matching.

Semiconductor device and manufacturing method of the semiconductor device

THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE

A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above th plane of the base 11 by four sloped walls 13, 1-13.4. The walls slope at an acute angl with reaped, to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

SUBSTRATE WITH BUILT-IN CHIP AND METHOD FOR MANUFACTURING SUBSTRATE WITH BUILT-IN CHIP

A method for manufacturing a substrate having a built-in chip is provided with a first step of mounting a semiconductor chip on a first substrate whereupon a first wiring is formed, and a second step of bonding a second substrate whereupon a second wiring is formed with the first substrate. In the second step, the semiconductor chip is sealed between the first substrate and the second substrate, the first wiring is electrically connected with the second wiring, and a multilayer wiring connected with the semiconductor chip is formed.

STRIP FOR INTEGRATED CIRCUIT PACKAGES HAVING A MAXIMIZED USABLE AREA

A strip (40) on which a plurality of integrated circuit package outlines (42) may be fabricated 'within a plurality of process tools. The strip includes one or more fiducial, notches (44) and/or guide pin notches (46) formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes (24, 26), with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes (92) filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.

A CLAMPING ASSEMBLY

A clamping assembly (1 ) for clamping a lead frame (7) with pre-attached semiconductor device, comprising of: a first member (2) to hold the lead frame (7), said first member (2) having a surface profile in contact with a surface profile of the semiconductor device, a second member (3)for allowing the mounting of the first member (2) thereon, an attachment means to secure the first member (2) onto the second member (3), wherein the attachment means is adjustable to conform the surface profile of the first member (2) to the surface profile of the lead frame (7).

METHODS AND APPARATUS FOR FABRICATING CHIP-ON-BOARD MODULES

A method of assembling a Chip-on-Board memory module as shown in Fig. 1, the method may be divided into several area or steps, mounting (step 100), patching (step 110), testing (step 120), and covering (step 130). During mounting (step 100), preferably, at least one unpackaged chip is mounted on a printing circuit board. In some embodiments, a selectively settable material may used to mount unpackaged memory parts. When mounting die on PC (step 101), a ring of selectively settable material is preferably used to surround the die and hold the die in place. Once mounted the alignment of each unpackaged chip may be adjusted (step 102), after which the ring selectively settable material disposed around the chip is cured or hardened (step 103). The hardened ring around each die keeps the die in place. In some embodiments, the ring is higher than the die it surround to facilitate the addition of bond wires.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Method of precisely aligning components in flexible integrated circuit module

The present invention is a method of aligning components on a flexible integrated circuit. First a rigid substrate is selected. Next a flexible interconnect is deposited on the substrate, the interconnect preferably consisting of alternating polyimide and metal layers. After depositing the interconnect on the substrate, solder bumps are applied to the interconnect. Next, attach electronic components to the interconnect. A second substrate is then attached to the electronic components. Then, remove the first substrate to expose the interconnect. Last, the second substrate is removed to release the integrated circuit module.

Semiconductor device and a method of manufacturing the same

A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.

Wire bonding apparatus

A wire bonding apparatus includes a frame, an X, Y, table, installed on the frame, including a linear stepping motor with a first stator and a first inductor, a transducer, pivotably installed on the X, Y table, to one end of which a capillary for bonding wire is installed, a first transferring portion installed to the frame to make the other end of the transducer ascend so that the capillary for wire bonding ascends, a second transferring portion installed on the X, Y table in front of the first transferring portion to, thereby, make the other end of the transducer ascend during bonding, and a first location detecting portion installed to the frame and the X, Y table to detect an amount of movement in the X and Y directions so that energy loss according to the driving of a head portion can be reduced.

Lead frame holding apparatus for use in wire bonders

A lead frame holding apparatus for wire bonding machines forcing an upward movement of a heater block and a frame retainer by a heater block raising-and-lowering cam and a frame retainer raising-and-lowering cam and a downward movement of the heater block and frame retainer via a spring force. When the heater block is raised and approaches its upper limit position, the frame retainer is raised by this upward motion of the heater block, thus positioning the lead frame at a standard bonding level.

Non-conductive and self-leveling leadframe clamp insert for wirebonding integrated circuits

A leadframe clamping apparatus includes a resilient polymeric membrane which permits self-leveling compensation of a variably movable clamp insert for variations in leadframe thickness. The clamp insert is formed of a polymer such as polyimide to provide further compensation for leadframe variations.

Adjustable height work holder for bonding semiconductor dies

In a semiconductor wire bonder, the need for frequently changing chucks and re-focusing optical equipment for each different die/package thickness combination is alleviated by providing an adjustable stop mechanism lifting the upward displacement of the die/package off of a carrier. The adjustable stop mechanism includes a first, stationary bracket having a leg extending towards a movable lifting member of the bonder, and a second bracket mounted to the movable lifting member. A set screw extending through the leg of the first bracket limits the upward movement of the movable member, and ensures that the front surface of a die being bonded is at an optimum position for bonding.

Wire bonding method with a frame, for connecting an electronic component for testing and mounting

A device and method are disclosed for connecting an electronic component so that it can be tested and mounted. According to the method, pads on the component are first connected to pads on a surrounding frame, by means of conducting wires. The component is tested by probes of the testing instruments to the pads of the surrounding frame. When the tests are done, the component and its frame is placed on the substrate on which it has to be mounted. The pads of the component are connected to pads on the substrate by the wires used for connection to the pads of the surrounding frame. After connection, the wires are cut between the substrate pads and the frame pads, and then the frame is removed.

MICROWAVE TRANSISTOR CARRIER FOR COMMON BASE CLASS A OPERATION

Lead-on-chip type semiconductor device having thin plate and method for manufacturing the same

In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Asymmetric alignment of substrate interconnect to semiconductor die

An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Automated method of attaching flip chip devices to a substrate

Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.

SEMICONDUCTOR MODULE AND IMAGE PICKUP APPARATUS

A semiconductor module including multiple semiconductor devices prevents a signal that flows through a bonding wire connected to one semiconductor device from acting as noise which affects the other semiconductor devices, thereby improving the operation reliability of the semiconductor module. A second semiconductor device layered on a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire. The bonding wire is provided across the side E1 of the second semiconductor device. A bonding wire connected to the first semiconductor device is provided across a side of the first semiconductor device other than the side F1 that corresponds to the side E1 of the second semiconductor device, i.e., across the side F2, F3, or F4 of the first semiconductor device.

Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Thermal enhanced upper and dual heat sink exposed molded leadless package

A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

RACETRACK DESIGN IN RADIO FREQUENCY SHIELDING APPLICATIONS

Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. Locations of where the racetrack can be adjusted (for example, narrowed) and/or removed without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, a portion of the racetrack can be removed to create a break and/or a portion of the racetrack can be narrowed in a selected area.

Integrated circuit packaging system with isolated pads and method of manufacture thereof

A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Methods for forming packaged products

An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Methods of operating electronic devices, and methods of providing electronic devices

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Packaged light emitting diodes including phosphor coating and phosphor coating systems

Light emitting structures are disclosed that can include a semiconductor light emitting diode (LED) that includes a p-n junction active layer. A first layer can include a binder material having a thickness that is less than about 1000 μm, wherein the first layer is directly on the LED. A second layer can include phosphor particles, where the second layer can have a thickness that is less than about 1000 μm and can be directly on the first layer so that the first layer is between the LED and the second layer.

Integrated circuit packaging system with die paddle and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Surface-modified silicate luminophores

A surface-modified silicate luminophore includes a silicate luminophore and a coating includes at least one of (a) a fluorinated coating including a fluorinated inorganic agent, a fluorinated organic agent, or a combination of fluorinated inorganic and organic agents, the fluorinated coating generating hydrophobic surface sites and (b) a combination of the fluorinated coating and at least one moisture barrier layer. The moisture barrier layer includes MgO, Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Gd 2 O 3 , Lu 2 O 3 , and SiO 2 or the corresponding precursors, and the coating is disposed on the surface of the silicate luminophore.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Semiconductor package integrated with conformal shield and antenna

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Integrated Power Converter Package With Die Stacking

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Led package, and mold and method of manufacturing the same

The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Atomic layer deposition encapsulation for power amplifiers in rf circuits

Power amplifiers and methods of coating a protective film of alumina (Al 2 O 3 ) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Semiconductor module

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Method for manufacturing semiconductor device

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Method for semiconductor leadframes in low volume and rapid turnaround

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Cerium and Europium Doped Phosphor Compositions and Light Emitting Devices Including the Same

Compounds of Formula I, which include both cerium and europium, may be useful as phosphors in solid state light emitting devices. Light emitting devices including such phosphors may emit warm white light.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Brace for long wire bond

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Bond package and approach therefor

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

Light source with tunable cri

A light-emitting device with at least two light-emitting dies encapsulated with two different types of the wavelength-converting materials is disclosed. Each of the wavelength-converting materials is configured to produce a visible light from a narrow band light near UV region produced by the light-emitting dies, but with different correlated color temperatures (CCT) and different spectral contents. The combination of the two visible light forms the desired visible white light. The Color rendering index of the light-emitting device is tunable by adjusting the supply current to the light-emitting dies. In another embodiment, a light module with tunable CRI for an illumination system is disclosed.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

(halo)silicate-based phosphor and manufacturing method of the same

Disclosed are a (halo)silicate-based phosphor and a manufacturing method of the same. More particularly, the disclosed phosphor is a novel (halo)silicate-based phosphor manufactured by using a (halo)silicate-based host material containing an alkaline earth metal, and europium as an activator.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Method of manufacturing film for semiconductor device

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Light emitting device package and manufacturing method thereof

A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package includes a circuit board comprising at least one device region, a plurality of electrode regions, at least one first thermal via exposed through upper and lower surfaces of the at least one device region, and a plurality of second thermal vias exposed through upper and lower surfaces of the plurality of electrode regions; at least one first thermal pad bonded to the upper surface of the at least one device region and connected to the first thermal via; at least one LED mounted on the at least one first thermal pad; a plurality of first electrode pads bonded to the upper surface of the electrode region and connected to the second thermal vias; and a plurality of wires to connect the at least one LED with the plurality of first electrode pads.

Unpackaged and packaged IC stacked in a system-in-package module

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Method for making circuit board

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Die attach film

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

Support structures and clamping systems for semiconductor devices during wire and ribbon bonding operations

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

Methods and devices for rescuing a distressed diver

The invention discloses devices and methods for identifying a diver in distress and initiating a rescue response. Specifically, embodiments of the present invention allow for identification of a diver who is not breathing properly and in response giving local stimuli to allow the diver to response. Should he/she not respond, the instant invention will initiate steps to bring the diver back to the water surface and alert others as to his/her need of assistance.

Package structure and manufacturing method thereof

A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Saw Type Package without Exposed Pad

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

White light emitting lamp and white led lighting apparatus including the same

An object is to provide a white light emitting lamp 1 comprising: a semiconductor light emitting element 2 which is placed on a board 3 and emits ultraviolet light or blue light; and a light emitting portion that is formed so as to cover a light emitting surface of the semiconductor light emitting element 2 , the light emitting portion containing a blue phosphor B, a green phosphor G, a red phosphor R and a deep red phosphor DR that are excited by the light emitted from the semiconductor light emitting element 2 to respectively emit blue light, green light, red light and a deep red light, the white light emitting lamp 1 emitting white light by mixing light emission colors from the blue phosphor B, the green phosphor G, the red phosphor R and a deep red phosphor DR with one another, wherein the deep red phosphor DR has a main emission peak in a longer wavelength region than a main emission peak of the red phosphor, the red phosphor R comprises at least one component selected from: a europium-activated SiAlON phosphor and a europium-activated CASN phosphor each having a predetermined composition, while the deep red phosphor DR comprises a manganese-activated magnesium florogermanate phosphor having a predetermined composition. According to the above white light emitting lamp, when the BGR phosphor is used in combination with the semiconductor element such as an LED or the like, and a deep red phosphor DR having a predetermined composition is further added in addition to the red phosphor R, so that luminance characteristics can be improved, whereby there can be provided a white light emitting lamp excellent in both high luminance and high color rendering properties.

Light emitting device

A light emitting device comprises two or more light emitting elements, two or more lead frames electrically connected to the light emitting elements, and a case formed as a slender flat box shape and having an accommodating recession for accommodating the light emitting elements and the lead frame, wherein the lead frames are buried in the case and provided side by side in a longitudinal direction of the case, and the surfaces of the lead frames are arranged coplanar, the light emitting elements are mounted on the lead frames, and the plurality of lead frames and the case are arranged in a nearly linear symmetric configuration with respect to a central line that bisects the light emitting device in the longitudinal direction, so that no uneven heat distribution takes place.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Method of Forming a Package Substrate

In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.

Method for assembling at least one chip using a fabric, and fabric including a chip device

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

Light emitting device and method for manufacturing the same

A light emitting device 10 includes a light emitting element 11 , a package 13 in which the light emitting element 11 is accommodated, and a sealing member 14 configured to seal the light emitting element 11 . The package 13 includes a base 13 B configured to hold the light emitting element 11 and a frame part 13 A vertically standing on the base 13 B so as to surround the light emitting element 11 . The sealing member 14 is embedded in a region surrounded by the frame part 13 A. The frame part 13 A includes a protruding wall 15 upwardly protruding from an upper end surface 132 a of the frame part 13 A and provided so as to surround the light emitting element 11.

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Low loop wire bonding

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Solid state light sources based on thermally conductive luminescent elements containing interconnects

Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor device and connection checking method for semiconductor device

A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Semiconductor light emitting module and method of manufacturing the same

Provided are a semiconductor light emitting module and a method of manufacturing the same, which allow achieving high luminance light emission as well as lightweight and compact features. In a semiconductor light emitting module ( 101 ), a projecting portion ( 202 ) serving as a reflecting member is formed on a metal thin plate ( 102 ) to surround a semiconductor light emitting element ( 104 ). The semiconductor light emitting element ( 104 ) is connected to a printed board ( 103 ) by using a wire ( 201 ), for example. The projecting portion ( 202 ) is formed by pressing and bending the metal thin plate ( 102 ) from a back surface, for example, to surround the element and to be higher than the semiconductor light emitting element ( 104 ).

Large panel leadframe

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice

Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

Microelectro mechanical system encapsulation scheme

A microelectro mechanical system (MEMS) assembly includes a carrier and a MEMS device disposed over the carrier. A buffer layer is disposed over the MEMS device. The Young's modulus of the buffer layer is less than that of the MEMS device.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Integrated circuit including a differential power amplifier with a single ended output and an integrated balun

An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging encasing the die with contact pins to connect between the integrated circuit and external elements; wires connecting between the pads and the contact pins; a converter that includes capacitors and inductors to combine the outputs from the differential power amplifier to form a single ended output at one of the contact pins; wherein inherent inductance of some of the wires serve as the inductors of the converter.

Solid state apparatus

A solid state apparatus comprising, a printed circuit board having a first and a second surface that are opposite surfaces, a semiconductor chip for imaging arranged on the first surface, a sealing resin arranged to cover the printed circuit board and the semiconductor chip, and a translucent member arranged on the sealing resin, the solid state apparatus having a first region located inward of an outer edge of the semiconductor chip, and a second region located outward of the outer edge, the printed circuit board comprising, on the first surface, a first terminal electrically connected to the semiconductor chip, and comprising, on the second surface, a second terminal electrically connected to the first terminal within the printed circuit board, the second terminal being arranged in the first region.

Doped 4n copper wires for bonding in microelectronics devices

A doped 4N copper wire for bonding in microelectronics contains one or more corrosion resistance dopant materials selected from Ag, Ni, Pd, Au, Pt, and Cr. A total concentration of the corrosion resistance dopant materials is between about 10 wt. ppm and about 80 wt. ppm.

Resin Sealed Semiconductor Device And Manufacturing Method Therefor

A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Wire bonding method in circuit device

A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.

Heavy-wire bond arrangement and method for producing same

The invention relates to a heavy-wire bond arrangement, having a substrate ( 2 ), a heavy wire ( 1 ) and a high-voltage heavy-wire bond connection, in which an end bond section ( 4 ) of the heavy wire ( 1 ), which extends towards the end ( 7 ) of the heavy wire ( 1 ), is bonded to the substrate ( 2 ), such that in the area of the bond section ( 4 ) a bond contact ( 5 ) between the heavy wire ( 1 ) and the substrate ( 2 ) is formed, the heavy wire ( 1 ) having a tapering section ( 6 ) which adjoins the end of the wire ( 7 ) and in which the wire cross-section tapers towards the end of the wire ( 7 ). The application additionally relates to a method for producing a heavy-wire bond arrangement.

Manufacturing method of semiconductor device

A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE 1 c of a first lead, a tip portion LE 2 c of a second lead, and a tip portion LE 3 c of a third lead by using a spanking die SDM 1 , the tip portion LE 1 c of the first lead, the tip portion LE 2 c of the second lead, and the tip portion LE 3 c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD 1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU 1 , and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD 1 and a flat pressing surface of the upper die SU 1.

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Lead frame with grooved lead finger

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

Methods of adjusting ultrasonic bonding energy on wire bonding machines

A method of adjusting ultrasonic bonding energy on a wire bonding machine, the method comprising the steps of: providing a reference relationship between free air ball squash and ultrasonic bonding energy; determining an actual relationship between free air ball squash and ultrasonic bonding energy on a subject wire bonding machine; and adjusting at least one ultrasonic bonding energy setting of the subject wire bonding machine such that the actual relationship of the subject wire bonding machine is closer to the reference relationship.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Thin film light emitting diode

Light emitting devices comprise a substrate having a surface and a side surface; a semiconductor structure on the surface of the substrate, the semiconductor structure having a first surface, a second surface and a side surface, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the substrate, and wherein the semiconductor structure comprises a first-type layer, a light emitting layer and a second-type layer; a first and a second electrodes; and a wavelength converting element arranged on the side surface of the semiconductor structure, wherein the wavelength converting element has an open space, and wherein the open space is a portion not covered by the wavelength converting element.

Ultrasonic bonding systems and methods of using the same

An ultrasonic bonding machine is provided. The ultrasonic bonding machine includes a support structure configured to support a workpiece during a bonding operation. The ultrasonic bonding machine further includes an upper bonding tool positioned above the support structure and configured for bonding an upper bonding material to an upper side of the workpiece, and a lower bonding tool positioned below the support structure and configured for bonding a lower bonding material to a lower side of the workpiece. The ultrasonic bonding machine may also be an ultrasonic ribbon bonding machine configured to bond an upper and lower conductive ribbon to a solar substrate.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Wedge bonder and a method of cleaning a wedge bonder

Disclosed is a wedge bonder, comprising a wedge for bonding a wire to surfaces to form an electrical interconnection therebetween, a cleaning device for cleaning the wedge, and a positioning device to which the wedge is mounted. In particular, the positioning device is operative to move the wedge to the cleaning device for cleaning. A method of cleaning a wedge of a wedge bonder is also disclosed.

Miniature Surface Mount Device

A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Parallel plate slot emission array

Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.

Very extremely thin semiconductor package

A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.